From 7fc99a9e1104703566945ace1b2e1ed59819ba48 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Wed, 10 Mar 2021 10:19:45 +0100
Subject: [PATCH 01/72] Call One time tu_fifo_write_n on cdcd_xfer_cb

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/class/cdc/cdc_device.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 5a74b487..64cb4ab2 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -432,25 +432,25 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   // Received new data
   if ( ep_addr == p_cdc->ep_out )
   {
+    tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
+    
     // TODO search for wanted char first for better performance
-    for(uint32_t i=0; i<xferred_bytes; i++)
-    {
-      tu_fifo_write(&p_cdc->rx_ff, &p_cdc->epout_buf[i]);
-
+    if (tud_cdc_rx_wanted_cb && ( ((signed char) p_cdc->wanted_char) != -1)) {
       // Check for wanted char and invoke callback if needed
-      if ( tud_cdc_rx_wanted_cb && ( ((signed char) p_cdc->wanted_char) != -1 ) && ( p_cdc->wanted_char == p_cdc->epout_buf[i] ) )
-      {
-        tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
+      for (uint32_t i=0; i<xferred_bytes; i++) {
+        if ( p_cdc->wanted_char == p_cdc->epout_buf[i] ) {
+          tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
+        }
       }
     }
-
+    
     // invoke receive callback (if there is still data)
     if (tud_cdc_rx_cb && tu_fifo_count(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
-
+    
     // prepare for OUT transaction
     _prep_out_transaction(p_cdc);
   }
-
+  
   // Data sent to host, we continue to fetch from tx fifo to send.
   // Note: This will cause incorrect baudrate set in line coding.
   //       Though maybe the baudrate is not really important !!!

From 5caad485f199ab6acfa237d84bf3d84cf41dcfdd Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 11 Mar 2021 20:36:46 +0100
Subject: [PATCH 02/72] Add fifo empty check.

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/class/cdc/cdc_device.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 64cb4ab2..d9b098bb 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -434,11 +434,10 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   {
     tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
     
-    // TODO search for wanted char first for better performance
+    // Check for wanted char and invoke callback if needed
     if (tud_cdc_rx_wanted_cb && ( ((signed char) p_cdc->wanted_char) != -1)) {
-      // Check for wanted char and invoke callback if needed
       for (uint32_t i=0; i<xferred_bytes; i++) {
-        if ( p_cdc->wanted_char == p_cdc->epout_buf[i] ) {
+        if ( p_cdc->wanted_char == p_cdc->epout_buf[i] && tu_fifo_count(&p_cdc->rx_ff) ) {
           tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
         }
       }

From 31373fd55cefced35cfaaa61fb8f9aa3e5ec0bc6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 12 Mar 2021 12:55:18 +0700
Subject: [PATCH 03/72] use !tu_fifo_empty() instead of tu_fifo_count()

---
 src/class/cdc/cdc_device.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index d9b098bb..c24edb75 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -95,7 +95,8 @@ static void _prep_out_transaction (cdcd_interface_t* p_cdc)
   // fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&p_cdc->rx_ff);
 
-  if ( available >= sizeof(p_cdc->epout_buf) )  {
+  if ( available >= sizeof(p_cdc->epout_buf) )
+  {
     usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
   }else
   {
@@ -435,16 +436,19 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
     tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
     
     // Check for wanted char and invoke callback if needed
-    if (tud_cdc_rx_wanted_cb && ( ((signed char) p_cdc->wanted_char) != -1)) {
-      for (uint32_t i=0; i<xferred_bytes; i++) {
-        if ( p_cdc->wanted_char == p_cdc->epout_buf[i] && tu_fifo_count(&p_cdc->rx_ff) ) {
+    if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
+    {
+      for ( uint32_t i = 0; i < xferred_bytes; i++ )
+      {
+        if ( (p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff) )
+        {
           tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
         }
       }
     }
     
     // invoke receive callback (if there is still data)
-    if (tud_cdc_rx_cb && tu_fifo_count(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
+    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
     
     // prepare for OUT transaction
     _prep_out_transaction(p_cdc);

From 3a27a9405f3354468c9ff8ae2ddd5d350e1ce19a Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 12 Mar 2021 15:10:47 +0700
Subject: [PATCH 04/72] Release 0.9.0 (#716)

* update change log for release
* move changelog into docs/
* more changelog
* increase macro version
---
 changelog.md => docs/changelog.md | 103 ++++++++++++++++++++++++++++--
 src/tusb_option.h                 |   2 +-
 2 files changed, 100 insertions(+), 5 deletions(-)
 rename changelog.md => docs/changelog.md (76%)

diff --git a/changelog.md b/docs/changelog.md
similarity index 76%
rename from changelog.md
rename to docs/changelog.md
index d645b4fb..0e5f12e8 100644
--- a/changelog.md
+++ b/docs/changelog.md
@@ -1,10 +1,105 @@
 # TinyUSB Changelog
 
-## WIP
+## 0.9.0 - 2021.03.12
+
+### Device Stack
+
+#### Device Controller Driver (DCD)
+
+RP2040
+
+- Fix endpoint buffer reallocation overrun problem
+- Fix osal_pico queue overflow in initialization
+- Fix Isochronous endpoint buffer size in transfer
+- Optimize hardware endpoint struct to reduce RAM usage
+- Fix enum walkaround forever check for SE0 when pull up is disabled
+
+Sony CXD56
+
+- Pass the correct speed on Spresense
+- Fix setup processed flag
+
+NXP Transdimention
+
+- Update dcd_init() to reset controller to device mode
+
+#### USB Device Driver (USBD)
+
+- Fix issue with status zlp (tud_control_status) is returned by class driver with SET/CLEAR_FEATURE for endpoint.
+- Correct endpoint size check for fullspeed bulk, can be 8, 16, 32, 64
+- Ack SET_INTERFACE even if it is not implemented by class driver.
+
+#### Device Class Driver
+
+DFU Runtime
+
+- rename dfu_rt to dfu_runtime for easy reading
+
+CDC
+
+- Add tud_cdc_send_break_cb() to support break request
+- Improve CDC receive, minor behavior changes: when tud_cdc_rx_wanted_cb() is invoked wanted_char may not be the last byte in the fifo 
+
+HID
+
+- [Breaking] Add itf argument to hid API to support multiple instances, follow API has signature changes
+  - tud_hid_descriptor_report_cb()
+  - tud_hid_get_report_cb()
+  - tud_hid_set_report_cb()
+  - tud_hid_boot_mode_cb()
+  - tud_hid_set_idle_cb()
+- Add report complete callback tud_hid_report_complete_cb() API
+- Add DPad/Hat support for HID Gamepad
+  - TUD_HID_REPORT_DESC_GAMEPAD() now support 16 buttons, 2 joysticks, 1 hat/dpad
+  - Add hid_gamepad_report_t along with GAMEPAD_BUTTON_ and GAMEPAD_HAT_ enum
+  - Add Gamepad to hid_composite / hid_composite_freertos example
+
+MIDI
 
 - Fix dropping MIDI sysex message when fifo is full
-- Add DPad/Hat support for HID Gamepad
-- Add tud_hid_report_complete_cb() API
+- Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
+- Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
+
+### Host Stack
+
+#### Host Controller Driver (HCD)
+
+- Add rhport to hcd_init()
+- Improve EHCI/OHCI driver abstraction
+  - Move echi/ohci files to portable/
+  - Rename hcd_lpc18_43 to hcd_transdimension
+  - Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
+- Update NXP transdimention hcd_init() to reset controller to host mode
+  - Ported hcd to rt10xx
+
+#### USB Host Driver (USBH)
+
+- No noticeable changes to usbh
+
+#### Host Class Driver
+
+MSC
+
+- Rename tuh_msc_scsi_inquiry() to tuh_msc_inquiry()
+- Rename tuh_msc_mounted_cb/tuh_msc_unmounted_cb to tuh_msc_mount_cb/tuh_msc_unmount_cb to match device stack naming
+- Change tuh_msc_is_busy() to tuh_msc_ready()
+- Add read10 and write10 function: tuh_msc_read10(), tuh_msc_write10()
+- Read_Capacity is invoked as part of enumeration process
+- Add tuh_msc_get_block_count(), tuh_msc_get_block_size()
+- Add CFG_TUH_MSC_MAXLUN (default to 4) to hold lun capacities
+
+### Others
+
+- Add basic support for rt-thread OS
+- Change zero bitfield length to more explicit padding
+- Build example now fetch required submodules on the fly while running `make` without prio submodule init for mcu drivers
+- Update pico-sdk to v1.1.0
+
+**New Boards**
+
+- Microchip SAM E54 Xplained Pro
+- LPCXpresso 55s28
+- LPCXpresso 18s37
 
 ## 0.8.0 - 2021.02.05
 
@@ -26,7 +121,7 @@
 
 ### USB Device 
 
-**UBSD**
+**USBD**
 
 - Rework usbd control transfer to have additional stage parameter for setup, data, status
 - Fix tusb_init() return true instead of TUSB_ERROR_NONE
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 6cbdefbf..cafe9e52 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -28,7 +28,7 @@
 #define _TUSB_OPTION_H_
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     8
+#define TUSB_VERSION_MINOR     9
 #define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 

From bcf9c8cb27d223e2b0078daf7e3311db3bb4bd82 Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Thu, 11 Mar 2021 18:19:08 +0100
Subject: [PATCH 05/72] SAM E54 XPlained Pro: free up DPLL1 for application

---
 hw/bsp/same54xplainedpro/board.mk            |  5 +--
 hw/bsp/same54xplainedpro/same54xplainedpro.c | 47 +++++++++++++-------
 2 files changed, 34 insertions(+), 18 deletions(-)

diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 508ab20f..1200fd9f 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -13,11 +13,10 @@ CFLAGS += \
   -D__SAME54P20A__ \
   -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
   -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
+  -DSAME54XPLAINEDPRO=1 \
+  -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
 
 
-
-#  -DSVC_Handler=SVCall_Handler
-
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
 
diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same54xplainedpro/same54xplainedpro.c
index a1d92075..0bdd477d 100644
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ b/hw/bsp/same54xplainedpro/same54xplainedpro.c
@@ -58,7 +58,6 @@ void USB_3_Handler(void)
 #define LED_PIN PIN_PC18
 #define BUTTON_PIN PIN_PB31
 #define BOARD_SERCOM SERCOM2
-#define BOARD_NAME "Microchip SAM E54 Xplained Pro"
 
 static inline void init_clock(void)
 {
@@ -72,16 +71,11 @@ static inline void init_clock(void)
 		OSCCTRL_XOSCCTRL_ENABLE;
 	while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
 
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(5) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 12 = 1Mhz, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000)-1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
+	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(2) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 6 = 2Mhz, input = XOSC1 */
+	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000 / 2) - 1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
 	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
 	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
 
-	OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(5) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 12 = 1Mhz, input = XOSC1 */
-	OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
-	OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-
 	/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
 	GCLK->GENCTRL[0].reg =
 		GCLK_GENCTRL_DIV(0) |
@@ -91,14 +85,37 @@ static inline void init_clock(void)
 		GCLK_GENCTRL_IDC;
 	while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
 
-	/* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
-	GCLK->GENCTRL[1].reg =
+	// configure GCLK2 for 12MHz from XOSC1
+	GCLK->GENCTRL[2].reg =
 		GCLK_GENCTRL_DIV(0) |
 		GCLK_GENCTRL_RUNSTDBY |
 		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL1 |
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
+		GCLK_GENCTRL_SRC_XOSC1 |
+		GCLK_GENCTRL_IDC;
+	while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
+
+	 /* setup DFLL48M to use GLCK2 */
+	GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
+
+	OSCCTRL->DFLLCTRLA.reg = 0;
+	while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
+
+	OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_MODE | OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL->DFLLMUL.bit.MUL = 4; // 4 * 12MHz -> 48MHz
+
+	OSCCTRL->DFLLCTRLA.reg =
+		OSCCTRL_DFLLCTRLA_ENABLE |
+		OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
+
+	// setup 48 MHz GCLK3 from DFLL48M
+	GCLK->GENCTRL[3].reg =
+		GCLK_GENCTRL_DIV(0) |
+		GCLK_GENCTRL_RUNSTDBY |
+		GCLK_GENCTRL_GENEN |
+		GCLK_GENCTRL_SRC_DFLL |
+		GCLK_GENCTRL_IDC;
+	while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
 }
 
 static inline void uart_init(void)
@@ -107,7 +124,7 @@ static inline void uart_init(void)
 	gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
 
 	MCLK->APBBMASK.bit.SERCOM2_ = 1;
-	GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK1 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK1 -> 48MHz */
+	GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
 
 	BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
 	while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
@@ -201,7 +218,7 @@ void board_init(void)
 	 * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
 	 * for low speed and full speed operation.
 	 */
-	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
+	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK3_Val | GCLK_PCHCTRL_CHEN);
 	hri_mclk_set_AHBMASK_USB_bit(MCLK);
 	hri_mclk_set_APBBMASK_USB_bit(MCLK);
 

From 01ec0d49ca24cda458d4c2fa4bb5f751ebd4b336 Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Thu, 11 Mar 2021 18:20:58 +0100
Subject: [PATCH 06/72] SAM E54 XPlained Pro: use proper defines SPI->USART for
 board init

---
 hw/bsp/same54xplainedpro/same54xplainedpro.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same54xplainedpro/same54xplainedpro.c
index 0bdd477d..70ea7d43 100644
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ b/hw/bsp/same54xplainedpro/same54xplainedpro.c
@@ -144,7 +144,7 @@ static inline void uart_init(void)
 	// BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
 	BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
 
-	BOARD_SERCOM->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+	BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
 	while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
 }
 
@@ -152,7 +152,7 @@ static inline void uart_send_buffer(uint8_t const *text, size_t len)
 {
 	for (size_t i = 0; i < len; ++i) {
 		BOARD_SERCOM->USART.DATA.reg = text[i];
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
+		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
 	}
 }
 
@@ -160,7 +160,7 @@ static inline void uart_send_str(const char* text)
 {
 	while (*text) {
 		BOARD_SERCOM->USART.DATA.reg = *text++;
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
+		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
 	}
 }
 

From 82e24306e2b0588e944476d71815f83ca392d1b9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Mar 2021 15:49:09 +0700
Subject: [PATCH 07/72] fix build with OPT_MCU_LPC177X_8X

---
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 3 ++-
 src/portable/nxp/lpc17_40/dcd_lpc17_40.h | 6 +++---
 src/portable/nxp/lpc17_40/hcd_lpc17_40.c | 3 ++-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 7d867aab..519d0915 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -26,7 +26,8 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
+#if TUSB_OPT_DEVICE_ENABLED && \
+    (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "device/dcd.h"
 #include "dcd_lpc17_40.h"
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
index 1e7c0fbc..07daa32e 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_DCD_LPC175X_6X_H_
-#define _TUSB_DCD_LPC175X_6X_H_
+#ifndef _TUSB_DCD_LPC17_40_H_
+#define _TUSB_DCD_LPC17_40_H_
 
 #include "common/tusb_common.h"
 
@@ -149,4 +149,4 @@ enum {
  }
 #endif
 
-#endif /* _TUSB_DCD_LPC175X_6X_H_ */
+#endif
diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
index 537b3dab..1c1faed9 100644
--- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
@@ -26,7 +26,8 @@
 
 #include "tusb_option.h"
 
-#if (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
+#if TUSB_OPT_HOST_ENABLED && \
+    (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "chip.h"
 

From 62d4652f86516e1fdd7fa79a29535cf39b2ab2f1 Mon Sep 17 00:00:00 2001
From: Michael Bruno <mikeb@xmos.com>
Date: Tue, 16 Mar 2021 10:48:42 -0400
Subject: [PATCH 08/72] Update usbtmc_device.c

Fix buffer alignment in TMC device class
---
 src/class/usbtmc/usbtmc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 88776d16..6c9b4244 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -131,9 +131,9 @@ typedef struct
   uint8_t ep_int_in;
   // IN buffer is only used for first packet, not the remainder
   // in order to deal with prepending header
-  uint8_t ep_bulk_in_buf[USBTMCD_MAX_PACKET_SIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_in_buf[USBTMCD_MAX_PACKET_SIZE];
   // OUT buffer receives one packet at a time
-  uint8_t ep_bulk_out_buf[USBTMCD_MAX_PACKET_SIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_out_buf[USBTMCD_MAX_PACKET_SIZE];
   uint32_t transfer_size_remaining; // also used for requested length for bulk IN.
   uint32_t transfer_size_sent;      // To keep track of data bytes that have been queued in FIFO (not header bytes)
 

From dc2f00cca157dc2279f917f59f9607fcd17b3fdb Mon Sep 17 00:00:00 2001
From: Jeremiah McCarthy <jeremiahmccarthy@xmos.com>
Date: Tue, 16 Mar 2021 17:04:40 -0400
Subject: [PATCH 09/72] Add Linux support to tmc example

Replaces visa include with pyvisa, as visa use with PyVISA is being
deprecated.
---
 examples/device/usbtmc/visaQuery.py | 38 +++++++++++++++++------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
index b5bf8d48..3f46b98e 100644
--- a/examples/device/usbtmc/visaQuery.py
+++ b/examples/device/usbtmc/visaQuery.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-import visa
+import pyvisa as visa
 import time
 import sys
 
@@ -36,8 +36,8 @@ def test_trig():
 	time.sleep(0.3) # SRQ may have some delay
 	assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds"
 	assert (inst.read_stb() == 0)
-	
-	
+
+
 def test_mav():
 	inst.write("delay 50")
 	inst.read_stb() # clear STB
@@ -45,15 +45,15 @@ def test_mav():
 	inst.write("123")
 	time.sleep(0.3)
 	assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds"
-	
+
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
-	
-	
+
+
 def test_srq():
 	assert (inst.read_stb() == 0)
 	inst.write("123")
-	
+
 	#inst.enable_event(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
 	#waitrsp = inst.wait_on_event(visa.constants.VI_EVENT_SERVICE_REQ, 5000)
 	#inst.discard_events(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
@@ -64,7 +64,7 @@ def test_srq():
 	assert (stb == 0x50),msg
 
 	assert (inst.read_stb() == 0x10), "SRQ set at second read!"
-	
+
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
 
@@ -110,14 +110,14 @@ def test_abort_in():
 	inst.timeout = 800
 	y = inst.read()
 	assert(y == "xxx\r\n")
-	
+
 def test_indicate():
 	# perform indicator pulse
 	usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
 	retv = inst.control_in(request_type_bitmap_field=0xA1, request_id=64, request_value=0x0000, index=usb_iface, length=0x0001)
 	assert((retv[1] == visa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
-	
-	
+
+
 def test_multi_read():
 	old_chunk_size = inst.chunk_size
 	longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10
@@ -129,7 +129,7 @@ def test_multi_read():
 	y = inst.read()
 	assert (x + "\r\n" == y)
 	#inst.chunk_size = old_chunk_size
-	
+
 def test_stall_ep0():
 	usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
 	inst.read_stb()
@@ -139,17 +139,25 @@ def test_stall_ep0():
 		assert false
 	except visa.VisaIOError:
 		pass
-	
+
 	assert (inst.read_stb() == 0)
 
+os = sys.platform
+if os == "linux" or os == "linux2":
+    rm = visa.ResourceManager("@py")
+elif os == "darwin":
+    ## Not tested
+    print("Mac not tested\n");
+    sys.exit()
+elif os == "win32":
+    rm = visa.ResourceManager("/c/Windows/system32/visa64.dll")
 
-rm = visa.ResourceManager("/c/Windows/system32/visa64.dll")
 reslist = rm.list_resources("USB?::?*::INSTR")
 print(reslist)
 
 if (len(reslist) == 0):
     sys.exit()
-	
+
 inst = rm.open_resource(reslist[0]);
 inst.timeout = 3000
 

From ed8f117dd10ecaee1b8169f0c4af5217e03a4951 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Mar 2021 16:52:07 +0700
Subject: [PATCH 10/72] explicitly add dcd source file without vendor/family

---
 .../device/net_lwip_webserver/src/usb_descriptors.c    |  1 -
 examples/rules.mk                                      |  3 +--
 hw/bsp/d5035_01/board.mk                               |  7 ++-----
 hw/bsp/da14695_dk_usb/board.mk                         |  9 +++------
 hw/bsp/da1469x_dk_pro/board.mk                         |  9 +++------
 hw/bsp/ea4088qs/board.mk                               |  5 +----
 hw/bsp/ea4357/board.mk                                 |  5 +----
 hw/bsp/fomu/family.mk                                  |  6 ++----
 hw/bsp/frdm_kl25z/board.mk                             |  5 +----
 hw/bsp/imxrt/family.mk                                 |  5 +----
 hw/bsp/lpc18/family.mk                                 |  5 +----
 hw/bsp/lpc55/family.mk                                 |  5 +----
 hw/bsp/lpcxpresso11u37/board.mk                        |  5 +----
 hw/bsp/lpcxpresso11u68/board.mk                        |  5 +----
 hw/bsp/lpcxpresso1347/board.mk                         |  5 +----
 hw/bsp/lpcxpresso1549/board.mk                         |  5 +----
 hw/bsp/lpcxpresso1769/board.mk                         |  5 +----
 hw/bsp/lpcxpresso51u68/board.mk                        |  5 +----
 hw/bsp/lpcxpresso54114/board.mk                        |  5 +----
 hw/bsp/mbed1768/board.mk                               |  5 +----
 hw/bsp/msp430/family.mk                                | 10 ++--------
 hw/bsp/ngx4330/board.mk                                |  5 +----
 hw/bsp/nrf/family.mk                                   |  5 +----
 hw/bsp/nutiny_nuc121s/board.mk                         |  5 +----
 hw/bsp/nutiny_nuc125s/board.mk                         |  7 ++-----
 hw/bsp/nutiny_nuc126v/board.mk                         |  5 +----
 hw/bsp/nutiny_sdk_nuc120/board.mk                      |  5 +----
 hw/bsp/nutiny_sdk_nuc505/board.mk                      |  5 +----
 hw/bsp/samd11/family.mk                                |  5 +----
 hw/bsp/samd21/family.mk                                |  5 +----
 hw/bsp/samd51/family.mk                                |  5 +----
 hw/bsp/same54xplainedpro/board.mk                      | 10 ++--------
 hw/bsp/same70_xplained/board.mk                        |  1 +
 hw/bsp/samg55xplained/board.mk                         |  5 +----
 hw/bsp/spresense/board.mk                              |  8 +++-----
 hw/bsp/stm32f070rbnucleo/board.mk                      |  5 +----
 hw/bsp/stm32f072disco/board.mk                         |  5 +----
 hw/bsp/stm32f103bluepill/board.mk                      |  5 +----
 hw/bsp/stm32f207nucleo/board.mk                        |  5 +----
 hw/bsp/stm32f303disco/board.mk                         |  5 +----
 hw/bsp/stm32f4/family.mk                               |  5 +----
 hw/bsp/stm32f7/family.mk                               |  5 +----
 hw/bsp/stm32h7/family.mk                               |  5 +----
 hw/bsp/stm32l0538disco/board.mk                        |  5 +----
 hw/bsp/stm32l476disco/board.mk                         |  5 +----
 hw/bsp/stm32l4r5nucleo/board.mk                        |  5 +----
 46 files changed, 56 insertions(+), 190 deletions(-)

diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index f1c0b478..1a77c39d 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -142,7 +142,6 @@ static uint8_t const ecm_configuration[] =
 // - Windows only works with RNDIS
 // - MacOS only works with CDC-ECM
 // - Linux will work on both
-// Note index is Num-1x
 static uint8_t const * const configuration_arr[2] =
 {
   [CONFIG_ID_RNDIS] = rndis_configuration,
diff --git a/examples/rules.mk b/examples/rules.mk
index a97eb566..7f0927a1 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -93,8 +93,7 @@ SRC_C += \
 	src/class/msc/msc_device.c \
 	src/class/net/net_device.c \
 	src/class/usbtmc/usbtmc_device.c \
-	src/class/vendor/vendor_device.c \
-	src/portable/$(VENDOR)/$(CHIP_FAMILY)/dcd_$(CHIP_FAMILY).c
+	src/class/vendor/vendor_device.c
 
 # TinyUSB stack include
 INC += $(TOP)/src
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
index dc364a70..b7556f0a 100644
--- a/hw/bsp/d5035_01/board.mk
+++ b/hw/bsp/d5035_01/board.mk
@@ -22,8 +22,9 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
 
 SRC_C += \
+  src/portable/microchip/samd/dcd_samd.c \
   hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \
-  hw/mcu/microchip/same51/gcc/system_same51.c \
+  hw/mcu/microchip/same51/gcc/system_same51.c
 
 ifdef SYSCALLS
 ifneq ($(SYSCALLS),0)
@@ -47,10 +48,6 @@ INC += \
 	$(TOP)/hw/mcu/microchip/same51/hri \
 	$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = microchip
-CHIP_FAMILY = samd
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
index 58f3947c..e969c79c 100644
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ b/hw/bsp/da14695_dk_usb/board.mk
@@ -16,7 +16,9 @@ MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
 
+# While this is for da1469x chip, there is chance that da1468x chip family will also work
 SRC_C += \
+	src/portable/dialog/da146xx/dcd_da146xx.c \
 	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
 	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
 	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
@@ -26,12 +28,7 @@ SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
 INC += \
 	$(TOP)/hw/bsp/$(BOARD) \
 	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include \
-
-# For TinyUSB port source
-VENDOR = dialog
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-CHIP_FAMILY = da146xx
+	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
index 5362498e..980fc422 100644
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ b/hw/bsp/da1469x_dk_pro/board.mk
@@ -16,7 +16,9 @@ MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
 
+# While this is for da1469x chip, there is chance that da1468x chip family will also work
 SRC_C += \
+	src/portable/dialog/da146xx/dcd_da146xx.c \
 	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
 	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
 	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
@@ -26,12 +28,7 @@ SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
 INC += \
 	$(TOP)/hw/bsp/$(BOARD) \
 	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include \
-
-# For TinyUSB port source
-VENDOR = dialog
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-CHIP_FAMILY = da146xx
+	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index 51e5babe..ff8bfd40 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -22,6 +22,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
 LD_FILE = hw/bsp/$(BOARD)/lpc4088.ld
 
 SRC_C += \
+	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -35,10 +36,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc17_40
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index 09c782ca..a553938c 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -21,6 +21,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
 
 SRC_C += \
+	src/portable/nxp/transdimension/dcd_transdimension.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
@@ -35,10 +36,6 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc \
 	$(TOP)/$(MCU_DIR)/inc/config_43xx
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = transdimension
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index f615216b..40cb5dd4 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -11,15 +11,13 @@ CROSS_COMPILE = riscv-none-embed-
 # All source paths should be relative to the top level.
 LD_FILE = $(FAMILY_PATH)/fomu.ld
 
+SRC_C += src/portable/valentyusb/eptri/dcd_eptri.c
+
 SRC_S += $(FAMILY_PATH)/crt0-vexriscv.S
 
 INC += \
 	$(TOP)/$(FAMILY_PATH)/include
 
-# For TinyUSB port source
-VENDOR = valentyusb
-CHIP_FAMILY = eptri
-
 # For freeRTOS port source
 FREERTOS_PORT = RISC-V
 
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 5ad4d205..f63b181a 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -16,6 +16,7 @@ MCU_DIR = hw/mcu/nxp/sdk/devices/MKL25Z4
 LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
 
 SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
 	$(MCU_DIR)/system_MKL25Z4.c \
 	$(MCU_DIR)/project_template/clock_config.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
@@ -31,10 +32,6 @@ INC += \
 
 SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = khci
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index c07e68d2..3aeac8e5 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -27,6 +27,7 @@ LDFLAGS += \
 	-Wl,--defsym,__stack_size__=0x800 \
 
 SRC_C += \
+	src/portable/nxp/transdimension/dcd_transdimension.c \
 	$(MCU_DIR)/system_$(MCU_VARIANT).c \
 	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
 	$(MCU_DIR)/project_template/clock_config.c \
@@ -44,10 +45,6 @@ INC += \
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = transdimension
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM7/r0p1
 
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 05ff27c3..f016f1a3 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -18,6 +18,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 
 SRC_C += \
+	src/portable/nxp/transdimension/dcd_transdimension.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
@@ -30,9 +31,5 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc \
 	$(TOP)/$(MCU_DIR)/inc/config_18xx
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = transdimension
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 8934cb42..557e3391 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -34,6 +34,7 @@ MCU_DIR = hw/mcu/nxp/sdk/devices/$(MCU_VARIANT)
 LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/system_$(MCU_CORE).c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_gpio.c \
@@ -54,9 +55,5 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index e1338c9a..1f4a4749 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -22,6 +22,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx
 LD_FILE = hw/bsp/$(BOARD)/lpc11u37.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc11xx.c \
 	$(MCU_DIR)/src/chip_11xx.c \
 	$(MCU_DIR)/src/clock_11xx.c \
@@ -33,10 +34,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
index e038a9cd..d750a7be 100644
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ b/hw/bsp/lpcxpresso11u68/board.mk
@@ -19,6 +19,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc11u6x/lpc_chip_11u6x
 LD_FILE = hw/bsp/$(BOARD)/lpc11u68.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc11u6x.c \
 	$(MCU_DIR)/src/chip_11u6x.c \
 	$(MCU_DIR)/src/clock_11u6x.c \
@@ -30,10 +31,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 277282b9..93e1c953 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -22,6 +22,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
 LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc13xx.c \
 	$(MCU_DIR)/src/chip_13xx.c \
 	$(MCU_DIR)/src/clock_13xx.c \
@@ -33,10 +34,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
 
diff --git a/hw/bsp/lpcxpresso1549/board.mk b/hw/bsp/lpcxpresso1549/board.mk
index 8d98379d..7daa2ab7 100644
--- a/hw/bsp/lpcxpresso1549/board.mk
+++ b/hw/bsp/lpcxpresso1549/board.mk
@@ -21,6 +21,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx
 LD_FILE = hw/bsp/$(BOARD)/lpc1549.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc15xx.c \
 	$(MCU_DIR)/src/chip_15xx.c \
 	$(MCU_DIR)/src/clock_15xx.c \
@@ -33,10 +34,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
 
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk
index 4b77ac0c..e67ba16f 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpcxpresso1769/board.mk
@@ -20,6 +20,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 LD_FILE = hw/bsp/$(BOARD)/lpc1769.ld
 
 SRC_C += \
+	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -32,10 +33,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc17_40
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
 
diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpcxpresso51u68/board.mk
index 57af215b..dedc0cc4 100644
--- a/hw/bsp/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpcxpresso51u68/board.mk
@@ -19,6 +19,7 @@ MCU_DIR = hw/mcu/nxp/sdk/devices/LPC51U68
 LD_FILE = $(MCU_DIR)/gcc/LPC51U68_flash.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/system_LPC51U68.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_gpio.c \
@@ -34,10 +35,6 @@ SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/lpcxpresso54114/board.mk b/hw/bsp/lpcxpresso54114/board.mk
index 431ad912..eea6f0c5 100644
--- a/hw/bsp/lpcxpresso54114/board.mk
+++ b/hw/bsp/lpcxpresso54114/board.mk
@@ -21,6 +21,7 @@ MCU_DIR = hw/mcu/nxp/sdk/devices/LPC54114
 LD_FILE = $(MCU_DIR)/gcc/LPC54114J256_cm4_flash.ld
 
 SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/system_LPC54114_cm4.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_gpio.c \
@@ -36,10 +37,6 @@ SRC_S += $(MCU_DIR)/gcc/startup_LPC54114_cm4.S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_cm4_hardabi.a
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc_ip3511
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
index 2b934aa1..eb6c8647 100644
--- a/hw/bsp/mbed1768/board.mk
+++ b/hw/bsp/mbed1768/board.mk
@@ -20,6 +20,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 LD_FILE = hw/bsp/$(BOARD)/lpc1768.ld
 
 SRC_C += \
+	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -32,10 +33,6 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = lpc17_40
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
 
diff --git a/hw/bsp/msp430/family.mk b/hw/bsp/msp430/family.mk
index 53ebca1c..913f48cf 100644
--- a/hw/bsp/msp430/family.mk
+++ b/hw/bsp/msp430/family.mk
@@ -8,23 +8,17 @@ CFLAGS += \
 	-DCFG_EXAMPLE_MSC_READONLY \
 	-DCFG_TUD_ENDPOINT0_SIZE=8
 
-#-mmcu=msp430f5529
-
-
-
 # All source paths should be relative to the top level.
 LD_FILE = hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld
 LDINC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include
 LDFLAGS += $(addprefix -L,$(LDINC))
 
+SRC_C += src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+
 INC += \
 	$(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include \
 	$(TOP)/$(BOARD_PATH)
 
-# For TinyUSB port source
-VENDOR = ti
-CHIP_FAMILY = msp430x5xx
-
 # export for libmsp430.so to same installation
 ifneq ($(OS),Windows_NT)
 export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher))
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index c78d4c02..6dbec1ee 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -21,6 +21,7 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
 
 SRC_C += \
+	src/portable/nxp/transdimension/dcd_transdimension.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
@@ -33,10 +34,6 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc \
 	$(TOP)/$(MCU_DIR)/inc/config_43xx
 
-# For TinyUSB port source
-VENDOR = nxp
-CHIP_FAMILY = transdimension
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 8756ad9a..8f55fd71 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -34,6 +34,7 @@ LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
 LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
 
 SRC_C += \
+	src/portable/nordic/nrf5x/dcd_nrf5x.c \
   hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
   hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c \
   hw/mcu/nordic/nrfx/mdk/system_$(MCU_VARIANT).c
@@ -52,10 +53,6 @@ SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
 
 ASFLAGS += -D__HEAP_SIZE=0
 
-# For TinyUSB port source
-VENDOR = nordic
-CHIP_FAMILY = nrf5x
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index 68688be7..d94af609 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -14,6 +14,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
 
 SRC_C += \
+	src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \
@@ -42,10 +43,6 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/StdDriver/inc \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = nuvoton
-CHIP_FAMILY = nuc121
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index cb75f2ba..6bf10ef0 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -14,9 +14,10 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/nuc125_flash.ld
 
 SRC_C += \
+  src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \
-    hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c
+  hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
@@ -26,10 +27,6 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/StdDriver/inc \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = nuvoton
-CHIP_FAMILY = nuc121
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 5beb5f45..d1ccd46a 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -14,6 +14,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
 
 SRC_C += \
+  src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/system_NUC126.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/acmp.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/adc.c \
@@ -46,10 +47,6 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc126/StdDriver/inc \
   $(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = nuvoton
-CHIP_FAMILY = nuc121
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index affa6405..bfb71ffb 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -12,6 +12,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
 
 SRC_C += \
+  src/portable/nuvoton/nuc120/dcd_nuc120.c \
   hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/system_NUC100Series.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/acmp.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/adc.c \
@@ -42,10 +43,6 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc100_120/StdDriver/inc \
   $(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = nuvoton
-CHIP_FAMILY = nuc120
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index 8b2e53d4..51560a4e 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -13,6 +13,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/nuc505_flashtoram.ld
 
 SRC_C += \
+  src/portable/nuvoton/nuc505/dcd_nuc505.c \
   hw/mcu/nuvoton/nuc505/Device/Nuvoton/NUC505Series/Source/system_NUC505Series.c \
   hw/mcu/nuvoton/nuc505/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc505/StdDriver/src/clk.c \
@@ -37,10 +38,6 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc505/StdDriver/inc \
   $(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = nuvoton
-CHIP_FAMILY = nuc505
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index e0005d85..653eb706 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -12,6 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD11
 
 SRC_C += \
+	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
 	hw/mcu/microchip/samd11/gcc/system_samd11.c \
 	hw/mcu/microchip/samd11/hpl/gclk/hpl_gclk.c \
@@ -32,9 +33,5 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Include \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
 
-# For TinyUSB port source
-VENDOR = microchip
-CHIP_FAMILY = samd
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index e748796f..abd2393a 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -13,6 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
 SRC_C += \
+	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
 	hw/mcu/microchip/samd21/gcc/system_samd21.c \
 	hw/mcu/microchip/samd21/hpl/gclk/hpl_gclk.c \
@@ -32,10 +33,6 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd21/hri \
 	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
 
-# For TinyUSB port source 
-VENDOR = microchip
-CHIP_FAMILY = samd
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 2cf8f090..841708a7 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -16,6 +16,7 @@ CFLAGS += \
 CFLAGS += -Wno-error=undef
 
 SRC_C += \
+	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd51/gcc/gcc/startup_samd51.c \
 	hw/mcu/microchip/samd51/gcc/system_samd51.c \
 	hw/mcu/microchip/samd51/hpl/gclk/hpl_gclk.c \
@@ -35,10 +36,6 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd51/hri \
 	$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = microchip
-CHIP_FAMILY = samd
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 508ab20f..2ad4ada0 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -12,9 +12,7 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -D__SAME54P20A__ \
   -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-
-
+  -DCFG_TUSB_MCU=OPT_MCU_SAME5X
 
 #  -DSVC_Handler=SVCall_Handler
 
@@ -22,6 +20,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
 
 SRC_C += \
+	src/portable/microchip/samd/dcd_samd.c \
   hw/mcu/microchip/same54/gcc/gcc/startup_same54.c \
   hw/mcu/microchip/same54/gcc/system_same54.c \
   hw/mcu/microchip/same54/hal/utils/src/utils_syscalls.c
@@ -36,14 +35,9 @@ INC += \
 	$(TOP)/hw/mcu/microchip/same54/hri \
 	$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
 
-# For TinyUSB port source
-VENDOR = microchip
-CHIP_FAMILY = samd
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
-
 # For flash-jlink target
 JLINK_DEVICE = ATSAME54P20
 
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index fd9dc5cf..0b3f0387 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -19,6 +19,7 @@ ASF_DIR = hw/mcu/microchip/same70
 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
 
 SRC_C += \
+	src/portable/template/dcd_template.c \
 	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
 	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
 	$(ASF_DIR)/hpl/core/hpl_init.c \
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index 3a783d31..1a1a3ffe 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -20,6 +20,7 @@ ASF_DIR = hw/mcu/microchip/samg55
 LD_FILE = hw/bsp/$(BOARD)/samg55j19_flash.ld
 
 SRC_C += \
+	src/portable/microchip/samg/dcd_samg.c \
 	$(ASF_DIR)/samg55/gcc/gcc/startup_samg55.c \
 	$(ASF_DIR)/samg55/gcc/system_samg55.c \
 	$(ASF_DIR)/hpl/core/hpl_init.c \
@@ -40,10 +41,6 @@ INC += \
 	$(TOP)/$(ASF_DIR)/hri \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
-# For TinyUSB port source
-VENDOR = microchip
-CHIP_FAMILY = samg
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index c04296cf..37cb957c 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -39,6 +39,8 @@ CFLAGS += -Wno-error=shadow
 
 SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
 
+SRC_C += src/portable/sony/cxd56/dcd_cxd56.c
+
 INC += \
 	$(SPRESENSE_SDK)/nuttx/include \
 	$(SPRESENSE_SDK)/nuttx/arch \
@@ -57,11 +59,7 @@ LDFLAGS += \
 	-nostartfiles \
 	-nodefaultlibs \
 	-Wl,--gc-sections \
-	-u spresense_main \
-
-# For TinyUSB port source
-VENDOR = sony
-CHIP_FAMILY = cxd56
+	-u spresense_main
 
 $(MKSPK): $(BUILD)/$(PROJECT).elf
 	$(MAKE) -C $(TOP)/hw/mcu/sony/cxd56/mkspk
diff --git a/hw/bsp/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f070rbnucleo/board.mk
index 0cf28b79..1478b282 100644
--- a/hw/bsp/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f070rbnucleo/board.mk
@@ -23,6 +23,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
 LD_FILE = hw/bsp/$(BOARD)/stm32F070rbtx_flash.ld
 
 SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -40,10 +41,6 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = stm32_fsdev
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/stm32f072disco/board.mk b/hw/bsp/stm32f072disco/board.mk
index 81fb0df8..6f38f481 100644
--- a/hw/bsp/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f072disco/board.mk
@@ -22,6 +22,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
 LD_FILE = hw/bsp/$(BOARD)/STM32F072RBTx_FLASH.ld
 
 SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -39,10 +40,6 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = stm32_fsdev
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/stm32f103bluepill/board.mk b/hw/bsp/stm32f103bluepill/board.mk
index e1cf26e8..1e0b0f53 100644
--- a/hw/bsp/stm32f103bluepill/board.mk
+++ b/hw/bsp/stm32f103bluepill/board.mk
@@ -21,6 +21,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/STM32F103XB_FLASH.ld
 
 SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -37,10 +38,6 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = stm32_fsdev
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
 
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk
index 4be6e250..a01f35ad 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f207nucleo/board.mk
@@ -21,6 +21,7 @@ CFLAGS += -Wno-error=sign-compare
 LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
 
 SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -37,10 +38,6 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = synopsys
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
 
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f303disco/board.mk
index 304fa9c5..6cd67da0 100644
--- a/hw/bsp/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f303disco/board.mk
@@ -22,6 +22,7 @@ CFLAGS += -Wno-error=unused-parameter
 LD_FILE = hw/bsp/$(BOARD)/STM32F303VCTx_FLASH.ld
 
 SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -38,10 +39,6 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = stm32_fsdev
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 1bfb3815..f615efbb 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -21,6 +21,7 @@ CFLAGS += \
 CFLAGS += -Wno-error=cast-align
 
 SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -35,10 +36,6 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = synopsys
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index ed767085..aca99060 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -34,6 +34,7 @@ endif
 CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
 SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -49,9 +50,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = synopsys
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM7/r0p1
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 8e49604e..2c2b6d79 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -30,6 +30,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
 # All source paths should be relative to the top level.
 SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -45,10 +46,6 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = synopsys
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM7/r0p1
 
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index 5c1929ae..500674f8 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -22,6 +22,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized
 LD_FILE = hw/bsp/$(BOARD)/STM32L053C8Tx_FLASH.ld
 
 SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -38,10 +39,6 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = stm32_fsdev
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0
 
diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk
index fefcd643..921fa1ed 100644
--- a/hw/bsp/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l476disco/board.mk
@@ -22,6 +22,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld
 
 SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -41,10 +42,6 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = synopsys
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
diff --git a/hw/bsp/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4r5nucleo/board.mk
index f9fccf9b..f5bdde9a 100644
--- a/hw/bsp/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4r5nucleo/board.mk
@@ -23,6 +23,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 LD_FILE = hw/bsp/$(BOARD)/STM32L4RXxI_FLASH.ld
 
 SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -42,10 +43,6 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = st
-CHIP_FAMILY = synopsys
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 

From 2307fc302367e2b3a961be905bcb302394a155ca Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Mar 2021 17:09:25 +0700
Subject: [PATCH 11/72] move esp32s2 and rp2040 target rule to its family.mk

---
 examples/make.mk         |  2 +-
 examples/rules.mk        | 78 ++++++----------------------------------
 hw/bsp/esp32s2/family.mk | 36 +++++++++++++++++++
 hw/bsp/rp2040/family.mk  | 17 +++++++++
 4 files changed, 65 insertions(+), 68 deletions(-)
 create mode 100644 hw/bsp/esp32s2/family.mk

diff --git a/examples/make.mk b/examples/make.mk
index 53f633b1..e04a2592 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -40,7 +40,7 @@ ifeq ($(FAMILY),)
   include $(TOP)/hw/bsp/$(BOARD)/board.mk
 else
   # Include Family and Board specific defs
-  -include $(TOP)/$(FAMILY_PATH)/family.mk
+  include $(TOP)/$(FAMILY_PATH)/family.mk
 
   SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
 endif
diff --git a/examples/rules.mk b/examples/rules.mk
index 7f0927a1..9265bb68 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -5,69 +5,9 @@
 # Set all as default goal
 .DEFAULT_GOAL := all
 
-ifeq ($(FAMILY),esp32s2)
-# ---------------------------------------
-# Espressif IDF use CMake build system, this add wrapper target to call idf.py
-# ---------------------------------------
-
-.PHONY: all clean flash
-
-all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
-
-build: all
-
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
-fullclean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) fullclean
-
-flash:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) flash
-
-bootloader-flash:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) bootloader-flash
-
-app-flash:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) app-flash
-
-erase:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) erase_flash
-
-monitor:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) monitor
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-UF2_FAMILY_ID = 0xbfdd4eee
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
-	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
-else ifeq ($(FAMILY),rp2040)
-# ---------------------------------------
-# RP2040 CMake
-# ---------------------------------------
-
-ifeq ($(DEBUG), 1)
-CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
-endif
-
-$(BUILD):
-	cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
-
-all: $(BUILD)
-	$(MAKE) -C $(BUILD)
-
-clean:
-	$(RM) -rf $(BUILD)
-
-#flash: flash-pyocd
-flash:
-	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
-
-else
+# ESP32-S2 and RP2040 has its own CMake build system
+ifneq ($(FAMILY),esp32s2)
+ifneq ($(FAMILY),rp2040)
 # ---------------------------------------
 # GNU Make build system
 # ---------------------------------------
@@ -194,12 +134,12 @@ else
 	$(RM) -rf $(BUILD)
 endif
 
+endif
 endif # GNU Make
 
-# Print out the value of a make variable.
-# https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
-print-%:
-	@echo $* = $($*)
+# ---------------------------------------
+# Flash Targets
+# ---------------------------------------
 
 # Flash binary using Jlink
 ifeq ($(OS),Windows_NT)
@@ -244,3 +184,7 @@ copy-artifact: $(BIN)
 	#@$(CP) $(BUILD)/$(PROJECT).hex $(BIN)
 	#@$(CP) $(BUILD)/$(PROJECT).elf $(BIN)
 
+# Print out the value of a make variable.
+# https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
+print-%:
+	@echo $* = $($*)
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk
new file mode 100644
index 00000000..fd8481fd
--- /dev/null
+++ b/hw/bsp/esp32s2/family.mk
@@ -0,0 +1,36 @@
+#DEPS_SUBMODULES =
+
+.PHONY: all clean flash
+
+all:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
+
+build: all
+
+clean:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
+
+fullclean:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) fullclean
+
+flash:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) flash
+
+bootloader-flash:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) bootloader-flash
+
+app-flash:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) app-flash
+
+erase:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) erase_flash
+
+monitor:
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) monitor
+
+uf2: $(BUILD)/$(PROJECT).uf2
+
+UF2_FAMILY_ID = 0xbfdd4eee
+$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
+	@echo CREATE $@
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
index 2778183f..c953840b 100644
--- a/hw/bsp/rp2040/family.mk
+++ b/hw/bsp/rp2040/family.mk
@@ -1,4 +1,21 @@
 DEPS_SUBMODULES = hw/mcu/raspberrypi/pico-sdk
 
+ifeq ($(DEBUG), 1)
+CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
+endif
+
+$(BUILD):
+	cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
+
+all: $(BUILD)
+	$(MAKE) -C $(BUILD)
+
+clean:
+	$(RM) -rf $(BUILD)
+
+#flash: flash-pyocd
+flash:
+	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
+
 JLINK_DEVICE = rp2040_m0_0
 PYOCD_TARGET = rp2040

From ec08dcf61a86686da101f480565c6fae2acc3359 Mon Sep 17 00:00:00 2001
From: Jeremiah McCarthy <jeremiahmccarthy@xmos.com>
Date: Wed, 17 Mar 2021 09:25:01 -0400
Subject: [PATCH 12/72] Implement requested changes for PR724

---
 src/class/usbtmc/usbtmc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 6c9b4244..d5f8fe41 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -145,7 +145,7 @@ typedef struct
   usbtmc_capabilities_specific_t const * capabilities;
 } usbtmc_interface_state_t;
 
-static usbtmc_interface_state_t usbtmc_state =
+CFG_TUSB_MEM_SECTION static usbtmc_interface_state_t usbtmc_state =
 {
     .itf_id = 0xFF,
 };

From e7e03db9f863b1425c9ad60571a59986e40835bd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Mar 2021 20:27:32 +0700
Subject: [PATCH 13/72] update issue template

---
 .github/ISSUE_TEMPLATE/bug_report.md      | 19 ++++++++++---------
 .github/ISSUE_TEMPLATE/feature_request.md |  2 +-
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
index 9f956f9d..1e1ffb7c 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -1,5 +1,5 @@
 ---
-name: Bug report
+name: Bug Report
 about: Create a report to help us improve
 title: ''
 labels: Bug 🐞
@@ -7,16 +7,17 @@ assignees: ''
 
 ---
 
-**Set up**
-[Mandatory] Provide details of your setup help us to reproduce the issue as quick as possible  
- - **PC OS**   : Ubuntu 18.04 / Windows 10/ macOS 10.15 
- - **Board**   : Feather nRF52840 Express
- - **Firmware**: examples/device/cdc_msc
+Please provide details for all required fields, otherwise issue could be CLOSED and/or LOCKED.
 
-**Describe the bug**
+**Set Up (required)**
+- **PC OS** e.g Ubuntu 20.04 / Windows 10/ macOS 10.15
+- **Board** e.g Feather nRF52840 Express (if custom specify your MCUs)
+- **Firmware** e.g examples/device/cdc_msc
+
+**Describe The Bug (required)**
 A clear and concise description of what the bug is.
 
-**To reproduce**
+**To Reproduce (required)**
 Steps to reproduce the behavior:
 1. Go to '...'
 2. Click on '....'
@@ -26,4 +27,4 @@ Steps to reproduce the behavior:
 If applicable, add screenshots, bus capture to help explain your problem. 
 
 **Log**
-Please provide the stack's log (uart/rtt/swo) where the issue occurred, best with comments to explain the actual events. To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
+If applicable, provide the stack's log (uart/rtt/swo) where the issue occurred, best with comments to explain the actual events. To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md
index 9842a229..562d3113 100644
--- a/.github/ISSUE_TEMPLATE/feature_request.md
+++ b/.github/ISSUE_TEMPLATE/feature_request.md
@@ -1,5 +1,5 @@
 ---
-name: Feature request
+name: Feature Request
 about: Suggest an idea for this project
 title: ''
 labels: Feature 💡

From b221cedf80fadc4e810cca9408d91b12cf583e7e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Mar 2021 21:36:52 +0700
Subject: [PATCH 14/72] spaces

---
 hw/bsp/nrf/family.mk              | 2 +-
 hw/bsp/nutiny_nuc121s/board.mk    | 2 +-
 hw/bsp/same54xplainedpro/board.mk | 2 +-
 hw/bsp/stm32f4/family.mk          | 2 +-
 hw/bsp/stm32f7/family.mk          | 2 +-
 hw/bsp/stm32h7/family.mk          | 2 +-
 hw/bsp/stm32l476disco/board.mk    | 2 +-
 hw/bsp/stm32l4r5nucleo/board.mk   | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 8f55fd71..90144f96 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -34,7 +34,7 @@ LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
 LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
 
 SRC_C += \
-	src/portable/nordic/nrf5x/dcd_nrf5x.c \
+  src/portable/nordic/nrf5x/dcd_nrf5x.c \
   hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
   hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c \
   hw/mcu/nordic/nrfx/mdk/system_$(MCU_VARIANT).c
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index d94af609..c3fb1be9 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -14,7 +14,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
 
 SRC_C += \
-	src/portable/nuvoton/nuc121/dcd_nuc121.c \
+  src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 2ad4ada0..f43a5fde 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -20,7 +20,7 @@ CFLAGS += \
 LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
 
 SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
+  src/portable/microchip/samd/dcd_samd.c \
   hw/mcu/microchip/same54/gcc/gcc/startup_same54.c \
   hw/mcu/microchip/same54/gcc/system_same54.c \
   hw/mcu/microchip/same54/hal/utils/src/utils_syscalls.c
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index f615efbb..bf0bfadf 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -21,7 +21,7 @@ CFLAGS += \
 CFLAGS += -Wno-error=cast-align
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index aca99060..be0bd2a6 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -34,7 +34,7 @@ endif
 CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 2c2b6d79..da21ef6f 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -30,7 +30,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
 # All source paths should be relative to the top level.
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk
index 921fa1ed..414e3d4f 100644
--- a/hw/bsp/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l476disco/board.mk
@@ -22,7 +22,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4r5nucleo/board.mk
index f5bdde9a..d6808182 100644
--- a/hw/bsp/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4r5nucleo/board.mk
@@ -23,7 +23,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 LD_FILE = hw/bsp/$(BOARD)/STM32L4RXxI_FLASH.ld
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/synopsys/dcd_synopsys.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \

From 161b8587bd435ae2dc6f0aafac41019a09580b80 Mon Sep 17 00:00:00 2001
From: Jeremiah McCarthy <jeremiahmccarthy@xmos.com>
Date: Wed, 17 Mar 2021 14:24:14 -0400
Subject: [PATCH 15/72] Revert "Add Linux support to tmc example"

This reverts commit dc2f00cca157dc2279f917f59f9607fcd17b3fdb.
---
 examples/device/usbtmc/visaQuery.py | 38 ++++++++++++-----------------
 1 file changed, 15 insertions(+), 23 deletions(-)

diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
index 3f46b98e..b5bf8d48 100644
--- a/examples/device/usbtmc/visaQuery.py
+++ b/examples/device/usbtmc/visaQuery.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-import pyvisa as visa
+import visa
 import time
 import sys
 
@@ -36,8 +36,8 @@ def test_trig():
 	time.sleep(0.3) # SRQ may have some delay
 	assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds"
 	assert (inst.read_stb() == 0)
-
-
+	
+	
 def test_mav():
 	inst.write("delay 50")
 	inst.read_stb() # clear STB
@@ -45,15 +45,15 @@ def test_mav():
 	inst.write("123")
 	time.sleep(0.3)
 	assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds"
-
+	
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
-
-
+	
+	
 def test_srq():
 	assert (inst.read_stb() == 0)
 	inst.write("123")
-
+	
 	#inst.enable_event(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
 	#waitrsp = inst.wait_on_event(visa.constants.VI_EVENT_SERVICE_REQ, 5000)
 	#inst.discard_events(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
@@ -64,7 +64,7 @@ def test_srq():
 	assert (stb == 0x50),msg
 
 	assert (inst.read_stb() == 0x10), "SRQ set at second read!"
-
+	
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
 
@@ -110,14 +110,14 @@ def test_abort_in():
 	inst.timeout = 800
 	y = inst.read()
 	assert(y == "xxx\r\n")
-
+	
 def test_indicate():
 	# perform indicator pulse
 	usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
 	retv = inst.control_in(request_type_bitmap_field=0xA1, request_id=64, request_value=0x0000, index=usb_iface, length=0x0001)
 	assert((retv[1] == visa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
-
-
+	
+	
 def test_multi_read():
 	old_chunk_size = inst.chunk_size
 	longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10
@@ -129,7 +129,7 @@ def test_multi_read():
 	y = inst.read()
 	assert (x + "\r\n" == y)
 	#inst.chunk_size = old_chunk_size
-
+	
 def test_stall_ep0():
 	usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
 	inst.read_stb()
@@ -139,25 +139,17 @@ def test_stall_ep0():
 		assert false
 	except visa.VisaIOError:
 		pass
-
+	
 	assert (inst.read_stb() == 0)
 
-os = sys.platform
-if os == "linux" or os == "linux2":
-    rm = visa.ResourceManager("@py")
-elif os == "darwin":
-    ## Not tested
-    print("Mac not tested\n");
-    sys.exit()
-elif os == "win32":
-    rm = visa.ResourceManager("/c/Windows/system32/visa64.dll")
 
+rm = visa.ResourceManager("/c/Windows/system32/visa64.dll")
 reslist = rm.list_resources("USB?::?*::INSTR")
 print(reslist)
 
 if (len(reslist) == 0):
     sys.exit()
-
+	
 inst = rm.open_resource(reslist[0]);
 inst.timeout = 3000
 

From 64f41dea62ee48452c4b353cb34ddbd57a8fffad Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 Mar 2021 15:07:07 +0700
Subject: [PATCH 16/72] fix race condition that could cause drop packet of Bulk
 OUT transfer

NRF_USBD->SIZE.EPOUT[epnum] only need to write once to enable
Bulk/Interrupt transfer. We only need to do it in dcd_edpt_open() and
dcd_edpt_clear_stall()
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 131 +++++++++++++-------------
 1 file changed, 66 insertions(+), 65 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index d9fe2b6a..6b8095a0 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -53,13 +53,11 @@ enum
 
 enum
 {
-  // Endpoint number is fixed (8) for ISOOUT and ISOIN.
-  EP_ISO_NUM = 8,
-  // CBI endpoints count
-  EP_COUNT = 8
+  EP_ISO_NUM   = 8, // Endpoint number is fixed (8) for ISOOUT and ISOIN
+  EP_CBI_COUNT = 8  // Control Bulk Interrupt endpoints count
 };
 
-// Transfer descriptor
+// Transfer Descriptor
 typedef struct
 {
   uint8_t* buffer;
@@ -67,9 +65,10 @@ typedef struct
   volatile uint16_t actual_len;
   uint16_t  mps; // max packet size
 
-  // nrf52840 will auto ACK OUT packet after DMA is done
+  // nRF will auto accept OUT packet after DMA is done
   // indicate packet is already ACK
   volatile bool data_received;
+
   // Set to true when data was transferred from RAM to ISO IN output buffer.
   // New data can be put in ISO IN output buffer after SOF.
   bool iso_in_transfer_ready;
@@ -81,7 +80,7 @@ static struct
 {
   // All 8 endpoints including control IN & OUT (offset 1)
   // +1 for ISO endpoints
-  xfer_td_t xfer[EP_COUNT + 1][2];
+  xfer_td_t xfer[EP_CBI_COUNT + 1][2];
 
   // Number of pending DMA that is started but not handled yet by dcd_int_handler().
   // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1.
@@ -133,7 +132,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
         {
           ended = NRF_USBD->EVENTS_ENDISOIN + NRF_USBD->EVENTS_ENDISOOUT;
 
-          for (uint8_t i=0; i<EP_COUNT; i++)
+          for (uint8_t i=0; i<EP_CBI_COUNT; i++)
           {
             ended += NRF_USBD->EVENTS_ENDEPIN[i] + NRF_USBD->EVENTS_ENDEPOUT[i];
           }
@@ -166,27 +165,6 @@ static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir)
   return &_dcd.xfer[epnum][dir];
 }
 
-/*------------- CBI OUT Transfer -------------*/
-
-// Prepare for a CBI transaction OUT, call at the start
-// Allow ACK incoming data
-static void xact_out_prepare(uint8_t epnum)
-{
-  if ( epnum == 0 )
-  {
-    NRF_USBD->TASKS_EP0RCVOUT = 1;
-  }
-  else
-  {
-    // Write zero value to SIZE register will allow hw to ACK (accept data)
-    // If it is not already done by DMA
-    // SIZE.ISOOUT can also be accessed this way
-    NRF_USBD->SIZE.EPOUT[epnum] = 0;
-  }
-
-  __ISB(); __DSB();
-}
-
 // Start DMA to move data from Endpoint -> RAM
 static void xact_out_dma(uint8_t epnum)
 {
@@ -217,15 +195,14 @@ static void xact_out_dma(uint8_t epnum)
 
     edpt_dma_start(&NRF_USBD->TASKS_STARTEPOUT[epnum]);
   }
+
   xfer->buffer     += xact_len;
   xfer->actual_len += xact_len;
 }
 
-/*------------- CBI IN Transfer -------------*/
-
 // Prepare for a CBI transaction IN, call at the start
 // it start DMA to transfer data from RAM -> Endpoint
-static void xact_in_prepare(uint8_t epnum)
+static void xact_in_dma(uint8_t epnum)
 {
   xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
 
@@ -327,6 +304,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     {
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + epnum);
       NRF_USBD->EPOUTEN |= TU_BIT(epnum);
+
+      // Write any value to SIZE register will allow nRF to ACK/accept data
+      NRF_USBD->SIZE.EPOUT[epnum] = 0;
     }else
     {
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
@@ -438,20 +418,31 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   }
   else if ( dir == TUSB_DIR_OUT )
   {
-    if ( xfer->data_received )
+    if ( epnum == 0 )
     {
-      // nrf52840 auto ACK OUT packet after DMA is done
-      // Data already received previously --> trigger DMA to copy to SRAM
-      xact_out_dma(epnum);
-    }
-    else
+      // Accept next Control Out packet
+      NRF_USBD->TASKS_EP0RCVOUT = 1;
+    }else
     {
-      xact_out_prepare(epnum);
+      if ( xfer->data_received )
+      {
+        // Data may already be received previously
+        xfer->data_received = false;
+
+        // start DMA to copy to SRAM
+        xact_out_dma(epnum);
+      }
+      else
+      {
+        // nRF auto accept next Bulk/Interrupt OUT packet
+        // nothing to do
+      }
     }
   }
   else
   {
-    xact_in_prepare(epnum);
+    // Start DMA to copy data from RAM -> Endpoint
+    xact_in_dma(epnum);
   }
 
   return true;
@@ -477,6 +468,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   if ( epnum != 0 && epnum != EP_ISO_NUM )
   {
@@ -486,6 +478,10 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
     // reset data toggle to DATA0
     NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
 
+    // Write any value to SIZE register will allow nRF to ACK/accept data
+    // Drop any pending data
+    if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0;
+
     __ISB(); __DSB();
   }
 }
@@ -594,17 +590,18 @@ void dcd_int_handler(uint8_t rhport)
   // Setup tokens are specific to the Control endpoint.
   if ( int_status & USBD_INTEN_EP0SETUP_Msk )
   {
-    uint8_t const setup[8] = {
-        NRF_USBD->BMREQUESTTYPE , NRF_USBD->BREQUEST, NRF_USBD->WVALUEL , NRF_USBD->WVALUEH,
-        NRF_USBD->WINDEXL       , NRF_USBD->WINDEXH , NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
+    uint8_t const setup[8] =
+    {
+      NRF_USBD->BMREQUESTTYPE , NRF_USBD->BREQUEST, NRF_USBD->WVALUEL , NRF_USBD->WVALUEH,
+      NRF_USBD->WINDEXL       , NRF_USBD->WINDEXH , NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
     };
 
     // nrf5x hw auto handle set address, there is no need to inform usb stack
     tusb_control_request_t const * request = (tusb_control_request_t const *) setup;
 
-    if ( !(TUSB_REQ_RCPT_DEVICE == request->bmRequestType_bit.recipient &&
+    if ( !(TUSB_REQ_RCPT_DEVICE   == request->bmRequestType_bit.recipient &&
            TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
-           TUSB_REQ_SET_ADDRESS == request->bRequest) )
+           TUSB_REQ_SET_ADDRESS   == request->bRequest) )
     {
       dcd_event_setup_received(0, setup, true);
     }
@@ -620,15 +617,15 @@ void dcd_int_handler(uint8_t rhport)
    * For CBI OUT:
    *  - Host -> Endpoint
    *      EPDATA (or EP0DATADONE) interrupted, check EPDATASTATUS.EPOUT[i]
-   *      to start DMA. This step can occur automatically (without sw),
-   *      which means data may or may not ready (data_received flag).
+   *      to start DMA. For Bulk/Interrupt, this step can occur automatically (without sw),
+   *      which means data may or may not be ready (data_received flag).
    *  - Endpoint -> RAM
    *      ENDEPOUT[i] interrupted, transaction complete, sw prepare next transaction
    *
    * For CBI IN:
    *  - RAM -> Endpoint
    *      ENDEPIN[i] interrupted indicate DMA is complete. HW will start
-   *      to move daat to host
+   *      to move data to host
    *  - Endpoint -> Host
    *      EPDATA (or EP0DATADONE) interrupted, check EPDATASTATUS.EPIN[i].
    *      Transaction is complete, sw prepare next transaction
@@ -640,27 +637,31 @@ void dcd_int_handler(uint8_t rhport)
 
   /* CBI OUT: Endpoint -> SRAM (aka transaction complete)
    * Note: Since nRF controller auto ACK next packet without SW awareness
-   * We must handle this stage before Host -> Endpoint just in case
-   * 2 event happens at once
-   * ISO OUT: Transaction must fit in single packed, it can be shorter then total
+   * We must handle this stage before Host -> Endpoint just in case 2 event happens at once
+   *
+   * ISO OUT: Transaction must fit in single packet, it can be shorter then total
    * len if Host decides to sent fewer bytes, it this case transaction is also
    * complete and next transfer is not initiated here like for CBI.
    */
-  for(uint8_t epnum=0; epnum<EP_COUNT+1; epnum++)
+  for(uint8_t epnum=0; epnum<EP_CBI_COUNT+1; epnum++)
   {
     if ( tu_bit_test(int_status, USBD_INTEN_ENDEPOUT0_Pos+epnum))
     {
       xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
       uint8_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT;
 
-      // Data in endpoint has been consumed
-      xfer->data_received = false;
-
       // Transfer complete if transaction len < Max Packet Size or total len is transferred
       if ( (epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len) )
       {
-        // Prepare for next transaction
-        xact_out_prepare(epnum);
+        if ( epnum == 0 )
+        {
+          // Accept next Control Out packet
+          NRF_USBD->TASKS_EP0RCVOUT = 1;
+        }else
+        {
+          // nRF auto accept next Bulk/Interrupt OUT packet
+          // nothing to do
+        }
       }else
       {
         xfer->total_len = xfer->actual_len;
@@ -673,7 +674,7 @@ void dcd_int_handler(uint8_t rhport)
     // Ended event for CBI IN : nothing to do
   }
 
-  // Endpoint <-> Host
+  // Endpoint <-> Host ( In & OUT )
   if ( int_status & (USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0DATADONE_Msk) )
   {
     uint32_t data_status = NRF_USBD->EPDATASTATUS;
@@ -687,9 +688,9 @@ void dcd_int_handler(uint8_t rhport)
     bool const is_control_out = (int_status & USBD_INTEN_EP0DATADONE_Msk) && !(NRF_USBD->BMREQUESTTYPE & TUSB_DIR_IN_MASK);
 
     // CBI In: Endpoint -> Host (transaction complete)
-    for(uint8_t epnum=0; epnum<8; epnum++)
+    for(uint8_t epnum=0; epnum<EP_CBI_COUNT; epnum++)
     {
-      if ( tu_bit_test(data_status, epnum ) || ( epnum == 0 && is_control_in) )
+      if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) )
       {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
 
@@ -697,8 +698,8 @@ void dcd_int_handler(uint8_t rhport)
 
         if ( xfer->actual_len < xfer->total_len )
         {
-          // prepare next transaction
-          xact_in_prepare(epnum);
+          // Start DMA to copy next data packet
+          xact_in_dma(epnum);
         } else
         {
           // CBI IN complete
@@ -708,9 +709,9 @@ void dcd_int_handler(uint8_t rhport)
     }
 
     // CBI OUT: Host -> Endpoint
-    for(uint8_t epnum=0; epnum<8; epnum++)
+    for(uint8_t epnum=0; epnum<EP_CBI_COUNT; epnum++)
     {
-      if ( tu_bit_test(data_status, 16+epnum ) || ( epnum == 0 && is_control_out) )
+      if ( tu_bit_test(data_status, 16+epnum) || (epnum == 0 && is_control_out) )
       {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
 
@@ -719,7 +720,7 @@ void dcd_int_handler(uint8_t rhport)
           xact_out_dma(epnum);
         }else
         {
-          // Data overflow !!! Nah, nrf52840 will auto ACK OUT packet after DMA is done
+          // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet
           // Mark this endpoint with data received
           xfer->data_received = true;
         }

From 2882390c82fc08a669093419abc69f25bc11a34f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 Mar 2021 15:23:08 +0700
Subject: [PATCH 17/72] clean up some examples

---
 examples/device/cdc_dual_ports/src/main.c     |  6 ++--
 .../device/cdc_dual_ports/src/tusb_config.h   |  2 ++
 examples/device/cdc_msc/src/main.c            | 28 +++++++++----------
 examples/device/cdc_msc/src/tusb_config.h     |  3 ++
 examples/device/cdc_msc_freertos/src/main.c   | 22 +++++++--------
 .../device/cdc_msc_freertos/src/tusb_config.h |  3 ++
 6 files changed, 34 insertions(+), 30 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 198c4252..34cd29ed 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -63,13 +63,11 @@ static void echo_serial_port(uint8_t itf, uint8_t buf[], uint32_t count)
     }
     else
     {
-      // echo back additional ports as upper case
+      // echo back 2nd port as upper case
       if (islower(buf[i])) buf[i] -= 'a' - 'A';
     }
 
     tud_cdc_n_write_char(itf, buf[i]);
-
-    if ( buf[i] == '\r' ) tud_cdc_n_write_char(itf, '\n');
   }
   tud_cdc_n_write_flush(itf);
 }
@@ -85,7 +83,7 @@ static void cdc_task(void)
   {
     // connected() check for DTR bit
     // Most but not all terminal client set this when making connection
-    if ( tud_cdc_n_connected(itf) )
+    // if ( tud_cdc_n_connected(itf) )
     {
       if ( tud_cdc_n_available(itf) )
       {
diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index 69001bde..7db520dd 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -104,6 +104,8 @@
 #define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index a20a80fc..131ae654 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -48,7 +48,6 @@ enum  {
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
 void led_blinking_task(void);
-
 void cdc_task(void);
 
 /*------------- MAIN -------------*/
@@ -112,18 +111,16 @@ void cdc_task(void)
     // connected and there are data available
     if ( tud_cdc_available() )
     {
-      uint8_t buf[64];
-
-      // read and echo back
+      // read datas
+      char buf[64];
       uint32_t count = tud_cdc_read(buf, sizeof(buf));
+      (void) count;
 
-      for(uint32_t i=0; i<count; i++)
-      {
-        tud_cdc_write_char(buf[i]);
-
-        if ( buf[i] == '\r' ) tud_cdc_write_char('\n');
-      }
-
+      // Echo back
+      // Note: Skip echo by commenting out write() and write_flush()
+      // for throughput test e.g
+      //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
+      tud_cdc_write(buf, count);
       tud_cdc_write_flush();
     }
   }
@@ -135,12 +132,13 @@ void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
   (void) itf;
   (void) rts;
 
-  // connected
+  // TODO set some indicator
   if ( dtr )
   {
-    // print initial message when connected
-    tud_cdc_write_str("\r\nTinyUSB CDC MSC device example\r\n");
-    tud_cdc_write_flush();
+    // Terminal connected
+  }else
+  {
+    // Terminal disconnected
   }
 }
 
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index e0099785..9a0262d3 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -106,6 +106,9 @@
 #define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
 // MSC Buffer size of Device Mass storage
 #define CFG_TUD_MSC_EP_BUFSIZE   512
 
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index e90c3f0d..5779b7d4 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -179,14 +179,13 @@ void cdc_task(void* params)
 
         // read and echo back
         uint32_t count = tud_cdc_read(buf, sizeof(buf));
+        (void) count;
 
-        for(uint32_t i=0; i<count; i++)
-        {
-          tud_cdc_write_char(buf[i]);
-
-          if ( buf[i] == '\r' ) tud_cdc_write_char('\n');
-        }
-
+        // Echo back
+        // Note: Skip echo by commenting out write() and write_flush()
+        // for throughput test e.g
+        //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
+        tud_cdc_write(buf, count);
         tud_cdc_write_flush();
       }
     }
@@ -202,12 +201,13 @@ void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
   (void) itf;
   (void) rts;
 
-  // connected
+  // TODO set some indicator
   if ( dtr )
   {
-    // print initial message when connected
-    tud_cdc_write_str("\r\nTinyUSB CDC MSC device with FreeRTOS example\r\n");
-    tud_cdc_write_flush();
+    // Terminal connected
+  }else
+  {
+    // Terminal disconnected
   }
 }
 
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index fe4845a0..ff543834 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -106,6 +106,9 @@
 #define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
 // MSC Buffer size of Device Mass storage
 #define CFG_TUD_MSC_EP_BUFSIZE   512
 

From 253430a76585f529340e480397e07de567370b5f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 Mar 2021 16:28:44 +0700
Subject: [PATCH 18/72] add example specific DEPS_SUBMODULES

---
 examples/device/cdc_msc_freertos/Makefile       | 2 ++
 examples/device/hid_composite_freertos/Makefile | 2 ++
 examples/device/net_lwip_webserver/Makefile     | 2 ++
 hw/bsp/d5035_01/board.mk                        | 2 +-
 hw/bsp/ea4088qs/board.mk                        | 2 +-
 hw/bsp/ea4357/board.mk                          | 2 +-
 hw/bsp/esp32s2/family.mk                        | 2 +-
 hw/bsp/frdm_kl25z/board.mk                      | 2 +-
 hw/bsp/imxrt/family.mk                          | 2 +-
 hw/bsp/lpc18/family.mk                          | 2 +-
 hw/bsp/lpc55/family.mk                          | 2 +-
 hw/bsp/lpcxpresso11u37/board.mk                 | 2 +-
 hw/bsp/lpcxpresso11u68/board.mk                 | 2 +-
 hw/bsp/lpcxpresso1347/board.mk                  | 2 +-
 hw/bsp/lpcxpresso1549/board.mk                  | 2 +-
 hw/bsp/lpcxpresso1769/board.mk                  | 2 +-
 hw/bsp/lpcxpresso51u68/board.mk                 | 2 +-
 hw/bsp/lpcxpresso54114/board.mk                 | 2 +-
 hw/bsp/mbed1768/board.mk                        | 2 +-
 hw/bsp/msp430/family.mk                         | 2 +-
 hw/bsp/ngx4330/board.mk                         | 2 +-
 hw/bsp/nrf/family.mk                            | 2 +-
 hw/bsp/nutiny_nuc121s/board.mk                  | 2 +-
 hw/bsp/nutiny_nuc125s/board.mk                  | 2 +-
 hw/bsp/nutiny_nuc126v/board.mk                  | 2 +-
 hw/bsp/nutiny_sdk_nuc120/board.mk               | 2 +-
 hw/bsp/nutiny_sdk_nuc505/board.mk               | 2 +-
 hw/bsp/rp2040/family.mk                         | 2 +-
 hw/bsp/samd11/family.mk                         | 2 +-
 hw/bsp/samd21/family.mk                         | 2 +-
 hw/bsp/samd51/family.mk                         | 2 +-
 hw/bsp/same54xplainedpro/board.mk               | 2 +-
 hw/bsp/same70_xplained/board.mk                 | 2 +-
 hw/bsp/samg55xplained/board.mk                  | 2 +-
 hw/bsp/spresense/board.mk                       | 2 +-
 hw/bsp/stm32f070rbnucleo/board.mk               | 2 +-
 hw/bsp/stm32f072disco/board.mk                  | 2 +-
 hw/bsp/stm32f103bluepill/board.mk               | 2 +-
 hw/bsp/stm32f207nucleo/board.mk                 | 2 +-
 hw/bsp/stm32f303disco/board.mk                  | 2 +-
 hw/bsp/stm32f4/family.mk                        | 2 +-
 hw/bsp/stm32f7/family.mk                        | 2 +-
 hw/bsp/stm32h7/family.mk                        | 2 +-
 hw/bsp/stm32l0538disco/board.mk                 | 2 +-
 hw/bsp/stm32l476disco/board.mk                  | 2 +-
 hw/bsp/stm32l4r5nucleo/board.mk                 | 2 +-
 46 files changed, 49 insertions(+), 43 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 36174b5e..86bacd2d 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,3 +1,5 @@
+DEPS_SUBMODULES += lib/FreeRTOS-Kernel
+
 include ../../../tools/top.mk
 include ../../make.mk
 
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index db7dfd34..1c195959 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -1,3 +1,5 @@
+DEPS_SUBMODULES += lib/FreeRTOS-Kernel
+
 include ../../../tools/top.mk
 include ../../make.mk
 
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index fa93cf87..c3e0d889 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -1,3 +1,5 @@
+DEPS_SUBMODULES += lib/lwip
+
 include ../../../tools/top.mk
 include ../../make.mk
 
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
index b7556f0a..1d09bd3d 100644
--- a/hw/bsp/d5035_01/board.mk
+++ b/hw/bsp/d5035_01/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 HWREV ?= 1
 
 CFLAGS += \
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index ff8bfd40..05e730d2 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index a553938c..1ad97057 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk
index fd8481fd..8bd290eb 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/esp32s2/family.mk
@@ -1,4 +1,4 @@
-#DEPS_SUBMODULES =
+#DEPS_SUBMODULES +=
 
 .PHONY: all clean flash
 
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index f63b181a..1a4d718c 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -mthumb \
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 3aeac8e5..1b6d7e8d 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x4fb2d5bd
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index f016f1a3..0908e187 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 557e3391..c8874f57 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x2abc77ec
-DEPS_SUBMODULES = lib/sct_neopixel hw/mcu/nxp
+DEPS_SUBMODULES += lib/sct_neopixel hw/mcu/nxp
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index 1f4a4749..7fa42f9a 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
index d750a7be..b59506d4 100644
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ b/hw/bsp/lpcxpresso11u68/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 93e1c953..0f63cefb 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/lpcxpresso1549/board.mk b/hw/bsp/lpcxpresso1549/board.mk
index 7daa2ab7..f4d109ec 100644
--- a/hw/bsp/lpcxpresso1549/board.mk
+++ b/hw/bsp/lpcxpresso1549/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk
index e67ba16f..678c703d 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpcxpresso1769/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpcxpresso51u68/board.mk
index dedc0cc4..2582e98f 100644
--- a/hw/bsp/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpcxpresso51u68/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/lpcxpresso54114/board.mk b/hw/bsp/lpcxpresso54114/board.mk
index eea6f0c5..b6bc0761 100644
--- a/hw/bsp/lpcxpresso54114/board.mk
+++ b/hw/bsp/lpcxpresso54114/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
index eb6c8647..bd48b29b 100644
--- a/hw/bsp/mbed1768/board.mk
+++ b/hw/bsp/mbed1768/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/msp430/family.mk b/hw/bsp/msp430/family.mk
index 913f48cf..ceafa6ec 100644
--- a/hw/bsp/msp430/family.mk
+++ b/hw/bsp/msp430/family.mk
@@ -1,5 +1,5 @@
 CROSS_COMPILE = msp430-elf-
-DEPS_SUBMODULES = hw/mcu/ti
+DEPS_SUBMODULES += hw/mcu/ti
 SKIP_NANOLIB = 1
 
 CFLAGS += \
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 6dbec1ee..0a0cb3ba 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nxp
+DEPS_SUBMODULES += hw/mcu/nxp
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 90144f96..d1afd258 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0xADA52840
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/nordic/nrfx
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index c3fb1be9..a0a208ca 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nuvoton
+DEPS_SUBMODULES += hw/mcu/nuvoton
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index 6bf10ef0..bb56e42a 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nuvoton
+DEPS_SUBMODULES += hw/mcu/nuvoton
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index d1ccd46a..848b19f9 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nuvoton
+DEPS_SUBMODULES += hw/mcu/nuvoton
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index bfb71ffb..90b3e91f 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nuvoton
+DEPS_SUBMODULES += hw/mcu/nuvoton
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index 51560a4e..e8514347 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/nuvoton
+DEPS_SUBMODULES += hw/mcu/nuvoton
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
index c953840b..ed7b1156 100644
--- a/hw/bsp/rp2040/family.mk
+++ b/hw/bsp/rp2040/family.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/raspberrypi/pico-sdk
+DEPS_SUBMODULES += hw/mcu/raspberrypi/pico-sdk
 
 ifeq ($(DEBUG), 1)
 CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index 653eb706..6fbdc35a 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index abd2393a..f1b063f2 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 841708a7..f4e260fb 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x55114460
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index f43a5fde..7325a5ff 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 CONF_CPU_FREQUENCY ?= 120000000
 
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 0b3f0387..90ffbb70 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 CFLAGS += \
   -mthumb \
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index 1a1a3ffe..aed4de68 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index 37cb957c..a46c42bd 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES = hw/mcu/sony/cxd56/spresense-exported-sdk
+DEPS_SUBMODULES += hw/mcu/sony/cxd56/spresense-exported-sdk
 
 # Platforms are: Linux, Darwin, MSYS, CYGWIN
 PLATFORM := $(firstword $(subst _, ,$(shell uname -s 2>/dev/null)))
diff --git a/hw/bsp/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f070rbnucleo/board.mk
index 1478b282..78dd0a39 100644
--- a/hw/bsp/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f070rbnucleo/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = f0
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f072disco/board.mk b/hw/bsp/stm32f072disco/board.mk
index 6f38f481..071c42b6 100644
--- a/hw/bsp/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f072disco/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = f0
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f103bluepill/board.mk b/hw/bsp/stm32f103bluepill/board.mk
index 1e0b0f53..656a3732 100644
--- a/hw/bsp/stm32f103bluepill/board.mk
+++ b/hw/bsp/stm32f103bluepill/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = f1
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk
index a01f35ad..2b979f3d 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f207nucleo/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = f2
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f303disco/board.mk
index 6cd67da0..9dd27a85 100644
--- a/hw/bsp/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f303disco/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = f3
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index bf0bfadf..584d6940 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -1,6 +1,6 @@
 UF2_FAMILY_ID = 0x57755a57
 ST_FAMILY = f4
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index be0bd2a6..ead0c977 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -1,6 +1,6 @@
 UF2_FAMILY_ID = 0x53b80f00
 ST_FAMILY = f7
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index da21ef6f..e35e7561 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -1,6 +1,6 @@
 UF2_FAMILY_ID = 0x6db66082
 ST_FAMILY = h7
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index 500674f8..c46887f1 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = l0
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk
index 414e3d4f..28824efd 100644
--- a/hw/bsp/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l476disco/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = l4
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4r5nucleo/board.mk
index d6808182..12a291d0 100644
--- a/hw/bsp/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4r5nucleo/board.mk
@@ -1,5 +1,5 @@
 ST_FAMILY = l4
-DEPS_SUBMODULES = lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

From 249852d25ced9852eb7f95dcc38b2a82b4c02390 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 Mar 2021 19:53:39 +0700
Subject: [PATCH 19/72] use boot2_generic_03h for adafruit feather rp2040

- also use boot2_generic_03h for now for itsy bitsy and qt rp2040
- change default flash target for rp2040 to flash-pyocd
---
 examples/device/audio_test/CMakeLists.txt              |  3 ++-
 examples/device/board_test/CMakeLists.txt              |  4 +++-
 examples/device/cdc_dual_ports/CMakeLists.txt          |  3 ++-
 examples/device/cdc_msc/CMakeLists.txt                 |  3 +--
 examples/device/dfu_runtime/CMakeLists.txt             |  3 ++-
 examples/device/dynamic_configuration/CMakeLists.txt   |  3 ++-
 examples/device/hid_composite/CMakeLists.txt           |  3 ++-
 examples/device/hid_generic_inout/CMakeLists.txt       |  3 ++-
 examples/device/hid_multiple_interface/CMakeLists.txt  |  3 ++-
 examples/device/midi_test/CMakeLists.txt               |  3 ++-
 examples/device/msc_dual_lun/CMakeLists.txt            |  3 ++-
 examples/device/net_lwip_webserver/CMakeLists.txt      |  3 ++-
 examples/device/uac2_headset/CMakeLists.txt            |  3 ++-
 examples/device/usbtmc/CMakeLists.txt                  |  2 +-
 examples/device/webusb_serial/CMakeLists.txt           |  3 ++-
 examples/host/cdc_msc_hid/CMakeLists.txt               |  3 ++-
 .../rp2040/boards/adafruit_feather_rp2040/board.cmake  |  1 +
 .../boards/adafruit_itsybitsy_rp2040/board.cmake       |  1 +
 hw/bsp/rp2040/boards/adafruit_qt_rp2040/board.cmake    |  1 +
 hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake     |  1 +
 hw/bsp/rp2040/family.cmake                             |  6 ++++++
 hw/bsp/rp2040/family.mk                                | 10 +++++-----
 22 files changed, 46 insertions(+), 22 deletions(-)
 create mode 100644 hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
 create mode 100644 hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
 create mode 100644 hw/bsp/rp2040/boards/adafruit_qt_rp2040/board.cmake
 create mode 100644 hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake

diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index 7038dd04..03f2439e 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 4e6a9b3f..b4c4ce4d 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -9,15 +9,17 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "esp32s2")
   cmake_minimum_required(VERSION 3.5)
+
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
   project(${PROJECT})
 
 elseif(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index 5e3ec090..94e4fc1f 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 41dd167b..f6cf6452 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -17,9 +17,8 @@ elseif(FAMILY STREQUAL "rp2040")
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
-
+    
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
 
   # Example source
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index 5e3ec090..ea294b3b 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index be622436..09a8dcc4 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index 5e3ec090..c85f2ace 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index 5e3ec090..5de4a932 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index 5e3ec090..5de4a932 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index 5e3ec090..5de4a932 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 0036dc68..48e183ed 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index c9aabc63..69a242be 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index 5e3ec090..5de4a932 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index 808bdbcf..f40d123b 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -11,8 +11,8 @@ if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index 5e3ec090..5de4a932 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -9,10 +9,11 @@ get_filename_component(TOP "${TOP}" REALPATH)
 # Check for -DFAMILY=
 if(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 2302678b..7413e408 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -14,10 +14,11 @@ if(FAMILY STREQUAL "esp32s2")
 
 elseif(FAMILY STREQUAL "rp2040")
   cmake_minimum_required(VERSION 3.12)
+  
   set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
   include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
+  
   project(${PROJECT})
-  pico_sdk_init()
   add_executable(${PROJECT})
 
   include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
diff --git a/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake b/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
new file mode 100644
index 00000000..ea4070cf
--- /dev/null
+++ b/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
@@ -0,0 +1 @@
+set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_SDK_PATH}/src/rp2_common/boot_stage2/boot2_generic_03h.S")
diff --git a/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake b/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
new file mode 100644
index 00000000..ea4070cf
--- /dev/null
+++ b/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
@@ -0,0 +1 @@
+set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_SDK_PATH}/src/rp2_common/boot_stage2/boot2_generic_03h.S")
diff --git a/hw/bsp/rp2040/boards/adafruit_qt_rp2040/board.cmake b/hw/bsp/rp2040/boards/adafruit_qt_rp2040/board.cmake
new file mode 100644
index 00000000..ea4070cf
--- /dev/null
+++ b/hw/bsp/rp2040/boards/adafruit_qt_rp2040/board.cmake
@@ -0,0 +1 @@
+set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_SDK_PATH}/src/rp2_common/boot_stage2/boot2_generic_03h.S")
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
new file mode 100644
index 00000000..eb9f219d
--- /dev/null
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
@@ -0,0 +1 @@
+set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_SDK_PATH}/src/rp2_common/boot_stage2/boot2_w25q080.S")
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index af23c236..63c7daa3 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -1,3 +1,9 @@
+# Board specific define e.g boot stage2
+# PICO_DEFAULT_BOOT_STAGE2_FILE must be set before pico_sdk_init()
+include(${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake)
+
+pico_sdk_init()
+
 target_link_libraries(${PROJECT}
   pico_stdlib
   pico_bootsel_via_double_reset
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
index ed7b1156..6df36732 100644
--- a/hw/bsp/rp2040/family.mk
+++ b/hw/bsp/rp2040/family.mk
@@ -1,5 +1,8 @@
 DEPS_SUBMODULES += hw/mcu/raspberrypi/pico-sdk
 
+JLINK_DEVICE = rp2040_m0_0
+PYOCD_TARGET = rp2040
+
 ifeq ($(DEBUG), 1)
 CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
 endif
@@ -13,9 +16,6 @@ all: $(BUILD)
 clean:
 	$(RM) -rf $(BUILD)
 
-#flash: flash-pyocd
-flash:
+flash: flash-pyocd
+flash-uf2:
 	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
-
-JLINK_DEVICE = rp2040_m0_0
-PYOCD_TARGET = rp2040

From c86e4c8bd3bf6f23f12daee5584bdab8cd4f9ebc Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Thu, 18 Mar 2021 20:56:26 +0700
Subject: [PATCH 20/72] Update boards.md

---
 docs/boards.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/docs/boards.md b/docs/boards.md
index 27514311..2b42b4d8 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -9,6 +9,11 @@ The board support code is only used for self-contained examples and testing. It
 
 This code base already had supported for a handful of following boards (sorted alphabetically)
 
+### Dialog DA146xx
+
+- [DA14695 Development Kit – USB](https://www.dialog-semiconductor.com/products/da14695-development-kit-usb)
+- [DA1469x Development Kit – Pro](https://www.dialog-semiconductor.com/products/da14695-development-kit-pro)
+
 ### Espressif ESP32-S2
 
 - Adafruit Feather ESP32-S2
@@ -17,11 +22,6 @@ This code base already had supported for a handful of following boards (sorted a
 - [ESP32-S2-Kaluga-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html)
 - [ESP32-S2-Saola-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html)
 
-### Dialog DA146xx
-
-- [DA14695 Development Kit – USB](https://www.dialog-semiconductor.com/products/da14695-development-kit-usb)
-- [DA1469x Development Kit – Pro](https://www.dialog-semiconductor.com/products/da14695-development-kit-pro)
-
 ### MicroChip SAMD11 & SAMD21
 
 - [Adafruit Circuit Playground Express](https://www.adafruit.com/product/3333)

From 6cf110b5d0efc8556fbb7aeabef583d8c000ae4b Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 19 Mar 2021 00:32:29 +0700
Subject: [PATCH 21/72] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index d4a0b38c..f5bd7ced 100644
--- a/README.md
+++ b/README.md
@@ -30,8 +30,8 @@ Special thanks to all the people who spent their precious time and effort to hel
 
 The stack supports the following MCUs:
 
-- **Espressif:** ESP32-S2
 - **Dialog:** DA1469x
+- **Espressif:** ESP32-S2
 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55
 - **NordicSemi:** nRF52833, nRF52840
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505

From a22206b77a237c1f8407c13ce519f642c73feaea Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 19 Mar 2021 11:15:58 +0700
Subject: [PATCH 22/72] Update bug_report.md

---
 .github/ISSUE_TEMPLATE/bug_report.md | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
index 1e1ffb7c..e3a083ab 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -7,24 +7,29 @@ assignees: ''
 
 ---
 
-Please provide details for all required fields, otherwise issue could be CLOSED and/or LOCKED.
+REMOVE ME: please provide all details at least for Setup/Describe/Reproduce. 
+
+**Set Up**
 
-**Set Up (required)**
 - **PC OS** e.g Ubuntu 20.04 / Windows 10/ macOS 10.15
 - **Board** e.g Feather nRF52840 Express (if custom specify your MCUs)
 - **Firmware** e.g examples/device/cdc_msc
 
-**Describe The Bug (required)**
+**Describe The Bug**
+
 A clear and concise description of what the bug is.
 
-**To Reproduce (required)**
+**To Reproduce**
+
 Steps to reproduce the behavior:
 1. Go to '...'
 2. Click on '....'
 3. See error
 
 **Screenshots**
+
 If applicable, add screenshots, bus capture to help explain your problem. 
 
 **Log**
+
 If applicable, provide the stack's log (uart/rtt/swo) where the issue occurred, best with comments to explain the actual events. To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)

From 7cdeed54e0dbd6f927020042dbdedf2d4d21cf97 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 19 Mar 2021 11:17:38 +0700
Subject: [PATCH 23/72] Update bug_report.md

---
 .github/ISSUE_TEMPLATE/bug_report.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
index e3a083ab..797f6f92 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -1,14 +1,12 @@
 ---
 name: Bug Report
 about: Create a report to help us improve
-title: ''
+title: 'Please provide all details at least for Setup/Describe/Reproduce'
 labels: Bug 🐞
 assignees: ''
 
 ---
 
-REMOVE ME: please provide all details at least for Setup/Describe/Reproduce. 
-
 **Set Up**
 
 - **PC OS** e.g Ubuntu 20.04 / Windows 10/ macOS 10.15

From aa54135087b396c563c08a528a829f622e1a4fce Mon Sep 17 00:00:00 2001
From: Ned Konz <ned@bike-nomad.com>
Date: Fri, 19 Mar 2021 10:57:58 -0700
Subject: [PATCH 24/72] Initial commit; copied from stmf072-disco and modified
 for -EVAL board

---
 hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld | 177 +++++++++++
 hw/bsp/stm32f072eval/board.mk               |  50 +++
 hw/bsp/stm32f072eval/stm32f072eval.c        | 248 +++++++++++++++
 hw/bsp/stm32f072eval/stm32f0xx_hal_conf.h   | 321 ++++++++++++++++++++
 4 files changed, 796 insertions(+)
 create mode 100644 hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld
 create mode 100644 hw/bsp/stm32f072eval/board.mk
 create mode 100644 hw/bsp/stm32f072eval/stm32f072eval.c
 create mode 100644 hw/bsp/stm32f072eval/stm32f0xx_hal_conf.h

diff --git a/hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld b/hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld
new file mode 100644
index 00000000..581613a5
--- /dev/null
+++ b/hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld
@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file      LinkerScript.ld
+ * @author    Auto-generated by STM32CubeIDE
+ *  Abstract    : Linker script for STM32072B-EVAL Board embedding STM32F072VBTx Device from stm32f0 series
+ *                      128Kbytes FLASH
+ *                      16Kbytes RAM
+ *
+ *            Set heap size, stack size and stack location according
+ *            to application requirements.
+ *
+ *            Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 16K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 128K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32f072eval/board.mk b/hw/bsp/stm32f072eval/board.mk
new file mode 100644
index 00000000..f5c66505
--- /dev/null
+++ b/hw/bsp/stm32f072eval/board.mk
@@ -0,0 +1,50 @@
+ST_FAMILY = f0
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DSTM32F072xB \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F0
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/$(BOARD)/STM32F072VBTx_FLASH.ld
+
+SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+
+INC += \
+  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/hw/bsp/$(BOARD)
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f072vb
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f072eval/stm32f072eval.c b/hw/bsp/stm32f072eval/stm32f072eval.c
new file mode 100644
index 00000000..ecc78674
--- /dev/null
+++ b/hw/bsp/stm32f072eval/stm32f072eval.c
@@ -0,0 +1,248 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "stm32f0xx_hal.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PIN_8	// LED1, GREEN
+// #define LED_PIN               GPIO_PIN_9	// LED2, ORANGE
+// #define LED_PIN               GPIO_PIN_10	// LED3, RED
+// #define LED_PIN               GPIO_PIN_11	// LED4, BLUE
+#define LED_STATE_ON          0
+
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0	// JOY_SEL
+#define BUTTON_STATE_ACTIVE   1
+
+#define UARTx                 USART2
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF0_USART2
+#define UART_TX_PIN           GPIO_PIN_5
+#define UART_RX_PIN           GPIO_PIN_6
+
+UART_HandleTypeDef UartHandle;
+
+
+// enable all LED, Button, Uart, USB clock
+static void all_rcc_clk_enable(void)
+{
+  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-, button
+  // __HAL_RCC_GPIOB_CLK_ENABLE();
+  //__HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();  // Uart tx, rx, LED
+  __HAL_RCC_USART2_CLK_ENABLE(); // Uart module
+}
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSI48)
+  *            SYSCLK(Hz)                     = 48000000
+  *            HCLK(Hz)                       = 48000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            HSI Frequency(Hz)              = 48000000
+  *            PREDIV                         = 2
+  *            PLLMUL                         = 2
+  *            Flash Latency(WS)              = 1
+  * @param  None
+  * @retval None
+  */
+static void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+   * in the RCC_OscInitTypeDef structure.
+   */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
+  RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    assert(false);
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+   */
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+	assert(false);
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART2;
+  PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
+  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+	assert(false);
+  }
+}
+
+
+void board_init(void)
+{
+  SystemClock_Config();
+  all_rcc_clk_enable();
+
+  #if CFG_TUSB_OS  == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+  #endif
+
+  // LED
+  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  // Uart
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle.Instance        = UARTx;
+  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+  UartHandle.Init.StopBits   = UART_STOPBITS_1;
+  UartHandle.Init.Parity     = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode       = UART_MODE_TX_RX;
+  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+  HAL_UART_Init(&UartHandle);
+
+  // USB Pins
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // USB Clock enable
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  asm("bkpt");
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  (void) file; (void) line;
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32f072eval/stm32f0xx_hal_conf.h b/hw/bsp/stm32f072eval/stm32f0xx_hal_conf.h
new file mode 100644
index 00000000..6fdf24f1
--- /dev/null
+++ b/hw/bsp/stm32f072eval/stm32f0xx_hal_conf.h
@@ -0,0 +1,321 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_CONF_H
+#define __STM32F0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CAN_MODULE_ENABLED   */
+/*#define HAL_CEC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+/*#define HAL_EXTI_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED */
+/*#define HAL_I2S_MODULE_ENABLED */
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED */
+
+/* ######################### Oscillator Values adaptation ################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE            8000000U  /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+  *        Timeout value 
+  */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT  100U      /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE            8000000U  /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+  *        Timeout value 
+  */
+#if !defined  (HSI_STARTUP_TIMEOUT) 
+  #define HSI_STARTUP_TIMEOUT  5000U     /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */  
+
+/**
+  * @brief Internal High Speed oscillator for ADC (HSI14) value.
+  */
+#if !defined  (HSI14_VALUE) 
+  #define HSI14_VALUE          14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator for USB (HSI48) value.
+  */
+#if !defined  (HSI48_VALUE) 
+  #define HSI48_VALUE          48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+  #define LSI_VALUE            40000U    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE            32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */     
+
+/**
+  * @brief Time out for LSE start up value in ms.
+  */
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT  5000U     /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default)             */
+                                                                              /*  Warning: Must be set to higher priority for HAL_Delay()  */
+                                                                              /*  and HAL_GetTick() usage under interrupt context          */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     0U
+#define  DATA_CACHE_ENABLE            0U
+#define  USE_SPI_CRC                  1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS        0U /* COMP register callback disabled      */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_TSC_REGISTER_CALLBACKS         0U /* TSC register callback disabled       */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+ #define USE_FULL_ASSERT   1 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f0xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f0xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32f0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32f0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */    
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

From 2f6f93155372cb282cf1f558cb963a93ef006e21 Mon Sep 17 00:00:00 2001
From: Ned Konz <ned@bike-nomad.com>
Date: Fri, 19 Mar 2021 12:12:09 -0700
Subject: [PATCH 25/72] Removed asserts

---
 hw/bsp/stm32f072eval/stm32f072eval.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/hw/bsp/stm32f072eval/stm32f072eval.c b/hw/bsp/stm32f072eval/stm32f072eval.c
index ecc78674..e8486d88 100644
--- a/hw/bsp/stm32f072eval/stm32f072eval.c
+++ b/hw/bsp/stm32f072eval/stm32f072eval.c
@@ -99,9 +99,9 @@ static void SystemClock_Config(void)
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
   RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-    assert(false);
-  }
+
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
   /** Initializes the CPU, AHB and APB buses clocks
    */
   RCC_ClkInitStruct.ClockType =
@@ -110,16 +110,13 @@ static void SystemClock_Config(void)
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-	assert(false);
-  }
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
+
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART2;
   PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
   PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
 
-  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
-	assert(false);
-  }
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
 }
 
 

From 5e74a7b548e99493a57490d9c6506d908d06b9ba Mon Sep 17 00:00:00 2001
From: Ned Konz <ned@bike-nomad.com>
Date: Fri, 19 Mar 2021 12:27:44 -0700
Subject: [PATCH 26/72] Fixed case in linker script name

---
 .../{STM32F072VBTX_FLASH.ld => STM32F072VBTx_FLASH.ld}            | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/stm32f072eval/{STM32F072VBTX_FLASH.ld => STM32F072VBTx_FLASH.ld} (100%)

diff --git a/hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld b/hw/bsp/stm32f072eval/STM32F072VBTx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32f072eval/STM32F072VBTX_FLASH.ld
rename to hw/bsp/stm32f072eval/STM32F072VBTx_FLASH.ld

From a2006ce21466d50e92c62f85a3802262938e3b84 Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Sun, 21 Mar 2021 09:38:02 +0100
Subject: [PATCH 27/72] SAM 54 Xplained Pro: remove board specific define

---
 hw/bsp/same54xplainedpro/board.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 1200fd9f..046ebbf6 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -13,7 +13,6 @@ CFLAGS += \
   -D__SAME54P20A__ \
   -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
   -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DSAME54XPLAINEDPRO=1 \
   -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
 
 

From 1a5a1136559aa8a78ec42cd49e3a7c28e55b711c Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Sun, 21 Mar 2021 09:43:29 +0100
Subject: [PATCH 28/72] SAM54 Xplained Pro: reduce board setup code for
 maintenance

The board now runs off the internal oscillator at 48 MHz.
This is sufficient to run the TinyUSB examples.

A better performing clock setup is keep in the file as init_clock_xtal()
as an example.
---
 hw/bsp/same54xplainedpro/board.mk            |  2 +-
 hw/bsp/same54xplainedpro/same54xplainedpro.c | 22 ++++++++++++++++----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 046ebbf6..89d6ce01 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -1,6 +1,6 @@
 DEPS_SUBMODULES = hw/mcu/microchip
 
-CONF_CPU_FREQUENCY ?= 120000000
+CONF_CPU_FREQUENCY ?= 48000000
 
 CFLAGS += \
   -mthumb \
diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same54xplainedpro/same54xplainedpro.c
index 70ea7d43..52e1b25f 100644
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ b/hw/bsp/same54xplainedpro/same54xplainedpro.c
@@ -59,7 +59,19 @@ void USB_3_Handler(void)
 #define BUTTON_PIN PIN_PB31
 #define BOARD_SERCOM SERCOM2
 
-static inline void init_clock(void)
+/** Initializes the clocks from the external 12 MHz crystal
+ *
+ * The goal of this setup is to preserve the second PLL
+ * for the application code while still having a reasonable
+ * 48 MHz clock for USB / UART.
+ *
+ * GCLK0:   CONF_CPU_FREQUENCY (default 120 MHz) from PLL0
+ * GCLK1:   unused
+ * GCLK2:   12 MHz from XOSC1
+ * DFLL48M: closed loop from GLCK2
+ * GCLK3:   48 MHz
+ */
+static inline void init_clock_xtal(void)
 {
 	/* configure for a 12MHz crystal connected to XIN1/XOUT1 */
 	OSCCTRL->XOSCCTRL[1].reg =
@@ -118,13 +130,14 @@ static inline void init_clock(void)
 	while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
 }
 
+/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
 static inline void uart_init(void)
 {
 	gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
 	gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
 
 	MCLK->APBBMASK.bit.SERCOM2_ = 1;
-	GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
+	GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
 
 	BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
 	while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
@@ -167,7 +180,8 @@ static inline void uart_send_str(const char* text)
 
 void board_init(void)
 {
-	init_clock();
+	// Uncomment this line to run off the XTAL
+	// init_clock_xtal();
 
 	SystemCoreClock = CONF_CPU_FREQUENCY;
 
@@ -218,7 +232,7 @@ void board_init(void)
 	 * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
 	 * for low speed and full speed operation.
 	 */
-	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK3_Val | GCLK_PCHCTRL_CHEN);
+	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);
 	hri_mclk_set_AHBMASK_USB_bit(MCLK);
 	hri_mclk_set_APBBMASK_USB_bit(MCLK);
 

From 1f9b7b0c4832a2d740bbfe9b437065ea3d24407a Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Sun, 21 Mar 2021 09:48:49 +0100
Subject: [PATCH 29/72] SAM54 Xplained Pro: update board setup documentation

---
 hw/bsp/same54xplainedpro/same54xplainedpro.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same54xplainedpro/same54xplainedpro.c
index 52e1b25f..4c38fc6e 100644
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ b/hw/bsp/same54xplainedpro/same54xplainedpro.c
@@ -180,7 +180,7 @@ static inline void uart_send_str(const char* text)
 
 void board_init(void)
 {
-	// Uncomment this line to run off the XTAL
+	// Uncomment this line and change the GCLK for UART/USB to run off the XTAL.
 	// init_clock_xtal();
 
 	SystemCoreClock = CONF_CPU_FREQUENCY;

From 567c6d437af06c804baa3cd310021c8cac37aecd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Mar 2021 15:19:38 +0700
Subject: [PATCH 30/72] remove ses project since it is all broken and occupies
 space

---
 .gitignore                                    |     3 +
 README.md                                     |     2 +-
 .../device/cdc_msc/ses/cdc_msc_hid.emProject  |    13 -
 .../cdc_msc/ses/lpc11u6x/LPC1100_Startup.s    |   145 -
 .../cdc_msc/ses/lpc11u6x/LPC1100_Target.js    |    50 -
 .../ses/lpc11u6x/LPC11U68_MemoryMap.xml       |     7 -
 .../ses/lpc11u6x/LPC11U6x_Registers.xml       | 11919 ------
 .../cdc_msc/ses/lpc11u6x/LPC11U6x_Vectors.s   |   405 -
 .../cdc_msc/ses/lpc11u6x/flash_placement.xml  |    41 -
 .../cdc_msc/ses/lpc11u6x/lpc11u6x.emProject   |   126 -
 .../device/cdc_msc/ses/lpc11u6x/thumb_crt0.s  |   415 -
 .../cdc_msc/ses/lpc13xx/LPC1300_Startup.s     |   113 -
 .../cdc_msc/ses/lpc13xx/LPC1300_Target.js     |    19 -
 .../ses/lpc13xx/LPC1347FBD64_MemoryMap.xml    |     7 -
 .../ses/lpc13xx/LPC13Uxx_Registers.xml        |  5515 ---
 .../cdc_msc/ses/lpc13xx/LPC13Uxx_Vectors.s    |   342 -
 .../cdc_msc/ses/lpc13xx/flash_placement.xml   |    41 -
 .../cdc_msc/ses/lpc13xx/lpc13xx.emProject     |   119 -
 .../device/cdc_msc/ses/lpc13xx/thumb_crt0.s   |   415 -
 .../cdc_msc/ses/lpc175x_6x/LPC1700_Startup.s  |   109 -
 .../cdc_msc/ses/lpc175x_6x/LPC1700_Target.js  |    19 -
 .../ses/lpc175x_6x/LPC1769_MemoryMap.xml      |     6 -
 .../ses/lpc175x_6x/LPC176x5x_Registers.xml    | 11058 -----
 .../ses/lpc175x_6x/LPC176x5x_Vectors.s        |   418 -
 .../ses/lpc175x_6x/flash_placement.xml        |    37 -
 .../ses/lpc175x_6x/lpc175x_6x.emProject       |   116 -
 .../cdc_msc/ses/lpc175x_6x/thumb_crt0.s       |   415 -
 .../cdc_msc/ses/lpc18xx/LPC1800_Startup.s     |   110 -
 .../cdc_msc/ses/lpc18xx/LPC1800_Target.js     |    19 -
 .../cdc_msc/ses/lpc18xx/LPC1857_MemoryMap.xml |     7 -
 .../cdc_msc/ses/lpc18xx/LPC18xx_Registers.xml | 30452 --------------
 .../cdc_msc/ses/lpc18xx/LPC18xx_Vectors.s     |   516 -
 .../cdc_msc/ses/lpc18xx/flash_placement.xml   |    37 -
 .../cdc_msc/ses/lpc18xx/lpc18xx.emProject     |   135 -
 .../device/cdc_msc/ses/lpc18xx/thumb_crt0.s   |   415 -
 .../cdc_msc/ses/lpc40xx/LPC4000_Startup.s     |   128 -
 .../cdc_msc/ses/lpc40xx/LPC4000_Target.js     |    19 -
 .../ses/lpc40xx/LPC4088FBD208_MemoryMap.xml   |     6 -
 .../ses/lpc40xx/LPC408x_7x_Registers.xml      | 18992 ---------
 .../cdc_msc/ses/lpc40xx/LPC408x_7x_Vectors.s  |   458 -
 .../cdc_msc/ses/lpc40xx/flash_placement.xml   |    37 -
 .../cdc_msc/ses/lpc40xx/lpc40xx.emProject     |   122 -
 .../device/cdc_msc/ses/lpc40xx/thumb_crt0.s   |   415 -
 .../cdc_msc/ses/lpc43xx/LPC4300_Startup.s     |   126 -
 .../cdc_msc/ses/lpc43xx/LPC4300_Target.js     |    19 -
 .../lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml   |     7 -
 .../cdc_msc/ses/lpc43xx/LPC43xx_Registers.xml | 33526 ----------------
 .../cdc_msc/ses/lpc43xx/LPC43xx_Vectors.s     |   540 -
 .../cdc_msc/ses/lpc43xx/flash_placement.xml   |    37 -
 .../cdc_msc/ses/lpc43xx/lpc43xx.emProject     |   136 -
 .../device/cdc_msc/ses/lpc43xx/thumb_crt0.s   |   415 -
 .../cdc_msc/ses/nrf5x/flash_placement.xml     |    37 -
 .../ses/nrf5x/nRF52840_xxAA_MemoryMap.xml     |     5 -
 .../nrf5x/nRF52840_xxAA_s140v6_MemoryMap.xml  |     5 -
 .../device/cdc_msc/ses/nrf5x/nRF_Target.js    |    19 -
 .../cdc_msc/ses/nrf5x/nrf52840_Registers.xml  | 22310 ----------
 .../device/cdc_msc/ses/nrf5x/nrf5x.emProject  |   132 -
 .../device/cdc_msc/ses/nrf5x/thumb_crt0.s     |   420 -
 .../ses/samd21/ATSAMD21G18A_MemoryMap.xml     |     5 -
 .../ses/samd21/ATSAMD21G18A_Registers.xml     |  9587 -----
 .../cdc_msc/ses/samd21/ATSAMD21G18A_Vectors.s |   331 -
 .../cdc_msc/ses/samd21/SAMD21_Startup.s       |   114 -
 .../cdc_msc/ses/samd21/SAMD21_Target.js       |    19 -
 .../cdc_msc/ses/samd21/flash_placement.xml    |    37 -
 .../cdc_msc/ses/samd21/samd21.emProject       |   108 -
 .../device/cdc_msc/ses/samd21/thumb_crt0.s    |   415 -
 .../ses/samd51/ATSAMD51J19A_MemoryMap.xml     |     6 -
 .../ses/samd51/ATSAMD51J19A_Registers.xml     | 23643 -----------
 .../cdc_msc/ses/samd51/ATSAMD51J19A_Vectors.s |  1227 -
 .../cdc_msc/ses/samd51/SAMD51_Startup.s       |   128 -
 .../cdc_msc/ses/samd51/SAMD51_Target.js       |    19 -
 .../cdc_msc/ses/samd51/flash_placement.xml    |    37 -
 .../cdc_msc/ses/samd51/samd51.emProject       |   112 -
 .../device/cdc_msc/ses/samd51/thumb_crt0.s    |   415 -
 .../ses/stm32f4/STM32F407VG_MemoryMap.xml     |     6 -
 .../ses/stm32f4/STM32F40x_Registers.xml       | 13923 -------
 .../cdc_msc/ses/stm32f4/STM32F40x_Vectors.s   |   817 -
 .../cdc_msc/ses/stm32f4/STM32F4xx_Startup.s   |   125 -
 .../cdc_msc/ses/stm32f4/STM32F4xx_Target.js   |    19 -
 .../cdc_msc/ses/stm32f4/flash_placement.xml   |    37 -
 .../cdc_msc/ses/stm32f4/stm32f4.emProject     |    87 -
 .../device/cdc_msc/ses/stm32f4/thumb_crt0.s   |   415 -
 .../ses/cdc_msc_hid_freertos.emProject        |     7 -
 .../ses/lpc175x_6x/FreeRTOSConfig.h           |   134 -
 .../ses/lpc175x_6x/LPC1700_Startup.s          |   109 -
 .../ses/lpc175x_6x/LPC1700_Target.js          |    19 -
 .../ses/lpc175x_6x/LPC1769_MemoryMap.xml      |     6 -
 .../ses/lpc175x_6x/LPC176x5x_Registers.xml    | 11058 -----
 .../ses/lpc175x_6x/LPC176x5x_Vectors.s        |   418 -
 .../ses/lpc175x_6x/flash_placement.xml        |    37 -
 .../ses/lpc175x_6x/lpc175x_6x.emProject       |   137 -
 .../ses/lpc175x_6x/thumb_crt0.s               |   415 -
 .../ses/nrf5x/flash_placement.xml             |    37 -
 .../ses/nrf5x/nRF52840_xxAA_MemoryMap.xml     |     5 -
 .../cdc_msc_freertos/ses/nrf5x/nRF_Target.js  |    19 -
 .../ses/nrf5x/nrf52840_Registers.xml          | 22310 ----------
 .../ses/nrf5x/nrf5x.emProject                 |   151 -
 .../cdc_msc_freertos/ses/nrf5x/thumb_crt0.s   |   420 -
 .../ses/samd21/ATSAMD21G18A_MemoryMap.xml     |     5 -
 .../ses/samd21/ATSAMD21G18A_Registers.xml     |  9587 -----
 .../ses/samd21/ATSAMD21G18A_Vectors.s         |   331 -
 .../ses/samd21/SAMD21_Startup.s               |   114 -
 .../ses/samd21/SAMD21_Target.js               |    19 -
 .../ses/samd21/flash_placement.xml            |    37 -
 .../ses/samd21/samd21.emProject               |   142 -
 .../cdc_msc_freertos/ses/samd21/thumb_crt0.s  |   415 -
 .../ses/samd51/ATSAMD51J19A_MemoryMap.xml     |     6 -
 .../ses/samd51/ATSAMD51J19A_Registers.xml     | 23643 -----------
 .../ses/samd51/ATSAMD51J19A_Vectors.s         |  1227 -
 .../ses/samd51/SAMD51_Startup.s               |   128 -
 .../ses/samd51/SAMD51_Target.js               |    19 -
 .../ses/samd51/flash_placement.xml            |    37 -
 .../ses/samd51/samd51.emProject               |   146 -
 .../cdc_msc_freertos/ses/samd51/thumb_crt0.s  |   415 -
 .../cdc_msc_hid/ses/cdc_msc_hid.emProject     |     9 -
 .../ses/lpc175x_6x/LPC1700_Startup.s          |   109 -
 .../ses/lpc175x_6x/LPC1700_Target.js          |    19 -
 .../ses/lpc175x_6x/LPC1769_MemoryMap.xml      |     6 -
 .../ses/lpc175x_6x/LPC176x5x_Registers.xml    | 11058 -----
 .../ses/lpc175x_6x/LPC176x5x_Vectors.s        |   418 -
 .../ses/lpc175x_6x/flash_placement.xml        |    37 -
 .../ses/lpc175x_6x/lpc175x_6x.emProject       |   119 -
 .../cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s   |   415 -
 .../cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s |   110 -
 .../cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js |    19 -
 .../ses/lpc18xx/LPC1857_MemoryMap.xml         |     7 -
 .../ses/lpc18xx/LPC18xx_Registers.xml         | 30452 --------------
 .../cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s |   516 -
 .../ses/lpc18xx/flash_placement.xml           |    37 -
 .../cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject |   139 -
 .../host/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s |   415 -
 .../cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s |   128 -
 .../cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js |    19 -
 .../ses/lpc40xx/LPC4088FBD208_MemoryMap.xml   |     6 -
 .../ses/lpc40xx/LPC408x_7x_Registers.xml      | 18992 ---------
 .../ses/lpc40xx/LPC408x_7x_Vectors.s          |   458 -
 .../ses/lpc40xx/flash_placement.xml           |    37 -
 .../cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject |   126 -
 .../host/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s |   415 -
 .../cdc_msc_hid/ses/lpc43xx/LPC4300_Startup.s |   126 -
 .../cdc_msc_hid/ses/lpc43xx/LPC4300_Target.js |    19 -
 .../lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml   |     7 -
 .../ses/lpc43xx/LPC43xx_Registers.xml         | 33526 ----------------
 .../cdc_msc_hid/ses/lpc43xx/LPC43xx_Vectors.s |   540 -
 .../ses/lpc43xx/flash_placement.xml           |    37 -
 .../cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject |   137 -
 .../host/cdc_msc_hid/ses/lpc43xx/thumb_crt0.s |   415 -
 147 files changed, 4 insertions(+), 363531 deletions(-)
 delete mode 100644 examples/device/cdc_msc/ses/cdc_msc_hid.emProject
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Startup.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Target.js
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/LPC11U68_MemoryMap.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Registers.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Vectors.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/flash_placement.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/lpc11u6x.emProject
 delete mode 100644 examples/device/cdc_msc/ses/lpc11u6x/thumb_crt0.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc13xx/LPC1300_Startup.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc13xx/LPC1300_Target.js
 delete mode 100644 examples/device/cdc_msc/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Registers.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Vectors.s
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 delete mode 100644 examples/device/cdc_msc/ses/lpc175x_6x/LPC1769_MemoryMap.xml
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 delete mode 100644 examples/device/cdc_msc/ses/lpc18xx/LPC1857_MemoryMap.xml
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 delete mode 100644 examples/device/cdc_msc/ses/lpc40xx/LPC4000_Target.js
 delete mode 100644 examples/device/cdc_msc/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
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 delete mode 100644 examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Vectors.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc40xx/flash_placement.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc40xx/lpc40xx.emProject
 delete mode 100644 examples/device/cdc_msc/ses/lpc40xx/thumb_crt0.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/LPC4300_Startup.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/LPC4300_Target.js
 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Registers.xml
 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Vectors.s
 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/flash_placement.xml
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 delete mode 100644 examples/device/cdc_msc/ses/lpc43xx/thumb_crt0.s
 delete mode 100644 examples/device/cdc_msc/ses/nrf5x/flash_placement.xml
 delete mode 100644 examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml
 delete mode 100644 examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_s140v6_MemoryMap.xml
 delete mode 100644 examples/device/cdc_msc/ses/nrf5x/nRF_Target.js
 delete mode 100644 examples/device/cdc_msc/ses/nrf5x/nrf52840_Registers.xml
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 delete mode 100644 examples/device/cdc_msc/ses/samd21/samd21.emProject
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 delete mode 100644 examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Startup.s
 delete mode 100644 examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Target.js
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 delete mode 100644 examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml
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diff --git a/.gitignore b/.gitignore
index ca43e63e..093bcc57 100644
--- a/.gitignore
+++ b/.gitignore
@@ -17,6 +17,9 @@ latex
 test_old/
 tests_obsolete/
 _build
+/examples/*/*/ses
+/examples/*/*/ozone
+/examples/obsolete
 # coverity intermediate files
 cov-int
 # cppcheck build directories
diff --git a/README.md b/README.md
index f5bd7ced..78ff5f0c 100644
--- a/README.md
+++ b/README.md
@@ -11,7 +11,7 @@ TinyUSB is an open-source cross-platform USB Host/Device stack for embedded syst
 ```
 .
 ├── docs            # Documentation
-├── examples        # Sample with Makefile and Segger Embedded build support
+├── examples        # Sample with Makefile build support
 ├── hw
 │   ├── bsp         # Supported boards source files
 │   └── mcu         # Low level mcu core & peripheral drivers
diff --git a/examples/device/cdc_msc/ses/cdc_msc_hid.emProject b/examples/device/cdc_msc/ses/cdc_msc_hid.emProject
deleted file mode 100644
index c02f7a58..00000000
--- a/examples/device/cdc_msc/ses/cdc_msc_hid.emProject
+++ /dev/null
@@ -1,13 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="cdc_msc_hid" target="8" version="2">
-  <import file_name="nrf5x/nrf5x.emProject" />
-  <import file_name="samd21/samd21.emProject" />
-  <import file_name="samd51/samd51.emProject" />
-  <import file_name="lpc43xx/lpc43xx.emProject" />
-  <import file_name="lpc175x_6x/lpc175x_6x.emProject" />
-  <import file_name="lpc13xx/lpc13xx.emProject" />
-  <import file_name="lpc11u6x/lpc11u6x.emProject" />
-  <import file_name="lpc18xx/lpc18xx.emProject" />
-  <import file_name="lpc40xx/lpc40xx.emProject" />
-  <import file_name="stm32f4/stm32f4.emProject" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Startup.s b/examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Startup.s
deleted file mode 100644
index 56918e1b..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Startup.s
+++ /dev/null
@@ -1,145 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*           www.segger.com     Support: support@segger.com           *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* conditions are met:                                                *
-*                                                                    *
-* - Redistributions of source code must retain the above copyright   *
-*   notice, this list of conditions and the following disclaimer.    *
-*                                                                    *
-* - Neither the name of SEGGER Microcontroller GmbH                  *
-*   nor the names of its contributors may be used to endorse or      *
-*   promote products derived from this software without specific     *
-*   prior written permission.                                        *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED.                                                        *
-* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-*********************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialize main stack */
-  ldr r0, =STACK_INIT_VAL
-  ldr r1, =0x7
-  bics r0, r1
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialize system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Target.js b/examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Target.js
deleted file mode 100644
index e0ee5776..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/LPC1100_Target.js
+++ /dev/null
@@ -1,50 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*           www.segger.com     Support: support@segger.com           *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* conditions are met:                                                *
-*                                                                    *
-* - Redistributions of source code must retain the above copyright   *
-*   notice, this list of conditions and the following disclaimer.    *
-*                                                                    *
-* - Neither the name of SEGGER Microcontroller GmbH                  *
-*   nor the names of its contributors may be used to endorse or      *
-*   promote products derived from this software without specific     *
-*   prior written permission.                                        *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED.                                                        *
-* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-*********************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/LPC11U68_MemoryMap.xml b/examples/device/cdc_msc/ses/lpc11u6x/LPC11U68_MemoryMap.xml
deleted file mode 100644
index 2913af3a..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/LPC11U68_MemoryMap.xml
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC11U68">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00040000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" />
-  <MemorySegment name="RAM3" start="0x20004000" size="0x00000800" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Registers.xml b/examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Registers.xml
deleted file mode 100644
index f1f465ea..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Registers.xml
+++ /dev/null
@@ -1,11919 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC11U6x" description="LPC11U6x ARM cortex-m0+">
-  <RegisterGroup name="I2C0" start="0x40000000" description="I2C-bus controller">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="STATUS" description="These bits give the actual status information about the I2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40004000" description="Windowed Watchdog Timer (WWDT)">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
-        <Enum name="STOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUNNING" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
-        <Enum name="INTERRUPT" start="0" description="A watchdog timeout will not cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1." />
-      <BitField start="3" size="1" name="WDINT" description="Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit can be set once by software and is only cleared by a reset.">
-        <Enum name="NOT_LOCKED" start="0" description="The watchdog time-out value (TC) can be changed at any time." />
-        <Enum name="LOCKED" start="1" description="The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="1" name="LOCK" description="A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7)." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This 24-bit register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="FEED" description="Feed value should be 0xAA followed by 0x55." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKSEL" description="Selects source of WDT clock">
-        <Enum name="IRC" start="0" description="IRC" />
-        <Enum name="WATCHDOG_OSCILLATOR_" start="1" description="Watchdog oscillator (WDOSC)" />
-      </BitField>
-      <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART0" start="0x40008000" description="USART0">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRINTEN" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupt." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREINTEN" description="THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupt." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RLSINTEN" description="Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RLS_INTE" start="0" description="Disable the RLS interrupt." />
-        <Enum name="ENABLE_THE_RLS_INTER" start="1" description="Enable the RLS interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="MSINTEN" description="Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.">
-        <Enum name="DISABLE_THE_MS_INTER" start="0" description="Disable the MS interrupt." />
-        <Enum name="ENABLE_THE_MS_INTERR" start="1" description="Enable the MS interrupt." />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="4_MODEM_STATUS" start="0x0" description="4   - Modem status" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOEN" description="These bits are equivalent to FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable">
-        <Enum name="DISABLED" start="0" description="USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset">
-        <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset">
-        <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and  RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="RBR_IS_EMPTY_" start="0" description="RBR is empty." />
-        <Enum name="RBR_CONTAINS_VALID_D" start="1" description="RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="THR_CONTAINS_VALID_D" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID_D" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERRO" start="1" description="USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Start mode">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write only accessible).">
-        <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write only accessible).">
-        <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA (remote control) mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable">
-        <Enum name="IRDA_MODE_IS_DISABLE" start="0" description="IrDA mode is disabled, USARTn acts as a standard USART." />
-        <Enum name="IRDA_MODE_IS_ENABLED" start="1" description="IrDA mode is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input inverter">
-        <Enum name="INVERTED" start="0" description="The serial input is not inverted." />
-        <Enum name="NOT_INVERTED" start="1" description="The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse width when FixPulseEn = 1.">
-        <Enum name="3_DIV_16_X_BAUD_RATE" start="0x0" description="3 / (16 x baud rate)" />
-        <Enum name="2_X_TPCLK" start="0x1" description="2 x TPCLK" />
-        <Enum name="4_X_TPCLK" start="0x2" description="4 x TPCLK" />
-        <Enum name="8_X_TPCLK" start="0x3" description="8 x TPCLK" />
-        <Enum name="16_X_TPCLK" start="0x4" description="16 x TPCLK" />
-        <Enum name="32_X_TPCLK" start="0x5" description="32 x TPCLK" />
-        <Enum name="64_X_TPCLK" start="0x6" description="64 x TPCLK" />
-        <Enum name="128_X_TPCLK" start="0x7" description="128 x TPCLK" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half duplex enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLE_HALF_DUPLEX_" start="0" description="Disable half-duplex mode." />
-        <Enum name="ENABLE_HALF_DUPLEX_M" start="1" description="Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface Control register. Enables and configures the Smart Card Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
-        <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="3" name="TXRETRY" description="When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared." />
-      <BitField start="8" size="8" name="XTRAGUARD" description="When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="THE_RECEIVER_IS_ENAB" start="0" description="The receiver is enabled." />
-        <Enum name="THE_RECEIVER_IS_DISA" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="AUTO_ADDRESS_DETECT_" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="AUTO_ADDRESS_DETECT_" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Select direction control pin">
-        <Enum name="RTS" start="0" description="If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Auto direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
-        <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Falling edge sampling.">
-        <Enum name="RISING" start="0" description="RxD is sampled on the rising edge of SCLK " />
-        <Enum name="FALLING" start="1" description="RxD is sampled on the falling edge of SCLK" />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNC" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic" />
-        <Enum name="NOSYNC" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
-        <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
-      </BitField>
-      <BitField start="5" size="1" name="SSDIS" description="Start/stop bits">
-        <Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND_STARTSTOP" start="1" description="Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
-        <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT16B0" start="0x4000C000" description="16-bit counter/timers CT16B0">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="DISABLED" start="0" description="The counters are disabled." />
-        <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="NOP" start="0" description="Do nothing." />
-        <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TCVAL" description="Timer counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PCVAL" description="Prescale value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PC" description="Prescale counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0:  a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1:  a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2:  a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode.  Increments every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUAL" start="0x3" description="Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved.">
-        <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
-        <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
-        <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
-        <Enum name="CAP0RISING" start="0x0" description="Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1RISING" start="0x2" description="Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP2RISING" start="0x4" description="Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1FALLING" start="0x5" description="Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="EM0" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="EM1" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="EM2" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
-        <Enum name="EM3" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT16B1" start="0x40010000" description="16-bit counter/timers CT16B1">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="DISABLED" start="0" description="The counters are disabled." />
-        <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="NOP" start="0" description="Do nothing." />
-        <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TCVAL" description="Timer counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PCVAL" description="Prescale value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PC" description="Prescale counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0:  a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1:  a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2:  a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 267 shows the encoding of these bits.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the&#xa;corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is&#xa;LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1&#xa;(CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding&#xa;External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode.  Increments every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUAL" start="0x3" description="Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved.">
-        <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
-        <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
-        <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
-        <Enum name="CAP0RISING" start="0x0" description="Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1RISING" start="0x2" description="Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP2RISING" start="0x4" description="Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1FALLING" start="0x5" description="Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="EM0" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="EM1" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="EM2" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
-        <Enum name="EM3" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT32B0" start="0x40014000" description="32-bit counter/timers CT32B0">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="DISABLED" start="0" description="The counters are disabled." />
-        <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="NOP" start="0" description="Do nothing." />
-        <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TCVAL" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0:  a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1:  a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2:  a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode.  Increments every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge.  TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_DUAL_ED" start="0x3" description="Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved.">
-        <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
-        <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
-        <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
-        <Enum name="CAP0RISING" start="0x0" description="Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1RISING" start="0x2" description="Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP2RISING" start="0x4" description="Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP2FALLING" start="0x5" description="Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="EM0" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="EM1" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="EM2" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
-        <Enum name="EM3" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT32B1" start="0x40018000" description="32-bit counter/timers CT32B1">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="DISABLED" start="0" description="The counters are disabled." />
-        <Enum name="ENABLED" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="NOP" start="0" description="Do nothing." />
-        <Enum name="RESET" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TCVAL" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Rising edge of capture channel 0:  a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Falling edge of capture channel 0:: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Generate interrupt on channel 0 capture event: a CR0 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Rising edge of capture channel 1:  a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Falling edge of capture channel 1:: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Generate interrupt on channel 1 capture event: a CR1 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Rising edge of capture channel 2:  a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Generate interrupt on channel 2 capture event: a CR2 load  generates an interrupt.">
-        <Enum name="ENABLED" start="1" description="Enabled." />
-        <Enum name="DISABLED" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register. CR is loaded with the value of TC when there is an event on the CAP input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear the corresponding&#xa;External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned&#xa;out)." />
-        <Enum name="SET" start="0x2" description="Set&#xa;the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin&#xa;is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment the Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode.  Increments every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge.  TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_DUAL_ED" start="0x3" description="Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 is reserved.">
-        <Enum name="CAPTURE_CHANNEL_0" start="0x0" description="Capture channel 0." />
-        <Enum name="CAPTURE_CHANNEL_1" start="0x1" description="Capture channel 1." />
-        <Enum name="CAPTURE_CHANNEL_2" start="0x2" description="Capture channel 2." />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
-        <Enum name="CAP0RISING" start="0x0" description="Rising Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP0FALLING" start="0x1" description="Falling Edge of the signal on capture channel 0 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1RISING" start="0x2" description="Rising Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP1FALLING" start="0x3" description="Falling Edge of the signal on capture channel 1 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP2RISING" start="0x4" description="Rising Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
-        <Enum name="CAP2FALLING" start="0x5" description="Falling Edge of the signal on capture channel 2 clears the timer (if bit 4 is set)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="EM0" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="EM1" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="EM2" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
-        <Enum name="EM3" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x4001C000" description="12-bit Analog-to-Digital Converter (ADC)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="A/D Control Register. Contains the clock divide value, enable bits for each sequence and the A/D power-down bit." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLKDIV" description="The system clock is divided by this value plus one to produce the clock for the A/D converter, which should be less than or equal to 50 MHz (up to 100 MHz in 10-bit mode).  Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="8" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="LPWRMODE" description="Select low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately 15 ADC clock delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. This mode will NOT power-up the A/D if the ADC_ENA bit is low.">
-        <Enum name="DISABLED" start="0" description="Disabled. The low-power ADC mode is disabled.  The analog circuitry remains activated even when no conversions are requested." />
-        <Enum name="ENABLED" start="1" description="Enabled. The low-power ADC mode is enabled." />
-      </BitField>
-      <BitField start="30" size="1" name="CAL_MODE" description="Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted until the full calibration cycle has ended." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SEQA_CTRL" access="Read/Write" description="A/D Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="CHANNELS" description="Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth.  When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel.  This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write." />
-      <BitField start="12" size="3" name="TRIGGER" description="Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field." />
-      <BitField start="15" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="18" size="1" name="TRIGPOL" description="Select the polarity of the selected input trigger for this conversion sequence.">
-        <Enum name="NEGATIVE_EDGE" start="0" description="Negative edge. A negative edge launches the conversion sequence on the selected trigger input." />
-        <Enum name="POSITIVE_EDGE" start="1" description="Positive edge. A positive edge launches the conversion sequence on the selected trigger input." />
-      </BitField>
-      <BitField start="19" size="1" name="SYNCBYPASS" description="Setting this bit allows the hardware trigger input to bypass  synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.">
-        <Enum name="ENABLE_SYNCHRONIZATI" start="0" description="Enable synchronization. The hardware trigger bypass is not enabled." />
-        <Enum name="BYPASS_SYNCHRONIZATI" start="1" description="Bypass synchronization. The hardware trigger bypass is enabled." />
-      </BitField>
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="1" name="START" description="Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero." />
-      <BitField start="27" size="1" name="BURST" description="Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated." />
-      <BitField start="28" size="1" name="SINGLESTEP" description="When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit." />
-      <BitField start="29" size="1" name="LOWPRIO" description="Set priority for sequence A.">
-        <Enum name="LOW_PRIORITY" start="0" description="Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost." />
-        <Enum name="HIGH_PRIORITY" start="1" description="High priority.  Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt this sequence and launch a B sequence in it's place. The conversion currently in progress will be terminated.  The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point." />
-      </BitField>
-      <BitField start="30" size="1" name="MODE" description="Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence.  Impacts when conversion-complete interrupt/DMA requests for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below:">
-        <Enum name="END_OF_CONVERSION" start="0" description="End of conversion. The sequence A interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled." />
-        <Enum name="END_OF_SEQUENCE" start="1" description="End of sequence. The sequence A interrupt/DMA flag will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode.  The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register may not be utilized in this mode." />
-      </BitField>
-      <BitField start="31" size="1" name="SEQA_ENA" description="Sequence Enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Sequence A is disabled. Sequence A triggers are ignored. If this bit is cleared while sequence A is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Sequence A is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="4" name="SEQB_CTRL" access="Read/Write" description="A/D Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="CHANNELS" description="Selects which one or more of the twelve channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth.  When this conversion sequence is triggered, either by a hardware trigger or via software command, A/D conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is permissible to change this field and set bit 31 in the same write." />
-      <BitField start="12" size="3" name="TRIGGER" description="Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field." />
-      <BitField start="15" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="18" size="1" name="TRIGPOL" description="Select the polarity of the selected input trigger for this conversion sequence.">
-        <Enum name="NEGATIVE_EDGE" start="0" description="Negative edge. A negative edge launches the conversion sequence on the selected trigger input." />
-        <Enum name="POSITIVE_EDGE" start="1" description="Positive edge. A positive edge launches the conversion sequence on the selected trigger input." />
-      </BitField>
-      <BitField start="19" size="1" name="SYNCBYPASS" description="Setting this bit allows the hardware trigger input to bypass  synchronization flip-flops stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode: Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode: Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.">
-        <Enum name="ENABLE_SYNCHRONIZATI" start="0" description="Enable synchronization. The hardware trigger bypass is not enabled." />
-        <Enum name="BYPASS_SYNCHRONIZATI" start="1" description="Bypass synchronization. The hardware trigger bypass is enabled." />
-      </BitField>
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="1" name="START" description="Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write a 1 to this bit if the BURST bit is set.   This bit is only set to a 1 momentarily when written-to to launch a conversion sequence. It will consequently always read-back as a zero." />
-      <BitField start="27" size="1" name="BURST" description="Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other B triggers will be ignored while this bit is set.  Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated." />
-      <BitField start="28" size="1" name="SINGLESTEP" description="When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel.  Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="30" size="1" name="MODE" description="Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence.   Impacts when conversion-complete interrupt/DMA requests for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below:">
-        <Enum name="END_OF_CONVERSION" start="0" description="End of conversion. The sequence B interrupt/DMA flag will be set at the end of each individual A/D conversion performed under sequence B. This flag will mirror the DATAVALID bit in the SEQB_GDAT register.  The OVERRUN bit in the SEQB_GDAT register will contribute to generation of an overrun interrupt/DMA request if enabled." />
-        <Enum name="END_OF_SEQUENCE" start="1" description="End of sequence. The sequence B interrupt/DMA flag will be set when the entire set of sequence B conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode.   The OVERRUN bit in the SEQB_GDAT register will NOT contribute to generation of an overrun interrupt/DMA request since it is assumed this register will not be utilized in this mode." />
-      </BitField>
-      <BitField start="31" size="1" name="SEQB_ENA" description="Sequence Enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Sequence B is disabled. Sequence B triggers are ignored. If this bit is cleared while sequence B is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Sequence B is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="4" name="SEQA_GDAT" access="Read/Write" description="A/D Sequence-A Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-A" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register.   The result is the  a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.  DATAVALID = 1 indicates that this result has not yet been read." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1...)." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read.  This bit will contribute to an overrun interrupt request if the MODE bit (in SEQA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read.  This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)." />
-    </Register>
-    <Register start="+0x014" size="4" name="SEQB_GDAT" access="Read/Write" description="A/D Sequence-B Global Data Register. This register contains the result of the most recent A/D conversion performed under sequence-B" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the most recent conversion performed under conversion sequence associated with this register.   This will be a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on V REFP.  DATAVALID = 1 indicates that this result has not yet been read." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).  Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 0b0000 identifies channel 0, 0b0001 channel 1...)." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read.  This bit will contribute to an overrun interrupt request if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled)." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read.  This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="DAT[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="DAT[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="DAT[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="DAT[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="DAT[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="DAT[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="DAT[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="DAT[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+32" size="4" name="DAT[8]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+36" size="4" name="DAT[9]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+40" size="4" name="DAT[10]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x020+44" size="4" name="DAT[11]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="12" name="RESULT" description="This field contains the 12-bit A/D conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="2" name="THCMPRANGE" description="Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved." />
-      <BitField start="18" size="2" name="THCMPCROSS" description="Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold." />
-      <BitField start="20" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="4" name="CHANNEL" description="This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)" />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-      <BitField start="31" size="1" name="DATAVALID" description="This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled." />
-    </Register>
-    <Register start="+0x050" size="4" name="THR0_LOW" access="Read/Write" description="A/D Low Compare Threshold Register 0 : Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="THRLOW" description="Low threshold value against which A/D results will be compared" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="THR1_LOW" access="Read/Write" description="A/D Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="THRLOW" description="Low threshold value against which A/D results will be compared" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="THR0_HIGH" access="Read/Write" description="A/D High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="THRHIGH" description="High threshold value against which A/D results will be compared" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="THR1_HIGH" access="Read/Write" description="A/D High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="THRHIGH" description="High threshold value against which A/D results will be compared" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x060" size="4" name="CHAN_THRSEL" access="ReadOnly" description="A/D Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 0 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 0 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 1 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 1 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 2 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 2 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 3 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 3 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 4 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 4 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 5 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 5 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 6 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 7 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 7 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 8 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 8 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 9 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 9 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 10 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 10 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11_THRSEL" description="Threshold select by channel.">
-        <Enum name="THRESHOLD_0" start="0" description="Threshold 0. Channel 11 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers" />
-        <Enum name="THRESHOLD_1" start="1" description="Threshold 1. Channel 11 results will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x064" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQA_INTEN" description="Sequence A interrupt enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The sequence A interrupt/DMA request is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register." />
-      </BitField>
-      <BitField start="1" size="1" name="SEQB_INTEN" description="Sequence B interrupt enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The sequence B interrupt/DMA request is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register." />
-      </BitField>
-      <BitField start="2" size="1" name="OVR_INTEN" description="Overrun interrupt enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The overrun interrupt is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted." />
-      </BitField>
-      <BitField start="3" size="2" name="ADCMPINTEN0" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="5" size="2" name="ADCMPINTEN1" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="7" size="2" name="ADCMPINTEN2" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="9" size="2" name="ADCMPINTEN3" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="11" size="2" name="ADCMPINTEN4" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="13" size="2" name="ADCMPINTEN5" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="15" size="2" name="ADCMPINTEN6" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="17" size="2" name="ADCMPINTEN7" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="19" size="2" name="ADCMPINTEN8" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="21" size="2" name="ADCMPINTEN9" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="23" size="2" name="ADCMPINTEN10" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="25" size="2" name="ADCMPINTEN11" description="Threshold comparison interrupt enable.">
-        <Enum name="DISABLED" start="0x0" description="Disabled." />
-        <Enum name="OUTSIDE_THRESHOLD" start="0x1" description="Outside threshold." />
-        <Enum name="CROSSING_THRESHOLD" start="0x2" description="Crossing threshold." />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="FLAGS" access="ReadOnly" description="A/D Flags Register. Contains the four interrupt request flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="THCMP0" description="Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="1" size="1" name="THCMP1" description="Threshold comparison event on Channel 1. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="2" size="1" name="THCMP2" description="Threshold comparison event on Channel 2. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="3" size="1" name="THCMP3" description="Threshold comparison event on Channel 3. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="4" size="1" name="THCMP4" description="Threshold comparison event on Channel 4. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="5" size="1" name="THCMP5" description="Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="6" size="1" name="THCMP6" description="Threshold comparison event on Channel 6. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="7" size="1" name="THCMP7" description="Threshold comparison event on Channel 7. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="8" size="1" name="THCMP8" description="Threshold comparison event on Channel 8. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="9" size="1" name="THCMP9" description="Threshold comparison event on Channel 9. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="10" size="1" name="THCMP10" description="Threshold comparison event on Channel 10. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="11" size="1" name="THCMP11" description="Threshold comparison event on Channel 11. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1." />
-      <BitField start="12" size="1" name="OVERRUN0" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 0" />
-      <BitField start="13" size="1" name="OVERRUN1" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 1" />
-      <BitField start="14" size="1" name="OVERRUN2" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 2" />
-      <BitField start="15" size="1" name="OVERRUN3" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 3" />
-      <BitField start="16" size="1" name="OVERRUN4" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 4" />
-      <BitField start="17" size="1" name="OVERRUN5" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 5" />
-      <BitField start="18" size="1" name="OVERRUN6" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 6" />
-      <BitField start="19" size="1" name="OVERRUN7" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 7" />
-      <BitField start="20" size="1" name="OVERRUN8" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 8" />
-      <BitField start="21" size="1" name="OVERRUN9" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 9" />
-      <BitField start="22" size="1" name="OVERRUN10" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 10" />
-      <BitField start="23" size="1" name="OVERRUN11" description="Mirrors the OVERRRUN status flag from the result register for A/D channel 11" />
-      <BitField start="24" size="1" name="SEQA_OVR" description="Mirrors the global OVERRUN status flag in the SEQA_GDAT register" />
-      <BitField start="25" size="1" name="SEQB_OVR" description="Mirrors the global OVERRUN status flag in the SEQB_GDAT register" />
-      <BitField start="26" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="28" size="1" name="SEQA_INT" description="Sequence A interrupt/DMA flag. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every A/D conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit.  This interrupt must be enabled in the INTEN register." />
-      <BitField start="29" size="1" name="SEQB_INT" description="Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit.  This interrupt must be enabled in the INTEN register." />
-      <BitField start="30" size="1" name="THCMP_INT" description="Threshold Comparison Interrupt/DMA flag. This bit will be set if any of the 12 THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the component flags in bits 11:0 are cleared via writing 1s to those bits." />
-      <BitField start="31" size="1" name="OVR_INT" description="Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt.  This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers." />
-    </Register>
-    <Register start="+0x06C" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0x00000F00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="VRANGE" description="Reserved.">
-        <Enum name="HIGH_VOLTAGE" start="0" description="High voltage. VDDA = 2.7 V to 3.6 V." />
-        <Enum name="LOW_VOLTAGE" start="1" description="Low voltage. VDDA = 1.8 V to 2.7 V." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x40020000" description="I2C1">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="STATUS" description="These bits give the actual status information about the I2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40024000" description="Real-Time Clock (RTC)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="RTC control register" reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRESET" description="Software reset control">
-        <Enum name="NOT_IN_RESET" start="0" description="Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC." />
-        <Enum name="IN_RESET" start="1" description="In reset. The RTC is held in reset.     All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register.   Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. This bit may also serve as a Power Fail Detect flag for the always-on voltage domain." />
-      </BitField>
-      <BitField start="1" size="1" name="OFD" description="Oscillator fail detect status.">
-        <Enum name="RUN" start="0" description="Run. The RTC oscillator is running properly. Writing a 0 has no effect." />
-        <Enum name="FAIL" start="1" description="Fail. RTC oscillator fail detected. Clear this flag after the following power-up. Writing a 1 clears this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="ALARM1HZ" description="RTC 1 Hz timer alarm flag status.">
-        <Enum name="NO_MATCH" start="0" description="No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect." />
-        <Enum name="MATCH" start="1" description="Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKE1KHZ" description="RTC 1 kHz timer wake-up flag status.">
-        <Enum name="RUN" start="0" description="Run. The RTC 1 kHz timer is running. Writing a 0 has no effect." />
-        <Enum name="TIME_OUT" start="1" description="Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit." />
-      </BitField>
-      <BitField start="4" size="1" name="ALARMDPD_EN" description="RTC 1 Hz timer alarm enable for Deep power-down.">
-        <Enum name="DISABLE" start="0" description="Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode." />
-        <Enum name="ENABLE" start="1" description="Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode." />
-      </BitField>
-      <BitField start="5" size="1" name="WAKEDPD_EN" description="RTC 1 kHz timer wake-up enable for Deep power-down.">
-        <Enum name="DISABLE" start="0" description="Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode." />
-        <Enum name="ENABLE" start="1" description="Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode." />
-      </BitField>
-      <BitField start="6" size="1" name="RTC1KHZ_EN" description="RTC 1 kHz clock enable.  This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).">
-        <Enum name="DISABLE" start="0" description="Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode." />
-        <Enum name="ENABLE" start="1" description="Enable. The 1 kHz RTC timer is enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RTC_EN" description="RTC enable.">
-        <Enum name="DISABLE" start="0" description="Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register." />
-        <Enum name="ENABLE" start="1" description="Enable. The 1 Hz RTC clock is running and RTC operation is enabled. You must set this bit to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="MATCH" access="Read/Write" description="RTC match register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATVAL" description="Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled." />
-    </Register>
-    <Register start="+0x008" size="4" name="COUNT" access="Read/Write" description="RTC counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer.  The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC1HZ_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC1HZ_EN bit is set." />
-    </Register>
-    <Register start="+0x00C" size="4" name="WAKE" access="Read/Write" description="RTC high-resolution/wake-up timer control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VAL" description="A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence.   Do not write to this register while counting is in progress." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMATRIGMUX" start="0x40028000" description="DMA controller">
-    <Register start="+0x000+0" size="4" name="DMA_ITRIG_PINMUX[0]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="DMA_ITRIG_PINMUX[1]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="DMA_ITRIG_PINMUX[2]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="DMA_ITRIG_PINMUX[3]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+16" size="4" name="DMA_ITRIG_PINMUX[4]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+20" size="4" name="DMA_ITRIG_PINMUX[5]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+24" size="4" name="DMA_ITRIG_PINMUX[6]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+28" size="4" name="DMA_ITRIG_PINMUX[7]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="DMA_ITRIG_PINMUX[8]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+36" size="4" name="DMA_ITRIG_PINMUX[9]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+40" size="4" name="DMA_ITRIG_PINMUX[10]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+44" size="4" name="DMA_ITRIG_PINMUX[11]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+48" size="4" name="DMA_ITRIG_PINMUX[12]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+52" size="4" name="DMA_ITRIG_PINMUX[13]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+56" size="4" name="DMA_ITRIG_PINMUX[14]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+60" size="4" name="DMA_ITRIG_PINMUX[15]" access="Read/Write" description="Trigger input select register for DMA channel 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INP_N" description="Trigger input number (decimal value) to DMA channel n. All other values are reserved.  0&#x9; = ADC0_SEQA_IRQ 1 = &#x9;ADC0_SEQB_IRQ 2&#x9; = CT16B0_MAT0 3 = &#x9;CT16B1_MAT0 4&#x9; = CT32B0_MAT0 5&#x9; = CT16B1_MAT0 6&#x9; = PINT0 ( pin interrupt 0) 7 = &#x9;PINT1 (pin interrupt1 ) 8 = &#x9;SCT0_DMA0 9 = &#x9;SCT0_DMA1 10&#x9; = SCT1_DMA0 11&#x9; = SCT1_DMA1" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMU" start="0x40038000" description="Power Management Unit (PMU)">
-    <Register start="+0x000" size="4" name="PCON" access="Read/Write" description="Power control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PM" description="Power mode">
-        <Enum name="DEFAULT" start="0x0" description="Default. The part is in active or sleep mode." />
-        <Enum name="DEEP_SLEEP" start="0x1" description="Deep-sleep. ARM WFI will enter Deep-sleep mode." />
-        <Enum name="POWER_DOWN" start="0x2" description="Power-down. ARM WFI will enter Power-down mode." />
-        <Enum name="DEEP_POWER_DOWN" start="0x3" description="Deep power-down. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down)." />
-      </BitField>
-      <BitField start="3" size="1" name="NODPD" description="A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed.   This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-      <BitField start="8" size="1" name="SLEEPFLAG" description="Sleep mode flag">
-        <Enum name="ACTIVE_MODE" start="0" description="Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect." />
-        <Enum name="LOW_POWER_MODE" start="1" description="Low power mode. Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0." />
-      </BitField>
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep power-down flag">
-        <Enum name="NOT_DEEP_POWER_DOWN" start="0" description="Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect." />
-        <Enum name="DEEP_POWER_DOWN" start="1" description="Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-    </Register>
-    <Register start="+0x004+0" size="4" name="GPREG0" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x004+4" size="4" name="GPREG1" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x004+8" size="4" name="GPREG2" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x004+12" size="4" name="GPREG3" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x014" size="4" name="GPREG4" access="Read/Write" description="Deep power down control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-      <BitField start="10" size="1" name="WAKEUPHYS" description="WAKEUP pin hysteresis enable">
-        <Enum name="DISABLE_HYSTERESIS_F" start="0" description="Disable Hysteresis for WAKUP pin disabled." />
-        <Enum name="ENABLE" start="1" description="Enable. Hysteresis for WAKEUP pin enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="WAKEPAD_DISABLE" description="WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the RTC wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used.">
-        <Enum name="ENABLE" start="0" description="Enable. The wake-up function is enabled on pin PIO0_16." />
-        <Enum name="DISABLE" start="1" description="Disable. Setting this bit disables the wake-up function on pin PIO0_16." />
-      </BitField>
-      <BitField start="12" size="20" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FLASHCTRL" start="0x4003C000" description=" Flash controller ">
-    <Register start="+0x010" size="4" name="FLASHCFG" access="Read/Write" description="Flash configuration register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="FLASHTIM" description="Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.">
-        <Enum name="1_SYSTEM_CLOCK_FLASH" start="0x0" description="1 system clock flash access time (for system clock frequencies of up to 20 MHz)." />
-        <Enum name="2_SYSTEM_CLOCKS_FLAS" start="0x1" description="2 system clocks flash access time (for system clock frequencies of up to 30 MHz)." />
-        <Enum name="RESERVED_" start="0x2" description="Reserved." />
-        <Enum name="RESERVED_" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read." />
-    </Register>
-    <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="STOPA" description="Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes.  If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111." />
-      <BitField start="17" size="1" name="STRTBIST" description="When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="Signature Word " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SIG" description="32-bit signature." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40040000" description="SSP/SPI ">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
-        <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
-        <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SPI Enable.">
-        <Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="IOCON" start="0x40044000" description="I/O control (IOCON) ">
-    <Register start="+0x000+0" size="4" name="PIO0_0" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="PIO0_1" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="PIO0_2" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="PIO0_3" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="PIO0_4" access="Read/Write" description="I/O configuration for open-drain pin PIO0_4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. " />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see  Section 7.3.8).  Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).">
-        <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
-        <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
-        <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="PIO0_5" access="Read/Write" description="I/O configuration for open-drain pin PIO0_5" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. " />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see  Section 7.3.8).  Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).">
-        <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
-        <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
-        <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="PIO0_6" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="PIO0_7" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="PIO0_8" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="PIO0_9" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+16" size="4" name="PIO0_10" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+20" size="4" name="PIO0_11" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+24" size="4" name="PIO0_12" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+28" size="4" name="PIO0_13" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+32" size="4" name="PIO0_14" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+36" size="4" name="PIO0_15" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+40" size="4" name="PIO0_16" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+44" size="4" name="PIO0_17" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+48" size="4" name="PIO0_18" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+52" size="4" name="PIO0_19" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+56" size="4" name="PIO0_20" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+60" size="4" name="PIO0_21" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+64" size="4" name="PIO0_22" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+68" size="4" name="PIO0_23" access="Read/Write" description="I/O configuration for  port PIO0" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+0" size="4" name="PIO1_0" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+4" size="4" name="PIO1_1" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+8" size="4" name="PIO1_2" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+12" size="4" name="PIO1_3" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+16" size="4" name="PIO1_4" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+20" size="4" name="PIO1_5" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+24" size="4" name="PIO1_6" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+28" size="4" name="PIO1_7" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+32" size="4" name="PIO1_8" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+36" size="4" name="PIO1_9" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+40" size="4" name="PIO1_10" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+44" size="4" name="PIO1_11" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+48" size="4" name="PIO1_12" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+52" size="4" name="PIO1_13" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+56" size="4" name="PIO1_14" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+60" size="4" name="PIO1_15" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+64" size="4" name="PIO1_16" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+68" size="4" name="PIO1_17" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+72" size="4" name="PIO1_18" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+76" size="4" name="PIO1_19" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+80" size="4" name="PIO1_20" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+84" size="4" name="PIO1_21" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+88" size="4" name="PIO1_22" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+92" size="4" name="PIO1_23" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+96" size="4" name="PIO1_24" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+100" size="4" name="PIO1_25" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+104" size="4" name="PIO1_26" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+108" size="4" name="PIO1_27" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+112" size="4" name="PIO1_28" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+116" size="4" name="PIO1_29" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+120" size="4" name="PIO1_30" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060+124" size="4" name="PIO1_31" access="Read/Write" description="I/O configuration for port PIO1" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F0+0" size="4" name="PIO2_0" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F0+4" size="4" name="PIO2_1" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+0" size="4" name="PIO2_2" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+4" size="4" name="PIO2_3" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+8" size="4" name="PIO2_4" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+12" size="4" name="PIO2_5" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+16" size="4" name="PIO2_6" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+20" size="4" name="PIO2_7" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+24" size="4" name="PIO2_8" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+28" size="4" name="PIO2_9" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+32" size="4" name="PIO2_10" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+36" size="4" name="PIO2_11" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+40" size="4" name="PIO2_12" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+44" size="4" name="PIO2_13" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+48" size="4" name="PIO2_14" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+52" size="4" name="PIO2_15" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+56" size="4" name="PIO2_16" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+60" size="4" name="PIO2_17" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+64" size="4" name="PIO2_18" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+68" size="4" name="PIO2_19" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+72" size="4" name="PIO2_20" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+76" size="4" name="PIO2_21" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+80" size="4" name="PIO2_22" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0FC+84" size="4" name="PIO2_23" access="Read/Write" description="I/O configuration for port PIO2" reset_value="0x00000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function." />
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLE" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED" start="0" description="Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE" start="0" description="Disable." />
-        <Enum name="ENABLED" start="1" description="Enabled. Open-drain mode enabled.  This is not a true open-drain mode." />
-      </BitField>
-      <BitField start="11" size="2" name="S_MODE" description="Digital filter sample mode.">
-        <Enum name="BYPASS_INPUT_FILTER" start="0x0" description="Bypass input filter." />
-        <Enum name="1_CLOCK_CYCLE" start="0x1" description="1 clock cycle. Input pulses shorter than one filter clock are rejected." />
-        <Enum name="2_CLOCK_CYCLES" start="0x2" description="2 clock cycles. Input pulses shorter than two filter clocks are rejected." />
-        <Enum name="3_CLOCK_CYCLES" start="0x3" description="3 clock cycles. Input pulses shorter than three filter clocks are rejected." />
-      </BitField>
-      <BitField start="13" size="3" name="CLKDIV" description="Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.">
-        <Enum name="IOCONCLKDIV0" start="0x0" description="IOCONCLKDIV0. Use IOCON clock divider 0." />
-        <Enum name="IOCONCLKDIV1" start="0x1" description="IOCONCLKDIV1. Use IOCON clock divider 1." />
-        <Enum name="IOCONCLKDIV2" start="0x2" description="IOCONCLKDIV2 Use IOCON clock divider 2." />
-        <Enum name="IOCONCLKDIV3" start="0x3" description="IOCONCLKDIV3. Use IOCON clock divider 3." />
-        <Enum name="IOCONCLKDIV4" start="0x4" description="IOCONCLKDIV4. Use IOCON clock divider 4." />
-        <Enum name="IOCONCLKDIV5" start="0x5" description="IOCONCLKDIV5. Use IOCON clock divider 5." />
-        <Enum name="IOCONCLKDIV6" start="0x6" description="IOCONCLKDIV6. Use IOCON clock divider 6." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x40048000" description="System configuration (SYSCON)">
-    <Register start="+0x000" size="4" name="SYSMEMREMAP" access="Read/Write" description="System memory remap" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MAP" description="System memory remap. Value 0x3 is reserved.">
-        <Enum name="BOOT_LOADER_MODE" start="0x0" description="Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM." />
-        <Enum name="USER_RAM_MODE" start="0x1" description="User RAM Mode. Interrupt vectors are re-mapped to Static RAM." />
-        <Enum name="USER_FLASH_MODE" start="0x2" description="User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESETCTRL" access="Read/Write" description="Peripheral reset control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSP0_RST_N" description="SSP0 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the SSP0 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. SSP0 reset de-asserted." />
-      </BitField>
-      <BitField start="1" size="1" name="I2C0_RST_N" description="I2C0 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the I2C0 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. I2C0 reset de-asserted." />
-      </BitField>
-      <BitField start="2" size="1" name="SSP1_RST_N" description="SSP1 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the SSP1 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. SSP1 reset de-asserted." />
-      </BitField>
-      <BitField start="3" size="1" name="I2C1_RST_N" description="I2C1 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the I2C1 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. I2C1 reset de-asserted." />
-      </BitField>
-      <BitField start="4" size="1" name="FRG_RST_N" description="FRG reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the FRG peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. FRG reset de-asserted." />
-      </BitField>
-      <BitField start="5" size="1" name="USART1_RST_N" description="USART1 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the USART1 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART1 reset de-asserted." />
-      </BitField>
-      <BitField start="6" size="1" name="USART2_RST_N" description="USART2 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the USART2 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART2 reset de-asserted." />
-      </BitField>
-      <BitField start="7" size="1" name="USART3_RST_N" description="USART3 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the USART3 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART3 reset de-asserted." />
-      </BitField>
-      <BitField start="8" size="1" name="USART4_RST_N" description="USART4 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the USART4 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. USART4 reset de-asserted." />
-      </BitField>
-      <BitField start="9" size="1" name="SCT0_RST_N" description="SCT0 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the SCT0 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. SCT0 reset de-asserted." />
-      </BitField>
-      <BitField start="10" size="1" name="SCT1_RST_N" description="SCT1 reset control">
-        <Enum name="RESET" start="0" description="Reset. Resets the SCT1 peripheral." />
-        <Enum name="CLEAR_RESET" start="1" description="Clear reset. SCT1 reset de-asserted." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="SYSPLLCTRL" access="Read/Write" description="System PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
-      <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
-        <Enum name="P_EQ_1" start="0x0" description="P = 1" />
-        <Enum name="P_EQ_2" start="0x1" description="P = 2" />
-        <Enum name="P_EQ_4" start="0x2" description="P = 4" />
-        <Enum name="P_EQ_8" start="0x3" description="P = 8" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SYSPLLSTAT" access="ReadOnly" description="System PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL lock status">
-        <Enum name="NO_LOCK" start="0" description="No lock. PLL not locked" />
-        <Enum name="LOCK" start="1" description="Lock. PLL locked" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="USBPLLCTRL" access="Read/Write" description="USB PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1.  00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
-      <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
-        <Enum name="P_EQ_1" start="0x0" description="P = 1" />
-        <Enum name="P_EQ_2" start="0x1" description="P = 2" />
-        <Enum name="P_EQ_4" start="0x2" description="P = 4" />
-        <Enum name="P_EQ_8" start="0x3" description="P = 8" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x014" size="4" name="USBPLLSTAT" access="ReadOnly" description="USB PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL lock status">
-        <Enum name="NO_LOCK" start="0" description="No lock. PLL not locked" />
-        <Enum name="LOCK" start="1" description="Lock. PLL locked" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="RTCOSCCTRL" access="Read/Write" description="RTC oscillator 32 kHz output control" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCOSCEN" description="Enable the RTC 32 kHz output.">
-        <Enum name="DISABLED" start="0" description="Disabled. 32 kHz output disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. 32 kHz output enabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="SYSOSCCTRL" access="Read/Write" description="System oscillator control" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BYPASS" description="Bypass system oscillator">
-        <Enum name="OSCILLATOR_IS_NOT_BY" start="0" description="Oscillator is not bypassed." />
-        <Enum name="BYPASS_ENABLED" start="1" description="Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator." />
-      </BitField>
-      <BitField start="1" size="1" name="FREQRANGE" description="Determines frequency range for Low-power oscillator.">
-        <Enum name="LOW" start="0" description="Low. 1 - 20 MHz frequency range." />
-        <Enum name="HIGH" start="1" description="High. 15 - 25 MHz frequency range." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="WDTOSCCTRL" access="Read/Write" description="Watchdog oscillator control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DIVSEL" description="Select divider for Fclkana.  wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64" />
-      <BitField start="5" size="4" name="FREQSEL" description="Select watchdog oscillator analog output frequency (Fclkana).">
-        <Enum name="0" start="0x1" description="0.6 MHz" />
-        <Enum name="1" start="0x2" description="1.05 MHz" />
-        <Enum name="1" start="0x3" description="1.4 MHz" />
-        <Enum name="1" start="0x4" description="1.75 MHz" />
-        <Enum name="2" start="0x5" description="2.1 MHz" />
-        <Enum name="2" start="0x6" description="2.4 MHz" />
-        <Enum name="2" start="0x7" description="2.7 MHz" />
-        <Enum name="3" start="0x8" description="3.0 MHz" />
-        <Enum name="3" start="0x9" description="3.25 MHz" />
-        <Enum name="3" start="0xA" description="3.5 MHz" />
-        <Enum name="3" start="0xB" description="3.75 MHz" />
-        <Enum name="4" start="0xC" description="4.0 MHz" />
-        <Enum name="4" start="0xD" description="4.2 MHz" />
-        <Enum name="4" start="0xE" description="4.4 MHz" />
-        <Enum name="4" start="0xF" description="4.6 MHz" />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="IRCCTRL" access="Read/Write" description="IRC control" reset_value="0x080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TRIM" description="Trim value" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="SYSRSTSTAT" access="Read/Write" description="System reset status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POR" description="POR reset status">
-        <Enum name="NO_POR_DETECTED" start="0" description="No POR detected" />
-        <Enum name="POR_DETECTED" start="1" description="POR detected" />
-      </BitField>
-      <BitField start="1" size="1" name="EXTRST" description="Status of the external RESET pin">
-        <Enum name="NO_RESET_EVENT_DETEC" start="0" description="No reset event detected" />
-        <Enum name="RESET_DETECTED" start="1" description="Reset detected" />
-      </BitField>
-      <BitField start="2" size="1" name="WDT" description="Status of the Watchdog reset">
-        <Enum name="NO_WDT_RESET_DETECTE" start="0" description="No WDT reset detected" />
-        <Enum name="WDT_RESET_DETECTED" start="1" description="WDT reset detected" />
-      </BitField>
-      <BitField start="3" size="1" name="BOD" description="Status of the Brown-out detect reset">
-        <Enum name="NO_BOD_RESET_DETECTE" start="0" description="No BOD reset detected" />
-        <Enum name="BOD_RESET_DETECTED" start="1" description="BOD reset detected" />
-      </BitField>
-      <BitField start="4" size="1" name="SYSRST" description="Status of the software system reset">
-        <Enum name="NO_SYSTEM_RESET_DETE" start="0" description="No System reset detected" />
-        <Enum name="SYSTEM_RESET_DETECTE" start="1" description="System reset detected" />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="SYSPLLCLKSEL" access="Read/Write" description="System PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="System PLL clock source">
-        <Enum name="IRC" start="0x0" description="IRC" />
-        <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator. Crystal Oscillator (SYSOSC)" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="32_KHZ_CLOCK" start="0x3" description="32 kHz clock.Select this option when the 32 kHz clock is the clock source for the main clock and select the pll input in the MAINCLKSEL register. Do not use the 32 kHz clock with the PLL." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="SYSPLLCLKUEN" access="Read/Write" description="System PLL clock source update enable" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA" description="Enable system PLL clock source update">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="USBPLLCLKSEL" access="Read/Write" description="USB PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="USB PLL clock source">
-        <Enum name="IRC" start="0x0" description="IRC. For full-speed USB, switch the USB PLL clock source to the system oscillator for correct USB operation. The IRC is  suitable for low-speed USB operation only." />
-        <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="USBPLLCLKUEN" access="Read/Write" description="USB PLL clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA" description="Enable USB PLL clock source update">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="MAINCLKSEL" access="Read/Write" description="Main clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="Clock source for main clock">
-        <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC Oscillator" />
-        <Enum name="PLL_INPUT" start="0x1" description="PLL input" />
-        <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
-        <Enum name="PLL_OUTPUT" start="0x3" description="PLL output" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="MAINCLKUEN" access="Read/Write" description="Main clock source update enable" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA" description="Enable main clock source update">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="SYSAHBCLKDIV" access="Read/Write" description="System clock divider" reset_value="0x001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="System AHB clock divider values  0: System clock disabled.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="SYSAHBCLKCTRL" access="Read/Write" description="System clock control" reset_value="0x3F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYS" description="This bit is read-only and always reads as 1. It configures the  always-on clock for the AHB, the APB bridges, the Cortex-M0 core clocks, SYSCON, reset control, SRAM0, and the PMU. Writes to this bit are ignored." />
-      <BitField start="1" size="1" name="ROM" description="Enables clock for ROM.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="RAM0" description="Enables clock for Main SRAM0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="FLASHREG" description="Enables clock for flash register interface.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="FLASHARRAY" description="Enables clock for flash access.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="I2C0" description="Enables clock for I2C.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="GPIO" description="Enables clock for GPIO port registers.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="CT16B0" description="Enables clock for 16-bit counter/timer 0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="CT16B1" description="Enables clock for 16-bit counter/timer 1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="CT32B0" description="Enables clock for 32-bit counter/timer 0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="CT32B1" description="Enables clock for 32-bit counter/timer 1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="SSP0" description="Enables clock for SSP0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="USART0" description="Enables clock for USART0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="ADC" description="Enables clock for ADC.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="USB" description="Enables clock to the USB register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="WWDT" description="Enables clock for WWDT.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="IOCON" description="Enables clock for I/O configuration block.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="SSP1" description="Enables clock for SSP1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="PINT" description="Enables clock to GPIO Pin interrupt register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="USART1" description="Enables clock to USART1 register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="21" size="1" name="USART2" description="Enables clock to USART2 register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="USART3_4" description="Enables clock to USART3 and USART4 register interfaces.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="GROUP0INT" description="Enables clock to GPIO GROUP0 interrupt register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="GROUP1INT" description="Enables clock to GPIO GROUP1 interrupt register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="I2C1" description="Enables clock for I2C1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="RAM1" description="Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="27" size="1" name="USBSRAM" description="Enables USB SRAM/SRAM2 block located at 0x2000 4000 to 0x2000 4800.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="28" size="1" name="CRC" description="Enables clock for CRC.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="29" size="1" name="DMA" description="Enables clock for DMA.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="30" size="1" name="RTC" description="Enables clock for RTC register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="31" size="1" name="SCT0_1" description="Enables clock for SCT0 and SCT1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x094" size="4" name="SSP0CLKDIV" access="Read/Write" description="SSP0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="SPI0_PCLK clock divider values.  0: System clock disabled.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="USART0CLKDIV" access="Read/Write" description="USART0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="UART_PCLK clock divider values  0: Disable UART_PCLK.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="SSP1CLKDIV" access="Read/Write" description="SSP1 clock divider" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="SSP1_PCLK clock divider values  0: Disable SSP1_PCLK.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="FRGCLKDIV" access="Read/Write" description="Clock divider for the common fractional baud rate generator of USART1, USART2, USART3, USART4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="USART fractional baud rate generator clock divider values.  0: Clock disabled.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="USBCLKSEL" access="Read/Write" description="USB clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="USB clock source. Values 0x2 and 0x3 are reserved.">
-        <Enum name="USB_PLL_OUT" start="0x0" description="USB PLL out" />
-        <Enum name="MAIN_CLOCK" start="0x1" description="Main clock" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="USBCLKUEN" access="Read/Write" description="USB clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA" description="Enable USB clock source update">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="USBCLKDIV" access="Read/Write" description="USB clock source divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="USB clock divider values  0: Disable USB clock.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0E0" size="4" name="CLKOUTSEL" access="Read/Write" description="CLKOUT clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="CLKOUT clock source">
-        <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC oscillator" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x1" description="Crystal oscillator (SYSOSC)" />
-        <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
-        <Enum name="MAIN_CLOCK" start="0x3" description="Main clock" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0E4" size="4" name="CLKOUTUEN" access="Read/Write" description="CLKOUT clock source update enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA" description="Enable CLKOUT clock source update">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="UPDATE_CLOCK_SOURCE" start="1" description="Update clock source" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0E8" size="4" name="CLKOUTDIV" access="Read/Write" description="CLKOUT clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="CLKOUT clock divider values  0: Disable CLKOUT clock divider.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F0" size="4" name="UARTFRGDIV" access="Read/Write" description="USART fractional generator divider value" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="UARTFRGMULT" access="Read/Write" description="USART fractional generator multiplier value" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MULT" description="Numerator of the fractional divider. MULT is equal to the programmed value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="EXTTRACECMD" access="Read/Write" description="External trace buffer command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well." />
-      <BitField start="1" size="1" name="STOP" description="Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="PIOPORCAP0" access="ReadOnly" description="POR captured PIO status 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="PIOSTAT" description="State of PIO0_23 through PIO0_0 at power-on reset" />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="PIOPORCAP1" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PIOSTAT" description="State of PIO1_31 through PIO1_0 at power-on reset" />
-    </Register>
-    <Register start="+0x108" size="4" name="PIOPORCAP2" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="PIOSTAT" description="State of PIO2_23 through PIO2_0 at power-on reset" />
-    </Register>
-    <Register start="+0x134" size="4" name="IOCONCLKDIV6" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x138" size="4" name="IOCONCLKDIV5" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x13C" size="4" name="IOCONCLKDIV4" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IOCONCLKDIV3" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IOCONCLKDIV2" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="IOCONCLKDIV1" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="IOCONCLKDIV0" access="Read/Write" description="Peripheral clock  to the IOCON block for programmable glitch filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x150" size="4" name="BODCTRL" access="Read/Write" description="Brown-Out Detect" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BODRSTLEV" description="BOD reset level">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3." />
-      </BitField>
-      <BitField start="2" size="2" name="BODINTVAL" description="BOD interrupt level">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3." />
-      </BitField>
-      <BitField start="4" size="1" name="BODRSTENA" description="BOD reset enable">
-        <Enum name="DISABLE_RESET_FUNCTI" start="0" description="Disable reset function." />
-        <Enum name="ENABLE_RESET_FUNCTIO" start="1" description="Enable reset function." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="SYSTCKCAL" access="Read/Write" description="System tick counter calibration" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="26" name="CAL" description="System tick timer calibration value" />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="IRQLATENCY" access="Read/Write" description="IRQ delay. Allows trade-off between interrupt latency and determinism." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LATENCY" description="8-bit latency value" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="NMISRC" access="Read/Write" description="NMI Source Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="IRQN" description="The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 6 for the list of interrupt sources and their IRQ numbers." />
-      <BitField start="5" size="26" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="NMIEN" description="Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." />
-    </Register>
-    <Register start="+0x178+0" size="4" name="PINTSEL0" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+4" size="4" name="PINTSEL1" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+8" size="4" name="PINTSEL2" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+12" size="4" name="PINTSEL3" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+16" size="4" name="PINTSEL4" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+20" size="4" name="PINTSEL5" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+24" size="4" name="PINTSEL6" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+28" size="4" name="PINTSEL7" access="Read/Write" description="GPIO Pin Interrupt Select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="INTPIN" description="Pin number. PIO0_0 = 0, ..., PIO0_23 = 23, PIO1_0 = 24, ..., PIO1_31 = 55, PIO2_0 = 56, ..., PIO2_7 = 63." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x198" size="4" name="USBCLKCTRL" access="Read/Write" description="USB clock control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="AP_CLK" description="USB need_clock signal control">
-        <Enum name="HARDWARE" start="0" description="Hardware. Under hardware control." />
-        <Enum name="FORCED" start="1" description="Forced. Forced HIGH." />
-      </BitField>
-      <BitField start="1" size="1" name="POL_CLK" description="USB need_clock polarity for triggering the USB wake-up interrupt">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. Falling edge of the USB need_clock triggers the USB wake-up (default)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. Rising edge of the USB need_clock triggers the USB wake-up." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Only write 0 to this bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x19C" size="4" name="USBCLKST" access="ReadOnly" description="USB clock status" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NEED_CLKST" description="USB need_clock signal status">
-        <Enum name="LOW" start="0" description="LOW" />
-        <Enum name="HIGH" start="1" description="HIGH" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="STARTERP0" access="Read/Write" description="Start logic 0 interrupt wake-up enable register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINT0" description="Pin interrupt 0 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="PINT1" description="Pin interrupt 1 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="PINT2" description="Pin interrupt 2 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="PINT3" description="Pin interrupt 3 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="PINT4" description="Pin interrupt 4 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="PINT5" description="Pin interrupt 5 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PINT6" description="Pin interrupt 6 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="PINT7" description="Pin interrupt 7 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x214" size="4" name="STARTERP1" access="Read/Write" description="Start logic 1 interrupt wake-up enable register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="RTCINT" description="RTC interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="WWDT_BODINT" description="Combined WWDT interrupt or Brown Out Detect (BOD) interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="14" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="USB_WAKEUP" description="USB need_clock signal wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="GROUP0INT" description="GPIO GROUP0 interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="GROUP1INT" description="GPIO GROUP1 interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="23" size="1" name="USART1_4" description="Combined USART1 and USART4 interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="USART2_3" description="Combined USART2 and USART3 interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x230" size="4" name="PDSLEEPCFG" access="Read/Write" description="Power-down states in deep-sleep mode" reset_value="0" reset_mask="0x00000000">
-      <BitField start="3" size="1" name="BOD_PD" description="BOD power-down control for Deep-sleep and Power-down mode">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down control for Deep-sleep and Power-down mode">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x234" size="4" name="PDAWAKECFG" access="Read/Write" description="Power-down states for wake-up from deep-sleep" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="2" size="1" name="FLASH_PD" description="Flash wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="3" size="1" name="BOD_PD" description="BOD wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="4" size="1" name="ADC_PD" description="ADC wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL wake-up configuration">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver wake-up configuration">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="TEMPSENSE_PD" description="Temperature sensor wake-up configuration">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x238" size="4" name="PDRUNCFG" access="Read/Write" description="Power configuration register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="2" size="1" name="FLASH_PD" description="Flash power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="3" size="1" name="BOD_PD" description="BOD power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="4" size="1" name="ADC_PD" description="ADC power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator power-down. After power-up, add a software delay of approximately 500 us before using.">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver power-down configuration">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="TEMPSENSE_PD" description="Temperature sensor wake-up configuration">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. Always write these bits as 0b11." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x3F4" size="4" name="DEVICE_ID" access="ReadOnly" description="Device ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="DEVICEID" description="PARTID" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART4" start="0x4004C000" description="USART4 ">
-    <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="USART Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if  enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
-        <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
-        <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
-        <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
-        <Enum name="NO_PARITY" start="0x0" description="No parity." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
-        <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
-      </BitField>
-      <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
-      </BitField>
-      <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
-        <Enum name="STANDARD" start="0" description="UART uses standard clocking." />
-        <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
-        <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
-        <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses  the CTS input (or RTS output in loopback mode) for flow control purposes." />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
-        <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
-        <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
-      </BitField>
-      <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
-        <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
-        <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
-      </BitField>
-      <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
-      </BitField>
-      <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
-        <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
-        <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
-      </BitField>
-      <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
-        <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
-      </BitField>
-      <BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
-        <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
-        <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
-      </BitField>
-      <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
-        <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
-        <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
-      </BitField>
-      <BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
-      </BitField>
-      <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
-        <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
-        <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
-      </BitField>
-      <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
-        <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
-        <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
-      <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when  the data is moved from the transmit buffer to the transmit shift register." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
-      <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
-      <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
-      <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
-      <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
-      <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
-      <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
-      <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
-      <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
-      <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
-      <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
-      <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit.  ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40058000" description="SSP1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
-        <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
-        <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SPI Enable.">
-        <Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GINT0" start="0x4005C000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL[0]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL[1]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL[2]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA[0]" access="Read/Write" description="GPIO grouped interrupt port  enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA[1]" access="Read/Write" description="GPIO grouped interrupt port  enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA[2]" access="Read/Write" description="GPIO grouped interrupt port  enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GINT1" start="0x40060000" description="GINT1">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL[0]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL[1]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL[2]" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL0" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA[0]" access="Read/Write" description="GPIO grouped interrupt port  enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA[1]" access="Read/Write" description="GPIO grouped interrupt port  enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA[2]" access="Read/Write" description="GPIO grouped interrupt port  enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA1" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA2" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA3" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA4" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA5" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA6" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA7" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA8" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA9" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA10" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA11" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA12" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA13" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA14" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA15" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA16" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA17" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA18" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA19" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA20" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA21" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA22" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA23" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA24" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA25" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA26" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA27" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA28" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA29" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA30" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA31" description="Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART1" start="0x4006C000" description="USART1">
-    <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="USART Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if  enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
-        <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
-        <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
-        <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
-        <Enum name="NO_PARITY" start="0x0" description="No parity." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
-        <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
-      </BitField>
-      <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
-      </BitField>
-      <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
-        <Enum name="STANDARD" start="0" description="UART uses standard clocking." />
-        <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
-        <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
-        <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses  the CTS input (or RTS output in loopback mode) for flow control purposes." />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
-        <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
-        <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
-      </BitField>
-      <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
-        <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
-        <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
-      </BitField>
-      <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
-      </BitField>
-      <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
-        <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
-        <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
-      </BitField>
-      <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
-        <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
-      </BitField>
-      <BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
-        <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
-        <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
-      </BitField>
-      <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
-        <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
-        <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
-      </BitField>
-      <BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
-      </BitField>
-      <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
-        <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
-        <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
-      </BitField>
-      <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
-        <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
-        <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
-      <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when  the data is moved from the transmit buffer to the transmit shift register." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
-      <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
-      <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
-      <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
-      <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
-      <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
-      <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
-      <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
-      <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
-      <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
-      <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
-      <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit.  ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x40070000" description="USART2">
-    <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="USART Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if  enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
-        <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
-        <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
-        <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
-        <Enum name="NO_PARITY" start="0x0" description="No parity." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
-        <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
-      </BitField>
-      <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
-      </BitField>
-      <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
-        <Enum name="STANDARD" start="0" description="UART uses standard clocking." />
-        <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
-        <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
-        <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses  the CTS input (or RTS output in loopback mode) for flow control purposes." />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
-        <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
-        <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
-      </BitField>
-      <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
-        <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
-        <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
-      </BitField>
-      <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
-      </BitField>
-      <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
-        <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
-        <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
-      </BitField>
-      <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
-        <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
-      </BitField>
-      <BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
-        <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
-        <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
-      </BitField>
-      <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
-        <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
-        <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
-      </BitField>
-      <BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
-      </BitField>
-      <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
-        <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
-        <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
-      </BitField>
-      <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
-        <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
-        <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
-      <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when  the data is moved from the transmit buffer to the transmit shift register." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
-      <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
-      <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
-      <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
-      <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
-      <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
-      <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
-      <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
-      <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
-      <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
-      <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
-      <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit.  ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x40074000" description="USART3">
-    <Register start="+0x000" size="4" name="CFG" access="Read/Write" description="USART Configuration register. Basic USART configuration settings that typically are not changed during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="USART Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if  enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART is enabled for operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="2" name="DATALEN" description="Selects the data size for the USART.">
-        <Enum name="7_BIT_DATA_LENGTH" start="0x0" description="7 bit Data length." />
-        <Enum name="8_BIT_DATA_LENGTH" start="0x1" description="8 bit Data length." />
-        <Enum name="9_BIT_DATA_LENGTH" start="0x2" description="9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="PARITYSEL" description="Selects what type of parity is used by the USART.">
-        <Enum name="NO_PARITY" start="0x0" description="No parity." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="EVEN_PARITY" start="0x2" description="Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even." />
-        <Enum name="ODD_PARITY" start="0x3" description="Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd." />
-      </BitField>
-      <BitField start="6" size="1" name="STOPLEN" description="Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. This setting should only be used for asynchronous communication." />
-      </BitField>
-      <BitField start="7" size="1" name="MODE32K" description="Selects standard or 32 kHz clocking mode.">
-        <Enum name="STANDARD" start="0" description="UART uses standard clocking." />
-        <Enum name="32KHZ" start="1" description="UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="CTSEN" description="CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 11.8.4 for more information.">
-        <Enum name="NO_FLOW_CONTROL" start="0" description="No flow control. The transmitter does not receive any automatic flow control signal." />
-        <Enum name="FLOW_CONTROL_ENABLED" start="1" description="Flow control enabled. The transmitter uses  the CTS input (or RTS output in loopback mode) for flow control purposes." />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="SYNCEN" description="Selects synchronous or asynchronous operation.">
-        <Enum name="ASYNCHRONOUS" start="0" description="Asynchronous mode is selected." />
-        <Enum name="SYNCHRONOUS" start="1" description="Synchronous mode is selected." />
-      </BitField>
-      <BitField start="12" size="1" name="CLKPOL" description="Selects the clock polarity and sampling edge of received data in synchronous mode.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. Un_RXD is sampled on the falling edge of SCLK." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. Un_RXD is sampled on the rising edge of SCLK." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SYNCMST" description="Synchronous mode Master select.">
-        <Enum name="SLAVE" start="0" description="Slave. When synchronous mode is enabled, the USART is a slave." />
-        <Enum name="MASTER" start="1" description="Master. When synchronous mode is enabled, the USART is a master." />
-      </BitField>
-      <BitField start="15" size="1" name="LOOP" description="Selects data loopback mode.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="LOOPBACK_MODE" start="1" description="Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN." />
-      </BitField>
-      <BitField start="16" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="18" size="1" name="OETA" description="Output Enable Turnaround time enable for RS-485 operation.">
-        <Enum name="DEASSERTED" start="0" description="Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission." />
-        <Enum name="ASSERTED" start="1" description="Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted." />
-      </BitField>
-      <BitField start="19" size="1" name="AUTOADDR" description="Automatic Address matching enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)." />
-        <Enum name="ENABLED" start="1" description="Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match." />
-      </BitField>
-      <BitField start="20" size="1" name="OESEL" description="Output Enable Select.">
-        <Enum name="FLOW_CONTROL" start="0" description="Flow control. The RTS signal is used as the standard flow control function." />
-        <Enum name="OUTPUT_ENABLE" start="1" description="Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver." />
-      </BitField>
-      <BitField start="21" size="1" name="OEPOL" description="Output Enable Polarity.">
-        <Enum name="LOW" start="0" description="Low. If selected by OESEL, the output enable is active low." />
-        <Enum name="HIGH" start="1" description="High. If selected by OESEL, the output enable is active high." />
-      </BitField>
-      <BitField start="22" size="1" name="RXPOL" description="Receive data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="23" size="1" name="TXPOL" description="Transmit data polarity.">
-        <Enum name="NOT_CHANGED" start="0" description="Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1." />
-        <Enum name="INVERTED" start="1" description="Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTL" access="Read/Write" description="USART Control register. USART control settings that are more likely to change during operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="TXBRKEN" description="Break Enable.">
-        <Enum name="NORMAL_OPERATION" start="0" description="Normal operation." />
-        <Enum name="CONTINUOUS_BREAK_IS" start="1" description="Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN." />
-      </BitField>
-      <BitField start="2" size="1" name="ADDRDET" description="Enable address detect mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. The USART presents all incoming data." />
-        <Enum name="ENABLED" start="1" description="Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="TXDIS" description="Transmit Disable.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled. USART transmitter is not disabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CC" description="Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.">
-        <Enum name="CLOCK_ON_CHARACTER" start="0" description="Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received." />
-        <Enum name="CONTINUOUS_CLOCK" start="1" description="Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)." />
-      </BitField>
-      <BitField start="9" size="1" name="CLRCCONRX" description="Clear Continuous Clock.">
-        <Enum name="NO_EFFECT" start="0" description="No effect on the CC bit." />
-        <Enum name="AUTO_CLEAR" start="1" description="Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="AUTOBAUD" description="Autobaud enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. UART is in normal operating mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. UART is in autobaud mode. This bit should only be set when the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="STAT" access="Read/Write" description="USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them." reset_value="0x000E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers." />
-      <BitField start="1" size="1" name="RXIDLE" description="Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when  the data is moved from the transmit buffer to the transmit shift register." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data." />
-      <BitField start="4" size="1" name="CTS" description="This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software." />
-      <BitField start="6" size="1" name="TXDISSTAT" description="Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="RXBRK" description="Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs. Cleared by software." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error. An auto-baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto-baud time-out." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTENSET" access="Read/Write" description="Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDYEN" description="When 1, enables an interrupt when there is a received character available to be read from the RXDAT register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYEN" description="When 1, enables an interrupt when the TXDAT register is available to take another character to transmit." />
-      <BitField start="3" size="1" name="TXIDLEEN" description="When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1)." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSEN" description="When 1, enables an interrupt when there is a change in the state of the CTS input." />
-      <BitField start="6" size="1" name="TXDISEN" description="When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNEN" description="When 1, enables an interrupt when an overrun error occurred." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKEN" description="When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)." />
-      <BitField start="12" size="1" name="STARTEN" description="When 1, enables an interrupt when a received start bit has been detected." />
-      <BitField start="13" size="1" name="FRAMERREN" description="When 1, enables an interrupt when a framing error has been detected." />
-      <BitField start="14" size="1" name="PARITYERREN" description="When 1, enables an interrupt when a parity error has been detected." />
-      <BitField start="15" size="1" name="RXNOISEEN" description="When 1, enables an interrupt when noise is detected." />
-      <BitField start="16" size="1" name="ABERREN" description="When 1, enables an interrupt when an auto-baud error occurs." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTENCLR" access="WriteOnly" description="Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDYCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="3" size="1" name="TXIDLECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTSCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="6" size="1" name="TXDISINTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRKCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="12" size="1" name="STARTCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="13" size="1" name="FRAMERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="14" size="1" name="PARITYERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="15" size="1" name="RXNOISECLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="16" size="1" name="ABERRCLR" description="Writing 1 clears the corresponding bit in the INTENSET register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RXDAT" access="None" description="Receiver Data register. Contains the last character received." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RXDATSTAT" access="None" description="Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="RXDAT" description="The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings." />
-      <BitField start="9" size="4" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="13" size="1" name="FRAMERR" description="Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source." />
-      <BitField start="14" size="1" name="PARITYERR" description="Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character." />
-      <BitField start="15" size="1" name="RXNOISE" description="Received Noise flag. See description of the RXNOISEINT bit in Table 133." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="TXDAT" access="Read/Write" description="Transmit Data register. Data to be transmitted is written here." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="TXDAT" description="Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="BRG" access="Read/Write" description="Baud Rate Generator register. 16-bit integer baud rate divisor value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BRGVAL" description="This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register. Reflects interrupts that are currently enabled." reset_value="0x0005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY" description="Receiver Ready flag." />
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TXRDY" description="Transmitter Ready flag." />
-      <BitField start="3" size="1" name="TXIDLE" description="Transmitter idle status." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="5" size="1" name="DELTACTS" description="This bit is set when a change in the state of the CTS input is detected." />
-      <BitField start="6" size="1" name="TXDISINT" description="Transmitter Disabled Interrupt flag." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="OVERRUNINT" description="Overrun Error interrupt flag." />
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="11" size="1" name="DELTARXBRK" description="This bit is set when a change in the state of receiver break detection occurs." />
-      <BitField start="12" size="1" name="START" description="This bit is set when a start is detected on the receiver input." />
-      <BitField start="13" size="1" name="FRAMERRINT" description="Framing Error interrupt flag." />
-      <BitField start="14" size="1" name="PARITYERRINT" description="Parity Error interrupt flag." />
-      <BitField start="15" size="1" name="RXNOISEINT" description="Received Noise interrupt flag." />
-      <BitField start="16" size="1" name="ABERR" description="Auto-baud Error flag." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="OSR" access="Read/Write" description="Oversample selection register for asynchronous communication." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OSRVAL" description="Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit.  ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="ADDR" access="Read/Write" description="Address register for automatic address matching." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDRESS" description="8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x40080000" description="USB device controller">
-    <Register start="+0x000" size="4" name="DEVCMDSTAT" access="Read/Write" description="USB Device Command/Status register" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DEV_ADDR" description="USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request." />
-      <BitField start="7" size="1" name="DEV_EN" description="USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR." />
-      <BitField start="8" size="1" name="SETUP" description="SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW." />
-      <BitField start="9" size="1" name="PLL_ON" description="USB Clock/PLL control.">
-        <Enum name="USB_NEEDCLK_FUNCTION" start="0" description="USB_NeedClk functional" />
-        <Enum name="USB_NEEDCLK_ALWAYS_1" start="1" description="USB_NeedClk always 1. Clock will not be stopped in case of suspend." />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="LPM_SUP" description="LPM Support.">
-        <Enum name="LPM_NOT_SUPPORTED" start="0" description="LPM not supported." />
-        <Enum name="LPM_SUPPORTED" start="1" description="LPM supported." />
-      </BitField>
-      <BitField start="12" size="1" name="INTONNAK_AO" description="Interrupt on NAK for interrupt and bulk OUT EP">
-        <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="13" size="1" name="INTONNAK_AI" description="Interrupt on NAK for interrupt and bulk IN EP">
-        <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="14" size="1" name="INTONNAK_CO" description="Interrupt on NAK for control OUT EP">
-        <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="15" size="1" name="INTONNAK_CI" description="Interrupt on NAK for control IN EP">
-        <Enum name="ONLY_ACKNOWLEDGED_PA" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="BOTH_ACKNOWLEDGED_AN" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="16" size="1" name="DCON" description="Device status - connect.  The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one." />
-      <BitField start="17" size="1" name="DSUS" description="Device status - suspend.  The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect." />
-      <BitField start="18" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="LPM_SUS" description="Device status - LPM Suspend.  This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one." />
-      <BitField start="20" size="1" name="LPM_REWP" description="LPM Remote Wake-up Enabled by USB host.  HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction." />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="DCON_C" description="Device status - connect change.  The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." />
-      <BitField start="25" size="1" name="DSUS_C" description="Device status - suspend change.  The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state  - The device is disconnected - The device receives resume signaling on its upstream port.  The bit is reset by writing a one to it." />
-      <BitField start="26" size="1" name="DRES_C" description="Device status - reset change.  This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="VBUSDEBOUNCED" description="This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="INFO" access="Read/Write" description="USB Info register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="FRAME_NR" description="Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device." />
-      <BitField start="11" size="4" name="ERR_CODE" description="The error code which last occurred:">
-        <Enum name="NO_ERROR" start="0x0" description="No error" />
-        <Enum name="PID_ENCODING_ERROR" start="0x1" description="PID encoding error" />
-        <Enum name="PID_UNKNOWN" start="0x2" description="PID unknown" />
-        <Enum name="PACKET_UNEXPECTED" start="0x3" description="Packet unexpected" />
-        <Enum name="TOKEN_CRC_ERROR" start="0x4" description="Token CRC error" />
-        <Enum name="DATA_CRC_ERROR" start="0x5" description="Data CRC error" />
-        <Enum name="TIME_OUT" start="0x6" description="Time out" />
-        <Enum name="BABBLE" start="0x7" description="Babble" />
-        <Enum name="TRUNCATED_EOP" start="0x8" description="Truncated EOP" />
-        <Enum name="SENT_RECEIVED_NAK" start="0x9" description="Sent/Received NAK" />
-        <Enum name="SENT_STALL" start="0xA" description="Sent Stall" />
-        <Enum name="OVERRUN" start="0xB" description="Overrun" />
-        <Enum name="SENT_EMPTY_PACKET" start="0xC" description="Sent empty packet" />
-        <Enum name="BITSTUFF_ERROR" start="0xD" description="Bitstuff error" />
-        <Enum name="SYNC_ERROR" start="0xE" description="Sync error" />
-        <Enum name="WRONG_DATA_TOGGLE" start="0xF" description="Wrong data toggle" />
-      </BitField>
-      <BitField start="15" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EPLISTSTART" access="Read/Write" description="USB EP Command/Status List start address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="24" name="EP_LIST" description="Start address of the USB EP Command/Status List." />
-    </Register>
-    <Register start="+0x00C" size="4" name="DATABUFSTART" access="Read/Write" description="USB Data buffer start address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="10" name="DA_BUF" description="Start address of the buffer pointer page where all endpoint data buffers are located." />
-    </Register>
-    <Register start="+0x010" size="4" name="LPM" access="Read/Write" description="Link Power Management register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="HIRD_HW" description="Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token" />
-      <BitField start="4" size="4" name="HIRD_SW" description="Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume." />
-      <BitField start="8" size="1" name="DATA_PENDING" description="As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="EPSKIP" access="Read/Write" description="USB Endpoint skip" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SKIP" description="Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit.  An interrupt will be generated when the Active bit goes from 1 to 0.  Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit." />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="EPINUSE" access="Read/Write" description="USB Endpoint Buffer in use" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
-      <BitField start="2" size="8" name="BUF" description="Buffer in use: This register has one bit per physical endpoint.  0: HW is accessing buffer 0.  1: HW is accessing buffer 1." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="EPBUFCFG" access="Read/Write" description="USB Endpoint Buffer Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
-      <BitField start="2" size="8" name="BUF_SB" description="Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer.  1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="INTSTAT" access="Read/Write" description="USB interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP0OUT" description="Interrupt status register bit for the Control EP0 OUT direction.  This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="1" size="1" name="EP0IN" description="Interrupt status register bit for the Control EP0 IN direction.  This bit will be set if NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="2" size="1" name="EP1OUT" description="Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="3" size="1" name="EP1IN" description="Interrupt status register bit for the EP1 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="4" size="1" name="EP2OUT" description="Interrupt status register bit for the EP2 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="5" size="1" name="EP2IN" description="Interrupt status register bit for the EP2 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="6" size="1" name="EP3OUT" description="Interrupt status register bit for the EP3 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="7" size="1" name="EP3IN" description="Interrupt status register bit for the EP3 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="8" size="1" name="EP4OUT" description="Interrupt status register bit for the EP4 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="9" size="1" name="EP4IN" description="Interrupt status register bit for the EP4 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="FRAME_INT" description="Frame interrupt.  This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints.  Software can clear this bit by writing a one to it." />
-      <BitField start="31" size="1" name="DEV_INT" description="Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTEN" access="Read/Write" description="USB interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EP_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="FRAME_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
-      <BitField start="31" size="1" name="DEV_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTSETSTAT" access="Read/Write" description="USB set interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EP_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="FRAME_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
-      <BitField start="31" size="1" name="DEV_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
-    </Register>
-    <Register start="+0x02C" size="4" name="INTROUTING" access="Read/Write" description="USB interrupt routing register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="ROUTE_INT9_0" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="ROUTE_INT30" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
-      <BitField start="31" size="1" name="ROUTE_INT31" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
-    </Register>
-    <Register start="+0x034" size="4" name="EPTOGGLE" access="ReadOnly" description="USB Endpoint toggle register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="TOGGLE" description="Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CRC" start="0x50000000" description="Cyclic Redundancy Check (CRC) engine">
-    <Register start="+0x00" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRC_POLY" description="CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial" />
-      <BitField start="2" size="1" name="BIT_RVS_WR" description="Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)" />
-      <BitField start="3" size="1" name="CMPL_WR" description="Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA" />
-      <BitField start="4" size="1" name="BIT_RVS_SUM" description="CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM" />
-      <BitField start="5" size="1" name="CMPL_SUM" description="CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM" />
-      <BitField start="6" size="26" name="Reserved" description="Always 0 when read" />
-    </Register>
-    <Register start="+0x04" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." />
-    </Register>
-    <Register start="+0x08" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." />
-    </Register>
-    <Register start="+0x08" size="4" name="WR_DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMA" start="0x50004000" description="DMA controller">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="DMA control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="DMA controller master enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. The DMA controller is enabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="ACTIVEINT" description="Summarizes whether any enabled interrupts are pending.">
-        <Enum name="NOT_PENDING" start="0" description="Not pending. No enabled interrupts are pending." />
-        <Enum name="PENDING" start="1" description="Pending. At least one enabled interrupt is pending." />
-      </BitField>
-      <BitField start="2" size="1" name="ACTIVEERRINT" description="Summarizes whether any error interrupts are pending.">
-        <Enum name="NOT_PENDING" start="0" description="Not pending. No error interrupts are pending." />
-        <Enum name="PENDING" start="1" description="Pending. At least one error interrupt is pending." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="SRAMBASE" access="Read/Write" description="SRAM address of the channel configuration table." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="22" name="OFFSET" description="Address of the beginning of the DMA descriptor table. The table must begin on a 1 kB boundary. Boundary needed for 18 channel DMA configuration: 512 bytes (bottom 9 bits = 0)" />
-    </Register>
-    <Register start="+0x020" size="4" name="ENABLESET0" access="Read/Write" description="Channel Enable read and Set for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENA" description="Enable for DMA channels 15:0. Bit n enables or disables DMA channel n.  0 = disabled. 1 = enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="ENABLECLR0" access="WriteOnly" description="Channel Enable Clear for all DMA channels." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="CLR" description="Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n." />
-    </Register>
-    <Register start="+0x030" size="4" name="ACTIVE0" access="ReadOnly" description="Channel Active status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ACT" description="Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x038" size="4" name="BUSY0" access="ReadOnly" description="Channel Busy status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BSY" description="Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x040" size="4" name="ERRINT0" access="Read/Write" description="Error Interrupt status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ERR" description="Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INTENSET0" access="Read/Write" description="Interrupt Enable read and Set for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTEN" description="Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTENCLR0" access="WriteOnly" description="Interrupt Enable Clear for all DMA channels." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="CLR" description="Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTA0" access="Read/Write" description="Interrupt A status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="IA" description="Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060" size="4" name="INTB0" access="Read/Write" description="Interrupt B status for all DMA channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="IB" description="Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="SETVALID0" access="WriteOnly" description="Set ValidPending control bits for all DMA channels." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="SV" description="SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="SETTRIG0" access="WriteOnly" description="Set Trigger control bits for all DMA channels." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="TRIG" description="Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x078" size="4" name="ABORT0" access="WriteOnly" description="Channel Abort control for all DMA channels." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="AORTCTRL" description="Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400+0" size="4" name="CFG0" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+16" size="4" name="CFG1" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+32" size="4" name="CFG2" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+48" size="4" name="CFG3" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+64" size="4" name="CFG4" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+80" size="4" name="CFG5" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+96" size="4" name="CFG6" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+112" size="4" name="CFG7" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+128" size="4" name="CFG8" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+144" size="4" name="CFG9" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+160" size="4" name="CFG10" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+176" size="4" name="CFG11" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+192" size="4" name="CFG12" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+208" size="4" name="CFG13" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+224" size="4" name="CFG14" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x400+240" size="4" name="CFG15" access="Read/Write" description="Configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PERIPHREQEN" description="Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.">
-        <Enum name="DISABLED" start="0" description="Disabled. Peripheral DMA requests are disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Peripheral DMA requests are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="HWTRIGEN" description="Hardware Triggering Enable for this channel.">
-        <Enum name="DISABLED" start="0" description="Disabled. Hardware triggering is not used." />
-        <Enum name="ENABLED" start="1" description="Enabled. Use hardware triggering." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="TRIGPOL" description="Trigger Polarity. Selects the polarity of a hardware trigger for this channel.">
-        <Enum name="ACTIVE_LOW__FALLING" start="0" description="Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE." />
-        <Enum name="ACTIVE_HIGH__RISING" start="1" description="Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE." />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGTYPE" description="Trigger Type. Selects hardware trigger as edge triggered or level triggered.">
-        <Enum name="EDGE" start="0" description="Edge. Hardware trigger is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel." />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGBURST" description="Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.">
-        <Enum name="SINGLE_TRANSFER" start="0" description="Single transfer. Hardware trigger causes a single transfer." />
-        <Enum name="BURST_TRANSFER" start="1" description="Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="4" name="BURSTPOWER" description="Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SRCBURSTWRAP" description="Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Source burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Source burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="15" size="1" name="DSTBURSTWRAP" description="Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.">
-        <Enum name="DISABLED" start="0" description="Disabled. Destination burst wrapping is not enabled for this DMA channel." />
-        <Enum name="ENABLED" start="1" description="Enabled. Destination burst wrapping is enabled for this DMA channel." />
-      </BitField>
-      <BitField start="16" size="2" name="CHPRIORITY" description="Priority of this channel when multiple DMA requests are pending. This description reflects a 2-bit priority field providing 4 priority levels. 0x0 = highest priority. 0x3 = lowest priority." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+0" size="4" name="CTLSTAT0" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+16" size="4" name="CTLSTAT1" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+32" size="4" name="CTLSTAT2" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+48" size="4" name="CTLSTAT3" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+64" size="4" name="CTLSTAT4" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+80" size="4" name="CTLSTAT5" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+96" size="4" name="CTLSTAT6" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+112" size="4" name="CTLSTAT7" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+128" size="4" name="CTLSTAT8" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+144" size="4" name="CTLSTAT9" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+160" size="4" name="CTLSTAT10" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+176" size="4" name="CTLSTAT11" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+192" size="4" name="CTLSTAT12" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+208" size="4" name="CTLSTAT13" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+224" size="4" name="CTLSTAT14" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x404+240" size="4" name="CTLSTAT15" access="ReadOnly" description="Control and status register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="VALIDPENDING" description="Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.">
-        <Enum name="NO_EFFECT_ON_DMA_OPE" start="0" description="No effect on DMA operation." />
-        <Enum name="VALID_PENDING" start="1" description="Valid pending." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="TRIG" description="Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.">
-        <Enum name="NOT_TRIGGERED" start="0" description="Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out." />
-        <Enum name="TRIGGERED" start="1" description="Triggered. The trigger for this DMA channel is set. DMA operations will be carried out." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+0" size="4" name="XFERCFG0" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+16" size="4" name="XFERCFG1" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+32" size="4" name="XFERCFG2" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+48" size="4" name="XFERCFG3" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+64" size="4" name="XFERCFG4" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+80" size="4" name="XFERCFG5" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+96" size="4" name="XFERCFG6" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+112" size="4" name="XFERCFG7" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+128" size="4" name="XFERCFG8" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+144" size="4" name="XFERCFG9" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+160" size="4" name="XFERCFG10" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+176" size="4" name="XFERCFG11" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+192" size="4" name="XFERCFG12" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+208" size="4" name="XFERCFG13" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+224" size="4" name="XFERCFG14" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x408+240" size="4" name="XFERCFG15" access="Read/Write" description="Transfer configuration register for DMA channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CFGVALID" description="Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.">
-        <Enum name="NOT_VALID" start="0" description="Not valid. The current channel descriptor is not considered valid." />
-        <Enum name="VALID" start="1" description="Valid. The current channel descriptor is considered valid." />
-      </BitField>
-      <BitField start="1" size="1" name="RELOAD" description="Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.">
-        <Enum name="DISABLED" start="0" description="Disabled. Do not reload the channels' control structure when the current descriptor is exhausted." />
-        <Enum name="ENABLED" start="1" description="Enabled. Reload the channels' control structure when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="2" size="1" name="SWTRIG" description="Software Trigger.">
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="0" description="When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel." />
-        <Enum name="WHEN_WRITTEN_BY_SOFT" start="1" description="When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRTRIG" description="Clear Trigger.">
-        <Enum name="NOT_CLEARED" start="0" description="Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started." />
-        <Enum name="CLEARED" start="1" description="Cleared. The trigger is cleared when this descriptor is exhausted." />
-      </BitField>
-      <BitField start="4" size="1" name="SETINTA" description="Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTA flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="5" size="1" name="SETINTB" description="Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="SET" start="1" description="Set. The INTB flag for this channel will be set when the current descriptor is exhausted." />
-      </BitField>
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="WIDTH" description="Transfer width used for this DMA channel.">
-        <Enum name="8_BIT_TRANSFERS" start="0x0" description="8-bit transfers are performed (8-bit source reads and destination writes)." />
-        <Enum name="16_BIT_TRANSFERS" start="0x1" description="16-bit transfers are performed (16-bit source reads and destination writes)." />
-        <Enum name="32_BIT_TRANSFERS" start="0x2" description="32-bit transfers are performed (32-bit source reads and destination writes)." />
-        <Enum name="RESERVED" start="0x3" description="Reserved setting, do not use." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="2" name="SRCINC" description="Determines whether the source address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="14" size="2" name="DSTINC" description="Determines whether the destination address is incremented for each DMA transfer.">
-        <Enum name="NO_INCREMENT" start="0x0" description="No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device." />
-        <Enum name="1_X_WIDTH" start="0x1" description="1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory." />
-        <Enum name="2_X_WIDTH" start="0x2" description="2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer." />
-        <Enum name="4_X_WIDTH" start="0x3" description="4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer." />
-      </BitField>
-      <BitField start="16" size="10" name="XFERCOUNT" description="Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCT0" start="0x5000C000" description="State Configurable Timers (SCTimer/PWM)">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="THE_SCT_OPERATES_AS" start="0" description="The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="THE_SCT_OPERATES_AS" start="1" description="The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="THE_BUS_CLOCK_CLOCKS" start="0x0" description="The bus clock clocks the SCT and prescalers." />
-        <Enum name="THE_SCT_CLOCK_IS_THE" start="0x1" description="The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="THE_INPUT_SELECTED_B" start="0x2" description="The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-        <Enum name="PRESCALED_SCT_INPUT" start="0x3" description="Prescaled SCT input. The SCT and prescalers are clocked by the input edge  selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the)  input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and  can the same or faster than the system clock." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="THE_COUNTER_COUNTS_U" start="0" description="The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="THE_COUNTER_COUNTS_U" start="1" description="The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not, run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="THE_H_COUNTER_COUNTS" start="0" description="The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="THE_H_COUNTER_COUNTS" start="1" description="The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DEV_0" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DEV_1" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="IEN" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLAG" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="NCEN" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="NCFLAG" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
-      <BitField start="4" size="26" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCT1" start="0x5000E000" description="SCT1">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="THE_SCT_OPERATES_AS" start="0" description="The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="THE_SCT_OPERATES_AS" start="1" description="The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="THE_BUS_CLOCK_CLOCKS" start="0x0" description="The bus clock clocks the SCT and prescalers." />
-        <Enum name="THE_SCT_CLOCK_IS_THE" start="0x1" description="The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="THE_INPUT_SELECTED_B" start="0x2" description="The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-        <Enum name="PRESCALED_SCT_INPUT" start="0x3" description="Prescaled SCT input. The SCT and prescalers are clocked by the input edge  selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the)  input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and  can the same or faster than the system clock." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="THE_COUNTER_COUNTS_U" start="0" description="The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="THE_COUNTER_COUNTS_U" start="1" description="The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not, run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="THE_H_COUNTER_COUNTS" start="0" description="The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="THE_H_COUNTER_COUNTS" start="1" description="The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 20). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="SET_AND_CLEAR_DO_NOT" start="0x0" description="Set and clear do not depend on any counter." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x1" description="Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="SET_AND_CLEAR_ARE_RE" start="0x2" description="Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DEV_0" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DEV_1" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="IEN" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLAG" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="NCEN" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="NCFLAG" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3)." />
-      <BitField start="4" size="26" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCHn_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCHn_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPn_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAPn_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOADn_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOADn_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CAPCONn_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5)." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="6" name="CAPCONn_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 21)." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STATEMSKn" description="If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 7 = bit 7)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="SELECTS_THE_L_STATE" start="0" description="Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="SELECTS_THE_H_STATE" start="1" description="Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="SELECTS_THE_INPUTS_E" start="0" description="Selects the inputs elected by IOSEL." />
-        <Enum name="SELECTS_THE_OUTPUTS" start="1" description="Selects the outputs selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal number (0 to 3) associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SET" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CLR" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0xA0000000" description="General Purpose I/O (GPIO) ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port 2. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin PIOm_n is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin: m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR[0]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR[1]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+8" size="4" name="DIR[2]" access="Read/Write" description="Port Direction registers " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin PIOm_n (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK[0]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK[1]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+8" size="4" name="MASK[2]" access="Read/Write" description="Port Mask register " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN[0]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN[1]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+8" size="4" name="PIN[2]" access="Read/Write" description="Port pin register " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN[0]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN[1]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+8" size="4" name="MPIN[2]" access="Read/Write" description="Masked port register " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 2; n = pin 0 to 31 for port 0 and 1 and pin 0 to 11 for port2.  0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET[0]" access="Read/Write" description="Write: Set port  register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET[1]" access="Read/Write" description="Write: Set port  register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+8" size="4" name="SET[2]" access="Read/Write" description="Write: Set port  register Read: port output bits " reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP00" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP01" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP02" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP03" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP04" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP05" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP06" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP07" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP08" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP09" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP010" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP011" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP012" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP013" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP014" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP015" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP016" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP017" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP018" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP019" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP020" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP021" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP022" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP023" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP024" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP025" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP026" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP027" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP028" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP029" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP030" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP031" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR[0]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR[1]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+8" size="4" name="CLR[2]" access="WriteOnly" description="Clear port" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT[0]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT[1]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+8" size="4" name="NOT[2]" access="WriteOnly" description="Toggle port " reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP00" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP01" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP02" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP03" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP04" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP05" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP06" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP07" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP08" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP09" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP010" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP011" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP012" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP013" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP014" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP015" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP016" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP017" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP018" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP019" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP020" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP021" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP022" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP023" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP024" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP025" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP026" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP027" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP028" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP029" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP030" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP031" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PINT" start="0xA0004000" description=" Pin interrupt&#xa;and pattern match (PINT) ">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin interrupt level or rising edge  interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Pin interrupt level or rising edge  interrupt set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Pin interrupt level (rising edge interrupt) clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin interrupt active level or falling edge  interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Pin interrupt active level or falling edge  interrupt set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Pin interrupt active level or falling edge  interrupt clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin interrupt rising edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin interrupt falling edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="PMCTRL" access="Read/Write" description="Pattern match interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEL_PMATCH" description="Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.">
-        <Enum name="PIN_INTERRUPT_INTER" start="0" description="Pin interrupt. Interrupts are driven in response to the standard pin interrupt function" />
-        <Enum name="PATTERN_MATCH_INTER" start="1" description="Pattern match. Interrupts are driven in response to pattern matches." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_RXEV" description="Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.">
-        <Enum name="DISABLED_RXEV_OUTPU" start="0" description="Disabled. RXEV output to the cpu is disabled." />
-        <Enum name="ENABLED_RXEV_OUTPUT" start="1" description="Enabled. RXEV output to the cpu is enabled." />
-      </BitField>
-      <BitField start="2" size="22" name="RESERVED" description="Reserved. Do not write 1s to unused bits." />
-      <BitField start="24" size="8" name="PMAT" description="This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs." />
-    </Register>
-    <Register start="+0x02C" size="4" name="PMSRC" access="Read/Write" description="Pattern match interrupt bit-slice source register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Reserved" description="Software should not write 1s to unused bits." />
-      <BitField start="8" size="3" name="SRC0" description="Selects the input source for bit slice 0">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects the output of pin interrupt select register 0 as the source to bit slice 0." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects the output of pin interrupt select register 1 as the source to bit slice 0." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects the output of pin interrupt select register 2 as the source to bit slice 0." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects the output of pin interrupt select register 3 as the source to bit slice 0." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects the output of pin interrupt select register 4 as the source to bit slice 0." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects the output of pin interrupt select register 5 as the source to bit slice 0." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects the output of pin interrupt select register 6 as the source to bit slice 0." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects the output of pin interrupt select register 7 as the source to bit slice 0." />
-      </BitField>
-      <BitField start="11" size="3" name="SRC1" description="Selects the input source for bit slice 1">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 1." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 1." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 1." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 1." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 1." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 1." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 1." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 1." />
-      </BitField>
-      <BitField start="14" size="3" name="SRC2" description="Selects the input source for bit slice 2">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 2." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 2." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 2." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 2." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 2." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 2." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 2." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 2." />
-      </BitField>
-      <BitField start="17" size="3" name="SRC3" description="Selects the input source for bit slice 3">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 3." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 3." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 3." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 3." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 3." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 3." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 3." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 3." />
-      </BitField>
-      <BitField start="20" size="3" name="SRC4" description="Selects the input source for bit slice 4">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 4." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 4." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 4." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 4." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 4." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 4." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 4." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 4." />
-      </BitField>
-      <BitField start="23" size="3" name="SRC5" description="Selects the input source for bit slice 5">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 5." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 5." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 5." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 5." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 5." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 5." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 5." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 5." />
-      </BitField>
-      <BitField start="26" size="3" name="SRC6" description="Selects the input source for bit slice 6">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 6." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 6." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 6." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 6." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 6." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 6." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 6." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 6." />
-      </BitField>
-      <BitField start="29" size="3" name="SRC7" description="Selects the input source for bit slice 7">
-        <Enum name="INPUT_0_SELECTS_PIN" start="0x0" description="Input 0. Selects pin interrupt input 0 as the source to bit slice 7." />
-        <Enum name="INPUT_1_SELECTS_PIN" start="0x1" description="Input 1. Selects pin interrupt input 1 as the source to bit slice 7." />
-        <Enum name="INPUT_2_SELECTS_PIN" start="0x2" description="Input 2. Selects pin interrupt input 2 as the source to bit slice 7." />
-        <Enum name="INPUT_3_SELECTS_PIN" start="0x3" description="Input 3. Selects pin interrupt input 3 as the source to bit slice 7." />
-        <Enum name="INPUT_4_SELECTS_PIN" start="0x4" description="Input 4. Selects pin interrupt input 4 as the source to bit slice 7." />
-        <Enum name="INPUT_5_SELECTS_PIN" start="0x5" description="Input 5. Selects pin interrupt input 5 as the source to bit slice 7." />
-        <Enum name="INPUT_6_SELECTS_PIN" start="0x6" description="Input 6. Selects pin interrupt input 6 as the source to bit slice 7." />
-        <Enum name="INPUT_7_SELECTS_PIN" start="0x7" description="Input 7. Selects pin interrupt input 7 as the source to bit slice 7." />
-      </BitField>
-    </Register>
-    <Register start="+0x030" size="4" name="PMCFG" access="Read/Write" description="Pattern match interrupt bit slice configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PROD_ENDPTS" description="A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Bit slice 7 is automatically considered a product end point." />
-      <BitField start="8" size="3" name="CFG0" description="Specifies the match contribution condition for bit slice 0.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="11" size="3" name="CFG1" description="Specifies the match contribution condition for bit slice 1.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="14" size="3" name="CFG2" description="Specifies the match contribution condition for bit slice 2.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="17" size="3" name="CFG3" description="Specifies the match contribution condition for bit slice 3.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="20" size="3" name="CFG4" description="Specifies the match contribution condition for bit slice 4.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="23" size="3" name="CFG5" description="Specifies the match contribution condition for bit slice 5.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="26" size="3" name="CFG6" description="Specifies the match contribution condition for bit slice 6.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-      <BitField start="29" size="3" name="CFG7" description="Specifies the match contribution condition for bit slice 7.">
-        <Enum name="CONSTANT_HIGH_THIS_" start="0x0" description="Constant HIGH. This bit slice always contributes to a product term match." />
-        <Enum name="STICKY_RISING_EDGEMA" start="0x1" description="Sticky rising edgeMatch occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_FALLING_EDGE_" start="0x2" description="Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="STICKY_RISING_OR_FAL" start="0x3" description="Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to." />
-        <Enum name="HIGH_LEVEL_MATCH_F" start="0x4" description="High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register." />
-        <Enum name="LOW_LEVEL_MATCH_OCC" start="0x5" description="Low level. Match occurs when there is a low level on the specified input." />
-        <Enum name="CONSTANT_0_THIS_BIT" start="0x6" description="Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices)." />
-        <Enum name="EVENT_NON_STICKY_RI" start="0x7" description="Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) . This bit is cleared after one clock cycle." />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="I2C1" start="10" size="1" />
-      <BitField name="USART1_4" start="11" size="1" />
-      <BitField name="USART2_3" start="12" size="1" />
-      <BitField name="SCT0_1" start="13" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C0" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC_A" start="24" size="1" />
-      <BitField name="RTC" start="25" size="1" />
-      <BitField name="BOD_WDT" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="DMA" start="28" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="I2C1" start="10" size="1" />
-      <BitField name="USART1_4" start="11" size="1" />
-      <BitField name="USART2_3" start="12" size="1" />
-      <BitField name="SCT0_1" start="13" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C0" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC_A" start="24" size="1" />
-      <BitField name="RTC" start="25" size="1" />
-      <BitField name="BOD_WDT" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="DMA" start="28" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="I2C1" start="10" size="1" />
-      <BitField name="USART1_4" start="11" size="1" />
-      <BitField name="USART2_3" start="12" size="1" />
-      <BitField name="SCT0_1" start="13" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C0" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC_A" start="24" size="1" />
-      <BitField name="RTC" start="25" size="1" />
-      <BitField name="BOD_WDT" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="DMA" start="28" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="I2C1" start="10" size="1" />
-      <BitField name="USART1_4" start="11" size="1" />
-      <BitField name="USART2_3" start="12" size="1" />
-      <BitField name="SCT0_1" start="13" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C0" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC_A" start="24" size="1" />
-      <BitField name="RTC" start="25" size="1" />
-      <BitField name="BOD_WDT" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="DMA" start="28" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="I2C1" start="10" size="1" />
-      <BitField name="USART1_4" start="11" size="1" />
-      <BitField name="USART2_3" start="12" size="1" />
-      <BitField name="SCT0_1" start="13" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C0" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC_A" start="24" size="1" />
-      <BitField name="RTC" start="25" size="1" />
-      <BitField name="BOD_WDT" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="DMA" start="28" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="PIN_INT0" start="4" size="4" />
-      <BitField name="PIN_INT1" start="12" size="4" />
-      <BitField name="PIN_INT2" start="20" size="4" />
-      <BitField name="PIN_INT3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="PIN_INT4" start="4" size="4" />
-      <BitField name="PIN_INT5" start="12" size="4" />
-      <BitField name="PIN_INT6" start="20" size="4" />
-      <BitField name="PIN_INT7" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="GINT0" start="4" size="4" />
-      <BitField name="GINT1" start="12" size="4" />
-      <BitField name="I2C1" start="20" size="4" />
-      <BitField name="USART1_4" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="USART2_3" start="4" size="4" />
-      <BitField name="SCT0_1" start="12" size="4" />
-      <BitField name="SSP1" start="20" size="4" />
-      <BitField name="I2C0" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="CT16B0" start="4" size="4" />
-      <BitField name="CT16B1" start="12" size="4" />
-      <BitField name="CT32B0" start="20" size="4" />
-      <BitField name="CT32B1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SSP0" start="4" size="4" />
-      <BitField name="USART" start="12" size="4" />
-      <BitField name="USB" start="20" size="4" />
-      <BitField name="USB_FIQ" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="ADC_A" start="4" size="4" />
-      <BitField name="RTC" start="12" size="4" />
-      <BitField name="BOD_WDT" start="20" size="4" />
-      <BitField name="FLASH" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="DMA" start="4" size="4" />
-      <BitField name="USBWAKEUP" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xe000e010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xe000e010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xe000e014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xe000e018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xe000e01c" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="0xe000e000" description="System Control Block">
-    <Register name="CPUID" start="0xe000ed00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xe000ed04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xe000ed08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xe000ed0c" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xe000ed10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xe000ed14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-    </Register>
-    <Register name="SHPR2" start="0xe000ed1c" description="System Handler Priority Register 2">
-      <BitField name="PRI_11(SVCall)" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xe000ed20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15(SysTick)" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14(PendSV)" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Vectors.s b/examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Vectors.s
deleted file mode 100644
index 4d661df3..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/LPC11U6x_Vectors.s
+++ /dev/null
@@ -1,405 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*           www.segger.com     Support: support@segger.com           *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* conditions are met:                                                *
-*                                                                    *
-* - Redistributions of source code must retain the above copyright   *
-*   notice, this list of conditions and the following disclaimer.    *
-*                                                                    *
-* - Neither the name of SEGGER Microcontroller GmbH                  *
-*   nor the names of its contributors may be used to endorse or      *
-*   promote products derived from this software without specific     *
-*   prior written permission.                                        *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED.                                                        *
-* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-*********************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 2
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak USART1_4_IRQHandler
-  .thumb_set USART1_4_IRQHandler,Dummy_Handler
-
-  .weak USART2_3_IRQHandler
-  .thumb_set USART2_3_IRQHandler,Dummy_Handler
-
-  .weak SCT0_1_IRQHandler
-  .thumb_set SCT0_1_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak CT16B0_IRQHandler
-  .thumb_set CT16B0_IRQHandler,Dummy_Handler
-
-  .weak CT16B1_IRQHandler
-  .thumb_set CT16B1_IRQHandler,Dummy_Handler
-
-  .weak CT32B0_IRQHandler
-  .thumb_set CT32B0_IRQHandler,Dummy_Handler
-
-  .weak CT32B1_IRQHandler
-  .thumb_set CT32B1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak USART_IRQHandler
-  .thumb_set USART_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak USB_FIQ_IRQHandler
-  .thumb_set USB_FIQ_IRQHandler,Dummy_Handler
-
-  .weak ADC_A_IRQHandler
-  .thumb_set ADC_A_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak BOD_WDT_IRQHandler
-  .thumb_set BOD_WDT_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak USBWAKEUP_IRQHandler
-  .thumb_set USBWAKEUP_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART1_4_IRQHandler
-USART1_4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_3_IRQHandler
-USART2_3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SCT0_1_IRQHandler
-SCT0_1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT16B0_IRQHandler
-CT16B0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT16B1_IRQHandler
-CT16B1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT32B0_IRQHandler
-CT32B0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT32B1_IRQHandler
-CT32B1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART_IRQHandler
-USART_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_FIQ_IRQHandler
-USB_FIQ_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_A_IRQHandler
-ADC_A_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_WDT_IRQHandler
-BOD_WDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USBWAKEUP_IRQHandler
-USBWAKEUP_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 2
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word I2C1_IRQHandler
-  .word USART1_4_IRQHandler
-  .word USART2_3_IRQHandler
-  .word SCT0_1_IRQHandler
-  .word SSP1_IRQHandler
-  .word I2C0_IRQHandler
-  .word CT16B0_IRQHandler
-  .word CT16B1_IRQHandler
-  .word CT32B0_IRQHandler
-  .word CT32B1_IRQHandler
-  .word SSP0_IRQHandler
-  .word USART_IRQHandler
-  .word USB_IRQHandler
-  .word USB_FIQ_IRQHandler
-  .word ADC_A_IRQHandler
-  .word RTC_IRQHandler
-  .word BOD_WDT_IRQHandler
-  .word FLASH_IRQHandler
-  .word DMA_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word USBWAKEUP_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 2
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/flash_placement.xml b/examples/device/cdc_msc/ses/lpc11u6x/flash_placement.xml
deleted file mode 100644
index 27a63d5b..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/flash_placement.xml
+++ /dev/null
@@ -1,41 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM3_NAME:RAM3)">
-    <ProgramSection alignment="4" load="No" name=".data3_run" />
-    <ProgramSection alignment="4" load="No" name=".bss3" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/lpc11u6x.emProject b/examples/device/cdc_msc/ses/lpc11u6x/lpc11u6x.emProject
deleted file mode 100644
index ea47e0db..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/lpc11u6x.emProject
+++ /dev/null
@@ -1,126 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc11u6x" target="8" version="2">
-  <project Name="lpc11u6x">
-    <configuration
-      CMSIS_CORE="Yes"
-      Name="Common"
-      Placement="Flash"
-      Target="LPC11U68"
-      arm_architecture="v6M"
-      arm_core_type="Cortex-M0+"
-      arm_endian="Little"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="256"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00040000;RAM;0x10000000;0x00008000;RAM;0x20000000;0x00000800"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC11U68"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="__LPC11U68__;__LPC1100_FAMILY;__LPC11U00_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;CORE_M0PLUS;CFG_TUSB_MCU=OPT_MCU_LPC11UXX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss3&quot;)));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc;$(rootDir)/src"
-      debug_register_definition_file="$(ProjectDir)/LPC11U6x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC11U68_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC1100;DeviceSubFamily=LPC11U00;Target=LPC11U68;Placement=Flash;rootDir=../../../../.."
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/LPC1100_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC1100_Startup.s" />
-      <file file_name="LPC11U6x_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="LPC1100_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-      <file file_name="LPC11U68_MemoryMap.xml" />
-      <file file_name="flash_placement.xml" />
-    </folder>
-    <configuration
-      Name="LPCXpresso 11U68"
-      c_preprocessor_definitions="BOARD_LPCXPRESSO11U68"
-      link_use_linker_script_file="No"
-      linker_section_placement_file="flash_placement.xml" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder
-          Name="lpcxpresso11u68"
-          exclude=""
-          filter="*.*"
-          path="../../../../../hw/bsp/lpcxpresso11u68"
-          recurse="No" />
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_11u6x">
-              <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/chip.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/clock_11u6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/cmsis.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cm0.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cm0plus.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cm3.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cm4.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cm4_simd.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cmFunc.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/core_cmInstr.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/error.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/gpio_11u6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/gpiogroup_11u6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/iocon_11u6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/lpc_types.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/sys_config.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/syscon_11u6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/uart_0_11u6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/inc/usbd_11u6x.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/src/chip_11u6x.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/src/clock_11u6x.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/src/gpio_11u6x.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/src/syscon_11u6x.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/src/sysinit_11u6x.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_11u6x/src/iocon_11u6x.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-  </project>
-  <configuration
-    Name="LPCXpresso 11U68"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc11u6x/thumb_crt0.s b/examples/device/cdc_msc/ses/lpc11u6x/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/lpc11u6x/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/lpc13xx/LPC1300_Startup.s b/examples/device/cdc_msc/ses/lpc13xx/LPC1300_Startup.s
deleted file mode 100644
index ad41afb9..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/LPC1300_Startup.s
+++ /dev/null
@@ -1,113 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/lpc13xx/LPC1300_Target.js b/examples/device/cdc_msc/ses/lpc13xx/LPC1300_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/LPC1300_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml b/examples/device/cdc_msc/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
deleted file mode 100644
index 29864528..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC1347FBD64">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00010000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00002000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" />
-  <MemorySegment name="RAM3" start="0x20004000" size="0x00000800" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Registers.xml b/examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Registers.xml
deleted file mode 100644
index 0f605ce0..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Registers.xml
+++ /dev/null
@@ -1,5515 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC13Uxx" description="LPC1315/16/17/35/36/37 Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM">
-  <RegisterGroup name="I2C" start="0x40000000" description="I2C">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40004000" description="Windowed Watchdog Timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
-        <Enum name="STOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUNNING" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
-        <Enum name="INTERRUPT" start="0" description="A watchdog timeout will not cause a chip reset." />
-        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1." />
-      <BitField start="3" size="1" name="WDINT" description="Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit can be set once by software and is only cleared by a reset.">
-        <Enum name="NOT_LOCKED" start="0" description="The watchdog time-out value (TC) can be changed at any time." />
-        <Enum name="LOCKED" start="1" description="The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="1" name="LOCK" description="A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7)." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This 24-bit register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="FEED" description="Feed value should be 0xAA followed by 0x55." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKSEL" description="Selects source of WDT clock">
-        <Enum name="IRC" start="0" description="IRC" />
-        <Enum name="WATCHDOG_OSCILLATOR_" start="1" description="Watchdog oscillator (WDOSC)" />
-      </BitField>
-      <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT16B0" start="0x4000C000" description="16-bit counter/timers CT16B0">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TC" description="Timer counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PCVAL" description="Prescale value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PC" description="Prescale counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT16B0_CAP0 falling edge: a sequence of 1 then 0 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT16B0_CAP0 event: a CR0 load due to a CT16B0_CAP0 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="CAP1RE" description="Capture on CT16B0_CAP1 rising edge: a sequence of 0 then 1 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP1FE" description="Capture on CT16B0_CAP1 falling edge: a sequence of 1 then 0 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP1I" description="Interrupt on CT16B0_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt. This bit is reserved for 16-bit timer1 CT16B1.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x034" size="4" name="CR1" access="ReadOnly" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B0_CAP1 input." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved.">
-        <Enum name="CT16B0_CAP0_" start="0x0" description="CT16B0_CAP0." />
-        <Enum name="RESERVED_" start="0x1" description="Reserved." />
-        <Enum name="CT16B0_CAP1_" start="0x2" description="CT16B0_CAP1." />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
-        <Enum name="RISING_EDGE_OF_CT16B" start="0x0" description="Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)." />
-        <Enum name="FALLING_EDGE_OF_CT16" start="0x1" description="Falling Edge of CT16B0_CCAP0 clears the timer (if bit 4 is set)." />
-        <Enum name="RESERVED_" start="0x2" description="Reserved." />
-        <Enum name="RESERVED_" start="0x3" description="Reserved." />
-        <Enum name="RISING_EDGE_OF_CT16B" start="0x4" description="Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)." />
-        <Enum name="FALLING_EDGE_OF_CT16" start="0x5" description="Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="CT16BN_MAT0_IS_CONTR" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="CT16BN_MAT01_IS_CONT" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="CT16BN_MAT2_IS_CONTR" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
-        <Enum name="CT16BN_MAT3_IS_CONTR" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT16B1" start="0x40010000" description="16-bit counter/timers CT16B1">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TC" description="Timer counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PCVAL" description="Prescale value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PC" description="Prescale counter value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT16B1_CAP0 rising edge: a sequence of 0 then 1 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT16B11_CAP0 falling edge: a sequence of 1 then 0 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CT16B1_CAP1 rising edge: a sequence of 0 then 1 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CT16B1_CAP1 falling edge: a sequence of 1 then 0 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CT16B1_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x030" size="4" name="CR1" access="ReadOnly" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B1_CAP1 input." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x2 to 0x3 are reserved.">
-        <Enum name="CT16B1_CAP0_" start="0x0" description="CT16B1_CAP0." />
-        <Enum name="CT16B1_CAP1_" start="0x1" description="CT16B1_CAP1." />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SELCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x6 to 0x7 are reserved.">
-        <Enum name="RISING_EDGE_OF_CT16B" start="0x0" description="Rising Edge of CT16B1_CAP0 clears the timer (if bit 4 is set)." />
-        <Enum name="FALLING_EDGE_OF_CT16" start="0x1" description="Falling Edge of CT16B1_CAP0 clears the timer (if bit 4 is set)." />
-        <Enum name="RISING_EDGE_OF_CT16B" start="0x2" description="Rising Edge of CT16B1_CAP1 clears the timer (if bit 4 is set)." />
-        <Enum name="FALLING_EDGE_OF_CT16" start="0x3" description="Falling Edge of CT16B1_CAP1 clears the timer (if bit 4 is set)." />
-        <Enum name="RESERVED_" start="0x4" description="Reserved." />
-        <Enum name="RESERVED_" start="0x5" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="CT16BN_MAT0_IS_CONTR" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="CT16BN_MAT01_IS_CONT" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="CT16BN_MAT2_IS_CONTR" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
-        <Enum name="CT16BN_MAT3_IS_CONTR" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT32B0" start="0x40014000" description="32-bit counter/timers CT32B0">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved," />
-      <BitField start="6" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="CAP1RE" description="Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP1FE" description="Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP1I" description="Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x034" size="4" name="CR1" access="Read/Write" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B0_CAP1 input." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking.  If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x1 and0x3 are reserved.">
-        <Enum name="CT32B0_CAP0" start="0x0" description="CT32B0_CAP0" />
-        <Enum name="RESERVED_" start="0x1" description="Reserved." />
-        <Enum name="CT32B0_CAP1" start="0x2" description="CT32B0_CAP1" />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SElCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
-        <Enum name="RISING_EDGE_OF_CT32B" start="0x0" description="Rising Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)" />
-        <Enum name="FALLING_EDGE_OF_CT32" start="0x1" description="Falling Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)" />
-        <Enum name="RESERVED" start="0x2" description="Reserved," />
-        <Enum name="RESERVED_" start="0x3" description="Reserved." />
-        <Enum name="RISING_EDGE_OF_CT32B" start="0x4" description="Rising Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)" />
-        <Enum name="FALLING_EDGE_OF_CT32" start="0x5" description="Falling Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="CT32BN_MAT0_IS_CONTR" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="CT32BN_MAT01_IS_CONT" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="CT32BN_MAT2_IS_CONTR" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
-        <Enum name="CT32BN_MAT3_IS_CONTR" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CT32B1" start="0x40018000" description="32-bit counter/timers CT32B1">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Counter enable.">
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
-      </BitField>
-      <BitField start="1" size="1" name="CRST" description="Counter reset.">
-        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
-        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
-        <Enum name="ENABLED" start="1" description="Enabled" />
-        <Enum name="DISABLED" start="0" description="Disabled" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT32B1_CAP0 rising edge: a sequence of 0 then 1 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT32B1_CAP0 falling edge: a sequence of 1 then 0 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT32B1_CAP0 event: a CR0 load due to a CT32B1_CAP0 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CT32B1_CAP1 rising edge: a sequence of 0 then 1 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CT32B1_CAP1 falling edge: a sequence of 1 then 0 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will generate an interrupt.">
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x030" size="4" name="CR1" access="Read/Write" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B1_CAP1 input." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking.  If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved.">
-        <Enum name="CT32B1_CAP0" start="0x0" description="CT32B1_CAP0" />
-        <Enum name="CT32B1_CAP1" start="0x1" description="CT32B1_CAP1" />
-      </BitField>
-      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
-      <BitField start="5" size="3" name="SElCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved.">
-        <Enum name="RISING_EDGE_OF_CT32B" start="0x0" description="Rising Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)" />
-        <Enum name="FALLING_EDGE_OF_CT32" start="0x1" description="Falling Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)" />
-        <Enum name="RISING_EDGE_OF_CT32B" start="0x2" description="Rising Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)" />
-        <Enum name="FALLING_EDGE_OF_CT32" start="0x3" description="Falling Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
-        <Enum name="CT32BN_MAT0_IS_CONTR" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
-        <Enum name="CT32BN_MAT01_IS_CONT" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
-        <Enum name="CT32BN_MAT2_IS_CONTR" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
-        <Enum name="CT32BN_MAT3_IS_CONTR" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART" start="0x40008000" description="USART">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRINTEN" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupt." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREINTEN" description="THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupt." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RLSINTEN" description="Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RLS_INTE" start="0" description="Disable the RLS interrupt." />
-        <Enum name="ENABLE_THE_RLS_INTER" start="1" description="Enable the RLS interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="MSINTEN" description="Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.">
-        <Enum name="DISABLE_THE_MS_INTER" start="0" description="Disable the MS interrupt." />
-        <Enum name="ENABLE_THE_MS_INTERR" start="1" description="Enable the MS interrupt." />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="4_MODEM_STATUS" start="0x0" description="4   - Modem status" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOEN" description="These bits are equivalent to FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable">
-        <Enum name="DISABLED" start="0" description="USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset">
-        <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset">
-        <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and  RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="RBR_IS_EMPTY_" start="0" description="RBR is empty." />
-        <Enum name="RBR_CONTAINS_VALID_D" start="1" description="RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="THR_CONTAINS_VALID_D" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID_D" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERRO" start="1" description="USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Start mode">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write only accessible).">
-        <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write only accessible).">
-        <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA (remote control) mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable">
-        <Enum name="IRDA_MODE_IS_DISABLE" start="0" description="IrDA mode is disabled, USARTn acts as a standard USART." />
-        <Enum name="IRDA_MODE_IS_ENABLED" start="1" description="IrDA mode is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input inverter">
-        <Enum name="INVERTED" start="0" description="The serial input is not inverted." />
-        <Enum name="NOT_INVERTED" start="1" description="The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse width when FixPulseEn = 1.">
-        <Enum name="3_DIV_16_X_BAUD_RATE" start="0x0" description="3 / (16 x baud rate)" />
-        <Enum name="2_X_TPCLK" start="0x1" description="2 x TPCLK" />
-        <Enum name="4_X_TPCLK" start="0x2" description="4 x TPCLK" />
-        <Enum name="8_X_TPCLK" start="0x3" description="8 x TPCLK" />
-        <Enum name="16_X_TPCLK" start="0x4" description="16 x TPCLK" />
-        <Enum name="32_X_TPCLK" start="0x5" description="32 x TPCLK" />
-        <Enum name="64_X_TPCLK" start="0x6" description="64 x TPCLK" />
-        <Enum name="128_X_TPCLK" start="0x7" description="128 x TPCLK" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half duplex enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLE_HALF_DUPLEX_" start="0" description="Disable half-duplex mode." />
-        <Enum name="ENABLE_HALF_DUPLEX_M" start="1" description="Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface Control register. Enables and configures the Smart Card Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
-        <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="3" name="TXRETRY" description="When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared." />
-      <BitField start="8" size="8" name="XTRAGUARD" description="When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="RS_485_EIA_485_NORMA" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="RS_485_EIA_485_NORMA" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="THE_RECEIVER_IS_ENAB" start="0" description="The receiver is enabled." />
-        <Enum name="THE_RECEIVER_IS_DISA" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="AUTO_ADDRESS_DETECT_" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="AUTO_ADDRESS_DETECT_" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Select direction control pin">
-        <Enum name="RTS" start="0" description="If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Auto direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
-        <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Falling edge sampling.">
-        <Enum name="RISING" start="0" description="RxD is sampled on the rising edge of SCLK " />
-        <Enum name="FALLING" start="1" description="RxD is sampled on the falling edge of SCLK" />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNC" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic" />
-        <Enum name="NOSYNC" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
-        <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
-      </BitField>
-      <BitField start="5" size="1" name="SSDIS" description="Start/stop bits">
-        <Enum name="SEND_START_STOP" start="0" description="Send start and stop bits as in other modes." />
-        <Enum name="NOT_SEND_START_STOP" start="1" description="Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
-        <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x4001C000" description="ADC">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7.  In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1.  In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)." />
-      <BitField start="8" size="8" name="CLKDIV" description="The main clock (PCLK_ADC) is divided by (this value plus one) to produce the clock for  the A/D converter. The clock should be less than or equal to 15.5 MHz(12-bit mode) or 31 MHz (10-bit mode) in software-controlled mode (BURST bit = 0).. Typically, software should program the smallest value in this field that yields a clock of 15.5 MHz or slightly less, but in certain cases (such as a high-impedance analog  source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode If BURST is set to 1, the ADGINTEN bit in the INTEN register (Table 327) must be set to 0.">
-        <Enum name="SOFTWARE_CONTROLLED_" start="0" description="Software-controlled mode: Conversions are software-controlled and require 31 clocks." />
-        <Enum name="HARDWARE_SCAN_MODE_" start="1" description="Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by ones in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher  bits (pins) set to one are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1, or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="22" size="1" name="LPWRMODE" description="Low-power mode">
-        <Enum name="DISABLE_THE_LOW_POWE" start="0" description="Disable the low-power ADC mode. The analog circuitry remains activated when no conversions are requested." />
-        <Enum name="ENABLE_THE_LOW_POWER" start="1" description="Enable the low-power ADC mode.  The analog circuitry is automatically powered-down when no conversions are taking  place. When any (hardware or software) triggering event is detected, the analog circuitry  is enabled. After the required start-up time, the requested conversion will be launched.  Once the conversion completes, the analog-circuitry will again be powered-down provided  no further conversions are pending.  This mode will NOT power-up the A/D if the ADC is powered down (ADC_PD bit in the PDRUNCFG register is HIGH) or if the part is in Deep-sleep, Power-down, or Deep power-down mode." />
-      </BitField>
-      <BitField start="23" size="1" name="MODE10BIT" description="10-bit conversion rate mode">
-        <Enum name="DISABLE_THE_10_BIT_C" start="0" description="Disable the 10-bit conversion rate mode." />
-        <Enum name="ENABLE_THE_10_BIT_CO" start="1" description="Enable the 10-bit conversion rate mode with high conversion rate.The A/D resolution is reduced to 10 bits (the two LSB of the conversion result will be forced  to 0). The clock rate (set via the CLKDIV field) can be doubled to up to 31 MHz to  achieve a conversion rate of up to one million samples per second." />
-      </BitField>
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
-        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="PIO0_2" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0." />
-        <Enum name="PIO1_5" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0." />
-        <Enum name="CT32B0_MAT0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]." />
-        <Enum name="CT32B0_MAT1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]." />
-        <Enum name="CT16B0_MAT0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]." />
-        <Enum name="CT16B0_MAT1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="Edge control. This bit is significant only when the START field contains 010-111.">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. These bits always read as zeros." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin or as it falls within the range of VREFP to  VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS/VREFN, while 0xFFF indicates that the voltage on ADn was close to, equal to, or greater than that on VDD/VREFP." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeros." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the result bits V_VREF were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeros." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. This bit must be set to 0 in burst mode (BURST = 1 in the CR register)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Unused, always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel n." />
-      <BitField start="8" size="8" name="OVERRUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Unused, always 0." />
-    </Register>
-    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="A/D trim register" reset_value="0xF00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
-      <BitField start="8" size="4" name="TRIM" description="Written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMU" start="0x40038000" description="Power Management Unit (PMU)">
-    <Register start="+0x000" size="4" name="PCON" access="Read/Write" description="Power control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PM" description="Power mode">
-        <Enum name="DEFAULT" start="0x0" description="Default. The part is in active or sleep mode." />
-        <Enum name="DEEPSLEEP" start="0x1" description="ARM WFI will enter Deep-sleep mode." />
-        <Enum name="POWERDOWN" start="0x2" description="ARM WFI will enter Power-down mode." />
-        <Enum name="DEEPPOWERDOWN" start="0x3" description="ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down)." />
-      </BitField>
-      <BitField start="3" size="1" name="NODPD" description="A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. Execution continues after the WFI if this bit is 1.  This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-      <BitField start="8" size="1" name="SLEEPFLAG" description="Sleep mode flag">
-        <Enum name="NOPOWERDOWN" start="0" description="Read: No power-down mode entered. LPC11U1x is in Active mode. Write: No effect." />
-        <Enum name="POWERDOWN" start="1" description="Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0." />
-      </BitField>
-      <BitField start="9" size="2" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep power-down flag">
-        <Enum name="DPNOTENTERED" start="0" description="Read: Deep power-down mode  not entered. Write: No effect." />
-        <Enum name="DPENTERED" start="1" description="Read: Deep power-down mode entered. Write: Clear the Deep power-down flag." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-    </Register>
-    <Register start="+0x004+0" size="4" name="GPREG0" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x004+4" size="4" name="GPREG1" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x004+8" size="4" name="GPREG2" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x004+12" size="4" name="GPREG3" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-    <Register start="+0x014" size="4" name="GPREG4" access="Read/Write" description="General purpose register 4" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="RESERVED" description="Reserved. Do not write ones to this bit." />
-      <BitField start="10" size="1" name="WAKEUPHYS" description="WAKEUP pin hysteresis enable">
-        <Enum name="DISABLED" start="0" description="Hysteresis for WAKEUP pin disabled." />
-        <Enum name="ENABLED" start="1" description="Hysteresis for WAKEUP pin enabled." />
-      </BitField>
-      <BitField start="11" size="21" name="GPDATA" description="Data retained during Deep power-down mode." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FLASHCTRL" start="0x4003C000" description="Flash programming firmware  ">
-    <Register start="+0x09C" size="4" name="EEMSSTART" access="Read/Write" description="EEPROM BIST start address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="STARTA" description="BIST start address: Bit 0 is fixed zero since only even addresses are allowed." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="EEMSSTOP" access="Read/Write" description="EEPROM BIST stop address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="STOPA" description="BIST stop address: Bit 0 is fixed zero since only even addresses are allowed." />
-      <BitField start="14" size="16" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DEVSEL" description="BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the  address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same." />
-      <BitField start="31" size="1" name="STRTBIST" description="BIST start bit Setting this bit will start the BIST. This bit is self-clearing." />
-    </Register>
-    <Register start="+0x0A4" size="4" name="EEMSSIG" access="ReadOnly" description="EEPROM 24-bit BIST signature register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA_SIG" description="BIST 16-bit signature calculated from only the data bytes" />
-      <BitField start="16" size="16" name="PARITY_SIG" description="BIST 16-bit signature calculated from only the parity bits of the data bytes" />
-    </Register>
-    <Register start="+0x010" size="4" name="FLASHCFG" access="Read/Write" description="Flash memory access time configuration register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="FLASHTIM" description="Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.">
-        <Enum name="1_SYSTEM_CLOCK_FLASH" start="0x0" description="1 system clock flash access time (for system clock frequencies of up to 20 MHz)." />
-        <Enum name="2_SYSTEM_CLOCKS_FLAS" start="0x1" description="2 system clocks flash access time (for system clock frequencies of up to 40 MHz)." />
-        <Enum name="3_SYSTEM_CLOCKS_FLAS" start="0x2" description="3 system clocks flash access time (for system clock frequencies of up to 50 MHz)." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read." />
-    </Register>
-    <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." />
-      <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation.">
-        <Enum name="SIGNATURE_GENERATION" start="0" description="Signature generation is stopped" />
-        <Enum name="INITIATE_SIGNATURE_G" start="1" description="Initiate signature generation" />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="Word 0 [31:0]" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." />
-    </Register>
-    <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="Word 1 [63:32]" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." />
-    </Register>
-    <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="Word 2 [95:64]" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." />
-    </Register>
-    <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="Word 3 [127:96]" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="FMSTAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="FMSTATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40040000" description="SSP/SPI">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
-        <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
-        <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SPI Enable.">
-        <Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="IOCON" start="0x40044000" description="IO ocnfiguration">
-    <Register start="+0x000" size="4" name="RESET_PIO0_0" access="Read/Write" description="I/O configuration for pin RESET/PIO0_0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="RESET_" start="0x0" description="RESET." />
-        <Enum name="PIO0_0_" start="0x1" description="PIO0_0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="PIO0_1" access="Read/Write" description="I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/ USB_FTOGGLE" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO0_1_" start="0x0" description="PIO0_1." />
-        <Enum name="CLKOUT_" start="0x1" description="CLKOUT." />
-        <Enum name="CT32B0_MAT2_" start="0x2" description="CT32B0_MAT2." />
-        <Enum name="USB_FTOGGLE_" start="0x3" description="USB_FTOGGLE." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="PIO0_2" access="Read/Write" description="I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO0_2_" start="0x0" description="PIO0_2." />
-        <Enum name="SSEL0_" start="0x1" description="SSEL0." />
-        <Enum name="CT16B0_CAP0_" start="0x2" description="CT16B0_CAP0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PIO0_3" access="Read/Write" description="I/O configuration for pin PIO0_3/USB_VBUS" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO0_3_" start="0x0" description="PIO0_3." />
-        <Enum name="USB_VBUS_" start="0x1" description="USB_VBUS." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="PIO0_4" access="Read/Write" description="I/O configuration for pin PIO0_4/SCL" reset_value="0x0000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO0_4_OPEN_DRAIN_P" start="0x0" description="PIO0_4 (open-drain pin)." />
-        <Enum name="I2C_SCL_OPEN_DRAIN_" start="0x1" description="I2C SCL (open-drain pin)." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 6.3.8). Select Standard mode (I2CMODE = 0, default) or Standard I/O functionality (I2CMODE = 1) if the pin function is GPIO (FUNC = 0).">
-        <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
-        <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
-        <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
-        <Enum name="RESERVED_" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="PIO0_5" access="Read/Write" description="I/O configuration for pin PIO0_5/SDA" reset_value="0x0000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO0_5_OPEN_DRAIN_P" start="0x0" description="PIO0_5 (open-drain pin)." />
-        <Enum name="I2C_SDA_OPEN_DRAIN_" start="0x1" description="I2C SDA (open-drain pin)." />
-      </BitField>
-      <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 6.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 0).">
-        <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
-        <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
-        <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
-        <Enum name="RESERVED_" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="PIO0_6" access="Read/Write" description="I/O configuration for pin PIO0_6/USB_CONNECT/SCK0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO0_6_" start="0x0" description="PIO0_6." />
-        <Enum name="USB_CONNECT_" start="0x1" description="USB_CONNECT." />
-        <Enum name="SCK0_" start="0x2" description="SCK0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PIO0_7" access="Read/Write" description="I/O configuration for pin PIO0_7/CTS" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO0_7_" start="0x0" description="PIO0_7." />
-        <Enum name="CTS_" start="0x1" description="CTS." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="PIO0_8" access="Read/Write" description="I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/ ARM_TRACE_CLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO0_8_" start="0x0" description="PIO0_8." />
-        <Enum name="MISO0_" start="0x1" description="MISO0." />
-        <Enum name="CT16B0_MAT0_" start="0x2" description="CT16B0_MAT0." />
-        <Enum name="ARM_TRACE_CLK" start="0x3" description="ARM_TRACE_CLK" />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="PIO0_9" access="Read/Write" description="I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/ ARM_TRACE_SWV" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO0_9_" start="0x0" description="PIO0_9." />
-        <Enum name="MOSI0_" start="0x1" description="MOSI0." />
-        <Enum name="CT16B0_MAT1_" start="0x2" description="CT16B0_MAT1." />
-        <Enum name="ARM_TRACE_SWV" start="0x3" description="ARM_TRACE_SWV" />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="SWCLK_PIO0_10" access="Read/Write" description="I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="SWCLK_" start="0x0" description="SWCLK." />
-        <Enum name="PIO0_10_" start="0x1" description="PIO0_10." />
-        <Enum name="SCK0_" start="0x2" description="SCK0." />
-        <Enum name="CT16B0_MAT2_" start="0x3" description="CT16B0_MAT2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TDI_PIO0_11" access="Read/Write" description="I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="TDI_" start="0x0" description="TDI." />
-        <Enum name="PIO0_11_" start="0x1" description="PIO0_11." />
-        <Enum name="AD0_" start="0x2" description="AD0." />
-        <Enum name="CT32B0_MAT3_" start="0x3" description="CT32B0_MAT3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x030" size="4" name="TMS_PIO0_12" access="Read/Write" description="I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="TMS_" start="0x0" description="TMS." />
-        <Enum name="PIO0_12_" start="0x1" description="PIO0_12." />
-        <Enum name="AD1_" start="0x2" description="AD1." />
-        <Enum name="CT32B1_CAP0_" start="0x3" description="CT32B1_CAP0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x034" size="4" name="TDO_PIO0_13" access="Read/Write" description="I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="TDO_" start="0x0" description="TDO." />
-        <Enum name="PIO0_13_" start="0x1" description="PIO0_13." />
-        <Enum name="AD2_" start="0x2" description="AD2." />
-        <Enum name="CT32B1_MAT0_" start="0x3" description="CT32B1_MAT0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x038" size="4" name="TRST_PIO0_14" access="Read/Write" description="I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="TRST_" start="0x0" description="TRST." />
-        <Enum name="PIO0_14_" start="0x1" description="PIO0_14." />
-        <Enum name="AD3_" start="0x2" description="AD3." />
-        <Enum name="CT32B1_MAT1_" start="0x3" description="CT32B1_MAT1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x03C" size="4" name="SWDIO_PIO0_15" access="Read/Write" description="I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="SWDIO_" start="0x0" description="SWDIO." />
-        <Enum name="PIO0_15_" start="0x1" description="PIO0_15." />
-        <Enum name="AD4_" start="0x2" description="AD4." />
-        <Enum name="CT32B1_MAT2_" start="0x3" description="CT32B1_MAT2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x040" size="4" name="PIO0_16" access="Read/Write" description="I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. This pin functions as WAKEUP pin if the LPC1315/16/17/45/46/47 is in Deep power-down mode regardless of the value of FUNC. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO0_16_" start="0x0" description="PIO0_16." />
-        <Enum name="AD5_" start="0x1" description="AD5." />
-        <Enum name="CT32B1_MAT3_" start="0x2" description="CT32B1_MAT3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044" size="4" name="PIO0_17" access="Read/Write" description="I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO0_17_" start="0x0" description="PIO0_17." />
-        <Enum name="RTS_" start="0x1" description="RTS." />
-        <Enum name="CT32B0_CAP0_" start="0x2" description="CT32B0_CAP0." />
-        <Enum name="SCLK_UART_SYNCHRONO" start="0x3" description="SCLK (UART synchronous clock)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="PIO0_18" access="Read/Write" description="I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO0_18_" start="0x0" description="PIO0_18." />
-        <Enum name="RXD_" start="0x1" description="RXD." />
-        <Enum name="CT32B0_MAT0_" start="0x2" description="CT32B0_MAT0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PIO0_19" access="Read/Write" description="I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO0_19_" start="0x0" description="PIO0_19." />
-        <Enum name="TXD_" start="0x1" description="TXD." />
-        <Enum name="CT32B0_MAT1_" start="0x2" description="CT32B0_MAT1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x050" size="4" name="PIO0_20" access="Read/Write" description="I/O configuration for pin PIO0_20/CT16B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO0_20_" start="0x0" description="PIO0_20." />
-        <Enum name="CT16B1_CAP0_" start="0x1" description="CT16B1_CAP0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="PIO0_21" access="Read/Write" description="I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO0_21_" start="0x0" description="PIO0_21." />
-        <Enum name="CT16B1_MAT0_" start="0x1" description="CT16B1_MAT0." />
-        <Enum name="MOSI1_" start="0x2" description="MOSI1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="PIO0_22" access="Read/Write" description="I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO0_22_" start="0x0" description="PIO0_22." />
-        <Enum name="AD6_" start="0x1" description="AD6." />
-        <Enum name="CT16B1_MAT1_" start="0x2" description="CT16B1_MAT1." />
-        <Enum name="MISO1_" start="0x3" description="MISO1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="PIO0_23" access="Read/Write" description="I/O configuration for pin PIO0_23/AD7" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO0_23_" start="0x0" description="PIO0_23." />
-        <Enum name="AD7_" start="0x1" description="AD7." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
-        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x060" size="4" name="PIO1_0" access="Read/Write" description="I/O configuration for pin PIO1_0/CT32B1_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_0_" start="0x0" description="PIO1_0." />
-        <Enum name="CT32B1_MAT1_" start="0x1" description="CT32B1_MAT1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x064" size="4" name="PIO1_1" access="Read/Write" description="I/O configuration for pin PIO1_1/CT32B1_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_1_" start="0x0" description="PIO1_1." />
-        <Enum name="CT32B1_MAT1_" start="0x1" description="CT32B1_MAT1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="PIO1_2" access="Read/Write" description="I/O configuration for pin PIO1_2/CT32B1_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_2_" start="0x0" description="PIO1_2." />
-        <Enum name="CT32B1_MAT2_" start="0x1" description="CT32B1_MAT2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="PIO1_3" access="Read/Write" description="I/O configuration for pin PIO1_3/CT32B1_MAT3" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_3_" start="0x0" description="PIO1_3." />
-        <Enum name="CT32B1_MAT3_" start="0x1" description="CT32B1_MAT3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="PIO1_4" access="Read/Write" description="I/O configuration for pin PIO1_4/CT32B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_4_" start="0x0" description="PIO1_4." />
-        <Enum name="CT32B1_CAP0_" start="0x1" description="CT32B1_CAP0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x074" size="4" name="PIO1_5" access="Read/Write" description="I/O configuration for pin PIO1_5/CT32B1_CAP1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_5_" start="0x0" description="PIO1_5." />
-        <Enum name="CT32B1_CAP1_" start="0x1" description="CT32B1_CAP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x07C" size="4" name="PIO1_7" access="Read/Write" description="I/O configuration for pin PIO1_7" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_7_" start="0x0" description="PIO1_7." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x080" size="4" name="PIO1_8" access="Read/Write" description="I/O configuration for pin PIO1_8" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
-        <Enum name="PIO1_8_" start="0x0" description="PIO1_8." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x088" size="4" name="PIO1_10" access="Read/Write" description="I/O configuration for pin PIO1_10" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
-        <Enum name="PIO1_10_" start="0x0" description="PIO1_10." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x08C" size="4" name="PIO1_11" access="Read/Write" description="I/O configuration for pin PIO1_11" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
-        <Enum name="PIO1_11_" start="0x0" description="PIO1_11." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x094" size="4" name="PIO1_13" access="Read/Write" description="I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO1_13" start="0x0" description="PIO1_13" />
-        <Enum name="DTR" start="0x1" description="DTR" />
-        <Enum name="CT16B0_MAT0" start="0x2" description="CT16B0_MAT0" />
-        <Enum name="TXD" start="0x3" description="TXD" />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x098" size="4" name="PIO1_14" access="Read/Write" description="I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO1_14_" start="0x0" description="PIO1_14." />
-        <Enum name="DSR" start="0x1" description="DSR" />
-        <Enum name="CT16B0_MAT1" start="0x2" description="CT16B0_MAT1" />
-        <Enum name="RXD" start="0x3" description="RXD" />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x09C" size="4" name="PIO1_15" access="Read/Write" description="I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
-        <Enum name="PIO1_15_" start="0x0" description="PIO1_15." />
-        <Enum name="DCD_" start="0x1" description="DCD." />
-        <Enum name="CT16B0_MAT2_" start="0x2" description="CT16B0_MAT2." />
-        <Enum name="SCK1_" start="0x3" description="SCK1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0A0" size="4" name="PIO1_16" access="Read/Write" description="I/O configuration for pin PIO1_16/RI/CT16B0_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_16_" start="0x0" description="PIO1_16." />
-        <Enum name="RI_" start="0x1" description="RI." />
-        <Enum name="CT16B0_CAP0_" start="0x2" description="CT16B0_CAP0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0A4" size="4" name="PIO1_17" access="Read/Write" description="I/O configuration for PIO1_17/CT16B0_CAP1/RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_17_" start="0x0" description="PIO1_17." />
-        <Enum name="CT16B0_CAP1" start="0x1" description="CT16B0_CAP1" />
-        <Enum name="RXD" start="0x2" description="RXD" />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0A8" size="4" name="PIO1_18" access="Read/Write" description="I/O configuration for PIO1_18/CT16B1_CAP1/TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_18" start="0x0" description="PIO1_18" />
-        <Enum name="CT16B1_CAP1" start="0x1" description="CT16B1_CAP1" />
-        <Enum name="TXD" start="0x2" description="TXD" />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0AC" size="4" name="PIO1_19" access="Read/Write" description="I/O configuration for pin PIO1_19/DTR/SSEL1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_19_" start="0x0" description="PIO1_19." />
-        <Enum name="DTR_" start="0x1" description="DTR." />
-        <Enum name="SSEL1_" start="0x2" description="SSEL1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0B0" size="4" name="PIO1_20" access="Read/Write" description="I/O configuration for pin PIO1_20/DSR/SCK1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_20_" start="0x0" description="PIO1_20." />
-        <Enum name="DSR_" start="0x1" description="DSR." />
-        <Enum name="SCK1_" start="0x2" description="SCK1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0B4" size="4" name="PIO1_21" access="Read/Write" description="I/O configuration for pin PIO1_21/DCD/MISO1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_21_" start="0x0" description="PIO1_21." />
-        <Enum name="DCD_" start="0x1" description="DCD." />
-        <Enum name="MISO1_" start="0x2" description="MISO1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0B8" size="4" name="PIO1_22" access="Read/Write" description="I/O configuration for pin PIO1_22/RI/MOSI1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_22_" start="0x0" description="PIO1_22." />
-        <Enum name="RI_" start="0x1" description="RI." />
-        <Enum name="MOSI1_" start="0x2" description="MOSI1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0BC" size="4" name="PIO1_23" access="Read/Write" description="I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_23_" start="0x0" description="PIO1_23." />
-        <Enum name="CT16B1_MAT1_" start="0x1" description="CT16B1_MAT1." />
-        <Enum name="SSEL1_" start="0x2" description="SSEL1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0C0" size="4" name="PIO1_24" access="Read/Write" description="I/O configuration for pin PIO1_24/ CT32B0_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_24_" start="0x0" description="PIO1_24." />
-        <Enum name="CT32B0_MAT0_" start="0x1" description="CT32B0_MAT0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0C4" size="4" name="PIO1_25" access="Read/Write" description="I/O configuration for pin PIO1_25/CT32B0_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
-        <Enum name="PIO1_25_" start="0x0" description="PIO1_25." />
-        <Enum name="CT32B0_MAT1_" start="0x1" description="CT32B0_MAT1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0C8" size="4" name="PIO1_26" access="Read/Write" description="I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_26_" start="0x0" description="PIO1_26." />
-        <Enum name="CT32B0_MAT2" start="0x1" description="CT32B0_MAT2" />
-        <Enum name="RXD_" start="0x2" description="RXD." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0CC" size="4" name="PIO1_27" access="Read/Write" description="I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_27_" start="0x0" description="PIO1_27." />
-        <Enum name="CT32B0_MAT3_" start="0x1" description="CT32B0_MAT3." />
-        <Enum name="TXD_" start="0x2" description="TXD." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0D0" size="4" name="PIO1_28" access="Read/Write" description="I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_28_" start="0x0" description="PIO1_28." />
-        <Enum name="CT32B0_CAP0_" start="0x1" description="CT32B0_CAP0." />
-        <Enum name="SCLK_" start="0x2" description="SCLK." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0D4" size="4" name="PIO1_29" access="Read/Write" description="I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
-        <Enum name="PIO1_29_" start="0x0" description="PIO1_29." />
-        <Enum name="SCK0_" start="0x1" description="SCK0." />
-        <Enum name="CT32B0_CAP1_" start="0x2" description="CT32B0_CAP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0DC" size="4" name="PIO1_31" access="Read/Write" description="I/O configuration for pin PIO1_31" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
-        <Enum name="PIO1_31_" start="0x0" description="PIO1_31." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
-      </BitField>
-      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x40048000" description="System control block ">
-    <Register start="+0x000" size="4" name="SYSMEMREMAP" access="Read/Write" description="System memory remap" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MAP" description="System memory remap. Value 0x3 is reserved.">
-        <Enum name="BOOT_LOADER_MODE_IN" start="0x0" description="Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM." />
-        <Enum name="USER_RAM_MODE_INTER" start="0x1" description="User RAM Mode. Interrupt vectors are re-mapped to Static RAM." />
-        <Enum name="USER_FLASH_MODE_INT" start="0x2" description="User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESETCTRL" access="Read/Write" description="Peripheral reset control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSP0_RST_N" description="SSP0 reset control">
-        <Enum name="RESETS_THE_SSP0_PERI" start="0" description="Resets the SSP0 peripheral." />
-        <Enum name="SSP0_RESET_DE_ASSERT" start="1" description="SSP0 reset de-asserted." />
-      </BitField>
-      <BitField start="1" size="1" name="I2C_RST_N" description="I2C reset control">
-        <Enum name="RESETS_THE_I2C_PERIP" start="0" description="Resets the I2C peripheral." />
-        <Enum name="I2C_RESET_DE_ASSERTE" start="1" description="I2C reset de-asserted." />
-      </BitField>
-      <BitField start="2" size="1" name="SSP1_RST_N" description="SSP1 reset control">
-        <Enum name="RESETS_THE_SSP0_PERI" start="0" description="Resets the SSP0 peripheral." />
-        <Enum name="SSP1_RESET_DE_ASSERT" start="1" description="SSP1 reset de-asserted." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="SYSPLLCTRL" access="Read/Write" description="System PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
-      <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
-        <Enum name="P_EQ_1" start="0x0" description="P = 1" />
-        <Enum name="P_EQ_2" start="0x1" description="P = 2" />
-        <Enum name="P_EQ_4" start="0x2" description="P = 4" />
-        <Enum name="P_EQ_8" start="0x3" description="P = 8" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SYSPLLSTAT" access="ReadOnly" description="System PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL lock status">
-        <Enum name="PLL_NOT_LOCKED" start="0" description="PLL not locked" />
-        <Enum name="PLL_LOCKED" start="1" description="PLL locked" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="USBPLLCTRL" access="Read/Write" description="USB PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1.  00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
-      <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
-        <Enum name="P_EQ_1" start="0x0" description="P = 1" />
-        <Enum name="P_EQ_2" start="0x1" description="P = 2" />
-        <Enum name="P_EQ_4" start="0x2" description="P = 4" />
-        <Enum name="P_EQ_8" start="0x3" description="P = 8" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x014" size="4" name="USBPLLSTAT" access="ReadOnly" description="USB PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL lock status">
-        <Enum name="PLL_NOT_LOCKED" start="0" description="PLL not locked" />
-        <Enum name="PLL_LOCKED" start="1" description="PLL locked" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="SYSOSCCTRL" access="Read/Write" description="System oscillator control" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BYPASS" description="Bypass system oscillator">
-        <Enum name="OSCILLATOR_IS_NOT_BY" start="0" description="Oscillator is not bypassed." />
-        <Enum name="BYPASS_ENABLED_PLL_" start="1" description="Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator." />
-      </BitField>
-      <BitField start="1" size="1" name="FREQRANGE" description="Determines frequency range for Low-power oscillator.">
-        <Enum name="1__20_MHZ_FREQUENCY" start="0" description="1 - 20 MHz frequency range." />
-        <Enum name="15__25_MHZ_FREQUENC" start="1" description="15 - 25 MHz frequency range" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="WDTOSCCTRL" access="Read/Write" description="Watchdog oscillator control" reset_value="0x0A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DIVSEL" description="Select divider for Fclkana.  wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64" />
-      <BitField start="5" size="4" name="FREQSEL" description="Select watchdog oscillator analog output frequency (Fclkana).">
-        <Enum name="0_6_MHZ" start="0x1" description="0.6 MHz" />
-        <Enum name="1_05_MHZ" start="0x2" description="1.05 MHz" />
-        <Enum name="1_4_MHZ" start="0x3" description="1.4 MHz" />
-        <Enum name="1_75_MHZ" start="0x4" description="1.75 MHz" />
-        <Enum name="2_1_MHZ" start="0x5" description="2.1 MHz" />
-        <Enum name="2_4_MHZ" start="0x6" description="2.4 MHz" />
-        <Enum name="2_7_MHZ" start="0x7" description="2.7 MHz" />
-        <Enum name="3_0_MHZ" start="0x8" description="3.0 MHz" />
-        <Enum name="3_25_MHZ" start="0x9" description="3.25 MHz" />
-        <Enum name="3_5_MHZ" start="0xA" description="3.5 MHz" />
-        <Enum name="3_75_MHZ" start="0xB" description="3.75 MHz" />
-        <Enum name="4_0_MHZ" start="0xC" description="4.0 MHz" />
-        <Enum name="4_2_MHZ" start="0xD" description="4.2 MHz" />
-        <Enum name="4_4_MHZ" start="0xE" description="4.4 MHz" />
-        <Enum name="4_6_MHZ" start="0xF" description="4.6 MHz" />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="SYSRSTSTAT" access="Read/Write" description="System reset status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POR" description="POR reset status">
-        <Enum name="NO_POR_DETECTED" start="0" description="No POR detected" />
-        <Enum name="POR_DETECTED" start="1" description="POR detected" />
-      </BitField>
-      <BitField start="1" size="1" name="EXTRST" description="Status of the external RESET pin">
-        <Enum name="NO_RESET_EVENT_DETEC" start="0" description="No reset event detected" />
-        <Enum name="RESET_DETECTED" start="1" description="Reset detected" />
-      </BitField>
-      <BitField start="2" size="1" name="WDT" description="Status of the Watchdog reset">
-        <Enum name="NO_WDT_RESET_DETECTE" start="0" description="No WDT reset detected" />
-        <Enum name="WDT_RESET_DETECTED" start="1" description="WDT reset detected" />
-      </BitField>
-      <BitField start="3" size="1" name="BOD" description="Status of the Brown-out detect reset">
-        <Enum name="NO_BOD_RESET_DETECTE" start="0" description="No BOD reset detected" />
-        <Enum name="BOD_RESET_DETECTED" start="1" description="BOD reset detected" />
-      </BitField>
-      <BitField start="4" size="1" name="SYSRST" description="Status of the software system reset">
-        <Enum name="NO_SYSTEM_RESET_DETE" start="0" description="No System reset detected" />
-        <Enum name="SYSTEM_RESET_DETECTE" start="1" description="System reset detected" />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="SYSPLLCLKSEL" access="Read/Write" description="System PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="System PLL clock source">
-        <Enum name="IRC" start="0x0" description="IRC" />
-        <Enum name="CRYSTAL_OSCILLATOR_" start="0x1" description="Crystal Oscillator (SYSOSC)" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="USBPLLCLKSEL" access="Read/Write" description="USB PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="USB PLL clock source">
-        <Enum name="IRC_THE_USB_PLL_CLO" start="0x0" description="IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation." />
-        <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="MAINCLKSEL" access="Read/Write" description="Main clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="Clock source for main clock">
-        <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC Oscillator" />
-        <Enum name="PLL_INPUT" start="0x1" description="PLL input" />
-        <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
-        <Enum name="PLL_OUTPUT" start="0x3" description="PLL output" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="SYSAHBCLKDIV" access="Read/Write" description="System clock divider" reset_value="0x001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="System AHB clock divider values  0: System clock disabled.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="SYSAHBCLKCTRL" access="Read/Write" description="System clock control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SYS" description="Enables the clock for the AHB, the APB bridge, the Cortex-M3 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.">
-        <Enum name="RESERVED" start="0" description="Reserved" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="ROM" description="Enables clock for ROM.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="RAM0" description="Enables clock for SRAM0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="FLASHREG" description="Enables clock for flash register interface.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="FLASHARRAY" description="Enables clock for flash array access.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="I2C" description="Enables clock for I2C.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="GPIO" description="Enables clock for GPIO port registers.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="CT16B0" description="Enables clock for 16-bit counter/timer 0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="CT16B1" description="Enables clock for 16-bit counter/timer 1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="CT32B0" description="Enables clock for 32-bit counter/timer 0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="CT32B1" description="Enables clock for 32-bit counter/timer 1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="SSP0" description="Enables clock for SSP0.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="USART" description="Enables clock for UART.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="ADC" description="Enables clock for ADC.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="USB" description="Enables clock to the USB register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="WWDT" description="Enables clock for WWDT.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="IOCON" description="Enables clock for I/O configuration block.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="SSP1" description="Enables clock for SSP1.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="PINT" description="Enables clock to GPIO Pin interrupts register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="23" size="1" name="GROUP0INT" description="Enables clock to GPIO GROUP0 interrupt register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="GROUP1INT" description="Enables clock to GPIO GROUP1 interrupt register interface.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="1" name="RAM1" description="Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="27" size="1" name="USBSRAM" description="Enables USB SRAM block located at 0x2000 4000 to 0x2000 4800.">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="SSP0CLKDIV" access="Read/Write" description="SSP0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="SPI0_PCLK clock divider values.  0: System clock disabled.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="UARTCLKDIV" access="Read/Write" description="UART clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="UART_PCLK clock divider values  0: Disable UART_PCLK.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="SSP1CLKDIV" access="Read/Write" description="SSP1 clock divider" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="SSP1_PCLK clock divider values  0: Disable SSP1_PCLK.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0AC" size="4" name="TRACECLKDIV" access="Read/Write" description="ARM trace clock divider" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="ARM trace clock divider values.  0: Disable TRACE_CLK.  1: Divide by 1.  to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0B0" size="4" name="SYSTICKCLKDIV" access="Read/Write" description="SYSTICK clock divider" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="SYSTICK clock divider values.  0: Disable SYSTICK timer clock.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="USBCLKSEL" access="Read/Write" description="USB clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="USB clock source. Values 0x2 and 0x3 are reserved.">
-        <Enum name="USB_PLL_OUT" start="0x0" description="USB PLL out" />
-        <Enum name="MAIN_CLOCK" start="0x1" description="Main clock" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="USBCLKDIV" access="Read/Write" description="USB clock source divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="USB clock divider values  0: Disable USB clock.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0E0" size="4" name="CLKOUTSEL" access="Read/Write" description="CLKOUT clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEL" description="CLKOUT clock source">
-        <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC oscillator" />
-        <Enum name="CRYSTAL_OSCILLATOR_" start="0x1" description="Crystal oscillator (SYSOSC)" />
-        <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
-        <Enum name="MAIN_CLOCK" start="0x3" description="Main clock" />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0E8" size="4" name="CLKOUTDIV" access="Read/Write" description="CLKOUT clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="CLKOUT clock divider values  0: Disable CLKOUT clock divider.  1: Divide by 1. to 255: Divide by 255." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="PIOPORCAP0" access="ReadOnly" description="POR captured PIO status 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="PIOSTAT" description="State of P0_23 through P0_0 at power-on reset" />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="PIOPORCAP1" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="PIOSTAT" description="State of P1_31 through P1_0 at power-on reset" />
-    </Register>
-    <Register start="+0x150" size="4" name="BODCTRL" access="Read/Write" description="Brown-Out Detect" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BODRSTLEV" description="BOD reset level">
-        <Enum name="LEVEL_0_THE_RESET_A" start="0x0" description="Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V." />
-        <Enum name="LEVEL_1_THE_RESET_A" start="0x1" description="Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V." />
-        <Enum name="LEVEL_2_THE_RESET_A" start="0x2" description="Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V." />
-        <Enum name="LEVEL_3_THE_RESET_A" start="0x3" description="Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V." />
-      </BitField>
-      <BitField start="2" size="2" name="BODINTVAL" description="BOD interrupt level">
-        <Enum name="RESERVED_" start="0x0" description="Reserved." />
-        <Enum name="LEVEL_1THE_INTERRUP" start="0x1" description="Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V." />
-        <Enum name="LEVEL_2_THE_INTERRU" start="0x2" description="Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V." />
-        <Enum name="LEVEL_3_THE_INTERRU" start="0x3" description="Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V." />
-      </BitField>
-      <BitField start="4" size="1" name="BODRSTENA" description="BOD reset enable">
-        <Enum name="DISABLE_RESET_FUNCTI" start="0" description="Disable reset function." />
-        <Enum name="ENABLE_RESET_FUNCTIO" start="1" description="Enable reset function." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="SYSTCKCAL" access="Read/Write" description="System tick counter calibration" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="26" name="CAL" description="System tick timer calibration value" />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="IRQLATENCY" access="Read/Write" description="IQR delay. Allows trade-off between interrupt latency and determinism." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LATENCY" description="8-bit latency value" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="NMISRC" access="Read/Write" description="NMI Source Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="IRQNO" description="The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 53 for the list of interrupt sources and their IRQ numbers." />
-      <BitField start="5" size="26" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="NMIEN" description="Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." />
-    </Register>
-    <Register start="+0x178+0" size="4" name="PINTSEL0" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+4" size="4" name="PINTSEL1" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+8" size="4" name="PINTSEL2" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+12" size="4" name="PINTSEL3" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+16" size="4" name="PINTSEL4" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+20" size="4" name="PINTSEL5" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+24" size="4" name="PINTSEL6" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178+28" size="4" name="PINTSEL7" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
-      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
-        <Enum name="PORT_0" start="0" description="Port 0" />
-        <Enum name="PORT_1" start="1" description="Port 1" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x198" size="4" name="USBCLKCTRL" access="Read/Write" description="USB clock control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="AP_CLK" description="USB need_clock signal control">
-        <Enum name="UNDER_HARDWARE_CONTR" start="0" description="Under hardware control." />
-        <Enum name="FORCED_HIGH_" start="1" description="Forced HIGH." />
-      </BitField>
-      <BitField start="1" size="1" name="POL_CLK" description="USB need_clock polarity for triggering the USB wake-up interrupt">
-        <Enum name="FALLING_EDGE_OF_THE_" start="0" description="Falling edge of the USB need_clock triggers the USB wake-up (default)." />
-        <Enum name="RISING_EDGE_OF_THE_U" start="1" description="Rising edge of the USB need_clock triggers the USB wake-up." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x19C" size="4" name="USBCLKST" access="ReadOnly" description="USB clock status" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NEED_CLKST" description="USB need_clock signal status">
-        <Enum name="LOW" start="0" description="LOW" />
-        <Enum name="HIGH" start="1" description="HIGH" />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="STARTERP0" access="Read/Write" description="Start logic 0 interrupt wake-up enable register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINT0" description="Pin interrupt 0 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="PINT1" description="Pin interrupt 1 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="PINT2" description="Pin interrupt 2 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="PINT3" description="Pin interrupt 3 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="PINT4" description="Pin interrupt 4 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="PINT5" description="Pin interrupt 5 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PINT6" description="Pin interrupt 6 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="PINT7" description="Pin interrupt 7 wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x214" size="4" name="STARTERP1" access="Read/Write" description="Start logic 1 interrupt wake-up enable register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="WWDTINT" description="WWDT interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="BODINT" description="Brown Out Detect (BOD) interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="14" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="USB_WAKEUP" description="USB need_clock signal wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="GPIOINT0" description="GPIO GROUP0 interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="GPIOINT1" description="GPIO GROUP1 interrupt wake-up">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x230" size="4" name="PDSLEEPCFG" access="Read/Write" description="Power-down states in deep-sleep mode" reset_value="0" reset_mask="0x00000000">
-      <BitField start="3" size="1" name="BOD_PD" description="BOD power-down control for Deep-sleep and Power-down mode">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down control for Deep-sleep and Power-down mode">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x234" size="4" name="PDAWAKECFG" access="Read/Write" description="Power-down states for wake-up from deep-sleep" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="2" size="1" name="FLASH_PD" description="Flash wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="3" size="1" name="BOD_PD" description="BOD wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="4" size="1" name="ADC_PD" description="ADC wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL wake-up configuration">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL wake-up configuration">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver wake-up configuration">
-        <Enum name="USB_TRANSCEIVER_POWE" start="0" description="USB transceiver powered" />
-        <Enum name="USB_TRANSCEIVER_POWE" start="1" description="USB transceiver powered down" />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x238" size="4" name="PDRUNCFG" access="Read/Write" description="Power configuration register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="2" size="1" name="FLASH_PD" description="Flash power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="3" size="1" name="BOD_PD" description="BOD power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="4" size="1" name="ADC_PD" description="ADC power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL power-down">
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-        <Enum name="POWERED" start="0" description="Powered" />
-      </BitField>
-      <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL power-down">
-        <Enum name="POWERED" start="0" description="Powered" />
-        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver power-down configuration">
-        <Enum name="USB_TRANSCEIVER_POWE" start="0" description="USB transceiver powered" />
-        <Enum name="USB_TRANSCEIVER_POWE" start="1" description="USB transceiver powered down (suspend mode)" />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved. Always write these bits as 111." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x3F8" size="4" name="DEVICE_ID" access="ReadOnly" description="Device ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="DEVICEID" description="LPC1345FHN33 = 0x2801 0541 LPC1345FBD48 = 0x2801 0541 LPC1346FHN33 = 0x0801 8542 LPC1346FBD48 = 0x0801 8542 LPC1347FHN33 = 0x0802 0543 LPC1347FBD48 = 0x0802 0543 LPC1347FBD64 = 0x0802 0543 LPC1315FHN33 = 0x3A01 0523 LPC1315FBD48 = 0x3A01 0523 LPC1316FHN33 = 0x1A01 8524 LPC1316FBD48 = 0x1A01 8524 LPC1317FHN33 = 0x1A02 0525 LPC1317FBD48 = 0x1A02 0525 LPC1317FBD64 = 0x1A02 0525" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PIN_INT" start="0x4004C000" description="GPIO pin interrupt ">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40058000" description="SSP/SPI">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
-        <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
-        <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SPI Enable.">
-        <Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT0" start="0x4005C000" description="GPIO group interrupt ">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40060000" description="GPIO group interrupt ">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x40064000" description="Repetitive Interrupt Timer (RI timer)">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare value LSB register. Holds the 32 LSBs of the compare value." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the 32 LSBs of the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask LSB register. This register holds the 32 LSB s of the mask value. A one  written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="MASK" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="NO_MASK" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="CLEAR_ON_O" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="NOT_CLEAR_ON_0" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="HALT_ON_DEBUG" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="NO_EFFECT_ON_DEBUG" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="Counter LSB register. 32 LSBs of the counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-    <Register start="+0x010" size="4" name="COMPVAL_H" access="Read/Write" description="Compare value MSB register. Holds the 16 MSBs of the compare value." reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RICOMP" description="Compare value MSB register. Holds the 16 MSBs of the compare value which is compared to the counter." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="MASK_H" access="Read/Write" description="Mask MSB register. This register holds the 16 MSBs of the mask value. A one written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RIMASK" description="Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="COUNTER_H" access="Read/Write" description="Counter MSB register. 16 MSBs of the counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RICOUNTER" description="16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x40080000" description="USB2.0 device controller">
-    <Register start="+0x000" size="4" name="DEVCMDSTAT" access="Read/Write" description="USB Device Command/Status register" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DEV_ADDR" description="USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request." />
-      <BitField start="7" size="1" name="DEV_EN" description="USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR." />
-      <BitField start="8" size="1" name="SETUP" description="SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW." />
-      <BitField start="9" size="1" name="PLL_ON" description="Always PLL Clock on:">
-        <Enum name="USB_NEEDCLK_FUNCTION" start="0" description="USB_NeedClk functional" />
-        <Enum name="USB_NEEDCLK_ALWAYS_1" start="1" description="USB_NeedClk always 1. Clock will not be stopped in case of suspend." />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="LPM_SUP" description="LPM Supported:">
-        <Enum name="LPM_NOT_SUPPORTED_" start="0" description="LPM not supported." />
-        <Enum name="LPM_SUPPORTED_" start="1" description="LPM supported." />
-      </BitField>
-      <BitField start="12" size="1" name="INTONNAK_AO" description="Interrupt on NAK for interrupt and bulk OUT EP">
-        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="13" size="1" name="INTONNAK_AI" description="Interrupt on NAK for interrupt and bulk IN EP">
-        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="14" size="1" name="INTONNAK_CO" description="Interrupt on NAK for control OUT EP">
-        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="15" size="1" name="INTONNAK_CI" description="Interrupt on NAK for control IN EP">
-        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
-        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
-      </BitField>
-      <BitField start="16" size="1" name="DCON" description="Device status - connect.  The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one." />
-      <BitField start="17" size="1" name="DSUS" description="Device status - suspend.  The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect." />
-      <BitField start="18" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="LPM_SUS" description="Device status - LPM Suspend.  This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one." />
-      <BitField start="20" size="1" name="LPM_REWP" description="LPM Remote Wake-up Enabled by USB host.  HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction." />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="DCON_C" description="Device status - connect change.  The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." />
-      <BitField start="25" size="1" name="DSUS_C" description="Device status - suspend change.  The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state  - The device is disconnected - The device receives resume signaling on its upstream port.  The bit is reset by writing a one to it." />
-      <BitField start="26" size="1" name="DRES_C" description="Device status - reset change.  This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="VBUSDEBOUNCED" description="This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="INFO" access="Read/Write" description="USB Info register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="FRAME_NR" description="Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device." />
-      <BitField start="11" size="4" name="ERR_CODE" description="The error code which last occurred:">
-        <Enum name="NO_ERROR" start="0x0" description="No error" />
-        <Enum name="PID_ENCODING_ERROR" start="0x1" description="PID encoding error" />
-        <Enum name="PID_UNKNOWN" start="0x2" description="PID unknown" />
-        <Enum name="PACKET_UNEXPECTED" start="0x3" description="Packet unexpected" />
-        <Enum name="TOKEN_CRC_ERROR" start="0x4" description="Token CRC error" />
-        <Enum name="DATA_CRC_ERROR" start="0x5" description="Data CRC error" />
-        <Enum name="TIME_OUT" start="0x6" description="Time out" />
-        <Enum name="BABBLE" start="0x7" description="Babble" />
-        <Enum name="TRUNCATED_EOP" start="0x8" description="Truncated EOP" />
-        <Enum name="SENT_RECEIVED_NAK" start="0x9" description="Sent/Received NAK" />
-        <Enum name="SENT_STALL" start="0xA" description="Sent Stall" />
-        <Enum name="OVERRUN" start="0xB" description="Overrun" />
-        <Enum name="SENT_EMPTY_PACKET" start="0xC" description="Sent empty packet" />
-        <Enum name="BITSTUFF_ERROR" start="0xD" description="Bitstuff error" />
-        <Enum name="SYNC_ERROR" start="0xE" description="Sync error" />
-        <Enum name="WRONG_DATA_TOGGLE" start="0xF" description="Wrong data toggle" />
-      </BitField>
-      <BitField start="15" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EPLISTSTART" access="Read/Write" description="USB EP Command/Status List start address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="24" name="EP_LIST" description="Start address of the USB EP Command/Status List." />
-    </Register>
-    <Register start="+0x00C" size="4" name="DATABUFSTART" access="Read/Write" description="USB Data buffer start address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="10" name="DA_BUF" description="Start address of the buffer pointer page where all endpoint data buffers are located." />
-    </Register>
-    <Register start="+0x010" size="4" name="LPM" access="Read/Write" description="Link Power Management register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="HIRD_HW" description="Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token" />
-      <BitField start="4" size="4" name="HIRD_SW" description="Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume." />
-      <BitField start="8" size="1" name="DATA_PENDING" description="As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="EPSKIP" access="Read/Write" description="USB Endpoint skip" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SKIP" description="Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit.  An interrupt will be generated when the Active bit goes from 1 to 0.  Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit." />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="EPINUSE" access="Read/Write" description="USB Endpoint Buffer in use" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
-      <BitField start="2" size="8" name="BUF" description="Buffer in use: This register has one bit per physical endpoint.  0: HW is accessing buffer 0.  1: HW is accessing buffer 1." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="EPBUFCFG" access="Read/Write" description="USB Endpoint Buffer Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
-      <BitField start="2" size="8" name="BUF_SB" description="Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer.  1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="INTSTAT" access="Read/Write" description="USB interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP0OUT" description="Interrupt status register bit for the Control EP0 OUT direction.  This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="1" size="1" name="EP0IN" description="Interrupt status register bit for the Control EP0 IN direction.  This bit will be set if NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="2" size="1" name="EP1OUT" description="Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="3" size="1" name="EP1IN" description="Interrupt status register bit for the EP1 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="4" size="1" name="EP2OUT" description="Interrupt status register bit for the EP2 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="5" size="1" name="EP2IN" description="Interrupt status register bit for the EP2 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="6" size="1" name="EP3OUT" description="Interrupt status register bit for the EP3 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="7" size="1" name="EP3IN" description="Interrupt status register bit for the EP3 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="8" size="1" name="EP4OUT" description="Interrupt status register bit for the EP4 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="9" size="1" name="EP4IN" description="Interrupt status register bit for the EP4 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction.  Software can clear this bit by writing a one to it." />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="FRAME_INT" description="Frame interrupt.  This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints.  Software can clear this bit by writing a one to it." />
-      <BitField start="31" size="1" name="DEV_INT" description="Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTEN" access="Read/Write" description="USB interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EP_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="FRAME_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
-      <BitField start="31" size="1" name="DEV_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTSETSTAT" access="Read/Write" description="USB set interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EP_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="FRAME_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
-      <BitField start="31" size="1" name="DEV_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
-    </Register>
-    <Register start="+0x02C" size="4" name="INTROUTING" access="Read/Write" description="USB interrupt routing register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="ROUTE_INT9_0" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
-      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="ROUTE_INT30" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
-      <BitField start="31" size="1" name="ROUTE_INT31" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
-    </Register>
-    <Register start="+0x034" size="4" name="EPTOGGLE" access="ReadOnly" description="USB Endpoint toggle register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="TOGGLE" description="Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0x50000000" description="GPIO port ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Portpin register port 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Portpin register port 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port 0/1  Read: output bits for port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port 0/1  Read: output bits for port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port 0/1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port 0/1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port 0/1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port 0/1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="RIT" start="12" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC" start="24" size="1" />
-      <BitField name="WWDT" start="25" size="1" />
-      <BitField name="BOD" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="RIT" start="12" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC" start="24" size="1" />
-      <BitField name="WWDT" start="25" size="1" />
-      <BitField name="BOD" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="RIT" start="12" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC" start="24" size="1" />
-      <BitField name="WWDT" start="25" size="1" />
-      <BitField name="BOD" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="RIT" start="12" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC" start="24" size="1" />
-      <BitField name="WWDT" start="25" size="1" />
-      <BitField name="BOD" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="RIT" start="12" size="1" />
-      <BitField name="SSP1" start="14" size="1" />
-      <BitField name="I2C" start="15" size="1" />
-      <BitField name="CT16B0" start="16" size="1" />
-      <BitField name="CT16B1" start="17" size="1" />
-      <BitField name="CT32B0" start="18" size="1" />
-      <BitField name="CT32B1" start="19" size="1" />
-      <BitField name="SSP0" start="20" size="1" />
-      <BitField name="USART" start="21" size="1" />
-      <BitField name="USB" start="22" size="1" />
-      <BitField name="USB_FIQ" start="23" size="1" />
-      <BitField name="ADC" start="24" size="1" />
-      <BitField name="WWDT" start="25" size="1" />
-      <BitField name="BOD" start="26" size="1" />
-      <BitField name="FLASH" start="27" size="1" />
-      <BitField name="USBWAKEUP" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="PIN_INT0" start="4" size="4" />
-      <BitField name="PIN_INT1" start="12" size="4" />
-      <BitField name="PIN_INT2" start="20" size="4" />
-      <BitField name="PIN_INT3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="PIN_INT4" start="4" size="4" />
-      <BitField name="PIN_INT5" start="12" size="4" />
-      <BitField name="PIN_INT6" start="20" size="4" />
-      <BitField name="PIN_INT7" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="GINT0" start="4" size="4" />
-      <BitField name="GINT1" start="12" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="RIT" start="4" size="4" />
-      <BitField name="SSP1" start="20" size="4" />
-      <BitField name="I2C" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="CT16B0" start="4" size="4" />
-      <BitField name="CT16B1" start="12" size="4" />
-      <BitField name="CT32B0" start="20" size="4" />
-      <BitField name="CT32B1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SSP0" start="4" size="4" />
-      <BitField name="USART" start="12" size="4" />
-      <BitField name="USB" start="20" size="4" />
-      <BitField name="USB_FIQ" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="ADC" start="4" size="4" />
-      <BitField name="WWDT" start="12" size="4" />
-      <BitField name="BOD" start="20" size="4" />
-      <BitField name="FLASH" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="USBWAKEUP" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Vectors.s b/examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Vectors.s
deleted file mode 100644
index 1cbd4bb2..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/LPC13Uxx_Vectors.s
+++ /dev/null
@@ -1,342 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak RIT_IRQHandler
-  .thumb_set RIT_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak I2C_IRQHandler
-  .thumb_set I2C_IRQHandler,Dummy_Handler
-
-  .weak CT16B0_IRQHandler
-  .thumb_set CT16B0_IRQHandler,Dummy_Handler
-
-  .weak CT16B1_IRQHandler
-  .thumb_set CT16B1_IRQHandler,Dummy_Handler
-
-  .weak CT32B0_IRQHandler
-  .thumb_set CT32B0_IRQHandler,Dummy_Handler
-
-  .weak CT32B1_IRQHandler
-  .thumb_set CT32B1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak USART_IRQHandler
-  .thumb_set USART_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak USB_FIQ_IRQHandler
-  .thumb_set USB_FIQ_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak BOD_IRQHandler
-  .thumb_set BOD_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak USBWAKEUP_IRQHandler
-  .thumb_set USBWAKEUP_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RIT_IRQHandler
-RIT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C_IRQHandler
-I2C_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT16B0_IRQHandler
-CT16B0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT16B1_IRQHandler
-CT16B1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT32B0_IRQHandler
-CT32B0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CT32B1_IRQHandler
-CT32B1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART_IRQHandler
-USART_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_FIQ_IRQHandler
-USB_FIQ_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_IRQHandler
-BOD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USBWAKEUP_IRQHandler
-USBWAKEUP_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word RIT_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word SSP1_IRQHandler
-  .word I2C_IRQHandler
-  .word CT16B0_IRQHandler
-  .word CT16B1_IRQHandler
-  .word CT32B0_IRQHandler
-  .word CT32B1_IRQHandler
-  .word SSP0_IRQHandler
-  .word USART_IRQHandler
-  .word USB_IRQHandler
-  .word USB_FIQ_IRQHandler
-  .word ADC_IRQHandler
-  .word WWDT_IRQHandler
-  .word BOD_IRQHandler
-  .word FLASH_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word USBWAKEUP_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/lpc13xx/flash_placement.xml b/examples/device/cdc_msc/ses/lpc13xx/flash_placement.xml
deleted file mode 100644
index 27a63d5b..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/flash_placement.xml
+++ /dev/null
@@ -1,41 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM3_NAME:RAM3)">
-    <ProgramSection alignment="4" load="No" name=".data3_run" />
-    <ProgramSection alignment="4" load="No" name=".bss3" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject b/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject
deleted file mode 100644
index f25307dd..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject
+++ /dev/null
@@ -1,119 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc13xx" target="8" version="2">
-  <project Name="lpc13xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC1347FBD64"
-      arm_architecture="v7M"
-      arm_core_type="Cortex-M3"
-      arm_endian="Little"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="0"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00010000;RAM;0x10000000;0x00002000;RAM;0x20000000;0x00000800"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC1347"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;CFG_TUSB_MCU=OPT_MCU_LPC13XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss3&quot;)));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc13xx/lpc_chip_13xx/inc;$(rootDir)/src"
-      debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC1347FBD64_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC1300;DeviceSubFamily=LPC134x;Target=LPC1347FBD64;Placement=Flash;rootDir=../../../../.."
-      package_dependencies="LPC1300"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC1300_Startup.s" />
-      <file file_name="LPC13Uxx_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="LPC1300_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-      <file file_name="LPC1347FBD64_MemoryMap.xml" />
-      <file file_name="flash_placement.xml" />
-    </folder>
-    <configuration
-      Name="Debug"
-      link_use_linker_script_file="No"
-      linker_section_placement_file="flash_placement.xml" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="lpcxpresso1347">
-          <file file_name="../../../../../hw/bsp/lpcxpresso1347/lpcxpresso1347.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_13xx">
-              <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/chip.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/clock_13xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/cmsis.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/cmsis_1347.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/core_cm3.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/core_cmFunc.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/core_cmInstr.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/gpio_13xx_1.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/gpio_13xx_2.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/iocon_13xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/lpc_types.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/sys_config.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/sysctl_13xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc/uart_13xx.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/src/chip_13xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/src/clock_13xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/src/gpio_13xx_1.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/src/sysctl_13xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/src/sysinit_13xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_13xx/src/iocon_13xx.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <configuration
-      Name="LPCXpresso 1347"
-      c_preprocessor_definitions="BOARD_LPCXPRESSO1347" />
-  </project>
-  <configuration
-    Name="LPCXpresso 1347"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc13xx/thumb_crt0.s b/examples/device/cdc_msc/ses/lpc13xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/lpc13xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/LPC1700_Startup.s b/examples/device/cdc_msc/ses/lpc175x_6x/LPC1700_Startup.s
deleted file mode 100644
index f039ad93..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/LPC1700_Startup.s
+++ /dev/null
@@ -1,109 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/LPC1700_Target.js b/examples/device/cdc_msc/ses/lpc175x_6x/LPC1700_Target.js
deleted file mode 100644
index 7f945a3d..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/LPC1700_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/LPC1769_MemoryMap.xml b/examples/device/cdc_msc/ses/lpc175x_6x/LPC1769_MemoryMap.xml
deleted file mode 100644
index d9c07aea..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/LPC1769_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC1769">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x2007C000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/LPC176x5x_Registers.xml b/examples/device/cdc_msc/ses/lpc175x_6x/LPC176x5x_Registers.xml
deleted file mode 100644
index fd38966b..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/LPC176x5x_Registers.xml
+++ /dev/null
@@ -1,11058 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC176x5x" description="LPC176x/LPC175x M3">
-  <RegisterGroup name="WDT" start="0x40000000" description="Watchdog Timer (WDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="STOP" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
-        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, cleared by software." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag.  Cleared by software." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="Count" description="Watchdog time-out interval." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="Count" description="Counter timer value." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLKSEL" description="Selects source of WDT clock">
-        <Enum name="IRC" start="0x0" description="IRC" />
-        <Enum name="PCLK" start="0x1" description="Peripheral clock" />
-        <Enum name="RTCOSC" start="0x2" description="RTC oscillator" />
-      </BitField>
-      <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.">
-        <Enum name="UNLOCKED" start="0" description="This bit is set to 0 on any reset. It cannot be cleared by software." />
-        <Enum name="LOCKED" start="1" description="Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;cannot be modified." />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40004000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40008000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40010000" description="UART1  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
-        <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
-        <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="MODEM" start="0x0" description="4   - Modem Interrupt." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="VALID" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM1) ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI" start="0x40020000" description="SPI ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
-        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
-      </BitField>
-      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
-        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
-        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
-      </BitField>
-      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
-        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
-        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
-      </BitField>
-      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
-        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
-        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
-      </BitField>
-      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
-        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
-        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
-      </BitField>
-      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
-        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
-        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
-      </BitField>
-      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
-        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
-        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
-        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
-        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
-        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
-        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
-        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
-        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
-        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
-      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC)  ">
-    <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
-        <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-        <Enum name="NO_EFFECT_" start="0" description="No effect." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
-        <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-      </BitField>
-    </Register>
-    <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
-    <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0INT" description="Port 0 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="P2INT" description="Port 2 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PINCONNECT" start="0x4002C000" description="Pin connect block">
-    <Register start="+0x000" size="4" name="PINSEL0" access="Read/Write" description="Pin function select register 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_0" description="Pin function select P0.0.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.0" />
-        <Enum name="RD1" start="0x1" description="RD1" />
-        <Enum name="TXD3" start="0x2" description="TXD3" />
-        <Enum name="SDA1" start="0x3" description="SDA1" />
-      </BitField>
-      <BitField start="2" size="2" name="P0_1" description="Pin function select P0.1.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.1" />
-        <Enum name="TD1" start="0x1" description="TD1" />
-        <Enum name="RXD3" start="0x2" description="RXD3" />
-        <Enum name="SCL1" start="0x3" description="SCL1" />
-      </BitField>
-      <BitField start="4" size="2" name="P0_2" description="Pin function select P0.2.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.2" />
-        <Enum name="TXD0" start="0x1" description="TXD0" />
-        <Enum name="AD0" start="0x2" description="AD0.7" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="P0_3" description="Pin function select P0.3.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.3." />
-        <Enum name="RXD0" start="0x1" description="RXD0" />
-        <Enum name="AD0" start="0x2" description="AD0.6" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_4" description="Pin function select P0.4.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.4." />
-        <Enum name="I2SRX_CLK" start="0x1" description="I2SRX_CLK" />
-        <Enum name="RD2" start="0x2" description="RD2" />
-        <Enum name="CAP2" start="0x3" description="CAP2.0" />
-      </BitField>
-      <BitField start="10" size="2" name="P0_5" description="Pin function select P0.5.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.5." />
-        <Enum name="I2SRX_WS" start="0x1" description="I2SRX_WS" />
-        <Enum name="TD2" start="0x2" description="TD2" />
-        <Enum name="CAP2" start="0x3" description="CAP2.1" />
-      </BitField>
-      <BitField start="12" size="2" name="P0_6" description="Pin function select P0.6.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.6." />
-        <Enum name="I2SRX_SDA" start="0x1" description="I2SRX_SDA" />
-        <Enum name="SSEL1" start="0x2" description="SSEL1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.0" />
-      </BitField>
-      <BitField start="14" size="2" name="P0_7" description="Pin function select P0.7.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.7." />
-        <Enum name="I2STX_CLK" start="0x1" description="I2STX_CLK" />
-        <Enum name="SCK1" start="0x2" description="SCK1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.1" />
-      </BitField>
-      <BitField start="16" size="2" name="P0_8" description="Pin function select P0.8.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.8." />
-        <Enum name="I2STX_WS" start="0x1" description="I2STX_WS" />
-        <Enum name="MISO1" start="0x2" description="MISO1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.2" />
-      </BitField>
-      <BitField start="18" size="2" name="P0_9" description="Pin function select P0.9.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.9" />
-        <Enum name="I2STX_SDA" start="0x1" description="I2STX_SDA" />
-        <Enum name="MOSI1" start="0x2" description="MOSI1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.3" />
-      </BitField>
-      <BitField start="20" size="2" name="P0_10" description="Pin function select P0.10.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.10" />
-        <Enum name="TXD2" start="0x1" description="TXD2" />
-        <Enum name="SDA2" start="0x2" description="SDA2" />
-        <Enum name="MAT3" start="0x3" description="MAT3.0" />
-      </BitField>
-      <BitField start="22" size="2" name="P0_11" description="Pin function select P0.11.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.11" />
-        <Enum name="RXD2" start="0x1" description="RXD2" />
-        <Enum name="SCL2" start="0x2" description="SCL2" />
-        <Enum name="MAT3" start="0x3" description="MAT3.1" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P0_15" description="Pin function select P0.15.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.15" />
-        <Enum name="TXD1" start="0x1" description="TXD1" />
-        <Enum name="SCK0" start="0x2" description="SCK0" />
-        <Enum name="SCK" start="0x3" description="SCK" />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="PINSEL1" access="Read/Write" description="Pin function select register 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_16" description="Pin function select P0.16.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.16" />
-        <Enum name="RXD1" start="0x1" description="RXD1" />
-        <Enum name="SSEL0" start="0x2" description="SSEL0" />
-        <Enum name="SSEL" start="0x3" description="SSEL" />
-      </BitField>
-      <BitField start="2" size="2" name="P0_17" description="Pin function select P0.17.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.17" />
-        <Enum name="CTS1" start="0x1" description="CTS1" />
-        <Enum name="MISO0" start="0x2" description="MISO0" />
-        <Enum name="MISO" start="0x3" description="MISO" />
-      </BitField>
-      <BitField start="4" size="2" name="P0_18" description="Pin function select P0.18.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.18" />
-        <Enum name="DCD1" start="0x1" description="DCD1" />
-        <Enum name="MOSI0" start="0x2" description="MOSI0" />
-        <Enum name="MOSI" start="0x3" description="MOSI" />
-      </BitField>
-      <BitField start="6" size="2" name="P0_19" description="Pin function select P019.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.19." />
-        <Enum name="DSR1" start="0x1" description="DSR1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="SDA1" start="0x3" description="SDA1" />
-      </BitField>
-      <BitField start="8" size="2" name="P0_20" description="Pin function select P0.20.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.20." />
-        <Enum name="DTR1" start="0x1" description="DTR1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="SCL1" start="0x3" description="SCL1" />
-      </BitField>
-      <BitField start="10" size="2" name="P0_21" description="Pin function select P0.21.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0.21." />
-        <Enum name="RI1" start="0x1" description="RI1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RD1" start="0x3" description="RD1" />
-      </BitField>
-      <BitField start="12" size="2" name="P0_22" description="Pin function select P022">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.22." />
-        <Enum name="RTS1" start="0x1" description="RTS1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="TD1" start="0x3" description="TD1" />
-      </BitField>
-      <BitField start="14" size="2" name="P0_23" description="Pin function select P023.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.23." />
-        <Enum name="AD0" start="0x1" description="AD0.0" />
-        <Enum name="I2SRX_CLK" start="0x2" description="I2SRX_CLK" />
-        <Enum name="CAP3" start="0x3" description="CAP3.0" />
-      </BitField>
-      <BitField start="16" size="2" name="P0_24" description="Pin function select P0.24.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.24." />
-        <Enum name="AD0" start="0x1" description="AD0.1" />
-        <Enum name="I2SRX_WS" start="0x2" description="I2SRX_WS" />
-        <Enum name="CAP3" start="0x3" description="CAP3.1" />
-      </BitField>
-      <BitField start="18" size="2" name="P0_25" description="Pin function select P0.25.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.25" />
-        <Enum name="AD0" start="0x1" description="AD0.2" />
-        <Enum name="I2SRX_SDA" start="0x2" description="I2SRX_SDA" />
-        <Enum name="TXD3" start="0x3" description="TXD3" />
-      </BitField>
-      <BitField start="20" size="2" name="P0_26" description="Pin function select P0.26.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.26" />
-        <Enum name="AD0" start="0x1" description="AD0.3" />
-        <Enum name="AOUT" start="0x2" description="AOUT" />
-        <Enum name="RXD3" start="0x3" description="RXD3" />
-      </BitField>
-      <BitField start="22" size="2" name="P0_27" description="Pin function select P0.27.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.27" />
-        <Enum name="SDA0" start="0x1" description="SDA0" />
-        <Enum name="USB_SDA" start="0x2" description="USB_SDA" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="2" name="P0_28" description="Pin function select P0.28.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.28" />
-        <Enum name="SCL0" start="0x1" description="SCL0" />
-        <Enum name="USB_SCL" start="0x2" description="USB_SCL" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="26" size="2" name="P0_29" description="Pin function select P0.29">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.29" />
-        <Enum name="USB_DP" start="0x1" description="USB_D+" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="28" size="2" name="P0_30" description="Pin function select P0.30.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.30" />
-        <Enum name="USB_DM" start="0x1" description="USB_D-" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="PINSEL2" access="Read/Write" description="Pin function select register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_0" description="Pin function select P1.0.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.0" />
-        <Enum name="ENET_TXD0" start="0x1" description="ENET_TXD0" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P1_1" description="Pin function select P1.1.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.1" />
-        <Enum name="ENET_TXD1" start="0x1" description="ENET_TXD1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="P1_4" description="Pin function select P1.4.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.4." />
-        <Enum name="ENET_TX_EN" start="0x1" description="ENET_TX_EN" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="2" name="P1_8" description="Pin function select P1.8.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.8." />
-        <Enum name="ENET_CRS" start="0x1" description="ENET_CRS" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="18" size="2" name="P1_9" description="Pin function select P1.9.">
-        <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.9" />
-        <Enum name="ENET_RXD0" start="0x1" description="ENET_RXD0" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="20" size="2" name="P1_10" description="Pin function select P1.10.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.10" />
-        <Enum name="ENET_RXD1" start="0x1" description="ENET_RXD1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="2" name="P1_14" description="Pin function select P1.14.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.14" />
-        <Enum name="ENET_RX_ER" start="0x1" description="ENET_RX_ER" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P1_15" description="Pin function select P1.15.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.15" />
-        <Enum name="ENET_REF_CLK" start="0x1" description="ENET_REF_CLK" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="4" name="PINSEL3" access="Read/Write" description="Pin function select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_16" description="Pin function select P1.16.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.16" />
-        <Enum name="ENET_MDC" start="0x1" description="ENET_MDC" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P1_17" description="Pin function select P1.17.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.17" />
-        <Enum name="ENET_MDIO" start="0x1" description="ENET_MDIO" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="P1_18" description="Pin function select P1.18.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.18" />
-        <Enum name="USB_UP_LED" start="0x1" description="USB_UP_LED" />
-        <Enum name="PWM1" start="0x2" description="PWM1.1" />
-        <Enum name="CAP1" start="0x3" description="CAP1.0" />
-      </BitField>
-      <BitField start="6" size="2" name="P1_19" description="Pin function select P1.19.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.19." />
-        <Enum name="MCOA0" start="0x1" description="MCOA0" />
-        <Enum name="USB_PPWR" start="0x2" description="USB_PPWR" />
-        <Enum name="CAP1" start="0x3" description="CAP1.1" />
-      </BitField>
-      <BitField start="8" size="2" name="P1_20" description="Pin function select P1.20.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.20." />
-        <Enum name="MCI0" start="0x1" description="MCI0" />
-        <Enum name="PWM1" start="0x2" description="PWM1.2" />
-        <Enum name="SCK0" start="0x3" description="SCK0" />
-      </BitField>
-      <BitField start="10" size="2" name="P1_21" description="Pin function select P1.21.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.21." />
-        <Enum name="MCABORT" start="0x1" description="MCABORT" />
-        <Enum name="PWM1" start="0x2" description="PWM1.3" />
-        <Enum name="SSEL0" start="0x3" description="SSEL0" />
-      </BitField>
-      <BitField start="12" size="2" name="P1_22" description="Pin function select P1.22">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.22." />
-        <Enum name="MCOB0" start="0x1" description="MCOB0" />
-        <Enum name="USB_PWRD" start="0x2" description="USB_PWRD" />
-        <Enum name="MAT1" start="0x3" description="MAT1.0" />
-      </BitField>
-      <BitField start="14" size="2" name="P1_23" description="Pin function select P1.23.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.23." />
-        <Enum name="MCI1" start="0x1" description="MCI1" />
-        <Enum name="PWM1" start="0x2" description="PWM1.4" />
-        <Enum name="MISO0" start="0x3" description="MISO0" />
-      </BitField>
-      <BitField start="16" size="2" name="P1_24" description="Pin function select P1.24.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.24." />
-        <Enum name="MCI2" start="0x1" description="MCI2" />
-        <Enum name="PWM1" start="0x2" description="PWM1.5" />
-        <Enum name="MOSI0" start="0x3" description="MOSI0" />
-      </BitField>
-      <BitField start="18" size="2" name="P1_25" description="Pin function select P1.25.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.25" />
-        <Enum name="MCOA1" start="0x1" description="MCOA1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="MAT1" start="0x3" description="MAT1.1" />
-      </BitField>
-      <BitField start="20" size="2" name="P1_26" description="Pin function select P1.26.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.26" />
-        <Enum name="MCOB1" start="0x1" description="MCOB1" />
-        <Enum name="PWM1" start="0x2" description="PWM1.6" />
-        <Enum name="CAP0" start="0x3" description="CAP0.0" />
-      </BitField>
-      <BitField start="22" size="2" name="P1_27" description="Pin function select P1.27.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.27" />
-        <Enum name="CLKOUT" start="0x1" description="CLKOUT" />
-        <Enum name="USB_OVRCR" start="0x2" description="USB_OVRCR" />
-        <Enum name="CAP0" start="0x3" description="CAP0.1" />
-      </BitField>
-      <BitField start="24" size="2" name="P1_28" description="Pin function select P1.28.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.28" />
-        <Enum name="MCOA2" start="0x1" description="MCOA2" />
-        <Enum name="PCAP1" start="0x2" description="PCAP1.0" />
-        <Enum name="MAT0" start="0x3" description="MAT0.0" />
-      </BitField>
-      <BitField start="26" size="2" name="P1_29" description="Pin function select P1.29">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.29" />
-        <Enum name="MCOB2" start="0x1" description="MCOB2" />
-        <Enum name="PCAP1" start="0x2" description="PCAP1.1" />
-        <Enum name="MAT0" start="0x3" description="MAT0.1" />
-      </BitField>
-      <BitField start="28" size="2" name="P1_30" description="Pin function select P1.30.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.30" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="VBUS" start="0x2" description="VBUS" />
-        <Enum name="AD0" start="0x3" description="AD0.4" />
-      </BitField>
-      <BitField start="30" size="2" name="P1_31" description="Pin function select P1.31.">
-        <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.31" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SCK1" start="0x2" description="SCK1" />
-        <Enum name="AD0" start="0x3" description="AD0.5" />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="4" name="PINSEL4" access="Read/Write" description="Pin function select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P2_0" description="Pin function select P2.0.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.0" />
-        <Enum name="PWM1" start="0x1" description="PWM1.1" />
-        <Enum name="TXD1" start="0x2" description="TXD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P2_1" description="Pin function select P2.1.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.1" />
-        <Enum name="PWM1" start="0x1" description="PWM1.2" />
-        <Enum name="RXD1" start="0x2" description="RXD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="P2_2" description="Pin function select P2.2.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.2" />
-        <Enum name="PWM1" start="0x1" description="PWM1.3" />
-        <Enum name="CTS1" start="0x2" description="CTS1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="P2_3" description="Pin function select P2.3.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.3." />
-        <Enum name="PWM1" start="0x1" description="PWM1.4" />
-        <Enum name="DCD1" start="0x2" description="DCD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="2" name="P2_4" description="Pin function select P2.4.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.4." />
-        <Enum name="PWM1" start="0x1" description="PWM1.5" />
-        <Enum name="DSR1" start="0x2" description="DSR1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="2" name="P2_5" description="Pin function select P2.5.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.5." />
-        <Enum name="PWM1" start="0x1" description="PWM1.6" />
-        <Enum name="DTR1" start="0x2" description="DTR1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="12" size="2" name="P2_6" description="Pin function select P2.6.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.6." />
-        <Enum name="PCAP1" start="0x1" description="PCAP1.0" />
-        <Enum name="RI1" start="0x2" description="RI1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="14" size="2" name="P2_7" description="Pin function select P2.7.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.7." />
-        <Enum name="RD2" start="0x1" description="RD2" />
-        <Enum name="RTS1" start="0x2" description="RTS1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="16" size="2" name="P2_8" description="Pin function select P2.8.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.8." />
-        <Enum name="TD2" start="0x1" description="TD2" />
-        <Enum name="TXD2" start="0x2" description="TXD2" />
-        <Enum name="ENET_MDC" start="0x3" description="ENET_MDC" />
-      </BitField>
-      <BitField start="18" size="2" name="P2_9" description="Pin function select P2.9.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.9" />
-        <Enum name="USB_CONNECT" start="0x1" description="USB_CONNECT" />
-        <Enum name="RXD2" start="0x2" description="RXD2" />
-        <Enum name="ENET_MDIO" start="0x3" description="ENET_MDIO" />
-      </BitField>
-      <BitField start="20" size="2" name="P2_10" description="Pin function select P2.10.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.10" />
-        <Enum name="EINT0" start="0x1" description="EINT0" />
-        <Enum name="NMI" start="0x2" description="NMI" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="22" size="2" name="P2_11" description="Pin function select P2.11.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.11" />
-        <Enum name="EINT1" start="0x1" description="EINT1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_CLK" start="0x3" description="I2STX_CLK" />
-      </BitField>
-      <BitField start="24" size="2" name="P2_12" description="Pin function select P2.12.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.12" />
-        <Enum name="EINT2" start="0x1" description="EINT2" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_WS" start="0x3" description="I2STX_WS" />
-      </BitField>
-      <BitField start="26" size="2" name="P2_13" description="Pin function select P2.13.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.13" />
-        <Enum name="EINT3" start="0x1" description="EINT3" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_SDA" start="0x3" description="I2STX_SDA" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PINSEL7" access="Read/Write" description="Pin function select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="18" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="2" name="P3_25" description="Pin function select P3.25.">
-        <Enum name="GPIO_P3" start="0x0" description="GPIO P3.25" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="MAT0" start="0x2" description="MAT0.0" />
-        <Enum name="PWM1" start="0x3" description="PWM1.2" />
-      </BitField>
-      <BitField start="20" size="2" name="P3_26" description="Pin function select P3.26.">
-        <Enum name="GPIO_P3" start="0x0" description="GPIO P3.26" />
-        <Enum name="STCLK" start="0x1" description="STCLK" />
-        <Enum name="MAT0" start="0x2" description="MAT0.1" />
-        <Enum name="PWM1" start="0x3" description="PWM1.3" />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="PINSEL9" access="Read/Write" description="Pin function select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="2" name="P4_28" description="Pin function select P4.28.">
-        <Enum name="GPIO_P4" start="0x0" description="GPIO P4.28" />
-        <Enum name="RX_MCLK" start="0x1" description="RX_MCLK" />
-        <Enum name="MAT2" start="0x2" description="MAT2.0" />
-        <Enum name="TXD3" start="0x3" description="TXD3" />
-      </BitField>
-      <BitField start="26" size="2" name="P4_29" description="Pin function select P4.29.">
-        <Enum name="GPIO_P4" start="0x0" description="GPIO P4.29" />
-        <Enum name="TX_MCLK" start="0x1" description="TX_MCLK" />
-        <Enum name="MAT2" start="0x2" description="MAT2.1" />
-        <Enum name="RXD3" start="0x3" description="RXD3" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="PINSEL10" access="Read/Write" description="Pin function select register 10" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
-      <BitField start="3" size="1" name="TPIUCTRL" description="TPIU interface pins control.">
-        <Enum name="DISABLED" start="0" description="Disabled. TPIU interface is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
-    </Register>
-    <Register start="+0x040" size="4" name="PINMODE0" access="Read/Write" description="Pin mode select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_00MODE" description="Port 0 pin 0 on-chip pull-up/down resistor control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P0_01MODE" description="Port 0 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P0_02MODE" description="Port 0 pin 2 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.2 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.2 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.2 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.2 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P0_03MODE" description="Port 0 pin 3 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.3 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.3 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.3 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.3 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_04MODE" description="Port 0 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P0_05MODE" description="Port 0 pin 5 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.5 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.5 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.5 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.5 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P0_06MODE" description="Port 0 pin 6 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.6 pin has a pull-up resistor enabled." />
-        <Enum name="DISABLED" start="0x1" description="Disabled. Repeater. P0.6 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.6 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.6 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P0_07MODE" description="Port 0 pin 7 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.7 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.7 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.7 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.7 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P0_08MODE" description="Port 0 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P0_09MODE" description="Port 0 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P0_10MODE" description="Port 0 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P0_11MODE" description="Port 0 pin 11 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.11 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.11 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.11 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.11 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P0_15MODE" description="Port 0 pin 15 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.15 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.15 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.15 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.15 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x044" size="4" name="PINMODE1" access="Read/Write" description="Pin mode select register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_16MODE" description="Port 1 pin 16 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.16 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.16 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.16 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.16 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P0_17MODE" description="Port 1 pin 17 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.17 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.17 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.17 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.17 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P0_18MODE" description="Port 1 pin 18 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.18 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.18 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.18 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.18 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P0_19MODE" description="Port 1 pin 19 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.19 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.19 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.19 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.19 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_20MODE" description="Port 1 pin 20 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.20 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.20 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.20 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.20 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P0_21MODE" description="Port 1 pin 21 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.21 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.21 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.21 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.21 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P0_22MODE" description="Port 1 pin 22 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.22 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.22 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.22 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.22 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P0_23MODE" description="Port 1 pin 23 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.23 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.23 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.23 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.23 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P0_24MODE" description="Port 1 pin 24 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.24 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.24 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.24 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.24 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P0_25MODE" description="Port 1 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P0_26MODE" description="Port 1 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="PINMODE2" access="Read/Write" description="Pin mode select register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_00MODE" description="Port 1 pin 0 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P1_01MODE" description="Port 1 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="P1_04MODE" description="Port 1 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="2" name="P1_08MODE" description="Port 1 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P1_09MODE" description="Port 1 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P1_10MODE" description="Port 1 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="2" name="P1_14MODE" description="Port 1 pin 14 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.14 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.14 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.14 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.14 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="30" size="2" name="P1_15MODE" description="Port 1 pin 15 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.15 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.15 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.15 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.15 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x04C" size="4" name="PINMODE3" access="Read/Write" description="Pin mode select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_16MODE" description="Port 1 pin 16 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.16 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.16 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.16 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.16 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P1_17MODE" description="Port 1 pin 17 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.17 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.17 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.17 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.17 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P1_18MODE" description="Port 1 pin 18 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.18 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.18 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.18 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.18 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P1_19MODE" description="Port 1 pin 19 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.19 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.19 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.19 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.19 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P1_20MODE" description="Port 1 pin 20 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.20 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.20 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.20 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.20 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P1_21MODE" description="Port 1 pin 21 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.21 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.21 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.21 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.21 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P1_22MODE" description="Port 1 pin 22 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.22 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.22 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.22 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.22 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P1_23MODE" description="Port 1 pin 23 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.23 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.23 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.23 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.23 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P1_24MODE" description="Port 1 pin 24 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.24 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.24 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.24 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.24 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P1_25MODE" description="Port 1 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P1_26MODE" description="Port 1 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P1_27MODE" description="Port 1 pin 27 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.27 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.27 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.27 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.27 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="2" name="P1_28MODE" description="Port 1 pin 28 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.28 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.28 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.28 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.28 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P1_29MODE" description="Port 1 pin 29 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.29 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.29 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.29 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.29 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="2" name="P1_30MODE" description="Port 1 pin 30 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.30 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.30 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.30 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.30 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="30" size="2" name="P1_31MODE" description="Port 1 pin 31 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.31 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.31 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.31 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.31 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x050" size="4" name="PINMODE4" access="Read/Write" description="Pin mode select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P2_00MODE" description="Port 2 pin 0 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P2_01MODE" description="Port 2 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P2_02MODE" description="Port 2 pin 2 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.2 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.2 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.2 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.2 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P2_03MODE" description="Port 2 pin 3 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.3 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.3 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.3 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.3 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P2_04MODE" description="Port 2 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P2_05MODE" description="Port 2 pin 5 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.5 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.5 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.5 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.5 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P2_06MODE" description="Port 2 pin 6 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.6 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.6 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.6 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.6 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P2_07MODE" description="Port 2 pin 7 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.7 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.7 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.7 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.7 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P2_08MODE" description="Port 2 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P2_09MODE" description="Port 2 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P2_10MODE" description="Port 2 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P2_11MODE" description="Port 2 pin 11 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.11 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.11 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.11 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.11 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="2" name="P2_12MODE" description="Port 2 pin 12 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.12 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.12 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.12 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.12 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P2_13MODE" description="Port 2 pin 13 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.13 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.13 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.13 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.13 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="PINMODE7" access="Read/Write" description="Pin mode select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="P3_25MODE" description="Port 3 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P3.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P3.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P3_26MODE" description="Port 3 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P3.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P3.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x064" size="4" name="PINMODE9" access="Read/Write" description="Pin mode select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="2" name="P4_28MODE" description="Port 4 pin 28 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.28 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P4.28 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P4.28 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.28 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P4_29MODE" description="Port 4 pin 29 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.29 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P4.29 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P4.29 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.29 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="PINMODE_OD0" access="Read/Write" description="Open drain mode control register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_00OD" description="Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P0_01OD" description="Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.1 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="1" name="P0_02OD" description="Port 0 pin 2 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.2 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.2 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="3" size="1" name="P0_03OD" description="Port 0 pin 3 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.3 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.3 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="4" size="1" name="P0_04OD" description="Port 0 pin 4 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="1" name="P0_05OD" description="Port 0 pin 5 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.5 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.5 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="6" size="1" name="P0_06OD" description="Port 0 pin 6 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.6 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.6 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="7" size="1" name="P0_07OD" description="Port 0 pin 7 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.7 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.7 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="8" size="1" name="P0_08OD" description="Port 0 pin 8 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P0_09OD" description="Port 0 pin 9 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P0_10OD" description="Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="1" name="P0_11OD" description="Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.11 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.11 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="P0_15OD" description="Port 0 pin 15 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.15 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.15 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="16" size="1" name="P0_16OD" description="Port 0 pin 16 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.16 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.16 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="17" size="1" name="P0_17OD" description="Port 0 pin 17 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.17 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.17 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="18" size="1" name="P0_18OD" description="Port 0 pin 18 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.18 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.18 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="19" size="1" name="P0_19OD" description="Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.19 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.19 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="20" size="1" name="P0_20OD" description="Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.20 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.20 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="21" size="1" name="P0_21OD" description="Port 0 pin 21 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.21 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.21 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="22" size="1" name="P0_22OD" description="Port 0 pin 22 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.22 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.22 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="23" size="1" name="P0_23OD" description="Port 0 pin 23 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="24" size="1" name="P0_24OD" description="Port 0 pin 24open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="25" size="1" name="P0_25OD" description="Port 0 pin 25 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P0_26OD" description="Port 0 pin 26 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.26 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.26 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="27" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="P0_29OD" description="Port 0 pin 29 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.29 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.29 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="30" size="1" name="P0_30OD" description="Port 0 pin 30 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.30 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.30 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="PINMODE_OD1" access="Read/Write" description="Open drain mode control register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P1_00OD" description="Port 1 pin 0 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P1.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P1_01OD" description="Port 1 pin 1 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.1 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="P1_04OD" description="Port 1 pin 4 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="P1_08OD" description="Port 1 pin 8 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P1_09OD" description="Port 1 pin 9 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P1_10OD" description="Port 1 pin 10 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="P1_14OD" description="Port 1 pin 14 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.14 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.14 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="15" size="1" name="P1_15OD" description="Port 1 pin 15 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.15 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.15 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="16" size="1" name="P1_16OD" description="Port 1 pin 16 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.16 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.16 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="17" size="1" name="P1_17OD" description="Port 1 pin 17 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.17 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.17 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="18" size="1" name="P1_18OD" description="Port 1 pin 18 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.18 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.18 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="19" size="1" name="P1_19OD" description="Port 1 pin 19 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.19 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.19 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="20" size="1" name="P1_20OD" description="Port 1 pin 20open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.20 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.20 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="21" size="1" name="P1_21OD" description="Port 1 pin 21 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.21 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.21 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="22" size="1" name="P1_22OD" description="Port 1 pin 22 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.22 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.22 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="23" size="1" name="P1_23OD" description="Port 1 pin 23 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="24" size="1" name="P1_24OD" description="Port 1 pin 24open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.24 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.24 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="25" size="1" name="P1_25OD" description="Port 1 pin 25 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P1_26OD" description="Port 1 pin 26 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.26 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.26 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="27" size="1" name="P1_27OD" description="Port 1 pin 27 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.27 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.27 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="28" size="1" name="P1_28OD" description="Port 1 pin 28 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.28 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.28 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="29" size="1" name="P1_29OD" description="Port 1 pin 29 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.29 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.29 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="30" size="1" name="P1_30OD" description="Port 1 pin 30 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.30 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.30 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="31" size="1" name="P1_31OD" description="Port 1 pin 31 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P1.31 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.31 pin is in the open drain mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x070" size="4" name="PINMODE_OD2" access="Read/Write" description="Open drain mode control register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_00OD" description="Port 2 pin 0 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P2.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P2_01OD" description="Port 2 pin 1 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.1p in is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="1" name="P2_02OD" description="Port 2 pin 2 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.2 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.2 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="3" size="1" name="P2_03OD" description="Port 2 pin 3 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.3 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.3 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="4" size="1" name="P2_04OD" description="Port 2 pin 4 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="1" name="P2_05OD" description="Port 2 pin 5 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.5 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.5 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="6" size="1" name="P2_06OD" description="Port 2 pin 6 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.6 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.6 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="7" size="1" name="P2_07OD" description="Port 2 pin 7 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.7 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.7 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="8" size="1" name="P2_08OD" description="Port 2 pin 8 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P2_09OD" description="Port 2 pin 9 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P2_10OD" description="Port 2 pin 10 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="1" name="P2_11OD" description="Port 2 pin 11 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.11 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.11 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="12" size="1" name="P2_12OD" description="Port 2 pin 12 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.12 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.12 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="13" size="1" name="P2_13OD" description="Port 2 pin 13 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.13 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.13 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x074" size="4" name="PINMODE_OD3" access="Read/Write" description="Open drain mode control register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="25" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="1" name="P3_25OD" description="Port 3 pin 25 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P3.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P3.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P3_26OD" description="Port 3 pin 26 open drain mode control, see P3.25OD" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x078" size="4" name="PINMODE_OD4" access="Read/Write" description="Open drain mode control register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="28" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="P4_28OD" description="Port 4 pin 28 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P4.28 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P4.28 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="29" size="1" name="P4_29OD" description="Port 4 pin 29 open drain mode control, see P4.28OD" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x07C" size="4" name="I2CPADCFG" access="Read/Write" description="I2C Pin Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDADRV0" description="Drive mode control for the SDA0 pin, P0.27.">
-        <Enum name="STANDARD" start="0" description="Standard. The SDA0 pin is in the standard drive mode." />
-        <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode." />
-      </BitField>
-      <BitField start="1" size="1" name="SDAI2C0" description="I 2C filter mode control for the SDA0 pin, P0.27.">
-        <Enum name="ENABLED" start="0" description="Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SCLDRV0" description="Drive mode control for the SCL0 pin, P0.28.">
-        <Enum name="STANDARD" start="0" description="Standard. The SCL0 pin is in the standard drive mode." />
-        <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode." />
-      </BitField>
-      <BitField start="3" size="1" name="SCLI2C0" description="I 2C filter mode control for the SCL0 pin, P0.28.">
-        <Enum name="ENABLED" start="0" description="Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
-        <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
-      </BitField>
-      <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="21" size="1" name="PDN" description="Power down mode">
-        <Enum name="POWERED" start="1" description="The A/D converter is operational." />
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
-        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
-        <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
-        <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
-        <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
-        <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
-        <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
-        <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
-      </BitField>
-      <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
-        <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
-        <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
-      <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
-      <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
-      <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
-      <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
-      <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
-      <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
-      <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
-      <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
-      <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
-      <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
-      <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
-      <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
-      <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
-      <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
-      <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
-      <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
-    <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAF" start="0x4003C000" description=" CAN controller acceptance filter ">
-    <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
-      <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
-      <BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
-        <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
-        <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
-    </Register>
-    <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCAN" start="0x40040000" description="Central CAN controller ">
-    <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
-      <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
-      <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
-      <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
-      <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
-      <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
-      <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN1" start="0x40044000" description="CAN1 controller ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN2" start="0x40048000" description="CAN1 controller ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x4008C000" description=" Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
-        <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
-        <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
-        <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
-        <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA access">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x40090000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x40094000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400B0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTER" access="Read/Write" description="Digital filter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
-      <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
-      <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
-      <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
-      <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
-      <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
-      <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
-      <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
-      <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
-      <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
-      <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
-      <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x400FC000" description="System and clock control">
-    <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0x303A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.">
-        <Enum name="1CLK" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock." />
-        <Enum name="2CLK" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock." />
-        <Enum name="3CLK" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock." />
-        <Enum name="4CLK" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock." />
-        <Enum name="5CLK" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only." />
-        <Enum name="6CLK" start="0x5" description="Flash accesses use 6 CPU clocks. This safe setting will work under any conditions." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="PLL0CON" access="Read/Write" description="PLL0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE0" description="PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register." />
-      <BitField start="1" size="1" name="PLLC0" description="PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="PLL0CFG" access="Read/Write" description="PLL0 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MSEL0" description="PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1.  Note: Not all values of M are needed, and therefore some are not supported by hardware." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="8" name="NSEL0" description="PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x088" size="4" name="PLL0STAT" access="ReadOnly" description="PLL0 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MSEL0" description="Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="8" name="NSEL0" description="Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider." />
-      <BitField start="24" size="1" name="PLLE0_STAT" description="Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered." />
-      <BitField start="25" size="1" name="PLLC0_STAT" description="Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered." />
-      <BitField start="26" size="1" name="PLOCK0" description="Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details." />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x08C" size="4" name="PLL0FEED" access="WriteOnly" description="PLL0 Feed Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLL0FEED" description="The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0" size="4" name="PLL1CON" access="Read/Write" description="PLL1 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE1" description="PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency." />
-      <BitField start="1" size="1" name="PLLC1" description="PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A4" size="4" name="PLL1CFG" access="Read/Write" description="PLL1 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL1" description="PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations." />
-      <BitField start="5" size="2" name="PSEL1" description="PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A8" size="4" name="PLL1STAT" access="ReadOnly" description="PLL1 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL1" description="Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1." />
-      <BitField start="5" size="2" name="PSEL1" description="Read-back for the PLL1 Divider value. This is the value currently used by PLL1." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE1_STAT" description="Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="PLLC1_STAT" description="Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="10" size="1" name="PLOCK1" description="Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0AC" size="4" name="PLL1FEED" access="WriteOnly" description="PLL1 Feed Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLL1FEED" description="The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode." />
-      <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode." />
-      <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit." />
-      <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0C4" size="4" name="PCONP" access="Read/Write" description="Power Control for Peripherals Register" reset_value="0x03BE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
-      <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
-      <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
-      <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
-      <BitField start="7" size="1" name="PCI2C0" description="The I2C0 interface power/clock control bit." />
-      <BitField start="8" size="1" name="PCSPI" description="The SPI interface power/clock control bit." />
-      <BitField start="9" size="1" name="PCRTC" description="The RTC power/clock control bit." />
-      <BitField start="10" size="1" name="PCSSP1" description="The SSP 1 interface power/clock control bit." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN." />
-      <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
-      <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
-      <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
-      <BitField start="16" size="1" name="PCRIT" description="Repetitive Interrupt Timer power/clock control bit." />
-      <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM" />
-      <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
-      <BitField start="19" size="1" name="PCI2C1" description="The I2C1 interface power/clock control bit." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="PCSSP0" description="The SSP0 interface power/clock control bit." />
-      <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
-      <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
-      <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
-      <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
-      <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
-      <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
-      <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
-      <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
-    </Register>
-    <Register start="+0x104" size="4" name="CCLKCFG" access="Read/Write" description="CPU Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCLKSEL" description="Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x108" size="4" name="USBCLKCFG" access="Read/Write" description="USB Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="USBSEL" description="Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output.  Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLKSRC" description="Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.">
-        <Enum name="SELECTS_THE_INTERNAL" start="0x0" description="Selects the Internal RC oscillator as the PLL0 clock source (default)." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the PLL0 clock source.  Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates &gt; 100 kBit/s." />
-        <Enum name="SELECTS_THE_RTC_OSCI" start="0x2" description="Selects the RTC oscillator as the PLL0 clock source." />
-        <Enum name="RESERVED" start="0x3" description="Reserved, do not use this setting." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
-      <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTMODE0" description="External interrupt 0 EINT0 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT0." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT0 is edge sensitive." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTMODE1" description="External interrupt 1 EINT1 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT1." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT1 is edge sensitive." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTMODE2" description="External interrupt 2 EINT2 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT2." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT2 is edge sensitive." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTMODE3" description="External interrupt 3 EINT3 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT3." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT3 is edge sensitive." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt 0 EINT0 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt 1 EINT1 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt 2 EINT2 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt 3 EINT3 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
-      <BitField start="1" size="1" name="EXTR" description="Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR." />
-      <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
-      <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System control and status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="OSCRANGE" description="Main oscillator range select.">
-        <Enum name="LOW" start="0" description="Low. The frequency range of the main oscillator is 1 MHz to 20 MHz." />
-        <Enum name="HIGH" start="1" description="High. The frequency range of the main oscillator is 15 MHz to 25 MHz." />
-      </BitField>
-      <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The main oscillator is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
-      </BitField>
-      <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
-        <Enum name="NOT_READY" start="0" description="Not ready. The main oscillator is not ready to be used as a clock source." />
-        <Enum name="READY" start="1" description="Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="PCLKSEL0" access="Read/Write" description="Peripheral Clock Selection register 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PCLK_WDT" description="Peripheral clock selection for WDT.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="2" size="2" name="PCLK_TIMER0" description="Peripheral clock selection for TIMER0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="4" size="2" name="PCLK_TIMER1" description="Peripheral clock selection for TIMER1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="6" size="2" name="PCLK_UART0" description="Peripheral clock selection for UART0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="8" size="2" name="PCLK_UART1" description="Peripheral clock selection for UART1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="2" name="PCLK_PWM1" description="Peripheral clock selection for PWM1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="14" size="2" name="PCLK_I2C0" description="Peripheral clock selection for I2C0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="16" size="2" name="PCLK_SPI" description="Peripheral clock selection for SPI.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="18" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="20" size="2" name="PCLK_SSP1" description="Peripheral clock selection for SSP1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="22" size="2" name="PCLK_DAC" description="Peripheral clock selection for DAC.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="24" size="2" name="PCLK_ADC" description="Peripheral clock selection for ADC.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="26" size="2" name="PCLK_CAN1" description="Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6." />
-      </BitField>
-      <BitField start="28" size="2" name="PCLK_CAN2" description="Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6," />
-      </BitField>
-      <BitField start="30" size="2" name="PCLK_ACF" description="Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6" />
-      </BitField>
-    </Register>
-    <Register start="+0x1AC" size="4" name="PCLKSEL1" access="Read/Write" description="Peripheral Clock Selection register 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PCLK_QEI" description="Peripheral clock selection for the Quadrature Encoder Interface.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="2" size="2" name="PCLK_GPIOINT" description="Peripheral clock selection for GPIO interrupts.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="4" size="2" name="PCLK_PCB" description="Peripheral clock selection for the Pin Connect block.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="6" size="2" name="PCLK_I2C1" description="Peripheral clock selection for I2C1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="8" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="2" name="PCLK_SSP0" description="Peripheral clock selection for SSP0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="12" size="2" name="PCLK_TIMER2" description="Peripheral clock selection for TIMER2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="14" size="2" name="PCLK_TIMER3" description="Peripheral clock selection for TIMER3.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="16" size="2" name="PCLK_UART2" description="Peripheral clock selection for UART2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="18" size="2" name="PCLK_UART3" description="Peripheral clock selection for UART3.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="20" size="2" name="PCLK_I2C2" description="Peripheral clock selection for I2C2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="22" size="2" name="PCLK_I2S" description="Peripheral clock selection for I2S.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="24" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="26" size="2" name="PCLK_RIT" description="Peripheral clock selection for Repetitive Interrupt Timer.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="28" size="2" name="PCLK_SYSCON" description="Peripheral clock selection for the System Control block.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="30" size="2" name="PCLK_MC" description="Peripheral clock selection for the Motor Control PWM.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
-      <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
-      <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
-      <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
-      <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
-      <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
-      <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
-      <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMASEL08" description="Selects the DMA request for GPDMA input 8: 0 - uart0 tx  1 - Timer 0 match 0 is selected." />
-      <BitField start="1" size="1" name="DMASEL09" description="Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected." />
-      <BitField start="2" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - uart1 tx  is selected. 1 - Timer 1 match 0 is selected." />
-      <BitField start="3" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - uart1 rx  is selected. 1 - Timer 1 match 1 is selected." />
-      <BitField start="4" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - uart2 tx  is selected. 1 - Timer 2 match 0 is selected." />
-      <BitField start="5" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - uart2 rx  is selected. 1 - Timer 2 match 1 is selected." />
-      <BitField start="6" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - uart3 tx  is selected. 1 - I2S channel 0 is selected." />
-      <BitField start="7" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.">
-        <Enum name="SELECTS_THE_CPU_CLOC" start="0x0" description="Selects the CPU clock as the CLKOUT source." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the CLKOUT source." />
-        <Enum name="SELECTS_THE_INTERNAL" start="0x2" description="Selects the Internal RC oscillator as the CLKOUT source." />
-        <Enum name="SELECTS_THE_USB_CLOC" start="0x3" description="Selects the USB clock as the CLKOUT source." />
-        <Enum name="SELECTS_THE_RTC_OSCI" start="0x4" description="Selects the RTC oscillator as the CLKOUT source." />
-      </BitField>
-      <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16." />
-      <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
-      <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMAC" start="0x50000000" description="Ethernet">
-    <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
-      <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
-      <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
-      <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
-      <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
-      <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
-      <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
-      <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
-      <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
-      <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
-      <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
-      <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
-      <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
-      <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
-      <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
-      <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
-      <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
-      <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
-      <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
-      <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
-      <BitField start="3" size="29" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
-      <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
-      <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
-      <BitField start="6" size="9" name="RESERVED" description="Unused" />
-      <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
-      <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
-      <BitField start="13" size="19" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
-      <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
-      <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
-      <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
-      <BitField start="4" size="28" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
-      <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
-      <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
-      <BitField start="2" size="1" name="RESERVED" description="Unused" />
-      <BitField start="3" size="1" name="REGRESET" description="When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
-      <BitField start="4" size="1" name="TXRESET" description="When a  1  is written, the transmit datapath is reset." />
-      <BitField start="5" size="1" name="RXRESET" description="When a  1  is written, the receive datapath is reset." />
-      <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
-      <BitField start="7" size="1" name="PASSRXFILTER" description="When set to  1 , disables receive filtering i.e. all frames received are written to memory." />
-      <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
-      <BitField start="9" size="1" name="RMII" description="When set to  1 , RMII mode is selected; if 0, MII mode is selected." />
-      <BitField start="10" size="1" name="FULLDUPLEX" description="When set to  1 , indicates full duplex operation." />
-      <BitField start="11" size="21" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
-      <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
-    </Register>
-    <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
-      <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
-    </Register>
-    <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
-    </Register>
-    <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
-    </Register>
-    <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
-      <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
-      <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
-      <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
-      <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
-      <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
-      <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
-      <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
-      <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
-      <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
-      <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
-      <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
-      <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
-      <BitField start="20" size="12" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
-      <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
-      <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
-      <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
-      <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
-      <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
-      <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
-      <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
-      <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
-      <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
-      <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-      <BitField start="31" size="1" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
-      <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
-    </Register>
-    <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
-      <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
-      <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
-      <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
-      <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
-      <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
-      <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
-      <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
-      <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
-      <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
-      <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
-      <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
-      <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
-      <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
-      <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
-      <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
-      <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
-      <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="RESERVED" description="Unused" />
-      <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x50004000" description="General purpose DMA controller">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
-      <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x50008000" description="USB device/host/OTG controller">
-    <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR" description="Timer time-out." />
-      <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
-      <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
-      <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="INTCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="STCTRL" access="Read/Write" description="OTG Status and Control and USB port select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PORT_FUNC" description="Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
-      <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
-      <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
-      <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
-      <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
-    </Register>
-    <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
-      <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
-      <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
-      <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
-      <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
-      <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
-      <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
-        <Enum name="READ" start="0x02" description="Read" />
-        <Enum name="WRITE" start="0x01" description="Write" />
-        <Enum name="COMMAND" start="0x05" description="Command" />
-      </BitField>
-      <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RX_DATA" description="Data received." />
-    </Register>
-    <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
-    </Register>
-    <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
-        <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
-        <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
-      </BitField>
-      <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
-        <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
-        <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-    </Register>
-    <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-    </Register>
-    <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-    </Register>
-    <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-    </Register>
-    <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-    </Register>
-    <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-    </Register>
-    <Register start="+0x248" size="4" name="EPIND" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 &lt;=  xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-    </Register>
-    <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
-      <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
-    </Register>
-    <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-    </Register>
-    <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RXDATA" description="Receive data." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_WO" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="TXDATA" description="Transmit data." />
-      <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
-      <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
-        <Enum name="NOT_COMPLETE" start="0" description="Transaction has not completed." />
-        <Enum name="COMPLETE" start="1" description="Transaction completed." />
-      </BitField>
-      <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
-        <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
-        <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
-      </BitField>
-      <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="ACKNOWLEDGE_RCVD" start="0" description="Last transmission received an acknowledge." />
-        <Enum name="NO_ACKNOWLEDGE_RCVD" start="1" description="Last transmission did not receive an acknowledge." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="BUSY" start="0" description="Master transmitter does not need data." />
-        <Enum name="NEED_DATA" start="1" description="Master transmitter needs data." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
-        <Enum name="BUSY" start="0" description="Slave transmitter does not need data." />
-        <Enum name="NEED_DATA" start="1" description="Slave transmitter needs data." />
-      </BitField>
-      <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
-      <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
-      <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
-      <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
-        <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
-        <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
-      </BitField>
-      <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
-        <Enum name="DATA" start="0" description="RX FIFO contains data." />
-        <Enum name="EMPTY" start="1" description="RX FIFO is empty" />
-      </BitField>
-      <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
-        <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
-        <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
-      </BitField>
-      <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
-        <Enum name="VALID_DATA" start="0" description="TX FIFO contains valid data." />
-        <Enum name="EMPTY" start="1" description="TX FIFO is empty" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
-        <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
-        <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
-        <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
-        <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
-      </BitField>
-      <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
-        <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
-        <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
-        <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
-        <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
-        <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
-        <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
-        <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
-        <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
-      </BitField>
-      <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
-        <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
-        <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
-      </BitField>
-      <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
-        <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
-        <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
-      </BitField>
-      <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
-        <Enum name="NO_RESET" start="0" description="No reset." />
-        <Enum name="RESET" start="1" description="Reset the I2C to idle state. Self clearing." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="USBCLKCTRL" access="Read/Write" description="USB Clock Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable.   Enables the usbclk input to the device controller" />
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PORTSEL_CLK_EN" description="Port select register clock enable." />
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB clock enable" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="OTGCLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
-        <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
-        <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
-        <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
-        <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
-        <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
-        <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
-        <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
-        <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
-        <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
-        <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="USBCLKST" access="ReadOnly" description="USB Clock Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock on. The usbclk input to the device controller is active&#x9;." />
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PORTSEL_CLK_ON" description="Port select register clock on." />
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB clock on." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="OTGCLKST" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
-        <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
-        <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
-        <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
-        <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
-        <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
-        <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
-        <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
-        <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
-        <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
-        <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO" start="0x2009C000" description="General Purpose I/O ">
-    <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="WDT" start="4" size="4" />
-      <BitField name="TIMER0" start="12" size="4" />
-      <BitField name="TIMER1" start="20" size="4" />
-      <BitField name="TIMER2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="TIMER3" start="4" size="4" />
-      <BitField name="UART0" start="12" size="4" />
-      <BitField name="UART1" start="20" size="4" />
-      <BitField name="UART2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="UART3" start="4" size="4" />
-      <BitField name="PWM1" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="I2C2" start="4" size="4" />
-      <BitField name="SPI" start="12" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="PLL0" start="4" size="4" />
-      <BitField name="RTC" start="12" size="4" />
-      <BitField name="EINT0" start="20" size="4" />
-      <BitField name="EINT1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="EINT2" start="4" size="4" />
-      <BitField name="EINT3" start="12" size="4" />
-      <BitField name="ADC" start="20" size="4" />
-      <BitField name="BOD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USB" start="4" size="4" />
-      <BitField name="CAN" start="12" size="4" />
-      <BitField name="DMA" start="20" size="4" />
-      <BitField name="I2S" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="ENET" start="4" size="4" />
-      <BitField name="RIT" start="12" size="4" />
-      <BitField name="MCPWM" start="20" size="4" />
-      <BitField name="QEI" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PLL1" start="4" size="4" />
-      <BitField name="USBActivity" start="12" size="4" />
-      <BitField name="CANActivity" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYS_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYS_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYS_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYS_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/LPC176x5x_Vectors.s b/examples/device/cdc_msc/ses/lpc175x_6x/LPC176x5x_Vectors.s
deleted file mode 100644
index c5fae131..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/LPC176x5x_Vectors.s
+++ /dev/null
@@ -1,418 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak WDT_IRQHandler
-  .thumb_set WDT_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak UART0_IRQHandler
-  .thumb_set UART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak UART2_IRQHandler
-  .thumb_set UART2_IRQHandler,Dummy_Handler
-
-  .weak UART3_IRQHandler
-  .thumb_set UART3_IRQHandler,Dummy_Handler
-
-  .weak PWM1_IRQHandler
-  .thumb_set PWM1_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Dummy_Handler
-
-  .weak SPI_IRQHandler
-  .thumb_set SPI_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak PLL0_IRQHandler
-  .thumb_set PLL0_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak EINT0_IRQHandler
-  .thumb_set EINT0_IRQHandler,Dummy_Handler
-
-  .weak EINT1_IRQHandler
-  .thumb_set EINT1_IRQHandler,Dummy_Handler
-
-  .weak EINT2_IRQHandler
-  .thumb_set EINT2_IRQHandler,Dummy_Handler
-
-  .weak EINT3_IRQHandler
-  .thumb_set EINT3_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak BOD_IRQHandler
-  .thumb_set BOD_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak CAN_IRQHandler
-  .thumb_set CAN_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak I2S_IRQHandler
-  .thumb_set I2S_IRQHandler,Dummy_Handler
-
-  .weak ENET_IRQHandler
-  .thumb_set ENET_IRQHandler,Dummy_Handler
-
-  .weak RIT_IRQHandler
-  .thumb_set RIT_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-  .weak PLL1_IRQHandler
-  .thumb_set PLL1_IRQHandler,Dummy_Handler
-
-  .weak USBActivity_IRQHandler
-  .thumb_set USBActivity_IRQHandler,Dummy_Handler
-
-  .weak CANActivity_IRQHandler
-  .thumb_set CANActivity_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak WDT_IRQHandler
-WDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART0_IRQHandler
-UART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART2_IRQHandler
-UART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART3_IRQHandler
-UART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM1_IRQHandler
-PWM1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_IRQHandler
-I2C2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI_IRQHandler
-SPI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PLL0_IRQHandler
-PLL0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT0_IRQHandler
-EINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT1_IRQHandler
-EINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT2_IRQHandler
-EINT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT3_IRQHandler
-EINT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_IRQHandler
-BOD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN_IRQHandler
-CAN_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S_IRQHandler
-I2S_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ENET_IRQHandler
-ENET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RIT_IRQHandler
-RIT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PLL1_IRQHandler
-PLL1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USBActivity_IRQHandler
-USBActivity_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CANActivity_IRQHandler
-CANActivity_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WDT_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word UART0_IRQHandler
-  .word UART1_IRQHandler
-  .word UART2_IRQHandler
-  .word UART3_IRQHandler
-  .word PWM1_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word SPI_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word PLL0_IRQHandler
-  .word RTC_IRQHandler
-  .word EINT0_IRQHandler
-  .word EINT1_IRQHandler
-  .word EINT2_IRQHandler
-  .word EINT3_IRQHandler
-  .word ADC_IRQHandler
-  .word BOD_IRQHandler
-  .word USB_IRQHandler
-  .word CAN_IRQHandler
-  .word DMA_IRQHandler
-  .word I2S_IRQHandler
-  .word ENET_IRQHandler
-  .word RIT_IRQHandler
-  .word MCPWM_IRQHandler
-  .word QEI_IRQHandler
-  .word PLL1_IRQHandler
-  .word USBActivity_IRQHandler
-  .word CANActivity_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/flash_placement.xml b/examples/device/cdc_msc/ses/lpc175x_6x/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/lpc175x_6x.emProject b/examples/device/cdc_msc/ses/lpc175x_6x/lpc175x_6x.emProject
deleted file mode 100644
index 7d49a90d..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/lpc175x_6x.emProject
+++ /dev/null
@@ -1,116 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc175x_6x" target="8" version="2">
-  <project Name="lpc175x_6x">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4357 Cortex-M4"
-      arm_architecture="v7M"
-      arm_core_type="Cortex-M3"
-      arm_endian="Little"
-      arm_fp_abi="Soft"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC1769"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc;$(rootDir)/src"
-      debug_register_definition_file="LPC176x5x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="LPC1769_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../.."
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/LPC1700_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="lpcxpresso1769">
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/lpcxpresso1769.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_175x_6x">
-              <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/chip.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/clock_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/cmsis.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/cmsis_175x_6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/core_cm3.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/core_cmFunc.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/core_cmInstr.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/lpc_types.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/sys_config.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc/uart_17xx_40xx.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/chip_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/clock_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/uart_17xx_40xx.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC1700_Startup.s" />
-      <file file_name="LPC1700_Target.js" />
-      <file file_name="LPC1769_MemoryMap.xml" />
-      <file file_name="LPC176x5x_Registers.xml" />
-      <file file_name="LPC176x5x_Vectors.s" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <configuration
-      Name="LPCXpresso 1769"
-      c_preprocessor_definitions="BOARD_LPCXPRESSO1769" />
-  </project>
-  <configuration Name="LPCXpresso 1769" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc175x_6x/thumb_crt0.s b/examples/device/cdc_msc/ses/lpc175x_6x/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/lpc175x_6x/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/lpc18xx/LPC1800_Startup.s b/examples/device/cdc_msc/ses/lpc18xx/LPC1800_Startup.s
deleted file mode 100644
index e17b6050..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/LPC1800_Startup.s
+++ /dev/null
@@ -1,110 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/lpc18xx/LPC1800_Target.js b/examples/device/cdc_msc/ses/lpc18xx/LPC1800_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/LPC1800_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/lpc18xx/LPC1857_MemoryMap.xml b/examples/device/cdc_msc/ses/lpc18xx/LPC1857_MemoryMap.xml
deleted file mode 100644
index 4ded8a9f..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/LPC1857_MemoryMap.xml
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC1857">
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00010000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/lpc18xx/LPC18xx_Registers.xml b/examples/device/cdc_msc/ses/lpc18xx/LPC18xx_Registers.xml
deleted file mode 100644
index 5e68d4c0..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/LPC18xx_Registers.xml
+++ /dev/null
@@ -1,30452 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC18xx" description="Register cmsis file for LPC18xx parts">
-  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
-        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
-      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
-      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
-      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
-      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
-      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
-      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
-        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
-      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
-      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
-      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
-        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
-        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
-        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
-        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
-      </BitField>
-      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
-        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
-        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
-      </BitField>
-      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
-        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
-        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
-        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
-        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
-      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
-        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
-        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
-      </BitField>
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRESS" description="Address." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
-    </Register>
-    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Input or output data" />
-    </Register>
-    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
-      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
-      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
-      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
-      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
-      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
-      </BitField>
-      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
-      </BitField>
-      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
-        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
-        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
-        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
-        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
-      </BitField>
-      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
-      </BitField>
-      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
-      </BitField>
-      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
-        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
-      </BitField>
-      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
-        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
-      </BitField>
-      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
-      </BitField>
-      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
-        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
-        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
-      </BitField>
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
-      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
-      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
-      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
-        <Enum name="NONE" start="0" description="None. No response expected from card" />
-        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
-      </BitField>
-      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
-        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
-        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
-      </BitField>
-      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
-        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
-        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
-      </BitField>
-      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
-        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
-        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
-      </BitField>
-      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
-        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
-        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
-      </BitField>
-      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
-        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
-      </BitField>
-      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
-        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
-        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
-      </BitField>
-      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
-        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
-        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
-      </BitField>
-      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
-        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
-        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
-      </BitField>
-      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
-        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
-        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
-      </BitField>
-      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
-      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
-        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
-      </BitField>
-      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
-        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-      </BitField>
-      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
-      </BitField>
-      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
-      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
-        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
-        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
-      </BitField>
-      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
-        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
-        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
-      </BitField>
-      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
-    </Register>
-    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
-    </Register>
-    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
-    </Register>
-    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
-    </Register>
-    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
-    </Register>
-    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
-      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
-      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
-      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
-      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
-      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
-      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
-      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
-      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
-      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
-      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
-      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
-    </Register>
-    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
-      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
-    </Register>
-    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
-    </Register>
-    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
-      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
-      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
-      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
-      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
-    </Register>
-    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
-    </Register>
-    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
-      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
-      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
-      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
-    </Register>
-    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
-        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
-        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
-        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode.">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
-        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
-        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy.">
-        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
-        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
-        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
-        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
-        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
-      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
-      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
-      </BitField>
-      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
-      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
-      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
-        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
-        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
-      </BitField>
-      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
-      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
-      </BitField>
-      <BitField start="8" size="1" name="ID" description="USB ID">
-        <Enum name="A_DEVICE" start="0" description="A-device" />
-        <Enum name="B_DEVICE" start="1" description="B-device" />
-      </BitField>
-      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
-      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
-      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
-      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
-      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
-      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
-      <BitField start="15" size="1" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
-      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
-      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
-      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
-      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
-      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
-      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
-      <BitField start="23" size="1" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="reserved" />
-      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
-      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
-      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
-      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
-      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
-        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
-        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
-      </BitField>
-      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
-        <Enum name="READ" start="0" description="Read" />
-        <Enum name="WRITE" start="1" description="Write" />
-      </BitField>
-      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
-      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
-    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
-      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
-      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
-    </Register>
-    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="WriteOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSTATSET" access="WriteOnly" description="EEPROM interrupt status set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_ST" description="Set program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
-    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
-      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
-      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
-      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
-      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
-      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
-      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
-      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
-      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
-      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
-      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
-      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
-      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
-      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
-      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
-      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
-      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
-      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
-      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
-      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
-    </Register>
-    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
-      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
-      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M3_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M3_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
-      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
-      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
-      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
-      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
-      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
-      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
-    </Register>
-    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
-      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
-      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
-      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
-      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
-      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
-      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
-      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
-      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
-    </Register>
-    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
-      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
-      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
-      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
-      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
-      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
-    </Register>
-    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="MO" description="Always 1" />
-    </Register>
-    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-    </Register>
-    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
-      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
-      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
-      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
-      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
-      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
-      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
-      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
-      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
-      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
-      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
-      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
-      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
-      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
-      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
-    </Register>
-    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
-    </Register>
-    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
-      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
-    </Register>
-    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
-    </Register>
-    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
-      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
-    </Register>
-    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
-    </Register>
-    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
-    </Register>
-    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
-      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
-      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
-      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
-      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
-      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
-      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
-      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
-      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
-      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
-      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
-      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
-      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
-      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
-    </Register>
-    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
-    </Register>
-    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
-      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
-      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
-      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
-      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
-      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
-      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
-      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
-      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
-      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
-      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
-      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
-      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
-      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
-      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
-      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
-      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
-      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
-      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
-      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
-      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
-      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
-      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
-      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
-      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
-      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
-      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
-      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
-      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
-      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
-      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
-      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
-      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
-      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
-      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
-      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
-    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
-    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
-    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M3 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
-    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
-        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
-        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
-        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
-        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
-        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
-        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
-      </BitField>
-      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
-        <Enum name="POWERED" start="0" description="Powered." />
-        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
-        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
-        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
-      </BitField>
-      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
-        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
-        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INACTIVE" start="0x3" description="Inactive." />
-      </BitField>
-      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the  data sheet for the trip values.">
-        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
-        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
-        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
-        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
-      </BitField>
-      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the  data sheet for the trip values.">
-        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
-        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
-        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
-        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
-      </BitField>
-      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
-        <Enum name="RESERVED" start="0x0" description="Reserved" />
-        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
-      </BitField>
-      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="M3MEMMAP" access="Read/Write" description="ARM Cortex-M3 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M3MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="M3TAPSEL" description="JTAG debug disable for M3 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
-        <Enum name="SPIFI" start="0x0" description="SPIFI" />
-        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
-      </BitField>
-      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
-        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
-        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
-        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
-        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
-      </BitField>
-      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
-        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
-        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
-        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
-        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
-        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
-        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
-        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
-        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
-      </BitField>
-      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
-        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
-        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
-        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
-        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-      </BitField>
-      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
-        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
-        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-      </BitField>
-      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
-        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
-        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-      </BitField>
-      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
-        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
-        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-      </BitField>
-      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
-        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
-        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-      </BitField>
-      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
-        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
-        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
-      </BitField>
-      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
-        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
-        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
-      </BitField>
-      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
-        <Enum name="ADC0" start="0x0" description="ADC0" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
-      </BitField>
-      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
-        <Enum name="ADC1" start="0x0" description="ADC1" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
-      </BitField>
-      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
-        <Enum name="DAC" start="0x0" description="DAC" />
-        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
-        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
-        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
-        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
-        <Enum name="MII" start="0x0" description="MII" />
-        <Enum name="RMII" start="0x4" description="RMII" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
-        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
-        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
-      </BitField>
-      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
-        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
-        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5284 E02B or 0x6284 E02B = LPC1850/30/20/10&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;(flashless parts)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;0x4284 E02B = LPC1857/53 (parts with on-chip flash)" />
-    </Register>
-    <Register start="+0x500" size="4" name="USB0FLADJ" access="None" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
-    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
-      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
-      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
-      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
-      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
-      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
-      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
-      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
-      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
-      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
-      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
-      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
-      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
-      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
-      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
-      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
-      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
-      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
-    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
-        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
-        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
-        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
-        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
-        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
-        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
-        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
-        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
-        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
-        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
-        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
-    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
-      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
-      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
-        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
-        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
-      </BitField>
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
-        <Enum name="IRC" start="0x01" description="IRC" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="RESERVED" start="0x0B" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="ENABLE" start="0" description="Enable" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
-        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
-      </BitField>
-      <BitField start="2" size="1" name="HF" description="Select frequency range">
-        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
-      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
-      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
-      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
-        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
-        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
-      </BitField>
-      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
-        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
-      </BitField>
-      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL1 power down">
-        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
-        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
-        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
-      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
-        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
-        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="PEQ2" start="0x1" description="2 (default)" />
-        <Enum name="PEQ4" start="0x2" description="4" />
-        <Enum name="8" start="0x3" description="8" />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="NEQ2" start="0x1" description="2" />
-        <Enum name="NEQ3" start="0x2" description="3 (default)" />
-        <Enum name="4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="RESERVED" start="0x09" description="Reserved" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
-        <Enum name="DIV1" start="0x0" description="1 (default)" />
-        <Enum name="DIV2" start="0x1" description="2" />
-        <Enum name="DIV3" start="0x2" description="3" />
-        <Enum name="DIV4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="BASE_M3_CLK" access="Read/Write" description="Output stage BASE_M3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_M3_BUS_CFG" access="Read/Write" description="CLK_M3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0408" size="4" name="CLK_M3_SPIFI_CFG" access="Read/Write" description="CLK_M3_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0410" size="4" name="CLK_M3_GPIO_CFG" access="Read/Write" description="CLK_M3_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0418" size="4" name="CLK_M3_LCD_CFG" access="Read/Write" description="CLK_M3_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0420" size="4" name="CLK_M3_ETHERNET_CFG" access="Read/Write" description="CLK_M3_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0428" size="4" name="CLK_M3_USB0_CFG" access="Read/Write" description="CLK_M3_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0430" size="4" name="CLK_M3_EMC_CFG" access="Read/Write" description="CLK_M3_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0438" size="4" name="CLK_M3_SDIO_CFG" access="Read/Write" description="CLK_M3_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0440" size="4" name="CLK_M3_DMA_CFG" access="Read/Write" description="CLK_M3_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0448" size="4" name="CLK_M3_M3CORE_CFG" access="Read/Write" description="CLK_M3_M3CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0468" size="4" name="CLK_M3_SCT_CFG" access="Read/Write" description="CLK_M3_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0470" size="4" name="CLK_M3_USB1_CFG" access="Read/Write" description="CLK_M3_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0478" size="4" name="CLK_M3_EMCDIV_CFG" access="Read/Write" description="CLK_M3_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0480" size="4" name="CLK_M3_FLASHA_CFG" access="Read/Write" description="CLK_M3_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0488" size="4" name="CLK_M3_FLASHB_CFG" access="Read/Write" description="CLK_M3_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A0" size="4" name="CLK_M3_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_M3_WWDT_CFG" access="Read/Write" description="CLK_M3_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0508" size="4" name="CLK_M3_USART0_CFG" access="Read/Write" description="CLK_M3_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0510" size="4" name="CLK_M3_UART1_CFG" access="Read/Write" description="CLK_M3_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0518" size="4" name="CLK_M3_SSP0_CFG" access="Read/Write" description="CLK_M3_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0520" size="4" name="CLK_M3_TIMER0_CFG" access="Read/Write" description="CLK_M3_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0528" size="4" name="CLK_M3_TIMER1_CFG" access="Read/Write" description="CLK_M3_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0530" size="4" name="CLK_M3_SCU_CFG" access="Read/Write" description="CLK_M3_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0538" size="4" name="CLK_M3_CREG_CFG" access="Read/Write" description="CLK_M3_CREG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_M3_RITIMER_CFG" access="Read/Write" description="CLK_M3_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0608" size="4" name="CLK_M3_USART2_CFG" access="Read/Write" description="CLK_M3_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0610" size="4" name="CLK_M3_USART3_CFG" access="Read/Write" description="CLK_M3_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0618" size="4" name="CLK_M3_TIMER2_CFG" access="Read/Write" description="CLK_M3_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0620" size="4" name="CLK_M3_TIMER3_CFG" access="Read/Write" description="CLK_M3_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0628" size="4" name="CLK_M3_SSP1_CFG" access="Read/Write" description="CLK_M3_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0630" size="4" name="CLK_M3_QEI_CFG" access="Read/Write" description="CLK_M3_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x404" size="4" name="CLK_M3_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040C" size="4" name="CLK_M3_SPIFI_STAT" access="ReadOnly" description="CLK_M3_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0414" size="4" name="CLK_M3_GPIO_STAT" access="ReadOnly" description="CLK_M3_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x041C" size="4" name="CLK_M3_LCD_STAT" access="ReadOnly" description="CLK_M3_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0424" size="4" name="CLK_M3_ETHERNET_STAT" access="ReadOnly" description="CLK_M3_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x042C" size="4" name="CLK_M3_USB0_STAT" access="ReadOnly" description="CLK_M3_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0434" size="4" name="CLK_M3_EMC_STAT" access="ReadOnly" description="CLK_M3_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x043C" size="4" name="CLK_M3_SDIO_STAT" access="ReadOnly" description="CLK_M3_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0444" size="4" name="CLK_M3_DMA_STAT" access="ReadOnly" description="CLK_M3_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044C" size="4" name="CLK_M3_M3CORE_STAT" access="ReadOnly" description="CLK_M3_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x046C" size="4" name="CLK_M3_SCT_STAT" access="ReadOnly" description="CLK_M3_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0474" size="4" name="CLK_M3_USB1_STAT" access="ReadOnly" description="CLK_M3_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x047C" size="4" name="CLK_M3_EMCDIV_STAT" access="ReadOnly" description="CLK_M3_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0484" size="4" name="CLK_M3_FLASHA_STAT" access="ReadOnly" description="CLK_M3_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048C" size="4" name="CLK_M3_FLASHB_STAT" access="ReadOnly" description="CLK_M3_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A4" size="4" name="CLK_M3_EEPROM_STAT" access="ReadOnly" description="CLK_M3_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504" size="4" name="CLK_M3_WWDT_STAT" access="ReadOnly" description="CLK_M3_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050C" size="4" name="CLK_M3_USART0_STAT" access="ReadOnly" description="CLK_M3_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0514" size="4" name="CLK_M3_UART1_STAT" access="ReadOnly" description="CLK_M3_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x051C" size="4" name="CLK_M3_SSP0_STAT" access="ReadOnly" description="CLK_M3_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0524" size="4" name="CLK_M3_TIMER0_STAT" access="ReadOnly" description="CLK_M3_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x052C" size="4" name="CLK_M3_TIMER1_STAT" access="ReadOnly" description="CLK_M3_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0534" size="4" name="CLK_M3_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x053C" size="4" name="CLK_M3_CREG_STAT" access="ReadOnly" description="CLK_M3_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x604" size="4" name="CLK_M3_RITIMER_STAT" access="ReadOnly" description="CLK_M3_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060C" size="4" name="CLK_M3_USART2_STAT" access="ReadOnly" description="CLK_M3_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0614" size="4" name="CLK_M3_USART3_STAT" access="ReadOnly" description="CLK_M3_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x061C" size="4" name="CLK_M3_TIMER2_STAT" access="ReadOnly" description="CLK_M3_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0624" size="4" name="CLK_M3_TIMER3_STAT" access="ReadOnly" description="CLK_M3_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x062C" size="4" name="CLK_M3_SSP1_STAT" access="ReadOnly" description="CLK_M3_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0634" size="4" name="CLK_M3_QEI_STAT" access="ReadOnly" description="CLK_M3_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
-    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
-      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="13" size="1" name="M3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="M3_RST" description="Status of the M3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-    </Register>
-    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="M3_RST" description="Current status of the M3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
-        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
-        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
-        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
-        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
-        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
-        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
-    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
-        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
-        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
-      </BitField>
-      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
-        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
-        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
-      </BitField>
-      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
-        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
-        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
-        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
-        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
-      </BitField>
-      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
-        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
-        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
-      </BitField>
-      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
-      </BitField>
-    </Register>
-    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
-      </BitField>
-      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
-      </BitField>
-      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DAC" description="Select DAC">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
-        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
-      </BitField>
-      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
-      <BitField start="20" size="12" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
-      <BitField start="1" size="31" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
-    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
-        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
-        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
-        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
-        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
-        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
-        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
-        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
-        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
-        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
-        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
-        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
-        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
-        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
-        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time">
-        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
-        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
-        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
-        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
-        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
-        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
-        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
-        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
-        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
-        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="DAC" start="4" size="4" />
-      <BitField name="DMA" start="20" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="FLASH" start="4" size="4" />
-      <BitField name="ETHERNET" start="12" size="4" />
-      <BitField name="SDIO" start="20" size="4" />
-      <BitField name="LCD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="USB0" start="4" size="4" />
-      <BitField name="USB1" start="12" size="4" />
-      <BitField name="SCT" start="20" size="4" />
-      <BitField name="RITIMER" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TIMER0" start="4" size="4" />
-      <BitField name="TIMER1" start="12" size="4" />
-      <BitField name="TIMER2" start="20" size="4" />
-      <BitField name="TIMER3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="MCPWM" start="4" size="4" />
-      <BitField name="ADC0" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="ADC1" start="12" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USART0" start="4" size="4" />
-      <BitField name="UART1" start="12" size="4" />
-      <BitField name="USART2" start="20" size="4" />
-      <BitField name="USART3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="I2S0" start="4" size="4" />
-      <BitField name="I2S1" start="12" size="4" />
-      <BitField name="SPIFI" start="20" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PIN_INT0" start="4" size="4" />
-      <BitField name="PIN_INT1" start="12" size="4" />
-      <BitField name="PIN_INT2" start="20" size="4" />
-      <BitField name="PIN_INT3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="PIN_INT4" start="4" size="4" />
-      <BitField name="PIN_INT5" start="12" size="4" />
-      <BitField name="PIN_INT6" start="20" size="4" />
-      <BitField name="PIN_INT7" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="GINT0" start="4" size="4" />
-      <BitField name="GINT1" start="12" size="4" />
-      <BitField name="EVENTROUTER" start="20" size="4" />
-      <BitField name="C_CAN1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="ATIMER" start="20" size="4" />
-      <BitField name="RTC" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
-      <BitField name="WWDT" start="12" size="4" />
-      <BitField name="C_CAN0" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
-      <BitField name="QEI" start="4" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/lpc18xx/LPC18xx_Vectors.s b/examples/device/cdc_msc/ses/lpc18xx/LPC18xx_Vectors.s
deleted file mode 100644
index 8f9a39e4..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/LPC18xx_Vectors.s
+++ /dev/null
@@ -1,516 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak USB0_IRQHandler
-  .thumb_set USB0_IRQHandler,Dummy_Handler
-
-  .weak USB1_IRQHandler
-  .thumb_set USB1_IRQHandler,Dummy_Handler
-
-  .weak SCT_IRQHandler
-  .thumb_set SCT_IRQHandler,Dummy_Handler
-
-  .weak RITIMER_IRQHandler
-  .thumb_set RITIMER_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak ADC0_IRQHandler
-  .thumb_set ADC0_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak USART0_IRQHandler
-  .thumb_set USART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Dummy_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Dummy_Handler
-
-  .weak I2S0_IRQHandler
-  .thumb_set I2S0_IRQHandler,Dummy_Handler
-
-  .weak I2S1_IRQHandler
-  .thumb_set I2S1_IRQHandler,Dummy_Handler
-
-  .weak SPIFI_IRQHandler
-  .thumb_set SPIFI_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak EVENTROUTER_IRQHandler
-  .thumb_set EVENTROUTER_IRQHandler,Dummy_Handler
-
-  .weak C_CAN1_IRQHandler
-  .thumb_set C_CAN1_IRQHandler,Dummy_Handler
-
-  .weak ATIMER_IRQHandler
-  .thumb_set ATIMER_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak C_CAN0_IRQHandler
-  .thumb_set C_CAN0_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak DAC_IRQHandler
-DAC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDIO_IRQHandler
-SDIO_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB0_IRQHandler
-USB0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB1_IRQHandler
-USB1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SCT_IRQHandler
-SCT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RITIMER_IRQHandler
-RITIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC0_IRQHandler
-ADC0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC1_IRQHandler
-ADC1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART0_IRQHandler
-USART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_IRQHandler
-USART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART3_IRQHandler
-USART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S0_IRQHandler
-I2S0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S1_IRQHandler
-I2S1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPIFI_IRQHandler
-SPIFI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EVENTROUTER_IRQHandler
-EVENTROUTER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN1_IRQHandler
-C_CAN1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ATIMER_IRQHandler
-ATIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN0_IRQHandler
-C_CAN0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word DAC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word DMA_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word FLASH_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDIO_IRQHandler
-  .word LCD_IRQHandler
-  .word USB0_IRQHandler
-  .word USB1_IRQHandler
-  .word SCT_IRQHandler
-  .word RITIMER_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word MCPWM_IRQHandler
-  .word ADC0_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word ADC1_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word USART0_IRQHandler
-  .word UART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word I2S0_IRQHandler
-  .word I2S1_IRQHandler
-  .word SPIFI_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word EVENTROUTER_IRQHandler
-  .word C_CAN1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word ATIMER_IRQHandler
-  .word RTC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word WWDT_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word C_CAN0_IRQHandler
-  .word QEI_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/lpc18xx/flash_placement.xml b/examples/device/cdc_msc/ses/lpc18xx/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/lpc18xx/lpc18xx.emProject b/examples/device/cdc_msc/ses/lpc18xx/lpc18xx.emProject
deleted file mode 100644
index 8f7d91b2..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/lpc18xx.emProject
+++ /dev/null
@@ -1,135 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc18xx" target="8" version="2">
-  <project Name="lpc18xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC1857"
-      arm_architecture="v7M"
-      arm_core_type="Cortex-M3"
-      arm_endian="Little"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="256"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00008000;ROM;0x1A000000;0x00080000;ROM;0x1B000000;0x00080000;RAM;0x20000000;0x00010000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC1857"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="LPC18xx;__LPC1800_FAMILY;__LPC185x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;CFG_TUSB_MCU=OPT_MCU_LPC18XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/config_18xx;$(rootDir)/src"
-      debug_register_definition_file="$(ProjectDir)/LPC18xx_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../.."
-      package_dependencies="LPC1800"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC1800_Startup.s" />
-      <file file_name="LPC18xx_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="LPC1857_MemoryMap.xml" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC1800_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-    </folder>
-    <configuration
-      Name="Debug"
-      link_use_linker_script_file="No"
-      linker_section_placement_file="flash_placement.xml" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="mcb1800">
-          <file file_name="../../../../../hw/bsp/mcb1800/mcb1800.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_18xx">
-              <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/arm_common_tables.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/arm_math.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/cguccu_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/chip.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/chip_clocks.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/chip_lpc18xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/chip_lpc43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/clock_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/cmsis.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/cmsis_18xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/cmsis_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/cmsis_43xx_m0app.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/cmsis_43xx_m0sub.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cm0.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cm0plus.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cm3.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cm4.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cm4_simd.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cmFunc.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_cmInstr.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_sc000.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/core_sc300.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/creg_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/gpio_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/lpc_types.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/uart_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/usbhs_18xx_43xx.h" />
-                <folder Name="config_18xx">
-                  <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/config_18xx/cmsis_18xx.h" />
-                  <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/inc/config_18xx/sys_config.h" />
-                </folder>
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/src/chip_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/src/clock_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/src/gpio_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/src/sysinit_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_18xx/src/uart_18xx_43xx.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <configuration
-      Name="MCB1800"
-      c_preprocessor_definitions="BOARD_MCB1800" />
-  </project>
-  <configuration
-    Name="MCB1800"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc18xx/thumb_crt0.s b/examples/device/cdc_msc/ses/lpc18xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/lpc18xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/lpc40xx/LPC4000_Startup.s b/examples/device/cdc_msc/ses/lpc40xx/LPC4000_Startup.s
deleted file mode 100644
index 03bf54de..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/LPC4000_Startup.s
+++ /dev/null
@@ -1,128 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/lpc40xx/LPC4000_Target.js b/examples/device/cdc_msc/ses/lpc40xx/LPC4000_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/LPC4000_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml b/examples/device/cdc_msc/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
deleted file mode 100644
index 9b8f2d9b..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC4088FBD208">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00010000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Registers.xml b/examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Registers.xml
deleted file mode 100644
index 4a4c0817..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Registers.xml
+++ /dev/null
@@ -1,18992 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC408x_7x" description="LPC408x/7x M4">
-  <RegisterGroup name="FLASHCTRL" start="0x00200000" description="EEPROM/flash">
-    <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." />
-      <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation.">
-        <Enum name="STOP" start="0" description="Signature generation is stopped" />
-        <Enum name="START" start="1" description="Initiate signature generation" />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="128-bit signature Word 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." />
-    </Register>
-    <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="128-bit signature Word 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." />
-    </Register>
-    <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="128-bit signature Word 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." />
-    </Register>
-    <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="128-bit signature Word 3" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." />
-    </Register>
-    <Register start="+0x080" size="4" name="EECMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved" />
-      <BitField start="3" size="1" name="RDPREFETCH" description="Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x084" size="4" name="EEADDR" access="Read/Write" description="EEPROM address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="ADDR" description="EEPROM Address.  Lower 6 bits are don't care." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x088" size="4" name="EEWDATA" access="WriteOnly" description="EEPROM write data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="WDATA" description="Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data." />
-    </Register>
-    <Register start="+0x08C" size="4" name="EERDATA" access="ReadOnly" description="EEPROM read data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="RDATA" description="Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data." />
-    </Register>
-    <Register start="+0x090" size="4" name="EEWSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x094" size="4" name="EECLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x098" size="4" name="EEPWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down)." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." />
-      <BitField start="3" size="23" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="1" name="END_OF_RDWR" description="EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="28" size="1" name="END_OF_PROG1" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="1" name="EE_RW_DONE" description="EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="28" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="STATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." />
-      <BitField start="3" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="26" size="1" name="RDWR_CLR_ST" description="Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="28" size="1" name="PROG1_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="ENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="26" size="1" name="RDWR_CLR_EN" description="Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="28" size="1" name="PROG1_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="ENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="26" size="1" name="RDWR_SET_EN" description="Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="28" size="1" name="PROG1_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x20080000" description="General Purpose DMA controller Modification">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
-      <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x20084000" description="Ethernet">
-    <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
-      <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
-      <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
-      <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
-      <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
-      <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
-      <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
-      <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
-      <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
-      <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
-      <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
-      <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
-      <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
-      <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
-      <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
-      <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
-      <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
-      <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
-      <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
-      <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
-      <BitField start="3" size="29" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
-      <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
-      <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
-      <BitField start="6" size="9" name="RESERVED" description="Unused" />
-      <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
-      <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
-      <BitField start="13" size="19" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
-      <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
-      <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
-      <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
-      <BitField start="4" size="28" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
-      <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
-      <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
-      <BitField start="2" size="1" name="RESERVED" description="Unused" />
-      <BitField start="3" size="1" name="REGRESET" description="When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
-      <BitField start="4" size="1" name="TXRESET" description="When a  1  is written, the transmit datapath is reset." />
-      <BitField start="5" size="1" name="RXRESET" description="When a  1  is written, the receive datapath is reset." />
-      <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
-      <BitField start="7" size="1" name="PASSRXFILTER" description="When set to  1 , disables receive filtering i.e. all frames received are written to memory." />
-      <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
-      <BitField start="9" size="1" name="RMII" description="When set to  1 , RMII mode is selected; if 0, MII mode is selected." />
-      <BitField start="10" size="1" name="FULLDUPLEX" description="When set to  1 , indicates full duplex operation." />
-      <BitField start="11" size="21" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
-      <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
-    </Register>
-    <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
-      <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
-    </Register>
-    <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
-    </Register>
-    <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
-    </Register>
-    <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
-      <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
-      <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
-      <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
-      <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
-      <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
-      <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
-      <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
-      <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
-      <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
-      <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
-      <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
-      <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
-      <BitField start="20" size="12" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
-      <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
-      <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
-      <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
-      <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
-      <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
-      <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
-      <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
-      <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
-      <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
-      <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-      <BitField start="31" size="1" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
-      <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
-    </Register>
-    <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
-      <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
-      <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
-      <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
-      <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
-      <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
-      <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
-      <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
-      <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
-      <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
-      <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
-      <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
-      <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
-      <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
-      <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
-      <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
-      <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
-      <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="RESERVED" description="Unused" />
-      <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x20088000" description="LCD controller Modification ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the input clock, LCD_DCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCD_DCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal. 0 = LCD_FP pin is active HIGH and inactive LOW. 1 = LCD_FP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal. 0 = LCD_LP pin is active HIGH and inactive LOW. 1 = LCD_LP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state. 0 = LCD_ENAB_M output pin is active HIGH in TFT mode. 1 = LCD_ENAB_M output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the LCD_TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are low. 1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel. Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the LCD_CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the LCD_INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the VCompIM bit in the LCD_INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the LCD_INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRON" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRSIZE" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x2008C000" description=" USB device controller ">
-    <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR" description="Timer time-out." />
-      <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
-      <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
-      <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="INCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="PORTSEL" access="Read/Write" description="USB Port Select. The USBPortSel register is identical to the OTGStCtrl register (see Section 15.8.6). In device-only operations only bits 0 and 1 of this register are used to control the routing of USB pins to Port 1 or Port 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PORTSEL" description="Selects which USB port the device controller signals are mapped to. Other values are reserved.">
-        <Enum name="PORTU1" start="0x0" description="The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1." />
-        <Enum name="PORTU2" start="0x3" description="The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
-      </BitField>
-      <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
-      <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
-      <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
-      <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
-      <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
-      <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
-      <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
-      <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
-      <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
-      <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
-        <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
-        <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-    </Register>
-    <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-    </Register>
-    <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-    </Register>
-    <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-    </Register>
-    <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-    </Register>
-    <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-    </Register>
-    <Register start="+0x248" size="4" name="EPIN" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RX_DATA" description="Data received." />
-    </Register>
-    <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
-        <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
-        <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
-      </BitField>
-      <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
-    </Register>
-    <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
-        <Enum name="READ" start="0x02" description="Read" />
-        <Enum name="WRITE" start="0x01" description="Write" />
-        <Enum name="COMMAND" start="0x05" description="Command" />
-      </BitField>
-      <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 &lt;=  xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-    </Register>
-    <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
-      <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
-    </Register>
-    <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-    </Register>
-    <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RX_DATA" description="Receive data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_TX" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="TXDATA" description="Transmit data." />
-      <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
-      <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
-        <Enum name="TRANSACTION_HAS_NOT_" start="0" description="Transaction has not completed." />
-        <Enum name="TRANSACTION_COMPLETE" start="1" description="Transaction completed." />
-      </BitField>
-      <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
-        <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
-        <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
-      </BitField>
-      <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="LAST_TRANSMISSION_RE" start="0" description="Last transmission received an acknowledge." />
-        <Enum name="LAST_TRANSMISSION_DI" start="1" description="Last transmission did not receive an acknowledge." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="MASTER_TRANSMITTER_D" start="0" description="Master transmitter does not need data." />
-        <Enum name="MASTER_TRANSMITTER_N" start="1" description="Master transmitter needs data." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
-        <Enum name="SLAVE_TRANSMITTER_DO" start="0" description="Slave transmitter does not need data." />
-        <Enum name="SLAVE_TRANSMITTER_NE" start="1" description="Slave transmitter needs data." />
-      </BitField>
-      <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
-      <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
-      <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
-      <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
-        <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
-        <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
-      </BitField>
-      <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
-        <Enum name="RX_FIFO_CONTAINS_DAT" start="0" description="RX FIFO contains data." />
-        <Enum name="RX_FIFO_IS_EMPTY" start="1" description="RX FIFO is empty" />
-      </BitField>
-      <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
-        <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
-        <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
-      </BitField>
-      <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
-        <Enum name="TX_FIFO_CONTAINS_VAL" start="0" description="TX FIFO contains valid data." />
-        <Enum name="TX_FIFO_IS_EMPTY" start="1" description="TX FIFO is empty" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
-        <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
-        <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
-        <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
-        <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
-      </BitField>
-      <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
-        <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
-        <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
-        <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
-        <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
-        <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
-        <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
-        <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
-        <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
-      </BitField>
-      <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
-        <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
-        <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
-      </BitField>
-      <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
-        <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
-        <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
-      </BitField>
-      <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
-        <Enum name="SEE_THE_TEXT_" start="0" description="See the text." />
-        <Enum name="RESET_THE_I2C_TO_IDL" start="1" description="Reset the I2C to idle state. Self clearing." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="CLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
-        <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
-        <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
-        <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
-        <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
-        <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
-        <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
-        <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
-        <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
-        <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
-        <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="OTGClkSt" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
-        <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
-        <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
-        <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
-        <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
-        <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
-        <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
-        <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
-        <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
-        <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
-        <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CRC" start="0x20090000" description="CRC engine ">
-    <Register start="+0x000" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRC_POLY" description="Select CRC polynomial">
-        <Enum name="CRC_CCITT_POLYNOMIAL" start="0x0" description="CRC-CCITT polynomial" />
-        <Enum name="CRC_16_POLYNOMIAL" start="0x1" description="CRC-16 polynomial" />
-        <Enum name="CRC_32_POLYNOMIAL" start="0x2" description="CRC-32 polynomial" />
-      </BitField>
-      <BitField start="2" size="1" name="BIT_RVS_WR" description="Select bit order for CRC_WR_DATA">
-        <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_WR_DATA (per byte)" />
-        <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_WR_DATA (per byte)" />
-      </BitField>
-      <BitField start="3" size="1" name="CMPL_WR" description="Select one's complement for CRC_WR_DATA">
-        <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_WR_DATA" />
-        <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_WR_DATA" />
-      </BitField>
-      <BitField start="4" size="1" name="BIT_RVS_SUM" description="Select bit order revers for CRC_SUM">
-        <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_SUM" />
-        <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_SUM" />
-      </BitField>
-      <BitField start="5" size="1" name="CMPL_SUM" description="Select one's complement for CRC_SUM">
-        <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_SUM" />
-        <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_SUM" />
-      </BitField>
-      <BitField start="6" size="26" name="Reserved" description="Always 0 when read" />
-    </Register>
-    <Register start="+0x004" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." />
-    </Register>
-    <Register start="+0x008" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." />
-    </Register>
-    <Register start="+0x008" size="4" name="DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO" start="0x20098000" description="GPIO">
-    <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="DIR5" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+160" size="4" name="MASK5" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+160" size="4" name="PIN5" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+160" size="4" name="SET5" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+160" size="4" name="CLR5" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x2009C000" description="External Memory Controller (EMC)">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled:">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled&#xa;(POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map:">
-        <Enum name="NORMAL" start="0" description="Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset memory map. Static memory EMC_CS1 is&#xa;mirrored onto EMC_CS0 and EMC_DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode:">
-        <Enum name="WARMRESET" start="0" description="Normal mode (warm&#xa;reset value)." />
-        <Enum name="LOWPOWER" start="1" description="Low-power&#xa;mode. Entering low-power mode reduces memory controller power consumption.&#xa;Dynamic memory is refreshed as necessary. The memory controller&#xa;returns to normal functional mode by clearing the low-power mode&#xa;bit (L), or by POR. This bit must only be modified when the EMC&#xa;is in idle state.[1]" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not.">
-        <Enum name="IDLE" start="0" description="EMC&#xa;is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="EMC&#xa;is busy performing memory transactions, commands, auto-refresh cycles,&#xa;or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status.This bit enables the EMC to enter low-power mode or disabled mode cleanly.">
-        <Enum name="EMPTY" start="0" description="Write buffers&#xa;empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Write&#xa;buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC.">
-        <Enum name="NORMAL" start="0" description="Normal mode" />
-        <Enum name="SELFREFRESH" start="1" description="Self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes.">
-        <Enum name="LITTLEENDIAN" start="0" description="Little-endian&#xa;mode (POR reset value)." />
-        <Enum name="BIGENDIAN" start="1" description="Big-endian&#xa;mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CLKR" description="CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC.">
-        <Enum name="PORRESET" start="0" description="1:1(POR reset value)" />
-        <Enum name="DONOTUSE" start="1" description="1:2 (this option is not available on the LPC178x/177x)" />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="POWERSAVE" start="0" description="Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="HIGH" start="1" description="All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE_" start="0" description="Normal mode." />
-        <Enum name="ENTER_SELF_REFRESH_M" start="1" description="Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="CLKOUT_ENABLED_POR_" start="0" description="CLKOUT enabled (POR reset value)." />
-        <Enum name="CLKOUT_DISABLED" start="1" description="CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures dynamic memory read strategy." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy">
-        <Enum name="CLOCK_OUT_DELAYED_ST" start="0x0" description="Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value." />
-        <Enum name="COMMAND_DELAYED_STRA" start="0x1" description="Command delayed strategy, using EMCCLKDELAY (command delayed, clock out not delayed)." />
-        <Enum name="COMMAND_DELAYED_STRA" start="0x2" description="Command delayed strategy plus one clock cycle, using EMCCLKDELAY (command delayed, clock out not delayed)." />
-        <Enum name="COMMAND_DELAYED_STRA" start="0x3" description="Command delayed strategy plus two clock cycles, using EMCCLKDELAY (command delayed, clock out not delayed)." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Precharge command period." reset_value="0x0F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Time for exit self-refresh to active command." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Latency for active bank A to active bank B." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Time for load mode register to active command." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Time for long static memory read and write transfers." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40000000" description=" Windowed Watchdog Timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="STOP" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
-        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section  WDTOF." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section  WDINT." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only. See Section  WDPROTECT.">
-        <Enum name="CHANGE" start="0" description="The watchdog reload value (WDTC) can be changed at any time." />
-        <Enum name="CHANGE_W_CNT" start="1" description="The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Watchdog time-out interval." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40004000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40008000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40010000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
-        <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
-        <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="MODEM" start="0x0" description="4   - Modem Interrupt." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="VALID" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM0" start="0x40014000" description="Pulse Width Modulators (PWM0/1)">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM0/1)">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="COMPARATOR" start="0x40020000" description="Comparators">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Comparator block control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMP_PD_IREF" description="Controls the current source used by the comparators. These bits must be set when either comparator is used.">
-        <Enum name="DISABLED" start="0x0" description="The comparator current source is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator current source is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The comparator current source is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The comparator current source is powered up." />
-      </BitField>
-      <BitField start="2" size="2" name="CMP_PD_VBG" description="Controls the bandgap reference source that is used by the comparators. These bits must be set when either comparator is used.">
-        <Enum name="DISABLED" start="0x0" description="The comparator bandgap reference is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator bandgap reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The comparator bandgap reference is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The comparator bandgap reference is powered up." />
-      </BitField>
-      <BitField start="4" size="2" name="CMP_VTEMP" description="Controls the voltage reference of the temperature sensor. These bits must be set when the temperature sensor is used.">
-        <Enum name="DISABLED" start="0x0" description="The temperature sensor voltage reference is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor voltage reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor voltage reference is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The temperature sensor voltage reference is powered up." />
-      </BitField>
-      <BitField start="6" size="2" name="CMP_TEMPSEN" description="Enables the temperature sensor. These bits must be set when the temperature sensor is used.">
-        <Enum name="DISABLED" start="0x0" description="Temperature sensor is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="Temperature sensor is enabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CMP_ROSCCTL" description="Selects the inputs for the flip/flops that provide the CMP_ROSC output.">
-        <Enum name="CMP1" start="0" description="The CMP_ROSC output is set by CMP1 and reset by CMP0." />
-        <Enum name="CMP0" start="1" description="The CMP_ROSC output is set by CMP0 and reset by CMP1." />
-      </BitField>
-      <BitField start="9" size="1" name="CMP_EXT_RESET" description="Selects the reset source for the CMP_ROSC output.">
-        <Enum name="INTRESET" start="0" description="The CMP_ROSC output is reset by the internal chip reset." />
-        <Enum name="CMP_RESETIN" start="1" description="The CMP_ROSC output is reset by the CMP_RESET input." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="CMP_T0CAP2" description="Selects the input for Timer 0 capture input 2.">
-        <Enum name="COMP0" start="0" description="T0CAP2 is connected to comparator 0 level output." />
-        <Enum name="COMP1" start="1" description="T0CAP2 is connected to comparator 1 level output." />
-      </BitField>
-      <BitField start="13" size="1" name="CMP_T0CAP3" description="Selects the input for Timer 0 capture input 3.">
-        <Enum name="COMP0" start="0" description="T0CAP3 is connected to comparator 0 edge output." />
-        <Enum name="COMP1" start="1" description="T0CAP3 is connected to comparator 1 edge output." />
-      </BitField>
-      <BitField start="14" size="1" name="CMP_T1CAP2" description="Selects the input for Timer 1 capture input 2.">
-        <Enum name="COMP1" start="0" description="T1CAP2 is connected to comparator 1 edge output." />
-        <Enum name="COMP0" start="1" description="T1CAP2 is connected to comparator 0 level output." />
-      </BitField>
-      <BitField start="15" size="1" name="CMP_T1CAP3" description="Selects the input for Timer 1 capture input 3.">
-        <Enum name="COMP1" start="0" description="T1CAP3 is connected to comparator 1 level output." />
-        <Enum name="COMP0" start="1" description="T1CAP3 is connected to comparator 0 edge output." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL0" access="Read/Write" description="Comparator 0 control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMP0_EN" description="Comparator 0 enable control.">
-        <Enum name="DISABLED" start="0x0" description="Comparator 0 disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 0 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 0 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="Comparator 0 is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CMP0_OE" description="Comparator 0 output enable.">
-        <Enum name="DISABLED" start="0" description="Comparator 0 output is disabled." />
-        <Enum name="ENABLED" start="1" description="Comparator 0 output is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CMP0_STAT" description="Comparator 0 status. This bit reflects the comparator 0 output, and is not affected by CMP0_OE." />
-      <BitField start="4" size="3" name="CMP0_VM" description="Comparator 0 VM input select.">
-        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
-        <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." />
-        <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." />
-        <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." />
-        <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." />
-        <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="3" name="CMP0_VP" description="Comparator 0 VP input select.">
-        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
-        <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." />
-        <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." />
-        <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." />
-        <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." />
-        <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="CMP0_SYNC" description="Comparator 0 output synchronization control.">
-        <Enum name="DIRECT" start="0" description="The comparator 0 output is used directly." />
-        <Enum name="SYNCH" start="1" description="The comparator 0 output is synchronized with the internal bus clock for output to other peripherals." />
-      </BitField>
-      <BitField start="13" size="2" name="CMP0_HYS" description="Comparator 0 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.">
-        <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." />
-        <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." />
-        <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." />
-        <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." />
-      </BitField>
-      <BitField start="15" size="1" name="CMP0_INTPOL" description="Selects the polarity of the CMP0 output for purposes of generating level interrupts. See Table 412.">
-        <Enum name="NOTINVERTED" start="0" description="The CMP0 output is used as-is for generating interrupts." />
-        <Enum name="INVERTED" start="1" description="The CMP0 output is used inverted for generating interrupts." />
-      </BitField>
-      <BitField start="16" size="1" name="CMP0_INTTYPE" description="Select comparator 0 interrupt type. See Table 412.">
-        <Enum name="EDGE" start="0" description="Comparator 0 interrupt is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Comparator 0 interrupt is level triggered." />
-      </BitField>
-      <BitField start="17" size="2" name="CMP0_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP0_IntType = 0. See Table 412.">
-        <Enum name="FALLING" start="0x0" description="Comparator 0 interrupt is active on falling edges." />
-        <Enum name="RISING" start="0x1" description="Comparator 0 interrupt is active on rising edges." />
-        <Enum name="DUALEDGE" start="0x2" description="Comparator 0 Interrupt is active on both edges." />
-      </BitField>
-      <BitField start="19" size="1" name="CMP0_INTFLAG" description="Comparator 0 interrupt flag.">
-        <Enum name="NOTPENDING" start="0" description="The Comparator 0 interrupt is not pending." />
-        <Enum name="PENDING" start="1" description="The Comparator 0 interrupt is pending. Writing a 1 to this bit clears the flag." />
-      </BitField>
-      <BitField start="20" size="2" name="CMP0_VLADEN" description="Voltage ladder enable for comparator 0.">
-        <Enum name="DISABLED" start="0x0" description="The Comparator 0 voltage ladder is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 0 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 0 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The Comparator 0 voltage ladder is enabled." />
-      </BitField>
-      <BitField start="22" size="1" name="CMP0_VLADREF" description="Voltage reference select for comparator 0 voltage ladder.">
-        <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." />
-        <Enum name="VDDA_PIN_" start="1" description="VDDA pin." />
-      </BitField>
-      <BitField start="23" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="5" name="CMP0_VSEL" description="Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of CMP0_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x  Vref0 / 31. 00010 = 2 x Vref0 / 31. ... 11111 = Vref0" />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL1" access="Read/Write" description="Comparator 1 control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMP1_EN" description="Comparator 1 enable control.">
-        <Enum name="DISABLED" start="0x0" description="Comparator 1 disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 1 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 1 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="Comparator 1 is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CMP1_OE" description="Comparator 1 output enable.">
-        <Enum name="DISABLED" start="0" description="Comparator 1 output is disabled." />
-        <Enum name="ENABLED" start="1" description="Comparator 1 output is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CMP1_STAT" description="Comparator 1 status. This bit reflects the comparator 1 output, and is not affected by CMP1_OE." />
-      <BitField start="4" size="3" name="CMP1_VM" description="Comparator 1 VM input select.">
-        <Enum name="VREF_DIVIDER_1_" start="0x0" description="Vref divider 1." />
-        <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." />
-        <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." />
-        <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." />
-        <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." />
-        <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="3" name="CMP1_VP" description="Comparator 1 VP input select.">
-        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
-        <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." />
-        <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." />
-        <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." />
-        <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." />
-        <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="CMP1_SYNC" description="Comparator 1 output synchronization control.">
-        <Enum name="DIRECT" start="0" description="The comparator 1 output is used directly." />
-        <Enum name="SYNCH" start="1" description="The comparator 1 output is synchronized with the internal bus clock for output to other peripherals." />
-      </BitField>
-      <BitField start="13" size="2" name="CMP1_HYS" description="Comparator 1 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.">
-        <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." />
-        <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." />
-        <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." />
-        <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." />
-      </BitField>
-      <BitField start="15" size="1" name="CMP1_INTPOL" description="Selects the polarity of the CMP1 output for purposes of generating level interrupts. See Table 412.">
-        <Enum name="NOTINVERTED" start="0" description="The CMP1 output is used as-is for generating interrupts." />
-        <Enum name="INVERTED" start="1" description="The CMP1 output is used inverted for generating interrupts." />
-      </BitField>
-      <BitField start="16" size="1" name="CMP1_INTTYPE" description="Select comparator 1 interrupt type. See Table 412.">
-        <Enum name="EDGE" start="0" description="Comparator 1 interrupt is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Comparator 1 interrupt is level triggered." />
-      </BitField>
-      <BitField start="17" size="2" name="CMP1_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP1_IntType = 0. See Table 412.">
-        <Enum name="FALLING" start="0x0" description="Comparator 1 interrupt is active on falling edges." />
-        <Enum name="RISING" start="0x1" description="Comparator 1 interrupt is active on rising edges." />
-        <Enum name="DUALEDGE" start="0x2" description="Comparator 1 Interrupt is active on both edges." />
-      </BitField>
-      <BitField start="19" size="1" name="CMP1_INTFLAG" description="Comparator 1 interrupt flag.">
-        <Enum name="NOTPENDING" start="0" description="The Comparator 1 interrupt is not pending." />
-        <Enum name="PENDING" start="1" description="The Comparator 1 interrupt is pending. Writing a 1 to this bit clears the flag." />
-      </BitField>
-      <BitField start="20" size="2" name="CMP1_VLADEN" description="Voltage ladder enable for comparator 1.">
-        <Enum name="DISABLED" start="0x0" description="The Comparator 1 voltage ladder is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 1 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 1 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The Comparator 1 voltage ladder is enabled." />
-      </BitField>
-      <BitField start="22" size="1" name="CMP1_VLADREF" description="Voltage reference select for comparator 1 voltage ladder.">
-        <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." />
-        <Enum name="VDDA_PIN_" start="1" description="VDDA pin." />
-      </BitField>
-      <BitField start="23" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="5" name="CMP1_VSel" description="Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of CMP1_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref1 / 31. 00010 = 2 x Vref1 / 31. ... 11111 = Vref1." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) ">
-    <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
-        <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-        <Enum name="NO_EFFECT_" start="0" description="No effect." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
-        <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-      </BitField>
-    </Register>
-    <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTROL" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wakeup enable for channel 0.">
-        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 0." />
-        <Enum name="AN_EVENT_IN_CHANNEL_" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="NOGPREG" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="CLRGPREG" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin RTC_EV0.">
-        <Enum name="NEG" start="0" description="A channel 0 event is defined as a negative edge on RTC_EV0." />
-        <Enum name="POS" start="1" description="A channel 0 event is defined as a positive edge on RTC_EV0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0.[1]">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wakeup enable for channel 1.">
-        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 1." />
-        <Enum name="WAKEUP" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="NOGPREG" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="CLRGPREG" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin RTC_EV1.">
-        <Enum name="NEG" start="0" description="A channel 1 event is defined as a negative edge on RTC_EV1." />
-        <Enum name="POS" start="1" description="A channel 1 event is defined as a positive edge on RTC_EV1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1.[1]">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wakeup enable for channel 2.">
-        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 2." />
-        <Enum name="WAKEUP" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="NOGPREG" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="CLRGPREG" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin RTC_EV2.">
-        <Enum name="NEG" start="0" description="A channel 2 event is defined as a negative edge on RTC_EV2." />
-        <Enum name="POS" start="1" description="A channel 2 event is defined as a positive edge on RTC_EV2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2.[1]">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2]">
-        <Enum name="DISABLED" start="0x0" description="Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="ENABLE_EVENT_MONITOR16HZ" start="0x1" description="Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="ENABLE_EVENT_MONITOR64HZ" start="0x2" description="Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="ENABLE_EVENT_MONITOR1KHZ" start="0x3" description="Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Event flag for channel 0 (RTC_EV0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 0." />
-        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Event flag for channel 1 (RTC_EV1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 1." />
-        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Event flag for channel 2 (RTC_EV2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 2." />
-        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOGPCLR" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="GPCLR" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wakeup request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_INTERRUPTWAKEUP_" start="0" description="No interrupt/wakeup request is pending" />
-        <Enum name="INTWAKEUP_PEND" start="1" description="An interrupt/wakeup request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
-    <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0Int" description="Port 0 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="P2Int" description="Port 2 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="P0_31REI" description="Status of Rising Edge Interrupt for P0[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-    </Register>
-    <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="P0_31FEI" description="Status of Falling Edge Interrupt for P0[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="P0_31CI" description="Clear GPIO port Interrupts for P0[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-    </Register>
-    <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="P0_31ER" description="Enable rising edge interrupt for P0[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="P0_31EF" description="Enable falling edge interrupt for P0[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-    </Register>
-    <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P2_14REI" description="Status of Rising Edge Interrupt for P2[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P2_15REI" description="Status of Rising Edge Interrupt for P2[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P2_16REI" description="Status of Rising Edge Interrupt for P2[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P2_17REI" description="Status of Rising Edge Interrupt for P2[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P2_18REI" description="Status of Rising Edge Interrupt for P2[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P2_19REI" description="Status of Rising Edge Interrupt for P2[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P2_20REI" description="Status of Rising Edge Interrupt for P2[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P2_21REI" description="Status of Rising Edge Interrupt for P2[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P2_22REI" description="Status of Rising Edge Interrupt for P2[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P2_23REI" description="Status of Rising Edge Interrupt for P2[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P2_24REI" description="Status of Rising Edge Interrupt for P2[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P2_25REI" description="Status of Rising Edge Interrupt for P2[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P2_26REI" description="Status of Rising Edge Interrupt for P2[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P2_27REI" description="Status of Rising Edge Interrupt for P2[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P2_28REI" description="Status of Rising Edge Interrupt for P2[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P2_29REI" description="Status of Rising Edge Interrupt for P2[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P2_30REI" description="Status of Rising Edge Interrupt for P2[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="P2_31REI" description="Status of Rising Edge Interrupt for P2[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-    </Register>
-    <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P2_14FEI" description="Status of Falling Edge Interrupt for P2[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P2_15FEI" description="Status of Falling Edge Interrupt for P2[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P2_16FEI" description="Status of Falling Edge Interrupt for P2[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P2_17FEI" description="Status of Falling Edge Interrupt for P2[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P2_18FEI" description="Status of Falling Edge Interrupt for P2[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P2_19FEI" description="Status of Falling Edge Interrupt for P2[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P2_20FEI" description="Status of Falling Edge Interrupt for P2[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P2_21FEI" description="Status of Falling Edge Interrupt for P2[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P2_22FEI" description="Status of Falling Edge Interrupt for P2[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P2_23FEI" description="Status of Falling Edge Interrupt for P2[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P2_24FEI" description="Status of Falling Edge Interrupt for P2[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P2_25FEI" description="Status of Falling Edge Interrupt for P2[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P2_26FEI" description="Status of Falling Edge Interrupt for P2[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P2_27FEI" description="Status of Falling Edge Interrupt for P2[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P2_28FEI" description="Status of Falling Edge Interrupt for P2[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P2_29FEI" description="Status of Falling Edge Interrupt for P2[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P2_30FEI" description="Status of Falling Edge Interrupt for P2[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="P2_31FEI" description="Status of Falling Edge Interrupt for P2[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P2_14CI" description="Clear GPIO port Interrupts for P2[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P2_15CI" description="Clear GPIO port Interrupts for P2[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P2_16CI" description="Clear GPIO port Interrupts for P2[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P2_17CI" description="Clear GPIO port Interrupts for P2[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P2_18CI" description="Clear GPIO port Interrupts for P2[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P2_19CI" description="Clear GPIO port Interrupts for P2[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P2_20CI" description="Clear GPIO port Interrupts for P2[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P2_21CI" description="Clear GPIO port Interrupts for P2[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P2_22CI" description="Clear GPIO port Interrupts for P2[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P2_23CI" description="Clear GPIO port Interrupts for P2[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P2_24CI" description="Clear GPIO port Interrupts for P2[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P2_25CI" description="Clear GPIO port Interrupts for P2[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P2_26CI" description="Clear GPIO port Interrupts for P2[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P2_27CI" description="Clear GPIO port Interrupts for P2[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P2_28CI" description="Clear GPIO port Interrupts for P2[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P2_29CI" description="Clear GPIO port Interrupts for P2[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P2_30CI" description="Clear GPIO port Interrupts for P2[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="P2_31CI" description="Clear GPIO port Interrupts for P2[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-    </Register>
-    <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P2_14ER" description="Enable rising edge interrupt for P2[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P2_15ER" description="Enable rising edge interrupt for P2[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P2_16ER" description="Enable rising edge interrupt for P2[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P2_17ER" description="Enable rising edge interrupt for P2[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P2_18ER" description="Enable rising edge interrupt for P2[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P2_19ER" description="Enable rising edge interrupt for P2[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P2_20ER" description="Enable rising edge interrupt for P2[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P2_21ER" description="Enable rising edge interrupt for P2[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P2_22ER" description="Enable rising edge interrupt for P2[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P2_23ER" description="Enable rising edge interrupt for P2[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P2_24ER" description="Enable rising edge interrupt for P2[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P2_25ER" description="Enable rising edge interrupt for P2[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P2_26ER" description="Enable rising edge interrupt for P2[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P2_27ER" description="Enable rising edge interrupt for P2[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P2_28ER" description="Enable rising edge interrupt for P2[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P2_29ER" description="Enable rising edge interrupt for P2[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P2_30ER" description="Enable rising edge interrupt for P2[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="P2_31ER" description="Enable rising edge interrupt for P2[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-    </Register>
-    <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P2_14EF" description="Enable falling edge interrupt for P2[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P2_15EF" description="Enable falling edge interrupt for P2[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P2_16EF" description="Enable falling edge interrupt for P2[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P2_17EF" description="Enable falling edge interrupt for P2[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P2_18EF" description="Enable falling edge interrupt for P2[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P2_19EF" description="Enable falling edge interrupt for P2[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P2_20EF" description="Enable falling edge interrupt for P2[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P2_21EF" description="Enable falling edge interrupt for P2[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P2_22EF" description="Enable falling edge interrupt for P2[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P2_23EF" description="Enable falling edge interrupt for P2[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P2_24EF" description="Enable falling edge interrupt for P2[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P2_25EF" description="Enable falling edge interrupt for P2[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P2_26EF" description="Enable falling edge interrupt for P2[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P2_27EF" description="Enable falling edge interrupt for P2[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P2_28EF" description="Enable falling edge interrupt for P2[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P2_29EF" description="Enable falling edge interrupt for P2[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P2_30EF" description="Enable falling edge interrupt for P2[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="P2_31EF" description="Enable falling edge interrupt for P2[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="IOCON" start="0x4002C000" description="IOCON pin configuration">
-    <Register start="+0x0" size="4" name="P0_0" access="Read/Write" description="I/O configuration register for pin P0[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[0]">
-        <Enum name="P0_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_RD1" start="0x1" description="CAN1 receiver input." />
-        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
-        <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="U0_TXD" start="0x4" description="Transmitter output for UART0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x4" size="4" name="P0_1" access="Read/Write" description="I/O configuration register for pin P0[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[1]">
-        <Enum name="P0_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_TD1" start="0x1" description="CAN1 transmitter output." />
-        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
-        <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="U0_RXD" start="0x4" description="Receiver input for UART0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x8" size="4" name="P0_2" access="Read/Write" description="I/O configuration register for pin P0[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[2]">
-        <Enum name="P0_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U0_TXD" start="0x1" description="Transmitter output for UART0." />
-        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC" size="4" name="P0_3" access="Read/Write" description="I/O configuration register for pin P0[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[3]">
-        <Enum name="P0_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U0_RXD" start="0x1" description="Receiver input for UART0." />
-        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x10" size="4" name="P0_4" access="Read/Write" description="I/O configuration register for pin P0[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[4]">
-        <Enum name="P0_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_RX_SCK" start="0x1" description="I2S Receive clock. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="CAN_RD2" start="0x2" description="CAN2 receiver input." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-        <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer                                 applications." />
-        <Enum name="LCD_VD_0" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x14" size="4" name="P0_5" access="Read/Write" description="I/O configuration register for pin P0[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[5]">
-        <Enum name="P0_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_RX_WS" start="0x1" description="I2S Receive word select. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="CAN_TD2" start="0x2" description="CAN2 transmitter output." />
-        <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." />
-        <Enum name="CMP_RESET" start="0x5" description="Comparator reset." />
-        <Enum name="LCD_VD_1" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x18" size="4" name="P0_6" access="Read/Write" description="I/O configuration register for pin P0[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[6]">
-        <Enum name="P0_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_RX_SDA" start="0x1" description="I2S Receive data. It is driven                                     by the transmitter and read by the receiver. Corresponds to the                                     signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." />
-        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
-        <Enum name="U1_RTS" start="0x4" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer                                 applications." />
-        <Enum name="LCD_VD_8" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C" size="4" name="P0_7" access="Read/Write" description="I/O configuration register for pin P0[7] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[7] ">
-        <Enum name="P0_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_TX_SCK" start="0x1" description="I2S transmit clock. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." />
-        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
-        <Enum name="RTC_EV0" start="0x4" description="Event input 0 to Event Monitor/Recorder." />
-        <Enum name="CMP_VREF" start="0x5" description="Comparator reference voltage." />
-        <Enum name="LCD_VD_9" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
-        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
-        <Enum name="DISABLED" start="1" description="No input filtering is done." />
-      </BitField>
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x20" size="4" name="P0_8" access="Read/Write" description="I/O configuration register for pin P0[8] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[8] ">
-        <Enum name="P0_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_TX_WS" start="0x1" description="I2S Transmit word select. It                                     is driven by the master and received by the slave. Corresponds                                     to the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." />
-        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
-        <Enum name="RTC_EV1" start="0x4" description="Event input 1 to Event Monitor/Recorder." />
-        <Enum name="CMP1_IN_3" start="0x5" description="Comparator 1, input 3." />
-        <Enum name="LCD_VD_16" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
-        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
-        <Enum name="DISABLED" start="1" description="No input filtering is done." />
-      </BitField>
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x24" size="4" name="P0_9" access="Read/Write" description="I/O configuration register for pin P0[9]" reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[9]">
-        <Enum name="P0_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_TX_SDA" start="0x1" description="I2S transmit data. It is                                     driven by the transmitter and read by the receiver. Corresponds                                     to the signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." />
-        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
-        <Enum name="RTC_EV2" start="0x4" description="Event input 2 to Event Monitor/Recorder." />
-        <Enum name="CMP1_IN_2" start="0x5" description="Comparator 1, input 2." />
-        <Enum name="LCD_VD_17" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
-        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
-        <Enum name="DISABLED" start="1" description="No input filtering is done." />
-      </BitField>
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x28" size="4" name="P0_10" access="Read/Write" description="I/O configuration register for pin P0[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[10]">
-        <Enum name="P0_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U2_TXD" start="0x1" description="Transmitter output for UART2." />
-        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
-        <Enum name="LCD_VD_5" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x2C" size="4" name="P0_11" access="Read/Write" description="I/O configuration register for pin P0[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[11]">
-        <Enum name="P0_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U2_RXD" start="0x1" description="Receiver input for UART2." />
-        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
-        <Enum name="LCD_VD_10" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x30" size="4" name="P0_12" access="Read/Write" description="I/O configuration register for pin P0[12]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[12]">
-        <Enum name="P0_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_PPWR2" start="0x1" description="Port Power enable signal for USB port 2." />
-        <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." />
-        <Enum name="ADC0_IN_6" start="0x3" description="A/D converter 0, input 6. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x34" size="4" name="P0_13" access="Read/Write" description="I/O configuration register for pin P0[13]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[13]">
-        <Enum name="P0_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_UP_LED2" start="0x1" description="USB port 2 GoodLink LED indicator. It is LOW when the                                     device is configured (non-control endpoints enabled), or when                                     the host is enabled and has detected a device on the bus. It is                                     HIGH when the device is not configured, or when host is enabled                                     and has not detected a device on the bus, or during global                                     suspend. It transitions between LOW and HIGH (flashes) when the                                     host is enabled and detects activity on the bus." />
-        <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." />
-        <Enum name="ADC0_IN_7" start="0x3" description="A/D converter 0, input 7. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x38" size="4" name="P0_14" access="Read/Write" description="I/O configuration register for pin P0[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[14]">
-        <Enum name="P0_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_HSTEN2" start="0x1" description="Host Enabled status for USB port 2." />
-        <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." />
-        <Enum name="USB_CONNECT2" start="0x3" description="SoftConnect control for USB port 2. Signal used to switch                                     an external 1.5 kW resistor under                                     software control. Used with the SoftConnect USB                                     feature." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x3C" size="4" name="P0_15" access="Read/Write" description="I/O configuration register for pin P0[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[15]">
-        <Enum name="P0_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_TXD" start="0x1" description="Transmitter output for UART1." />
-        <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." />
-        <Enum name="SPIFI_IO_2" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x40" size="4" name="P0_16" access="Read/Write" description="I/O configuration register for pin P0[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[16]">
-        <Enum name="P0_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_RXD" start="0x1" description="Receiver input for UART1." />
-        <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." />
-        <Enum name="SPIFI_IO_3" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x44" size="4" name="P0_17" access="Read/Write" description="I/O configuration register for pin P0[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[17]">
-        <Enum name="P0_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_CTS" start="0x1" description="Clear to Send input for UART1." />
-        <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." />
-        <Enum name="SPIFI_IO_1" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x48" size="4" name="P0_18" access="Read/Write" description="I/O configuration register for pin P0[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[18]">
-        <Enum name="P0_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_DCD" start="0x1" description="Data Carrier Detect input for UART1." />
-        <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." />
-        <Enum name="SPIFI_IO_0" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x4C" size="4" name="P0_19" access="Read/Write" description="I/O configuration register for pin P0[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[19]">
-        <Enum name="P0_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_DSR" start="0x1" description="Data Set Ready input for UART1." />
-        <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." />
-        <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="LCD_VD_13" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x50" size="4" name="P0_20" access="Read/Write" description="I/O configuration register for pin P0[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[20]">
-        <Enum name="P0_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_DTR" start="0x1" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." />
-        <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="LCD_VD_14" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x54" size="4" name="P0_21" access="Read/Write" description="I/O configuration register for pin P0[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[21]">
-        <Enum name="P0_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_RI" start="0x1" description="Ring Indicator input for UART1." />
-        <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power                                     supply." />
-        <Enum name="U4_OE" start="0x3" description="RS-485/EIA-485 output enable signal for                                     UART4." />
-        <Enum name="CAN_RD1" start="0x4" description="CAN1 receiver input." />
-        <Enum name="U4_SCLK" start="0x5" description="USART 4 clock input or output in synchronous                                     mode." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x58" size="4" name="P0_22" access="Read/Write" description="I/O configuration register for pin P0[22]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[22]">
-        <Enum name="P0_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_RTS" start="0x1" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." />
-        <Enum name="U4_TXD" start="0x3" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
-        <Enum name="CAN_TD1" start="0x4" description="CAN1 transmitter output." />
-        <Enum name="SPIFI_CLK" start="0x5" description="Clock output for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x5C" size="4" name="P0_23" access="Read/Write" description="I/O configuration register for pin P0[23]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[23]">
-        <Enum name="P0_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_0" start="0x1" description="A/D converter 0, input 0. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2S_RX_SCK" start="0x2" description="Receive Clock. It is driven by the master and received by                                     the slave. Corresponds to the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
-      </BitField>
-    </Register>
-    <Register start="+0x60" size="4" name="P0_24" access="Read/Write" description="I/O configuration register for pin P0[24]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[24]">
-        <Enum name="P0_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_1" start="0x1" description="A/D converter 0, input 1. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2S_RX_WS" start="0x2" description="Receive Word Select. It is driven by the master and                                     received by the slave. Corresponds to the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x64" size="4" name="P0_25" access="Read/Write" description="I/O configuration register for pin P0[25]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[25]">
-        <Enum name="P0_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_2" start="0x1" description="A/D converter 0, input 2. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2S_RX_SDA" start="0x2" description="Receive data. It is driven by the transmitter and read by                                     the receiver. Corresponds to the signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="U3_TXD" start="0x3" description="Transmitter output for UART3." />
-      </BitField>
-    </Register>
-    <Register start="+0x68" size="4" name="P0_26" access="Read/Write" description="I/O configuration register for pin P0[26]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[26]">
-        <Enum name="P0_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_3" start="0x1" description="A/D converter 0, input 3. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="DAC_OUT" start="0x2" description="D/A converter output. When configured as the DAC output,                                     the digital function of the pin must be disabled." />
-        <Enum name="U3_RXD" start="0x3" description="Receiver input for UART3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="DACEN" description="DAC output enable.">
-        <Enum name="DISABLE" start="0" description="DAC disable." />
-        <Enum name="ENABLE" start="1" description="DAC enable." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x6C" size="4" name="P0_27" access="Read/Write" description="I/O configuration register for pin P0[27]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[27]">
-        <Enum name="P0_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2C0_SDA" start="0x1" description="I2C0 data input/output. (This                                     pin uses a specialized I2C pad)." />
-        <Enum name="USB_SDA1" start="0x2" description="I2C serial data for communication with an external USB                                     transceiver." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x70" size="4" name="P0_28" access="Read/Write" description="I/O configuration register for pin P0[28]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[28]">
-        <Enum name="P0_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2C0_SCL" start="0x1" description="I2C0 clock input/output (this                                     pin uses a specialized I2C pad." />
-        <Enum name="USB_SCL1" start="0x2" description="I2C serial clock for communication with an external USB                                     transceiver." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x74" size="4" name="P0_29" access="Read/Write" description="I/O configuration register for pin P0[29]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[29]">
-        <Enum name="P0_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_DP1" start="0x1" description="USB port 1 bidirectional D+ line." />
-        <Enum name="EINT0" start="0x2" description="External interrupt 0 input." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x78" size="4" name="P0_30" access="Read/Write" description="I/O configuration register for pin P0[30]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[30]">
-        <Enum name="P0_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_DM1" start="0x1" description="USB port 1 bidirectional D-                                     line." />
-        <Enum name="EINT1" start="0x2" description="External interrupt 1 input." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x7C" size="4" name="P0_31" access="Read/Write" description="I/O configuration register for pin P0[31]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[31]">
-        <Enum name="P0_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_DP2" start="0x1" description="USB port 2 bidirectional D+ line." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x80" size="4" name="P1_0" access="Read/Write" description="I/O configuration register for pin P1[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[0]">
-        <Enum name="P1_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD0" start="0x1" description="Ethernet transmit data 0 (RMII/MII                                     interface)." />
-        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
-        <Enum name="SSP2_SCK" start="0x4" description="Serial clock for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x84" size="4" name="P1_1" access="Read/Write" description="I/O configuration register for pin P1[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[1]">
-        <Enum name="P1_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD1" start="0x1" description="Ethernet transmit data 1 (RMII/MII                                     interface)." />
-        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
-        <Enum name="SSP2_MOSI" start="0x4" description="Master Out Slave In for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x88" size="4" name="P1_2" access="Read/Write" description="I/O configuration register for pin P1[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[2]">
-        <Enum name="P1_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD2" start="0x1" description="Ethernet transmit data 2 (MII interface)." />
-        <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." />
-        <Enum name="PWM0_1" start="0x3" description="Pulse Width Modulator 0, output 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x8C" size="4" name="P1_3" access="Read/Write" description="I/O configuration register for pin P1[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[3]">
-        <Enum name="P1_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD3" start="0x1" description="Ethernet transmit data 3 (MII interface)." />
-        <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." />
-        <Enum name="PWM0_2" start="0x3" description="Pulse Width Modulator 0, output 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x90" size="4" name="P1_4" access="Read/Write" description="I/O configuration register for pin P1[4] " reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[4] ">
-        <Enum name="P1_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TX_EN" start="0x1" description="Ethernet transmit data enable (RMII/MII                                     interface)." />
-        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
-        <Enum name="SSP2_MISO" start="0x4" description="Master In Slave Out for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x94" size="4" name="P1_5" access="Read/Write" description="I/O configuration register for pin P1[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[5]">
-        <Enum name="P1_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TX_ER" start="0x1" description="Ethernet Transmit Error (MII interface)." />
-        <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power                                     supply." />
-        <Enum name="PWM0_3" start="0x3" description="Pulse Width Modulator 0, output 3." />
-        <Enum name="CMP1_IN_1" start="0x5" description="Comparator 1, input 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x98" size="4" name="P1_6" access="Read/Write" description="I/O configuration register for pin P1[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[6]">
-        <Enum name="P1_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TX_CLK" start="0x1" description="Ethernet Transmit Clock (MII interface)." />
-        <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." />
-        <Enum name="PWM0_4" start="0x3" description="Pulse Width Modulator 0, output 4." />
-        <Enum name="CMP0_IN_3" start="0x5" description="Comparator 0, input 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x9C" size="4" name="P1_7" access="Read/Write" description="I/O configuration register for pin P1[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[7]">
-        <Enum name="P1_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_COL" start="0x1" description="Ethernet Collision detect (MII interface)." />
-        <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." />
-        <Enum name="PWM0_5" start="0x3" description="Pulse Width Modulator 0, output 5." />
-        <Enum name="CMP1_IN_0" start="0x5" description="Comparator 1, input 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xA0" size="4" name="P1_8" access="Read/Write" description="I/O configuration register for pin P1[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[8]">
-        <Enum name="P1_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_CRS_CRS_DV" start="0x1" description="Ethernet Carrier Sense (MII interface) or Ethernet                                     Carrier Sense/Data Valid (RMII interface)." />
-        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
-        <Enum name="SSP2_SSEL" start="0x4" description="Slave Select for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xA4" size="4" name="P1_9" access="Read/Write" description="I/O configuration register for pin P1[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[9]">
-        <Enum name="P1_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD0" start="0x1" description="Ethernet receive data 0 (RMII/MII interface)." />
-        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xA8" size="4" name="P1_10" access="Read/Write" description="I/O configuration register for pin P1[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[10]">
-        <Enum name="P1_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD1" start="0x1" description="Ethernet receive data 1 (RMII/MII interface)." />
-        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xAC" size="4" name="P1_11" access="Read/Write" description="I/O configuration register for pin P1[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[11]">
-        <Enum name="P1_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD2" start="0x1" description="Ethernet Receive Data 2 (MII interface)." />
-        <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." />
-        <Enum name="PWM0_6" start="0x3" description="Pulse Width Modulator 0, output 6." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xB0" size="4" name="P1_12" access="Read/Write" description="I/O configuration register for pin P1[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[12]">
-        <Enum name="P1_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD3" start="0x1" description="Ethernet Receive Data (MII interface)." />
-        <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." />
-        <Enum name="PWM0_CAP0" start="0x3" description="Capture input for PWM0, channel 0." />
-        <Enum name="CMP1_OUT" start="0x5" description="Comparator 1, output." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xB4" size="4" name="P1_13" access="Read/Write" description="I/O configuration register for pin P1[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[13]">
-        <Enum name="P1_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RX_DV" start="0x1" description="Ethernet Receive Data Valid (MII interface)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xB8" size="4" name="P1_14" access="Read/Write" description="I/O configuration register for pin P1[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[14]">
-        <Enum name="P1_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RX_ER" start="0x1" description="Ethernet receive error (RMII/MII interface)." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-        <Enum name="CMP0_IN_0" start="0x5" description="Comparator 0, input 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xBC" size="4" name="P1_15" access="Read/Write" description="I/O configuration register for pin P1[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[15]">
-        <Enum name="P1_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RX_CLK_REF_CLK" start="0x1" description="Ethernet Receive Clock (MII interface) or Ethernet                                     Reference Clock (RMII interface)." />
-        <Enum name="I2C2_SDA" start="0x3" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC0" size="4" name="P1_16" access="Read/Write" description="I/O configuration register for pin P1[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[16]">
-        <Enum name="P1_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_MDC" start="0x1" description="Ethernet MIIM clock." />
-        <Enum name="I2S_TX_MCLK" start="0x2" description="I2S transmit master clock." />
-        <Enum name="CMP0_IN_1" start="0x5" description="Comparator 0, input 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC4" size="4" name="P1_17" access="Read/Write" description="I/O configuration register for pin P1[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[17]">
-        <Enum name="P1_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_MDIO" start="0x1" description="Ethernet MIIM data input and output." />
-        <Enum name="I2S_RX_MCLK" start="0x2" description="I2S receive master clock." />
-        <Enum name="CMP0_IN_2" start="0x5" description="Comparator 0, input 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC8" size="4" name="P1_18" access="Read/Write" description="I/O configuration register for pin P1[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[18]">
-        <Enum name="P1_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_UP_LED1" start="0x1" description="It is LOW when the device is configured (non-control                                     endpoints enabled), or when the host is enabled and has detected                                     a device on the bus. It is HIGH when the device is not                                     configured, or when host is enabled and has not detected a                                     device on the bus, or during global suspend. It transitions                                     between LOW and HIGH (flashes) when the host is enabled and                                     detects activity on the bus." />
-        <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, channel 1 output." />
-        <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." />
-        <Enum name="SSP1_MISO" start="0x5" description="Master In Slave Out for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xCC" size="4" name="P1_19" access="Read/Write" description="I/O configuration register for pin P1[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[19]">
-        <Enum name="P1_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_TX_E1" start="0x1" description="Transmit Enable signal for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="USB_PPWR1" start="0x2" description="Port Power enable signal for USB port 1." />
-        <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." />
-        <Enum name="MC_0A" start="0x4" description="Motor control PWM channel 0, output A." />
-        <Enum name="SSP1_SCK" start="0x5" description="Serial clock for SSP1." />
-        <Enum name="U2_OE" start="0x6" description="RS-485/EIA-485 output enable signal for                                     UART2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xD0" size="4" name="P1_20" access="Read/Write" description="I/O configuration register for pin P1[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[20]">
-        <Enum name="P1_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_TX_DP1" start="0x1" description="D+ transmit data for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, channel 2 output." />
-        <Enum name="QEI_PHA" start="0x3" description="Quadrature Encoder Interface PHA input." />
-        <Enum name="MC_FB0" start="0x4" description="Motor control PWM channel 0 feedback input." />
-        <Enum name="SSP0_SCK" start="0x5" description="Serial clock for SSP0." />
-        <Enum name="LCD_VD_6" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_10" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xD4" size="4" name="P1_21" access="Read/Write" description="I/O configuration register for pin P1[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[21]">
-        <Enum name="P1_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_TX_DM1" start="0x1" description="D- transmit data for USB port                                     1 (OTG transceiver)." />
-        <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, channel 3 output." />
-        <Enum name="SSP0_SSEL" start="0x3" description="Slave Select for SSP0." />
-        <Enum name="MC_ABORT" start="0x4" description="Motor control PWM, active low fast abort." />
-        <Enum name="LCD_VD_7" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_11" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xD8" size="4" name="P1_22" access="Read/Write" description="I/O configuration register for pin P1[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[22]">
-        <Enum name="P1_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_RCV1" start="0x1" description="Differential receive data for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="USB_PWRD1" start="0x2" description="Power Status for USB port 1 (host power                                     switch)." />
-        <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." />
-        <Enum name="MC_0B" start="0x4" description="Motor control PWM channel 0, output B." />
-        <Enum name="SSP1_MOSI" start="0x5" description="Master Out Slave In for SSP1." />
-        <Enum name="LCD_VD_8" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_12" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xDC" size="4" name="P1_23" access="Read/Write" description="I/O configuration register for pin P1[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[23]">
-        <Enum name="P1_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_RX_DP1" start="0x1" description="D+ receive data for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, channel 4 output." />
-        <Enum name="QEI_PHB" start="0x3" description="Quadrature Encoder Interface PHB input." />
-        <Enum name="MC_FB1" start="0x4" description="Motor control PWM channel 1 feedback input." />
-        <Enum name="SSP0_MISO" start="0x5" description="Master In Slave Out for SSP0." />
-        <Enum name="LCD_VD_9" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_13" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xE0" size="4" name="P1_24" access="Read/Write" description="I/O configuration register for pin P1[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[24]">
-        <Enum name="P1_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_RX_DM1" start="0x1" description="D- receive data for USB port 1                                     (OTG transceiver)." />
-        <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, channel 5 output." />
-        <Enum name="QEI_IDX" start="0x3" description="Quadrature Encoder Interface INDEX input." />
-        <Enum name="MC_FB2" start="0x4" description="Motor control PWM channel 2 feedback input." />
-        <Enum name="SSP0_MOSI" start="0x5" description="Master Out Slave in for SSP0." />
-        <Enum name="LCD_VD_10" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_14" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xE4" size="4" name="P1_25" access="Read/Write" description="I/O configuration register for pin P1[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[25]">
-        <Enum name="P1_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_LS1" start="0x1" description="Low Speed status for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="USB_HSTEN1" start="0x2" description="Host Enabled status for USB port 1." />
-        <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." />
-        <Enum name="MC_1A" start="0x4" description="Motor control PWM channel 1, output A." />
-        <Enum name="CLKOUT" start="0x5" description="Selectable clock output." />
-        <Enum name="LCD_VD_11" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_15" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xE8" size="4" name="P1_26" access="Read/Write" description="I/O configuration register for pin P1[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[26]">
-        <Enum name="P1_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_SSPND1" start="0x1" description="USB port 1 Bus Suspend status (OTG                                     transceiver)." />
-        <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, channel 6 output." />
-        <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." />
-        <Enum name="MC_1B" start="0x4" description="Motor control PWM channel 1, output B." />
-        <Enum name="SSP1_SSEL" start="0x5" description="Slave Select for SSP1." />
-        <Enum name="LCD_VD_12" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_20" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xEC" size="4" name="P1_27" access="Read/Write" description="I/O configuration register for pin P1[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[27]">
-        <Enum name="P1_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_INT1" start="0x1" description="USB port 1 OTG transceiver interrupt (OTG                                     transceiver)." />
-        <Enum name="USB_OVRCR1" start="0x2" description="USB port 1 Over-Current status." />
-        <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." />
-        <Enum name="CLKOUT" start="0x4" description="Selectable clock output." />
-        <Enum name="LCD_VD_13" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_21" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xF0" size="4" name="P1_28" access="Read/Write" description="I/O configuration register for pin P1[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[28]">
-        <Enum name="P1_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_SCL1" start="0x1" description="USB port 1 I2C serial clock                                     (OTG transceiver)." />
-        <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." />
-        <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." />
-        <Enum name="MC_2A" start="0x4" description="Motor control PWM channel 2, output A." />
-        <Enum name="SSP0_SSEL" start="0x5" description="Slave Select for SSP0." />
-        <Enum name="LCD_VD_14" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_22" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xF4" size="4" name="P1_29" access="Read/Write" description="I/O configuration register for pin P1[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[29]">
-        <Enum name="P1_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_SDA1" start="0x1" description="USB port 1 I2C serial data                                     (OTG transceiver)." />
-        <Enum name="PWM1_CAP1" start="0x2" description="Capture input for PWM1, channel 1." />
-        <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." />
-        <Enum name="MC_2B" start="0x4" description="Motor control PWM channel 2, output B." />
-        <Enum name="U4_TXD" start="0x5" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
-        <Enum name="LCD_VD_15" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_23" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xF8" size="4" name="P1_30" access="Read/Write" description="I/O configuration register for pin P1[30]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[30]">
-        <Enum name="P1_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_PWRD2" start="0x1" description="Power Status for USB port 2." />
-        <Enum name="USB_VBUS" start="0x2" description="Monitors the presence of USB bus power.This signal must be HIGH for USB reset to                                     occur." />
-        <Enum name="ADC0_IN_4" start="0x3" description="A/D converter 0, input 4. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2C0_SDA" start="0x4" description="I2C0 data input/output (this                                     pin does not use a specialized I2C pad." />
-        <Enum name="U3_OE" start="0x5" description="RS-485/EIA-485 output enable signal for                                     UART3." />
-      </BitField>
-    </Register>
-    <Register start="+0xFC" size="4" name="P1_31" access="Read/Write" description="I/O configuration register for pin P1[31]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[31]">
-        <Enum name="P1_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_OVRCR2" start="0x1" description="Over-Current status for USB port 2." />
-        <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." />
-        <Enum name="ADC0_IN_5" start="0x3" description="A/D converter 0, input 5. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2C0_SCL" start="0x4" description="I2C0 clock input/output (this                                     pin does not use a specialized I2C pad." />
-      </BitField>
-    </Register>
-    <Register start="+0x100" size="4" name="P2_0" access="Read/Write" description="I/O configuration register for pin P2[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[0]">
-        <Enum name="P2_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_1" start="0x1" description="Pulse Width Modulator 1, channel 1 output." />
-        <Enum name="U1_TXD" start="0x2" description="Transmitter output for UART1." />
-        <Enum name="LCD_PWR" start="0x7" description="LCD panel power enable." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="P2_1" access="Read/Write" description="I/O configuration register for pin P2[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[1]">
-        <Enum name="P2_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_2" start="0x1" description="Pulse Width Modulator 1, channel 2 output." />
-        <Enum name="U1_RXD" start="0x2" description="Receiver input for UART1." />
-        <Enum name="LCD_LE" start="0x7" description="Line end signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x108" size="4" name="P2_2" access="Read/Write" description="I/O configuration register for pin P2[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[2]">
-        <Enum name="P2_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_3" start="0x1" description="Pulse Width Modulator 1, channel 3 output." />
-        <Enum name="U1_CTS" start="0x2" description="Clear to Send input for UART1." />
-        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
-        <Enum name="TRACEDATA_3" start="0x5" description="Trace data, bit 3." />
-        <Enum name="LCD_DCLK" start="0x7" description="LCD panel clock." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x10C" size="4" name="P2_3" access="Read/Write" description="I/O configuration register for pin P2[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[3]">
-        <Enum name="P2_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_4" start="0x1" description="Pulse Width Modulator 1, channel 4 output." />
-        <Enum name="U1_DCD" start="0x2" description="Data Carrier Detect input for UART1." />
-        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
-        <Enum name="TRACEDATA_2" start="0x5" description="Trace data, bit 2." />
-        <Enum name="LCD_FP" start="0x7" description="Frame pulse (STN). Vertical synchronization pulse                                     (TFT)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x110" size="4" name="P2_4" access="Read/Write" description="I/O configuration register for pin P2[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[4]">
-        <Enum name="P2_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_5" start="0x1" description="Pulse Width Modulator 1, channel 5 output." />
-        <Enum name="U1_DSR" start="0x2" description="Data Set Ready input for UART1." />
-        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
-        <Enum name="TRACEDATA_1" start="0x5" description="Trace data, bit 1." />
-        <Enum name="LCD_ENAB_M" start="0x7" description="STN AC bias drive or TFT data enable output." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x114" size="4" name="P2_5" access="Read/Write" description="I/O configuration register for pin P2[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[5]">
-        <Enum name="P2_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_6" start="0x1" description="Pulse Width Modulator 1, channel 6 output." />
-        <Enum name="U1_DTR" start="0x2" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
-        <Enum name="TRACEDATA_0" start="0x5" description="Trace data, bit 0." />
-        <Enum name="LCD_LP" start="0x7" description="Line synchronization pulse (STN). Horizontal                                     synchronization pulse (TFT)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x118" size="4" name="P2_6" access="Read/Write" description="I/O configuration register for pin P2[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[6]">
-        <Enum name="P2_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_CAP0" start="0x1" description="Capture input for PWM1, channel 0." />
-        <Enum name="U1_RI" start="0x2" description="Ring Indicator input for UART1." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-        <Enum name="U2_OE" start="0x4" description="RS-485/EIA-485 output enable signal for                                     UART2." />
-        <Enum name="TRACECLK" start="0x5" description="Trace clock." />
-        <Enum name="LCD_VD_0" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_4" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="P2_7" access="Read/Write" description="I/O configuration register for pin P2[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[7]">
-        <Enum name="P2_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_RD2" start="0x1" description="CAN2 receiver input." />
-        <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="SPIFI_CS" start="0x5" description="Chip select output for SPIFI." />
-        <Enum name="LCD_VD_1" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_5" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x120" size="4" name="P2_8" access="Read/Write" description="I/O configuration register for pin P2[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[8]">
-        <Enum name="P2_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_TD2" start="0x1" description="CAN2 transmitter output." />
-        <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." />
-        <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." />
-        <Enum name="ENET_MDC" start="0x4" description="Ethernet MIIM clock." />
-        <Enum name="LCD_VD_2" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_6" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x124" size="4" name="P2_9" access="Read/Write" description="I/O configuration register for pin P2[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[9]">
-        <Enum name="P2_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_CONNECT1" start="0x1" description="USB1 SoftConnect control. Signal used to switch an                                     external 1.5 kW resistor under the                                     software control. Used with the SoftConnect USB                                     feature." />
-        <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." />
-        <Enum name="U4_RXD" start="0x3" description="Receiver input for USART4." />
-        <Enum name="ENET_MDIO" start="0x4" description="Ethernet MIIM data input and output." />
-        <Enum name="LCD_VD_3" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_7" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x128" size="4" name="P2_10" access="Read/Write" description="I/O configuration register for pin P2[10]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[10]">
-        <Enum name="P2_10" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter.A LOW on this pin while RESET is LOW forces the on-chip&#xa;                                    boot loader to take over control of the part after a reset and&#xa;                                    go into ISP mode. " />
-        <Enum name="EINT0" start="0x1" description="External interrupt 0 input." />
-        <Enum name="NMI" start="0x2" description="Non-maskable interrupt input." />
-      </BitField>
-    </Register>
-    <Register start="+0x12C" size="4" name="P2_11" access="Read/Write" description="I/O configuration register for pin P2[11]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[11]">
-        <Enum name="P2_11" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
-        <Enum name="EINT1" start="0x1" description="External interrupt 1 input." />
-        <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." />
-        <Enum name="I2S_TX_SCK" start="0x3" description="Transmit Clock. It is driven by the master and received                                     by the slave. Corresponds to the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="LCD_CLKIN" start="0x7" description="LCD clock." />
-      </BitField>
-    </Register>
-    <Register start="+0x130" size="4" name="P2_12" access="Read/Write" description="I/O configuration register for pin P2[12]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[12]">
-        <Enum name="P2_12" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
-        <Enum name="EINT2" start="0x1" description="External interrupt 2 input." />
-        <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." />
-        <Enum name="I2S_TX_WS" start="0x3" description="Transmit Word Select. It is driven by the master and                                     received by the slave. Corresponds to the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="LCD_VD_4" start="0x4" description="LCD data." />
-        <Enum name="LCD_VD_3" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_8" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_18" start="0x7" description="LCD data." />
-      </BitField>
-    </Register>
-    <Register start="+0x134" size="4" name="P2_13" access="Read/Write" description="I/O configuration register for pin P2[13]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[13]">
-        <Enum name="P2_13" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
-        <Enum name="EINT3" start="0x1" description="External interrupt 3 input." />
-        <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." />
-        <Enum name="I2S_TX_SDA" start="0x3" description="Transmit data. It is driven by the transmitter and read                                     by the receiver. Corresponds to the signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="LCD_VD_5" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_9" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_19" start="0x7" description="LCD data." />
-      </BitField>
-    </Register>
-    <Register start="+0x138" size="4" name="P2_14" access="Read/Write" description="I/O configuration register for pin P2[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[14]">
-        <Enum name="P2_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS2" start="0x1" description="LOW active Chip Select 2 signal." />
-        <Enum name="I2C1_SDA" start="0x2" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x13C" size="4" name="P2_15" access="Read/Write" description="I/O configuration register for pin P2[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[15]">
-        <Enum name="P2_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS3" start="0x1" description="LOW active Chip Select 3 signal." />
-        <Enum name="I2C1_SCL" start="0x2" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140" size="4" name="P2_16" access="Read/Write" description="I/O configuration register for pin P2[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[16]">
-        <Enum name="P2_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CAS" start="0x1" description="LOW active SDRAM Column Address Strobe." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x144" size="4" name="P2_17" access="Read/Write" description="I/O configuration register for pin P2[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[17]">
-        <Enum name="P2_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_RAS" start="0x1" description="LOW active SDRAM Row Address Strobe." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="P2_18" access="Read/Write" description="I/O configuration register for pin P2[18]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[18]">
-        <Enum name="P2_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CLK_0" start="0x1" description="SDRAM clock 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x14C" size="4" name="P2_19" access="Read/Write" description="I/O configuration register for pin P2[19]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[19]">
-        <Enum name="P2_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CLK_1" start="0x1" description="SDRAM clock 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x150" size="4" name="P2_20" access="Read/Write" description="I/O configuration register for pin P2[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[20]">
-        <Enum name="P2_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS0" start="0x1" description="SDRAM chip select 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x154" size="4" name="P2_21" access="Read/Write" description="I/O configuration register for pin P2[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[21]">
-        <Enum name="P2_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS1" start="0x1" description="SDRAM chip select 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x158" size="4" name="P2_22" access="Read/Write" description="I/O configuration register for pin P2[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[22]">
-        <Enum name="P2_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS2" start="0x1" description="SDRAM chip select 2." />
-        <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." />
-        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x15C" size="4" name="P2_23" access="Read/Write" description="I/O configuration register for pin P2[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[23]">
-        <Enum name="P2_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS3" start="0x1" description="SDRAM chip select 3." />
-        <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." />
-        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="P2_24" access="Read/Write" description="I/O configuration register for pin P2[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[24]">
-        <Enum name="P2_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE0" start="0x1" description="SDRAM clock enable 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="P2_25" access="Read/Write" description="I/O configuration register for pin P2[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[25]">
-        <Enum name="P2_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE1" start="0x1" description="SDRAM clock enable 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x168" size="4" name="P2_26" access="Read/Write" description="I/O configuration register for pin P2[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[26]">
-        <Enum name="P2_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE2" start="0x1" description="SDRAM clock enable 2." />
-        <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." />
-        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x16C" size="4" name="P2_27" access="Read/Write" description="I/O configuration register for pin P2[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[27]">
-        <Enum name="P2_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE3" start="0x1" description="SDRAM clock enable 3." />
-        <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." />
-        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x170" size="4" name="P2_28" access="Read/Write" description="I/O configuration register for pin P2[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[28]">
-        <Enum name="P2_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM0" start="0x1" description="Data mask 0 used with SDRAM and static                                     devices." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x174" size="4" name="P2_29" access="Read/Write" description="I/O configuration register for pin P2[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[29]">
-        <Enum name="P2_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM1" start="0x1" description="Data mask 1 used with SDRAM and static                                     devices." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x178" size="4" name="P2_30" access="Read/Write" description="I/O configuration register for pin P2[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[30]">
-        <Enum name="P2_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM2" start="0x1" description="Data mask 2 used with SDRAM and static                                     devices." />
-        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x17C" size="4" name="P2_31" access="Read/Write" description="I/O configuration register for pin P2[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[31]">
-        <Enum name="P2_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM3" start="0x1" description="Data mask 3 used with SDRAM and static                                     devices." />
-        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x180" size="4" name="P3_0" access="Read/Write" description="I/O configuration register for pin P3[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[0]">
-        <Enum name="P3_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_0" start="0x1" description="External memory data line 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x184" size="4" name="P3_1" access="Read/Write" description="I/O configuration register for pin P3[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[1]">
-        <Enum name="P3_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_1" start="0x1" description="External memory data line 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x188" size="4" name="P3_2" access="Read/Write" description="I/O configuration register for pin P3[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[2]">
-        <Enum name="P3_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_2" start="0x1" description="External memory data line 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x18C" size="4" name="P3_3" access="Read/Write" description="I/O configuration register for pin P3[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[3]">
-        <Enum name="P3_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_3" start="0x1" description="External memory data line 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x190" size="4" name="P3_4" access="Read/Write" description="I/O configuration register for pin P3[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[4]">
-        <Enum name="P3_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_4" start="0x1" description="External memory data line 4." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x194" size="4" name="P3_5" access="Read/Write" description="I/O configuration register for pin P3[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[5]">
-        <Enum name="P3_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_5" start="0x1" description="External memory data line 5." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x198" size="4" name="P3_6" access="Read/Write" description="I/O configuration register for pin P3[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[6]">
-        <Enum name="P3_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_6" start="0x1" description="External memory data line 6." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x19C" size="4" name="P3_7" access="Read/Write" description="I/O configuration register for pin P3[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[7]">
-        <Enum name="P3_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_7" start="0x1" description="External memory data line 7." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="P3_8" access="Read/Write" description="I/O configuration register for pin P3[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[8]">
-        <Enum name="P3_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_8" start="0x1" description="External memory data line 8." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1A4" size="4" name="P3_9" access="Read/Write" description="I/O configuration register for pin P3[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[9]">
-        <Enum name="P3_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_9" start="0x1" description="External memory data line 9." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="P3_10" access="Read/Write" description="I/O configuration register for pin P3[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[10]">
-        <Enum name="P3_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_10" start="0x1" description="External memory data line 10." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1AC" size="4" name="P3_11" access="Read/Write" description="I/O configuration register for pin P3[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[11]">
-        <Enum name="P3_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_11" start="0x1" description="External memory data line 11." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1B0" size="4" name="P3_12" access="Read/Write" description="I/O configuration register for pin P3[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[12]">
-        <Enum name="P3_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_12" start="0x1" description="External memory data line 12." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1B4" size="4" name="P3_13" access="Read/Write" description="I/O configuration register for pin P3[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[13]">
-        <Enum name="P3_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_13" start="0x1" description="External memory data line 13." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1B8" size="4" name="P3_14" access="Read/Write" description="I/O configuration register for pin P3[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[14]">
-        <Enum name="P3_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_14" start="0x1" description="External memory data line 14. " />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1BC" size="4" name="P3_15" access="Read/Write" description="I/O configuration register for pin P3[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[15]">
-        <Enum name="P3_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_15" start="0x1" description="External memory data line 15. " />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C0" size="4" name="P3_16" access="Read/Write" description="I/O configuration register for pin P3[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[16]">
-        <Enum name="P3_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_16" start="0x1" description="External memory data line 16." />
-        <Enum name="PWM0_1" start="0x2" description="Pulse Width Modulator 0, output 1." />
-        <Enum name="U1_TXD" start="0x3" description="Transmitter output for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="P3_17" access="Read/Write" description="I/O configuration register for pin P3[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[17]">
-        <Enum name="P3_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_17" start="0x1" description="External memory data line 17." />
-        <Enum name="PWM0_2" start="0x2" description="Pulse Width Modulator 0, output 2." />
-        <Enum name="U1_RXD" start="0x3" description="Receiver input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="P3_18" access="Read/Write" description="I/O configuration register for pin P3[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[18]">
-        <Enum name="P3_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_18" start="0x1" description="External memory data line 18." />
-        <Enum name="PWM0_3" start="0x2" description="Pulse Width Modulator 0, output 3." />
-        <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1CC" size="4" name="P3_19" access="Read/Write" description="I/O configuration register for pin P3[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[19]">
-        <Enum name="P3_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_19" start="0x1" description="External memory data line 19." />
-        <Enum name="PWM0_4" start="0x2" description="Pulse Width Modulator 0, output 4." />
-        <Enum name="U1_DCD" start="0x3" description="Data Carrier Detect input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1D0" size="4" name="P3_20" access="Read/Write" description="I/O configuration register for pin P3[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[20]">
-        <Enum name="P3_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_20" start="0x1" description="External memory data line 20." />
-        <Enum name="PWM0_5" start="0x2" description="Pulse Width Modulator 0, output 5." />
-        <Enum name="U1_DSR" start="0x3" description="Data Set Ready input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1D4" size="4" name="P3_21" access="Read/Write" description="I/O configuration register for pin P3[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[21]">
-        <Enum name="P3_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_21" start="0x1" description="External memory data line 21." />
-        <Enum name="PWM0_6" start="0x2" description="Pulse Width Modulator 0, output 6." />
-        <Enum name="U1_DTR" start="0x3" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1D8" size="4" name="P3_22" access="Read/Write" description="I/O configuration register for pin P3[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[22]">
-        <Enum name="P3_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_22" start="0x1" description="External memory data line 22." />
-        <Enum name="PWM0_CAP0" start="0x2" description="Capture input for PWM0, channel 0." />
-        <Enum name="U1_RI" start="0x3" description="Ring Indicator input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1DC" size="4" name="P3_23" access="Read/Write" description="I/O configuration register for pin P3[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[23]">
-        <Enum name="P3_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_23" start="0x1" description="External memory data line 23." />
-        <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." />
-        <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1E0" size="4" name="P3_24" access="Read/Write" description="I/O configuration register for pin P3[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[24]">
-        <Enum name="P3_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_24" start="0x1" description="External memory data line 24." />
-        <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, output 1." />
-        <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1E4" size="4" name="P3_25" access="Read/Write" description="I/O configuration register for pin P3[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[25]">
-        <Enum name="P3_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_25" start="0x1" description="External memory data line 25." />
-        <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, output 2." />
-        <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1E8" size="4" name="P3_26" access="Read/Write" description="I/O configuration register for pin P3[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[26]">
-        <Enum name="P3_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_26" start="0x1" description="External memory data line 26." />
-        <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, output 3." />
-        <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." />
-        <Enum name="STCLK" start="0x4" description="System tick timer clock input." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1EC" size="4" name="P3_27" access="Read/Write" description="I/O configuration register for pin P3[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[27]">
-        <Enum name="P3_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_27" start="0x1" description="External memory data line 27." />
-        <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, output 4." />
-        <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1F0" size="4" name="P3_28" access="Read/Write" description="I/O configuration register for pin P3[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[28]">
-        <Enum name="P3_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_28" start="0x1" description="External memory data line 28." />
-        <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, output 5." />
-        <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1F4" size="4" name="P3_29" access="Read/Write" description="I/O configuration register for pin P3[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[29]">
-        <Enum name="P3_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_29" start="0x1" description="External memory data line 29." />
-        <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, output 6." />
-        <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1F8" size="4" name="P3_30" access="Read/Write" description="I/O configuration register for pin P3[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[30]">
-        <Enum name="P3_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_30" start="0x1" description="External memory data line 30." />
-        <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1FC" size="4" name="P3_31" access="Read/Write" description="I/O configuration register for pin P3[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[31]">
-        <Enum name="P3_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_31" start="0x1" description="External memory data line 31." />
-        <Enum name="T1_MAT2" start="0x3" description="Match output for Timer 1, channel 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="P4_0" access="Read/Write" description="I/O configuration register for pin P4[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[0]">
-        <Enum name="P4_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_0" start="0x1" description="External memory address line 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x204" size="4" name="P4_1" access="Read/Write" description="I/O configuration register for pin P4[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[1]">
-        <Enum name="P4_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_1" start="0x1" description="External memory address line 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x208" size="4" name="P4_2" access="Read/Write" description="I/O configuration register for pin P4[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[2]">
-        <Enum name="P4_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_2" start="0x1" description="External memory address line 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x20C" size="4" name="P4_3" access="Read/Write" description="I/O configuration register for pin P4[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[3]">
-        <Enum name="P4_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_3" start="0x1" description="External memory address line 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x210" size="4" name="P4_4" access="Read/Write" description="I/O configuration register for pin P4[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[4]">
-        <Enum name="P4_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_4" start="0x1" description="External memory address line 4." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x214" size="4" name="P4_5" access="Read/Write" description="I/O configuration register for pin P4[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[5]">
-        <Enum name="P4_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_5" start="0x1" description="External memory address line 5." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x218" size="4" name="P4_6" access="Read/Write" description="I/O configuration register for pin P4[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[6]">
-        <Enum name="P4_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_6" start="0x1" description="External memory address line 6." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x21C" size="4" name="P4_7" access="Read/Write" description="I/O configuration register for pin P4[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[7]">
-        <Enum name="P4_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_7" start="0x1" description="External memory address line 7." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x220" size="4" name="P4_8" access="Read/Write" description="I/O configuration register for pin P4[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[8]">
-        <Enum name="P4_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_8" start="0x1" description="External memory address line 8." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x224" size="4" name="P4_9" access="Read/Write" description="I/O configuration register for pin P4[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[9]">
-        <Enum name="P4_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_9" start="0x1" description="External memory address line 9." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x228" size="4" name="P4_10" access="Read/Write" description="I/O configuration register for pin P4[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[10]">
-        <Enum name="P4_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_10" start="0x1" description="External memory address line 10." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x22C" size="4" name="P4_11" access="Read/Write" description="I/O configuration register for pin P4[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[11]">
-        <Enum name="P4_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_11" start="0x1" description="External memory address line 11." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x230" size="4" name="P4_12" access="Read/Write" description="I/O configuration register for pin P4[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[12]">
-        <Enum name="P4_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_12" start="0x1" description="External memory address line 12." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x234" size="4" name="P4_13" access="Read/Write" description="I/O configuration register for pin P4[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[13]">
-        <Enum name="P4_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_13" start="0x1" description="External memory address line 13." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x238" size="4" name="P4_14" access="Read/Write" description="I/O configuration register for pin P4[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[14]">
-        <Enum name="P4_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_14" start="0x1" description="External memory address line 14." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x23C" size="4" name="P4_15" access="Read/Write" description="I/O configuration register for pin P4[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[15]">
-        <Enum name="P4_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_15" start="0x1" description="External memory address line 15." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240" size="4" name="P4_16" access="Read/Write" description="I/O configuration register for pin P4[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[16]">
-        <Enum name="P4_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_16" start="0x1" description="External memory address line 16." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x244" size="4" name="P4_17" access="Read/Write" description="I/O configuration register for pin P4[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[17]">
-        <Enum name="P4_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_17" start="0x1" description="External memory address line 17." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x248" size="4" name="P4_18" access="Read/Write" description="I/O configuration register for pin P4[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[18]">
-        <Enum name="P4_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_18" start="0x1" description="External memory address line 18." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x24C" size="4" name="P4_19" access="Read/Write" description="I/O configuration register for pin P4[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[19]">
-        <Enum name="P4_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_19" start="0x1" description="External memory address line 19." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x250" size="4" name="P4_20" access="Read/Write" description="I/O configuration register for pin P4[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[20]">
-        <Enum name="P4_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_20" start="0x1" description="External memory address line 20." />
-        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="SSP1_SCK" start="0x3" description="Serial Clock for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x254" size="4" name="P4_21" access="Read/Write" description="I/O configuration register for pin P4[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[21]">
-        <Enum name="P4_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_21" start="0x1" description="External memory address line 21." />
-        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="SSP1_SSEL" start="0x3" description="Slave Select for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x258" size="4" name="P4_22" access="Read/Write" description="I/O configuration register for pin P4[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[22]">
-        <Enum name="P4_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_22" start="0x1" description="External memory address line 22." />
-        <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." />
-        <Enum name="SSP1_MISO" start="0x3" description="Master In Slave Out for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x25C" size="4" name="P4_23" access="Read/Write" description="I/O configuration register for pin P4[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[23]">
-        <Enum name="P4_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_23" start="0x1" description="External memory address line 23." />
-        <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." />
-        <Enum name="SSP1_MOSI" start="0x3" description="Master Out Slave In for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x260" size="4" name="P4_24" access="Read/Write" description="I/O configuration register for pin P4[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[24]">
-        <Enum name="P4_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_OE" start="0x1" description="LOW active Output Enable signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x264" size="4" name="P4_25" access="Read/Write" description="I/O configuration register for pin P4[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[25]">
-        <Enum name="P4_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_WE" start="0x1" description="LOW active Write Enable signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x268" size="4" name="P4_26" access="Read/Write" description="I/O configuration register for pin P4[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[26]">
-        <Enum name="P4_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS0" start="0x1" description="LOW active Byte Lane select signal 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x26C" size="4" name="P4_27" access="Read/Write" description="I/O configuration register for pin P4[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[27]">
-        <Enum name="P4_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS1" start="0x1" description="LOW active Byte Lane select signal 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x270" size="4" name="P4_28" access="Read/Write" description="I/O configuration register for pin P4[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[28]">
-        <Enum name="P4_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS2" start="0x1" description="LOW active Byte Lane select signal 2." />
-        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
-        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
-        <Enum name="LCD_VD_6" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_10" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_2" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x274" size="4" name="P4_29" access="Read/Write" description="I/O configuration register for pin P4[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[29]">
-        <Enum name="P4_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS3" start="0x1" description="LOW active Byte Lane select signal 3." />
-        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
-        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
-        <Enum name="I2C2_SCL" start="0x4" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="LCD_VD_7" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_11" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_3" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x278" size="4" name="P4_30" access="Read/Write" description="I/O configuration register for pin P4[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[30]">
-        <Enum name="P4_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS0" start="0x1" description="LOW active Chip Select 0 signal." />
-        <Enum name="CMP0_OUT" start="0x5" description="Comparator 0, output." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x27C" size="4" name="P4_31" access="Read/Write" description="I/O configuration register for pin P4[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[31]">
-        <Enum name="P4_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS1" start="0x1" description="LOW active Chip Select 1 signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x280" size="4" name="P5_0" access="Read/Write" description="I/O configuration register for pin P5[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[0]">
-        <Enum name="P5_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_24" start="0x1" description="External memory address line 24." />
-        <Enum name="SSP2_MOSI" start="0x2" description="Master Out Slave In for SSP2." />
-        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x284" size="4" name="P5_1" access="Read/Write" description="I/O configuration register for pin P5[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[1]">
-        <Enum name="P5_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_25" start="0x1" description="External memory address line 25." />
-        <Enum name="SSP2_MISO" start="0x2" description="Master In Slave Out for SSP2." />
-        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x288" size="4" name="P5_2" access="Read/Write" description="I/O configuration register for pin P5[2]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[2]">
-        <Enum name="P5_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
-        <Enum name="I2C0_SDA" start="0x5" description="I2C0 data input/output (this                                     pin uses a specialized I2C pad that                                     supports I2C Fast Mode                                     Plus)." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x28C" size="4" name="P5_3" access="Read/Write" description="I/O configuration register for pin P5[3]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[3]">
-        <Enum name="P5_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U4_RXD" start="0x4" description="Receiver input for USART4." />
-        <Enum name="I2C0_SCL" start="0x5" description="I2C0 clock input/output (this                                     pin uses a specialized I2C pad that                                     supports I2C Fast Mode                                     Plus." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x290" size="4" name="P5_4" access="Read/Write" description="I/O configuration register for pin P5[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[4]">
-        <Enum name="P5_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U0_OE" start="0x1" description="RS-485/EIA-485 output enable signal for                                     UART0." />
-        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
-        <Enum name="U4_TXD" start="0x4" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC)">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
-        <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
-      </BitField>
-      <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="21" size="1" name="PDN" description="Power down mode">
-        <Enum name="POWERED" start="1" description="The A/D converter is operational." />
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
-        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
-        <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
-        <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
-        <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
-        <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
-        <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
-        <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
-      </BitField>
-      <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
-        <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
-        <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
-      <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
-      <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
-      <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
-      <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
-      <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
-      <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
-      <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
-      <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
-      <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
-      <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
-      <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
-      <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
-      <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
-      <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
-      <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
-      <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
-    <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAF" start="0x4003C000" description="CAN controller">
-    <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
-      <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
-      <BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
-        <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
-        <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
-    </Register>
-    <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCAN" start="0x40040000" description=" CAN controller">
-    <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
-      <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
-      <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
-      <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
-      <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
-      <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
-      <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN1" start="0x40044000" description="CAN controller  ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN2" start="0x40048000" description="CAN controller  ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x4008C000" description="Digital-to-Analog Converter (DAC) Modification">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
-        <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
-        <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
-        <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
-        <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA access">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x40090000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x40094000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART4" start="0x400A4000" description="UART4  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART4 Receiver Buffer Register contains the oldest received byte in the UART4 Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART4 Transmit Holding Register causes the data to be stored in the UART4 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART4 Divisor Latch LSB Register, along with the U4DLM register, determines the baud rate of the UART4." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART4 Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART4." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that U4IIR[0] is active low. The pending interrupt can be determined by evaluating U4IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. U4IER[3:1] identifies an interrupt corresponding to the UART4 Rx or TX FIFO. All other combinations of U4IER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of U4FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="THE_UARTN_RECEIVER_F" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="THE_UARTN_RECEIVER_F" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="OVERRUN_ERROR_STATUS" start="0" description="Overrun error status is inactive." />
-        <Enum name="OVERRUN_ERROR_STATUS" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="PARITY_ERROR_STATUS_" start="0" description="Parity error status is inactive." />
-        <Enum name="PARITY_ERROR_STATUS_" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="FRAMING_ERROR_STATUS" start="0" description="Framing error status is inactive." />
-        <Enum name="FRAMING_ERROR_STATUS" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="UNTHR_CONTAINS_VALID" start="0" description="UnTHR contains valid data." />
-        <Enum name="UNTHR_IS_EMPTY_" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALID_DATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="UNRBR_CONTAINS_NO_UA" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="UARTN_RBR_CONTAINS_A" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode">
-        <Enum name="DISABLED_IRDA_MODE_" start="0" description="Disabled. IrDA mode on UART4 is disabled, UART4 acts as a standard UART." />
-        <Enum name="ENABLED_IRDA_MODE_O" start="1" description="Enabled. IrDA mode on UART4 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED_" start="0" description="Not inverted." />
-        <Enum name="INVERTED_THIS_HAS_N" start="1" description="Inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1.">
-        <Enum name="2XTPCLK" start="0x0" description="2xTPCLK" />
-        <Enum name="4XTPCLK" start="0x1" description="4xTPCLK" />
-        <Enum name="8XTPCLK" start="0x2" description="8xTPCLK" />
-        <Enum name="16XTPCLK" start="0x3" description="16xTPCLK" />
-        <Enum name="32XTPCLK" start="0x4" description="32xTPCLK" />
-        <Enum name="64XTPCLK" start="0x5" description="64xTPCLK" />
-        <Enum name="128XTPCLK" start="0x6" description="128xTPCLK" />
-        <Enum name="256XTPCLK" start="0x7" description="256xTPCLK" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud Rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART4 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud Rate pre-scaler multiplier value. This field must be greater or equal 1 for UART4 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In smartcard mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface control register. Enables and configures the smartcard Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
-        <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="A_NACK_RESPONSE_IS_E" start="0" description="A NACK response is enabled." />
-        <Enum name="A_NACK_RESPONSE_IS_I" start="1" description="A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. See Section 20.6.18 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (U4OE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
-        <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Falling edge sampling.">
-        <Enum name="RXD_IS_SAMPLED_ON_TH" start="0" description="RxD is sampled on the rising edge of SCLK" />
-        <Enum name="RXD_IS_SAMPLED_ON_TH" start="1" description="RxD is sampled on the falling edge of SCLK" />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="THE_INPUT_CLOCK_IS_S" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="THE_INPUT_CLOCK_IS_N" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
-        <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." />
-        <Enum name="NOSTARTSTOPBIT" start="1" description="Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
-        <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI)  ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on PHA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay for PhA." />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on PHB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay for PhB." />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on IDX" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay for the index." />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width." />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
-      <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
-      <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
-      <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
-      <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
-      <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
-      <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
-      <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
-      <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
-      <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
-      <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
-      <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x400C0000" description="SD card">
-    <Register start="+0x000" size="4" name="PWR" access="Read/Write" description="Power control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTRL" description="Power control">
-        <Enum name="POWER_OFF" start="0x0" description="Power-off" />
-        <Enum name="POWER_UP" start="0x2" description="Power-up" />
-        <Enum name="POWER_ON" start="0x3" description="Power-on" />
-      </BitField>
-      <BitField start="2" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="OPENDRAIN" description="SD_CMD output control." />
-      <BitField start="7" size="1" name="ROD" description="Rod control." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CLOCK" access="Read/Write" description="Clock control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLKDIV" description="Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)]." />
-      <BitField start="8" size="1" name="ENABLE" description="Enable SD card bus clock:">
-        <Enum name="CLOCK_DISABLED_" start="0" description="Clock disabled." />
-        <Enum name="CLOCK_ENABLED_" start="1" description="Clock enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="PWRSAVE" description="Disable SD_CLK output when bus is idle:">
-        <Enum name="ALWAYS_ENABLED_" start="0" description="Always enabled." />
-        <Enum name="CLOCK_ENABLED_WHEN_B" start="1" description="Clock enabled when bus is active." />
-      </BitField>
-      <BitField start="10" size="1" name="BYPASS" description="Enable bypass of clock divide logic:">
-        <Enum name="DISABLE_BYPASS_" start="0" description="Disable bypass." />
-        <Enum name="ENABLE_BYPASS_MCLK_" start="1" description="Enable bypass. MCLK driven to card bus output (SD_CLK)." />
-      </BitField>
-      <BitField start="11" size="1" name="WIDEBUS" description="Enable wide bus mode.">
-        <Enum name="STANDARD_BUS_MODE_O" start="0" description="Standard bus mode (only SD_DAT[0] used)." />
-        <Enum name="WIDE_BUS_MODE_SD_DA" start="1" description="Wide bus mode (SD_DAT[3:0] used)" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="ARGUMENT" access="Read/Write" description="Argument register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CmdArg" description="Command argument" />
-    </Register>
-    <Register start="+0x00C" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CmdIndex" description="Command index." />
-      <BitField start="6" size="1" name="Response" description="If set, CPSM waits for a response." />
-      <BitField start="7" size="1" name="LongRsp" description="If set, CPSM receives a 136 bit long response." />
-      <BitField start="8" size="1" name="Interrupt" description="If set, CPSM disables command timer and waits for interrupt request." />
-      <BitField start="9" size="1" name="Pending" description="If set, CPSM waits for CmdPend before it starts sending a command." />
-      <BitField start="10" size="1" name="Enable" description="If set, CPSM is enabled." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="RESPCMD" access="ReadOnly" description="Response command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESPCMD" description="Response command index" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="RESPONSE0" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x014+4" size="4" name="RESPONSE1" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x014+8" size="4" name="RESPONSE2" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x014+12" size="4" name="RESPONSE3" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x024" size="4" name="DATATIMER" access="Read/Write" description="Data Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATATIME" description="Data timeout period." />
-    </Register>
-    <Register start="+0x028" size="4" name="DATALENGTH" access="Read/Write" description="Data length register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATALENGTH" description="Data length value" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATACTRL" access="Read/Write" description="Data control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Data transfer enable." />
-      <BitField start="1" size="1" name="DIRECTION" description="Data transfer direction">
-        <Enum name="FROM_CONTROLLER_TO_C" start="0" description="From controller to card." />
-        <Enum name="FROM_CARD_TO_CONTROL" start="1" description="From card to controller." />
-      </BitField>
-      <BitField start="2" size="1" name="MODE" description="Data transfer mode">
-        <Enum name="BLOCK_DATA_TRANSFER_" start="0" description="Block data transfer." />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAENABLE" description="Enable DMA">
-        <Enum name="DMA_DISABLED_" start="0" description="DMA disabled." />
-        <Enum name="DMA_ENABLED_" start="1" description="DMA enabled." />
-      </BitField>
-      <BitField start="4" size="4" name="BLOCKSIZE" description="Data block length" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="DATACNT" access="ReadOnly" description="Data counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATACOUNT" description="Remaining data" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDCRCFAIL" description="Command response received (CRC check failed)." />
-      <BitField start="1" size="1" name="DATACRCFAIL" description="Data block sent/received (CRC check failed)." />
-      <BitField start="2" size="1" name="CMDTIMEOUT" description="Command response timeout." />
-      <BitField start="3" size="1" name="DATATIMEOUT" description="Data timeout." />
-      <BitField start="4" size="1" name="TXUNDERRUN" description="Transmit FIFO underrun error." />
-      <BitField start="5" size="1" name="RXOVERRUN" description="Receive FIFO overrun error." />
-      <BitField start="6" size="1" name="CMDRESPEND" description="Command response received (CRC check passed)." />
-      <BitField start="7" size="1" name="CMDSENT" description="Command sent (no response required)." />
-      <BitField start="8" size="1" name="DATAEND" description="Data end (data counter is zero)." />
-      <BitField start="9" size="1" name="STARTBITERR" description="Start bit not detected on all data signals in wide bus mode." />
-      <BitField start="10" size="1" name="DATABLOCKEND" description="Data block sent/received (CRC check passed)." />
-      <BitField start="11" size="1" name="CMDACTIVE" description="Command transfer in progress." />
-      <BitField start="12" size="1" name="TXACTIVE" description="Data transmit in progress." />
-      <BitField start="13" size="1" name="RXACTIVE" description="Data receive in progress." />
-      <BitField start="14" size="1" name="TXFIFOHALFEMPTY" description="Transmit FIFO half empty." />
-      <BitField start="15" size="1" name="RXFIFOHALFFULL" description="Receive FIFO half full." />
-      <BitField start="16" size="1" name="TXFIFOFULL" description="Transmit FIFO full." />
-      <BitField start="17" size="1" name="RXFIFOFULL" description="Receive FIFO full." />
-      <BitField start="18" size="1" name="TXFIFOEMPTY" description="Transmit FIFO empty." />
-      <BitField start="19" size="1" name="RXFIFOEMPTY" description="Receive FIFO empty." />
-      <BitField start="20" size="1" name="TXDATAAVLBL" description="Data available in transmit FIFO." />
-      <BitField start="21" size="1" name="RXDATAAVLBL" description="Data available in receive FIFO." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="CLEAR" access="WriteOnly" description="Clear register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CMDCRCFAILCLR" description="Clears CmdCrcFail flag." />
-      <BitField start="1" size="1" name="DATACRCFAILCLR" description="Clears DataCrcFail flag." />
-      <BitField start="2" size="1" name="CMDTIMEOUTCLR" description="Clears CmdTimeOut flag." />
-      <BitField start="3" size="1" name="DATATIMEOUTCLR" description="Clears DataTimeOut flag." />
-      <BitField start="4" size="1" name="TXUNDERRUNCLR" description="Clears TxUnderrun flag." />
-      <BitField start="5" size="1" name="RXOVERRUNCLR" description="Clears RxOverrun flag." />
-      <BitField start="6" size="1" name="CMDRESPENDCLR" description="Clears CmdRespEnd flag." />
-      <BitField start="7" size="1" name="CMDSENTCLR" description="Clears CmdSent flag." />
-      <BitField start="8" size="1" name="DATAENDCLR" description="Clears DataEnd flag." />
-      <BitField start="9" size="1" name="STARTBITERRCLR" description="Clears StartBitErr flag." />
-      <BitField start="10" size="1" name="DATABLOCKENDCLR" description="Clears DataBlockEnd flag." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x03C" size="4" name="MASK0" access="Read/Write" description="Interrupt 0 mask register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASK0" description="Mask CmdCrcFail flag." />
-      <BitField start="1" size="1" name="MASK1" description="Mask DataCrcFail flag." />
-      <BitField start="2" size="1" name="MASK2" description="Mask CmdTimeOut flag." />
-      <BitField start="3" size="1" name="MASK3" description="Mask DataTimeOut flag." />
-      <BitField start="4" size="1" name="MASK4" description="Mask TxUnderrun flag." />
-      <BitField start="5" size="1" name="MASK5" description="Mask RxOverrun flag." />
-      <BitField start="6" size="1" name="MASK6" description="Mask CmdRespEnd flag." />
-      <BitField start="7" size="1" name="MASK7" description="Mask CmdSent flag." />
-      <BitField start="8" size="1" name="MASK8" description="Mask DataEnd flag." />
-      <BitField start="9" size="1" name="MASK9" description="Mask StartBitErr flag." />
-      <BitField start="10" size="1" name="MASK10" description="Mask DataBlockEnd flag." />
-      <BitField start="11" size="1" name="MASK11" description="Mask CmdActive flag." />
-      <BitField start="12" size="1" name="MASK12" description="Mask TxActive flag." />
-      <BitField start="13" size="1" name="MASK13" description="Mask RxActive flag." />
-      <BitField start="14" size="1" name="MASK14" description="Mask TxFifoHalfEmpty flag." />
-      <BitField start="15" size="1" name="MASK15" description="Mask RxFifoHalfFull flag." />
-      <BitField start="16" size="1" name="MASK16" description="Mask TxFifoFull flag." />
-      <BitField start="17" size="1" name="MASK17" description="Mask RxFifoFull flag." />
-      <BitField start="18" size="1" name="MASK18" description="Mask TxFifoEmpty flag." />
-      <BitField start="19" size="1" name="MASK19" description="Mask RxFifoEmpty flag." />
-      <BitField start="20" size="1" name="MASK20" description="Mask TxDataAvlbl flag." />
-      <BitField start="21" size="1" name="MASK21" description="Mask RxDataAvlbl flag." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x048" size="4" name="FIFOCNT" access="ReadOnly" description="FIFO Counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="DATACOUNT" description="Remaining data" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x080+0" size="4" name="FIFO0" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+4" size="4" name="FIFO1" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+8" size="4" name="FIFO2" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+12" size="4" name="FIFO3" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+16" size="4" name="FIFO4" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+20" size="4" name="FIFO5" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+24" size="4" name="FIFO6" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+28" size="4" name="FIFO7" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+32" size="4" name="FIFO8" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+36" size="4" name="FIFO9" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+40" size="4" name="FIFO10" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+44" size="4" name="FIFO11" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+48" size="4" name="FIFO12" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+52" size="4" name="FIFO13" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+56" size="4" name="FIFO14" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+60" size="4" name="FIFO15" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x400FC000" description=" System and clock control ">
-    <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. All other values are reserved.">
-        <Enum name="FLASH_ACCESSES_USE_1" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_2" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_3" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_4" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost off. Use this setting for operation from 100 to 120 MHz operation with power boost on." />
-        <Enum name="FLASH_ACCESSES_USE_5" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_6" start="0x5" description="Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x080+0" size="4" name="PLLCON0" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x080+32" size="4" name="PLLCON1" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x084+0" size="4" name="PLLCFG0" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value &quot;M&quot; in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." />
-      <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value &quot;P&quot; in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x084+32" size="4" name="PLLCFG1" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value &quot;M&quot; in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." />
-      <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value &quot;P&quot; in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x088+0" size="4" name="PLLSTAT0" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." />
-      <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x088+32" size="4" name="PLLSTAT1" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." />
-      <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x08C+0" size="4" name="PLLFEED0" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x08C+32" size="4" name="PLLFEED1" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details." />
-      <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details." />
-      <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x0C4" size="4" name="PCONP0" access="Read/Write" description="Power Control for Peripherals" reset_value="0x0408829E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLCD" description="LCD controller power/clock control bit." />
-      <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
-      <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
-      <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
-      <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
-      <BitField start="5" size="1" name="PCPWM0" description="PWM0 power/clock control bit." />
-      <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
-      <BitField start="7" size="1" name="PCI2C0" description="I2C0 interface power/clock control bit." />
-      <BitField start="8" size="1" name="PCUART4" description="UART4 power/clock control bit." />
-      <BitField start="9" size="1" name="PCRTC" description="RTC and Event Monitor/Recorder power/clock control bit." />
-      <BitField start="10" size="1" name="PCSSP1" description="SSP 1 interface power/clock control bit." />
-      <BitField start="11" size="1" name="PCEMC" description="External Memory Controller power/clock control bit." />
-      <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before attempting to set PDN." />
-      <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
-      <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
-      <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
-      <BitField start="16" size="1" name="PCSPIFI" description="SPI Flash Interface power/clock control bit." />
-      <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM power/clock control bit." />
-      <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
-      <BitField start="19" size="1" name="PCI2C1" description="I2C1 interface power/clock control bit." />
-      <BitField start="20" size="1" name="PCSSP2" description="SSP2 interface power/clock control bit." />
-      <BitField start="21" size="1" name="PCSSP0" description="SSP0 interface power/clock control bit." />
-      <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
-      <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
-      <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
-      <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
-      <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
-      <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
-      <BitField start="28" size="1" name="PCSDC" description="SD Card interface power/clock control bit." />
-      <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
-      <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
-      <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
-    </Register>
-    <Register start="+0x0C8" size="4" name="PCONP1" access="Read/Write" description="Power Control for Peripherals" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PCCMP" description="comparator 0/1 power/clock control bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="EMCCLKSEL" access="Read/Write" description="External Memory Controller Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EMCDIV" description="Selects the EMC clock rate relative to the CPU clock.">
-        <Enum name="THE_EMC_USES_THE_SAM" start="0" description="The EMC uses the same clock as the CPU." />
-        <Enum name="THE_EMC_USES_A_CLOCK" start="1" description="The EMC uses a clock at half the rate of the CPU." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="CCLKSEL" access="Read/Write" description="CPU Clock Selection register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="CCLKDIV" description="Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. ... 31 = The input clock is divided by 31 to produce the CPU clock." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CCLKSEL" description="Selects the input clock for the CPU clock divider.">
-        <Enum name="SYSCLK_IS_USED_AS_TH" start="0" description="Sysclk is used as the input to the CPU clock divider." />
-        <Enum name="THE_OUTPUT_OF_THE_MA" start="1" description="The output of the Main PLL is used as the input to the CPU clock divider." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="USBCLKSEL" access="Read/Write" description="USB Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="USBDIV" description="Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation.">
-        <Enum name="THE_DIVIDER_IS_TURNE" start="0x0" description="The divider is turned off, no clock will be provided to the USB subsystem." />
-        <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x4" description="PLL0 output is divided by 4. PLL0 output must be 192 MHz." />
-        <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x6" description="PLL0 output is divided by 6. PLL0 output must be 288 MHz." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="USBSEL" description="Selects the input clock for the USB clock divider.">
-        <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions." />
-        <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the USB clock divider." />
-        <Enum name="ALTPLLOOUT" start="0x2" description="The output of the Alt PLL is used as the input to the USB clock divider." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKSRC" description="Selects the clock source for sysclk and PLL0 as follows:">
-        <Enum name="SELECTS_THE_INTERNAL" start="0" description="Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default)." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="1" description="Selects the main oscillator as the sysclk and PLL0 clock source." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
-      <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTMODE0" description="Level or edge sensitivity select for EINT0.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTMODE1" description="Level or edge sensitivity select for EINT1.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTMODE2" description="Level or edge sensitivity select for EINT2.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTMODE3" description="Level or edge sensitivity select for EINT3.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt polarity for EINT0.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE0)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE0)." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt polarity for EINT1.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE1)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE1)." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt polarity for EINT2.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE2)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE2)." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt polarity for EINT3.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE3)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE3)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
-      <BitField start="1" size="1" name="EXTR" description="Assertion of the external RESET signal sets this bit. This bit is cleared only by software or POR." />
-      <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
-      <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
-      <BitField start="4" size="1" name="SYSRESET" description="This bit is set if the processor has been reset due to a system reset request. Setting the SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is cleared only by software or POR." />
-      <BitField start="5" size="1" name="LOCKUP" description="This bit is set if the processor has been reset due to a &quot;lockup&quot;. The lockup state causes a chip reset. This bit is cleared only by software or POR." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x188" size="4" name="MATRIXARB" access="Read/Write" description="Matrix arbitration register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="PRI_ICODE" description="I-Code bus priority. Should be lower than PRI_DCODE for proper operation." />
-      <BitField start="2" size="2" name="PRI_DCODE" description="D-Code bus priority." />
-      <BitField start="4" size="2" name="PRI_SYS" description="System bus priority." />
-      <BitField start="6" size="2" name="PRI_GPDMA" description="General Purpose DMA controller priority." />
-      <BitField start="8" size="2" name="PRI_ETH" description="Ethernet DMA priority." />
-      <BitField start="10" size="2" name="PRI_LCD" description="LCD DMA priority." />
-      <BitField start="12" size="2" name="PRI_USB" description="USB DMA priority." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="ROM_LAT" description="ROM latency select. Should always be 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System Control and Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EMCSC" description="EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter.">
-        <Enum name="STATIC_MEMORY_ADDRES" start="0" description="Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift." />
-        <Enum name="STATIC_MEMORY_ADDRES" start="1" description="Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices." />
-      </BitField>
-      <BitField start="1" size="1" name="EMCRD" description="EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter.">
-        <Enum name="BOTH_EMC_RESETS_ARE_" start="0" description="Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition." />
-        <Enum name="MANY_PORTIONS_OF_THE" start="1" description="Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset." />
-      </BitField>
-      <BitField start="2" size="1" name="EMCBC" description="External Memory Controller burst control. Also see Section 9.10 in the EMC chapter.">
-        <Enum name="BURST_ENABLED_" start="0" description="Burst enabled." />
-        <Enum name="BURST_DISABLED_THIS" start="1" description="Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices." />
-      </BitField>
-      <BitField start="3" size="1" name="MCIPWRAL" description="MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR.">
-        <Enum name="SD_PWR_IS_ACTIVE_LOW" start="0" description="SD_PWR is active low (inverted output of the SD Card interface block)." />
-        <Enum name="SD_PWR_IS_ACTIVE_HIG" start="1" description="SD_PWR is active high (follows the output of the SD Card interface block)." />
-      </BitField>
-      <BitField start="4" size="1" name="OSCRS" description="Main oscillator range select.">
-        <Enum name="THE_FREQUENCY_RANGE_" start="0" description="The frequency range of the main oscillator is 1 MHz to 20 MHz." />
-        <Enum name="THE_FREQUENCY_RANGE_" start="1" description="The frequency range of the main oscillator is 15 MHz to 25 MHz." />
-      </BitField>
-      <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
-        <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is disabled." />
-        <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
-      </BitField>
-      <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
-        <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is not ready to be used as a clock source." />
-        <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="PCLKSEL" access="Read/Write" description="Peripheral Clock Selection register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCLKDIV" description="Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals. 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. ... 31 = The input clock is divided by 31 to produce the APB peripheral clock." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1B0" size="4" name="PBOOST" access="Read/Write" description="Power boost register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="Boost" description="Boost control bits. 00 : Boost is off, operation must be below 100 MHz. 11 : Boost is on, operation up to 120 MHz is supported. Other values are not allowed." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1B4" size="4" name="SPIFICLKSEL" access="Read/Write" description="SPIFI Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="SPIFIDIV" description="Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. ... 31 = The input clock is divided by 31 to produce the SPIFI clock." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="SPIFISEL" description="Selects the input clock for the USB clock divider.">
-        <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the SPIFI clock divider." />
-        <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the SPIFI clock divider." />
-        <Enum name="ALTPLLOUT" start="0x2" description="The output of the Alt PLL is used as the input to the SPIFI clock divider." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1B8" size="4" name="LCD_CFG" access="Read/Write" description="LCD Clock configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="CLKDIV" description="LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
-      <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
-      <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
-      <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
-      <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
-      <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
-      <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 3.12.8 &quot;Wake-up from Reduced Power Modes&quot; for details). Also see Section 3.10.3 &quot;PLLs and Power-down mode&quot; and Section 3.3.7 &quot;Power Control for Peripherals registers&quot; for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
-      <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMASEL00" description="Selects the DMA request for GPDMA input 0: 0 - (unused) 1 - Timer 0 match 0 is selected." />
-      <BitField start="1" size="1" name="DMASEL01" description="Selects the DMA request for GPDMA input 1: 0 - SD card interface is selected. 1 - Timer 0 match 1 is selected." />
-      <BitField start="2" size="1" name="DMASEL02" description="Selects the DMA request for GPDMA input 2: 0 - SSP0 transmit is selected. 1 - Timer 1 match 0 is selected." />
-      <BitField start="3" size="1" name="DMASEL03" description="Selects the DMA request for GPDMA input 3: 0 - SSP0 receive is selected. 1 - Timer 1 match 1 is selected." />
-      <BitField start="4" size="1" name="DMASEL04" description="Selects the DMA request for GPDMA input 4: 0 - SSP1 transmit is selected. 1 - Timer 2 match 0 is selected." />
-      <BitField start="5" size="1" name="DMASEL05" description="Selects the DMA request for GPDMA input 5: 0 - SSP1 receive is selected. 1 - Timer 2 match 1 is selected." />
-      <BitField start="6" size="1" name="DMASEL06" description="Selects the DMA request for GPDMA input 6: 0 - SSP2 transmit is selected. 1 - I2S channel 0 is selected." />
-      <BitField start="7" size="1" name="DMASEL07" description="Selects the DMA request for GPDMA input 7: 0 - SSP2 receive is selected. 1 - I2S channel 1 is selected." />
-      <BitField start="8" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - UART0 transmit is selected. 1 - UART3 transmit is selected." />
-      <BitField start="11" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - UART0 receive is selected. 1 - UART3 receive is selected." />
-      <BitField start="12" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - UART1 transmit is selected. 1 - UART4 transmit is selected." />
-      <BitField start="13" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - UART1 receive is selected. 1 - UART4 receive is selected." />
-      <BitField start="14" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - UART2 transmit is selected. 1 - Timer 3 match 0 is selected." />
-      <BitField start="15" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - UART2 receive is selected. 1 - Timer 3 match 1 is selected." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. 0x0 = Selects the CPU clock as the CLKOUT source. 0x1 = Selects the main oscillator as the CLKOUT source. 0x2 = Selects the Internal RC oscillator as the CLKOUT source. 0x3 = Selects the USB clock as the CLKOUT source. 0x4 = Selects the RTC oscillator as the CLKOUT source. 0x5 = Selects the SPIFI clock as the CLKOUT source. 0x6 = Selects the Watchdog oscillator as the CLKOUT source. Other settings are reserved. Do not use." />
-      <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0x0 = Clock is divided by 1. 0x1 = Clock is divided by 2. 0x2 = Clock is divided by 3. ... 0xF = Clock is divided by 16." />
-      <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
-      <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1CC" size="4" name="RSTCON0" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RSTLCD" description="LCD controller reset control bit." />
-      <BitField start="1" size="1" name="RSTTIM0" description="Timer/Counter 0 reset control bit." />
-      <BitField start="2" size="1" name="RSTTIM1" description="Timer/Counter 1 reset control bit." />
-      <BitField start="3" size="1" name="RSTUART0" description="UART0 reset control bit." />
-      <BitField start="4" size="1" name="RSTUART1" description="UART1 reset control bit." />
-      <BitField start="5" size="1" name="RSTPWM0" description="PWM0 reset control bit." />
-      <BitField start="6" size="1" name="RSTPWM1" description="PWM1 reset control bit." />
-      <BitField start="7" size="1" name="RSTI2C0" description="The I2C0 interface reset control bit." />
-      <BitField start="8" size="1" name="RSTUART4" description="UART4 reset control bit." />
-      <BitField start="9" size="1" name="RSTRTC" description="RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see Table 626 &quot;Register overview: Real-Time Clock (base address 0x4002 4000)&quot; for details." />
-      <BitField start="10" size="1" name="RSTSSP1" description="The SSP 1 interface reset control bit." />
-      <BitField start="11" size="1" name="RSTEMC" description="External Memory Controller reset control bit." />
-      <BitField start="12" size="1" name="RSTADC" description="A/D converter (ADC) reset control bit." />
-      <BitField start="13" size="1" name="RSTCAN1" description="CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." />
-      <BitField start="14" size="1" name="RSTCAN2" description="CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." />
-      <BitField start="15" size="1" name="RSTGPIO" description="Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a separate bit in the RSTCON1 register." />
-      <BitField start="16" size="1" name="RSTSPIFI" description="SPI Flash Interface reset control bit." />
-      <BitField start="17" size="1" name="RSTMCPWM" description="Motor Control PWM reset control bit." />
-      <BitField start="18" size="1" name="RSTQEI" description="Quadrature Encoder Interface reset control bit." />
-      <BitField start="19" size="1" name="RSTI2C1" description="The I2C1 interface reset control bit." />
-      <BitField start="20" size="1" name="RSTSSP2" description="The SSP2 interface reset control bit." />
-      <BitField start="21" size="1" name="RSTSSP0" description="The SSP0 interface reset control bit." />
-      <BitField start="22" size="1" name="RSTTIM2" description="Timer 2 reset control bit." />
-      <BitField start="23" size="1" name="RSTTIM3" description="Timer 3 reset control bit." />
-      <BitField start="24" size="1" name="RSTUART2" description="UART 2 reset control bit." />
-      <BitField start="25" size="1" name="RSTUART3" description="UART 3 reset control bit." />
-      <BitField start="26" size="1" name="RSTI2C2" description="I2C interface 2 reset control bit." />
-      <BitField start="27" size="1" name="RSTI2S" description="I2S interface reset control bit." />
-      <BitField start="28" size="1" name="RSTSDC" description="SD Card interface reset control bit." />
-      <BitField start="29" size="1" name="RSTGPDMA" description="GPDMA function reset control bit." />
-      <BitField start="30" size="1" name="RSTENET" description="Ethernet block reset control bit." />
-      <BitField start="31" size="1" name="RSTUSB" description="USB interface reset control bit." />
-    </Register>
-    <Register start="+0x1D0" size="4" name="RSTCON1" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RSTIOCON" description="Reset control bit for the IOCON registers." />
-      <BitField start="1" size="1" name="RSTDAC" description="D/A converter (DAC) reset control bit." />
-      <BitField start="2" size="1" name="RSTCANACC" description="CAN acceptance filter reset control bit." />
-      <BitField start="3" size="1" name="RSTCMP" description="Comparator 0/1 reset control bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1DC" size="4" name="EMCDLYCTL" access="Read/Write" description="Values for the 4 programmable delays associated with SDRAM operation." reset_value="0x210" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="CMDDLY" description="Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="5" name="FBCLKDLY" description="Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="5" name="CLKOUT0DLY" description="Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet." />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="5" name="CLKOUT1DLY" description="Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1E0" size="4" name="EMCCAL" access="Read/Write" description="Controls the calibration counter for programmable delays and returns the result value." reset_value="0x1F00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CALVALUE" description="Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the IRC oscillator. This represents the composite effect of processing variation, internal regulator supply voltage, and ambient temperature." />
-      <BitField start="8" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="START" description="Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the measurement process. This bit is cleared automatically when the measurement is complete." />
-      <BitField start="15" size="1" name="DONE" description="Measurement completion flag. this bit is set when a calibration measurement is completed. This bit is cleared automatically when the START bit is set." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="WWDT" start="4" size="4" />
-      <BitField name="TIMER0" start="12" size="4" />
-      <BitField name="TIMER1" start="20" size="4" />
-      <BitField name="TIMER2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="TIMER3" start="4" size="4" />
-      <BitField name="UART0" start="12" size="4" />
-      <BitField name="UART1" start="20" size="4" />
-      <BitField name="UART2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="UART3" start="4" size="4" />
-      <BitField name="PWM1" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="I2C2" start="4" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="RTC" start="12" size="4" />
-      <BitField name="EINT0" start="20" size="4" />
-      <BitField name="EINT1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="EINT2" start="4" size="4" />
-      <BitField name="EINT3" start="12" size="4" />
-      <BitField name="ADC" start="20" size="4" />
-      <BitField name="BOD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USB" start="4" size="4" />
-      <BitField name="CAN" start="12" size="4" />
-      <BitField name="GPDMA" start="20" size="4" />
-      <BitField name="I2S" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="ETHERNET" start="4" size="4" />
-      <BitField name="SDMMC" start="12" size="4" />
-      <BitField name="MCPWM" start="20" size="4" />
-      <BitField name="QEI" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="USB_NEED_CLK" start="12" size="4" />
-      <BitField name="UART4" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="SSP2" start="4" size="4" />
-      <BitField name="LCD" start="12" size="4" />
-      <BitField name="GPIOINT" start="20" size="4" />
-      <BitField name="PWM0" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="EEPROM" start="4" size="4" />
-      <BitField name="CMP0" start="12" size="4" />
-      <BitField name="CMP1" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Vectors.s b/examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Vectors.s
deleted file mode 100644
index 02568546..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/LPC408x_7x_Vectors.s
+++ /dev/null
@@ -1,458 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak UART0_IRQHandler
-  .thumb_set UART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak UART2_IRQHandler
-  .thumb_set UART2_IRQHandler,Dummy_Handler
-
-  .weak UART3_IRQHandler
-  .thumb_set UART3_IRQHandler,Dummy_Handler
-
-  .weak PWM1_IRQHandler
-  .thumb_set PWM1_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak EINT0_IRQHandler
-  .thumb_set EINT0_IRQHandler,Dummy_Handler
-
-  .weak EINT1_IRQHandler
-  .thumb_set EINT1_IRQHandler,Dummy_Handler
-
-  .weak EINT2_IRQHandler
-  .thumb_set EINT2_IRQHandler,Dummy_Handler
-
-  .weak EINT3_IRQHandler
-  .thumb_set EINT3_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak BOD_IRQHandler
-  .thumb_set BOD_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak CAN_IRQHandler
-  .thumb_set CAN_IRQHandler,Dummy_Handler
-
-  .weak GPDMA_IRQHandler
-  .thumb_set GPDMA_IRQHandler,Dummy_Handler
-
-  .weak I2S_IRQHandler
-  .thumb_set I2S_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDMMC_IRQHandler
-  .thumb_set SDMMC_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-  .weak USB_NEED_CLK_IRQHandler
-  .thumb_set USB_NEED_CLK_IRQHandler,Dummy_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Dummy_Handler
-
-  .weak SSP2_IRQHandler
-  .thumb_set SSP2_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak GPIOINT_IRQHandler
-  .thumb_set GPIOINT_IRQHandler,Dummy_Handler
-
-  .weak PWM0_IRQHandler
-  .thumb_set PWM0_IRQHandler,Dummy_Handler
-
-  .weak EEPROM_IRQHandler
-  .thumb_set EEPROM_IRQHandler,Dummy_Handler
-
-  .weak CMP0_IRQHandler
-  .thumb_set CMP0_IRQHandler,Dummy_Handler
-
-  .weak CMP1_IRQHandler
-  .thumb_set CMP1_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART0_IRQHandler
-UART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART2_IRQHandler
-UART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART3_IRQHandler
-UART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM1_IRQHandler
-PWM1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_IRQHandler
-I2C2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT0_IRQHandler
-EINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT1_IRQHandler
-EINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT2_IRQHandler
-EINT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT3_IRQHandler
-EINT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_IRQHandler
-BOD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN_IRQHandler
-CAN_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GPDMA_IRQHandler
-GPDMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S_IRQHandler
-I2S_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDMMC_IRQHandler
-SDMMC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_NEED_CLK_IRQHandler
-USB_NEED_CLK_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART4_IRQHandler
-UART4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP2_IRQHandler
-SSP2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GPIOINT_IRQHandler
-GPIOINT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM0_IRQHandler
-PWM0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EEPROM_IRQHandler
-EEPROM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CMP0_IRQHandler
-CMP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CMP1_IRQHandler
-CMP1_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDT_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word UART0_IRQHandler
-  .word UART1_IRQHandler
-  .word UART2_IRQHandler
-  .word UART3_IRQHandler
-  .word PWM1_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word RTC_IRQHandler
-  .word EINT0_IRQHandler
-  .word EINT1_IRQHandler
-  .word EINT2_IRQHandler
-  .word EINT3_IRQHandler
-  .word ADC_IRQHandler
-  .word BOD_IRQHandler
-  .word USB_IRQHandler
-  .word CAN_IRQHandler
-  .word GPDMA_IRQHandler
-  .word I2S_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDMMC_IRQHandler
-  .word MCPWM_IRQHandler
-  .word QEI_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word USB_NEED_CLK_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word UART4_IRQHandler
-  .word SSP2_IRQHandler
-  .word LCD_IRQHandler
-  .word GPIOINT_IRQHandler
-  .word PWM0_IRQHandler
-  .word EEPROM_IRQHandler
-  .word CMP0_IRQHandler
-  .word CMP1_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/lpc40xx/flash_placement.xml b/examples/device/cdc_msc/ses/lpc40xx/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/lpc40xx/lpc40xx.emProject b/examples/device/cdc_msc/ses/lpc40xx/lpc40xx.emProject
deleted file mode 100644
index 4a61181c..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/lpc40xx.emProject
+++ /dev/null
@@ -1,122 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc40xx" target="8" version="2">
-  <project Name="lpc40xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4088FBD208"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="256"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00080000;RAM;0x10000000;0x00010000;RAM;0x20000000;0x00008000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC4088"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="CORE_M4;__LPC4000_FAMILY;__LPC408x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_LPC40XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc;$(rootDir)/src"
-      debug_register_definition_file="$(ProjectDir)/LPC408x_7x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC4088FBD208_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC4000;DeviceSubFamily=LPC408x;Target=LPC4088FBD208;Placement=Flash;rootDir=../../../../.."
-      package_dependencies="LPC4000"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC4000_Startup.s" />
-      <file file_name="LPC408x_7x_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="LPC4088FBD208_MemoryMap.xml" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC4000_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-    </folder>
-    <configuration
-      Name="EA4088 QuickStart"
-      c_preprocessor_definitions="BOARD_EA4088QS"
-      link_use_linker_script_file="No"
-      linker_section_placement_file="flash_placement.xml" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="ea4088qs">
-          <file file_name="../../../../../hw/bsp/ea4088qs/ea4088qs.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_40xx">
-              <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/chip.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/chip_lpc175x_6x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/chip_lpc177x_8x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/chip_lpc407x_8x.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/clock_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/cmsis.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/cmsis_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/core_cm4.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/core_cm4_simd.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/core_cmFunc.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/core_cmInstr.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/gpio_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/sys_config.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/sysctl_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/uart_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/usb_17xx_40xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/inc/iocon_17xx_40xx.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/chip_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/clock_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/gpio_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/iocon_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/sysctl_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/sysinit_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_40xx/src/uart_17xx_40xx.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-  </project>
-  <configuration
-    Name="EA4088 QuickStart"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc40xx/thumb_crt0.s b/examples/device/cdc_msc/ses/lpc40xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/lpc40xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/lpc43xx/LPC4300_Startup.s b/examples/device/cdc_msc/ses/lpc43xx/LPC4300_Startup.s
deleted file mode 100644
index 3df2ad96..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/LPC4300_Startup.s
+++ /dev/null
@@ -1,126 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  ldr r1, =0x7
-  bics r0, r1
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/lpc43xx/LPC4300_Target.js b/examples/device/cdc_msc/ses/lpc43xx/LPC4300_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/LPC4300_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml b/examples/device/cdc_msc/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml
deleted file mode 100644
index eb42b7bf..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml	
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC4357 Cortex-M4">
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00010000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Registers.xml b/examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Registers.xml
deleted file mode 100644
index 9c094646..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Registers.xml
+++ /dev/null
@@ -1,33526 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC43xx" description="Register cmsis file for LPC43xx parts">
-  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
-        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
-      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
-      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
-      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
-      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
-      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
-      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
-        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
-      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
-      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
-      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
-        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
-        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
-        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
-        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
-      </BitField>
-      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
-        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
-        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
-      </BitField>
-      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
-        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
-        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
-        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
-        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
-      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
-        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
-        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
-      </BitField>
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRESS" description="Address." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
-    </Register>
-    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Input or output data" />
-    </Register>
-    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
-      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
-      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
-      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
-      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
-      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
-      </BitField>
-      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
-      </BitField>
-      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
-        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
-        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
-        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
-        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
-      </BitField>
-      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
-      </BitField>
-      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
-      </BitField>
-      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
-        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
-      </BitField>
-      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
-        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
-      </BitField>
-      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
-      </BitField>
-      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
-        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
-        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
-      </BitField>
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
-      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
-      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
-      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
-        <Enum name="NONE" start="0" description="None. No response expected from card" />
-        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
-      </BitField>
-      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
-        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
-        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
-      </BitField>
-      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
-        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
-        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
-      </BitField>
-      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
-        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
-        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
-      </BitField>
-      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
-        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
-        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
-      </BitField>
-      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
-        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
-      </BitField>
-      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
-        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
-        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
-      </BitField>
-      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
-        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
-        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
-      </BitField>
-      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
-        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
-        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
-      </BitField>
-      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
-        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
-        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
-      </BitField>
-      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
-      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
-        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
-      </BitField>
-      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
-        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-      </BitField>
-      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
-      </BitField>
-      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
-      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
-        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
-        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
-      </BitField>
-      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
-        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
-        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
-      </BitField>
-      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
-    </Register>
-    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
-    </Register>
-    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
-    </Register>
-    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
-    </Register>
-    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
-    </Register>
-    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
-      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
-      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
-      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
-      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
-      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
-      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
-      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
-      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
-      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
-      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
-      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
-    </Register>
-    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
-      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
-    </Register>
-    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
-    </Register>
-    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
-      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
-      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
-      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
-      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
-    </Register>
-    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
-    </Register>
-    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
-      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
-      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
-      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
-    </Register>
-    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
-        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
-        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
-        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode.">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
-        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
-        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy.">
-        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
-        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
-        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
-        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
-        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
-      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
-      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
-      </BitField>
-      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
-      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
-      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
-        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
-        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
-      </BitField>
-      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
-      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
-      </BitField>
-      <BitField start="8" size="1" name="ID" description="USB ID">
-        <Enum name="A_DEVICE" start="0" description="A-device" />
-        <Enum name="B_DEVICE" start="1" description="B-device" />
-      </BitField>
-      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
-      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
-      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
-      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
-      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
-      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
-      <BitField start="15" size="1" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
-      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
-      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
-      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
-      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
-      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
-      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
-      <BitField start="23" size="1" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="reserved" />
-      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
-      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
-      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
-      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
-      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
-        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
-        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
-      </BitField>
-      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
-        <Enum name="READ" start="0" description="Read" />
-        <Enum name="WRITE" start="1" description="Write" />
-      </BitField>
-      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
-      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
-    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
-      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
-      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
-    </Register>
-    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
-    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
-      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
-      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
-      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
-      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
-      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
-      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
-      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
-      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
-      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
-      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
-      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
-      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
-      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
-      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
-      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
-      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
-      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
-      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
-      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
-    </Register>
-    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
-      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
-      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
-      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
-      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
-      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
-      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
-      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
-      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
-    </Register>
-    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
-      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
-      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
-      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
-      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
-      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
-      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
-      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
-      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
-    </Register>
-    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
-      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
-      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
-      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
-      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
-      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
-    </Register>
-    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="MO" description="Always 1" />
-    </Register>
-    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-    </Register>
-    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
-      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
-      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
-      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
-      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
-      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
-      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
-      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
-      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
-      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
-      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
-      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
-      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
-      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
-      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
-    </Register>
-    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
-    </Register>
-    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
-      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
-    </Register>
-    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
-    </Register>
-    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
-      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
-    </Register>
-    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
-    </Register>
-    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
-    </Register>
-    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
-      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
-      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
-      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
-      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
-      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
-      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
-      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
-      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
-      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
-      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
-      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
-      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
-      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
-    </Register>
-    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
-    </Register>
-    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
-      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
-      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
-      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
-      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
-      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
-      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
-      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
-      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
-      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
-      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
-      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
-      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
-      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
-      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
-      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
-      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
-      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
-      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
-      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
-      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
-      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
-      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
-      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
-      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
-      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
-      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
-      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
-      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
-      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
-      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
-      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
-      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
-      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
-      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
-      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
-    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
-    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
-    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M4 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register." />
-      <BitField start="1" size="1" name="ENA_EVENT1" description="Writing a 1 enables the Cortex-M0 core and the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Cortex-M0 subsystem core to put the part into any of&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;the Power-down modes Deep-sleep, Power-down, or&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Deep power-down depending on the value in the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;PD0_SLEEP0_MODE register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 3CBA = Power-down mode with M0SUB SRAM maintained&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
-    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
-        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
-        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
-        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
-        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
-        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
-        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
-      </BitField>
-      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
-        <Enum name="POWERED" start="0" description="Powered." />
-        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
-        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
-        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
-      </BitField>
-      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
-        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
-        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INACTIVE" start="0x3" description="Inactive." />
-      </BitField>
-      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.">
-        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
-        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
-        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
-        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
-      </BitField>
-      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.">
-        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
-        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
-        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
-        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
-      </BitField>
-      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
-        <Enum name="RESERVED" start="0x0" description="Reserved" />
-        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
-      </BitField>
-      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="M4MEMMAP" access="Read/Write" description="ARM Cortex-M4 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M4MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="M0SUBTAPSEL" description="JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="11" size="1" name="M4TAPSEL" description="JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="12" size="1" name="M0APPTAPSEL" description="JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="13" size="19" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
-        <Enum name="SPIFI" start="0x0" description="SPIFI" />
-        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
-        <Enum name="SGPIO14" start="0x2" description="SGPIO14" />
-        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
-      </BitField>
-      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
-        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
-        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
-        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
-        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
-        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
-        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
-        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
-        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
-        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
-        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
-        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
-        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
-      </BitField>
-      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
-        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
-        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="SGPIO15" start="0x3" description="SGPIO15" />
-      </BitField>
-      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
-        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
-        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="SGPIO14" start="0x3" description="SGPIO14" />
-      </BitField>
-      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
-        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
-        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-        <Enum name="ADCHS_WRITE" start="0x3" description="ADCHS write" />
-      </BitField>
-      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
-        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
-        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-        <Enum name="ADCHS_READ" start="0x3" description="ADCHS read" />
-      </BitField>
-      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
-        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
-        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
-        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
-        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
-        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
-        <Enum name="SGPIO14" start="0x1" description="SGPIO14" />
-        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
-        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
-        <Enum name="SGPIO15" start="0x1" description="SGPIO15" />
-        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
-        <Enum name="ADC0" start="0x0" description="ADC0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
-      </BitField>
-      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
-        <Enum name="ADC1" start="0x0" description="ADC1" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
-      </BitField>
-      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
-        <Enum name="DAC" start="0x0" description="DAC" />
-        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
-        <Enum name="SGPIO15" start="0x2" description="SGPIO15" />
-        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
-        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
-        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
-        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
-        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
-        <Enum name="MII" start="0x0" description="MII" />
-        <Enum name="RMII" start="0x4" description="RMII" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
-        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
-        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
-      </BitField>
-      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
-        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
-        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x130" size="4" name="M4TXEVENT" access="Read/Write" description="Cortex-M4 TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M4 TXEV event.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)" />
-    </Register>
-    <Register start="+0x308" size="4" name="M0SUBMEMMAP" access="Read/Write" description="ARM Cortex-M0SUB memory mapping" reset_value="0x18400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M0SUBMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x314" size="4" name="M0SUBTXEVENT" access="Read/Write" description="Cortex-M0SUB TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0SUB TXEV event handling.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="M0APPTXEVENT" access="Read/Write" description="Cortex-M0APP TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0APP TXEV event handling.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="M0APPMEMMAP" access="Read/Write" description="ARM Cortex-M0APP memory mapping" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M0APPMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x500" size="4" name="USB0FLADJ" access="Read/Write" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
-    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
-      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
-      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
-      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
-      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
-      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
-      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
-      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
-      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
-      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
-      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
-      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
-      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
-      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
-      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
-      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
-      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
-      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
-    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
-        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
-        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
-        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
-        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
-        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
-        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
-        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
-        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
-        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
-        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
-        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
-    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
-      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
-      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
-        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
-        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
-      </BitField>
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
-        <Enum name="IRC" start="0x01" description="IRC" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="RESERVED" start="0x0B" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="ENABLE" start="0" description="Enable" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
-        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
-      </BitField>
-      <BitField start="2" size="1" name="HF" description="Select frequency range">
-        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
-      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
-      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
-      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
-        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
-        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
-      </BitField>
-      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
-        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
-      </BitField>
-      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL1 power down">
-        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
-        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
-        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
-      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
-        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
-        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="PEQ2" start="0x1" description="2 (default)" />
-        <Enum name="PEQ4" start="0x2" description="4" />
-        <Enum name="8" start="0x3" description="8" />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="NEQ2" start="0x1" description="2" />
-        <Enum name="NEQ3" start="0x2" description="3 (default)" />
-        <Enum name="4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="RESERVED" start="0x09" description="Reserved" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
-        <Enum name="DIV1" start="0x0" description="1 (default)" />
-        <Enum name="DIV2" start="0x1" description="2" />
-        <Enum name="DIV3" start="0x2" description="3" />
-        <Enum name="DIV4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="BASE_M4_CLK" access="Read/Write" description="Output stage BASE_M4_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="BASE_SPI_CLK" access="Read/Write" description="Output stage BASE_SPI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_M4_BUS_CFG" access="Read/Write" description="CLK_M4_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0408" size="4" name="CLK_M4_SPIFI_CFG" access="Read/Write" description="CLK_M4_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0410" size="4" name="CLK_M4_GPIO_CFG" access="Read/Write" description="CLK_M4_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0418" size="4" name="CLK_M4_LCD_CFG" access="Read/Write" description="CLK_M4_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0420" size="4" name="CLK_M4_ETHERNET_CFG" access="Read/Write" description="CLK_M4_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0428" size="4" name="CLK_M4_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0430" size="4" name="CLK_M4_EMC_CFG" access="Read/Write" description="CLK_M4_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0438" size="4" name="CLK_M4_SDIO_CFG" access="Read/Write" description="CLK_M4_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0440" size="4" name="CLK_M4_DMA_CFG" access="Read/Write" description="CLK_M4_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0448" size="4" name="CLK_M4_M4CORE_CFG" access="Read/Write" description="CLK_M4_M4CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0468" size="4" name="CLK_M4_SCT_CFG" access="Read/Write" description="CLK_M4_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0470" size="4" name="CLK_M4_USB1_CFG" access="Read/Write" description="CLK_M4_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0478" size="4" name="CLK_M4_EMCDIV_CFG" access="Read/Write" description="CLK_M4_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0480" size="4" name="CLK_M4_FLASHA_CFG" access="Read/Write" description="CLK_M4_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0488" size="4" name="CLK_M4_FLASHB_CFG" access="Read/Write" description="CLK_M4_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0490" size="4" name="CLK_M4_M0APP_CFG" access="Read/Write" description="CLK_M0APP_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0498" size="4" name="CLK_M4_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A0" size="4" name="CLK_M4_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_M4_WWDT_CFG" access="Read/Write" description="CLK_M4_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0508" size="4" name="CLK_M4_USART0_CFG" access="Read/Write" description="CLK_M4_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0510" size="4" name="CLK_M4_UART1_CFG" access="Read/Write" description="CLK_M4_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0518" size="4" name="CLK_M4_SSP0_CFG" access="Read/Write" description="CLK_M4_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0520" size="4" name="CLK_M4_TIMER0_CFG" access="Read/Write" description="CLK_M4_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0528" size="4" name="CLK_M4_TIMER1_CFG" access="Read/Write" description="CLK_M4_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0530" size="4" name="CLK_M4_SCU_CFG" access="Read/Write" description="CLK_M4_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0538" size="4" name="CLK_M4_CREG_CFG" access="Read/Write" description="CLK_M4_CREGclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_M4_RITIMER_CFG" access="Read/Write" description="CLK_M4_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0608" size="4" name="CLK_M4_USART2_CFG" access="Read/Write" description="CLK_M4_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0610" size="4" name="CLK_M4_USART3_CFG" access="Read/Write" description="CLK_M4_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0618" size="4" name="CLK_M4_TIMER2_CFG" access="Read/Write" description="CLK_M4_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0620" size="4" name="CLK_M4_TIMER3_CFG" access="Read/Write" description="CLK_M4_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0628" size="4" name="CLK_M4_SSP1_CFG" access="Read/Write" description="CLK_M4_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0630" size="4" name="CLK_M4_QEI_CFG" access="Read/Write" description="CLK_M4_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0700" size="4" name="CLK_PERIPH_BUS_CFG" access="Read/Write" description="CLK_PERIPH_BUS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0710" size="4" name="CLK_PERIPH_CORE_CFG" access="Read/Write" description="CLK_PERIPH_CORE_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0718" size="4" name="CLK_PERIPH_SGPIO_CFG" access="Read/Write" description="CLK_PERIPH_SGPIO_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xA00" size="4" name="CLK_SPI_CFG" access="Read/Write" description="CLK_SPI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xB00" size="4" name="CLK_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x404" size="4" name="CLK_M4_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040C" size="4" name="CLK_M4_SPIFI_STAT" access="ReadOnly" description="CLK_M4_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0414" size="4" name="CLK_M4_GPIO_STAT" access="ReadOnly" description="CLK_M4_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x041C" size="4" name="CLK_M4_LCD_STAT" access="ReadOnly" description="CLK_M4_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0424" size="4" name="CLK_M4_ETHERNET_STAT" access="ReadOnly" description="CLK_M4_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x042C" size="4" name="CLK_M4_USB0_STAT" access="ReadOnly" description="CLK_M4_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0434" size="4" name="CLK_M4_EMC_STAT" access="ReadOnly" description="CLK_M4_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x043C" size="4" name="CLK_M4_SDIO_STAT" access="ReadOnly" description="CLK_M4_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0444" size="4" name="CLK_M4_DMA_STAT" access="ReadOnly" description="CLK_M4_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044C" size="4" name="CLK_M4_M4CORE_STAT" access="ReadOnly" description="CLK_M4_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x046C" size="4" name="CLK_M4_SCT_STAT" access="ReadOnly" description="CLK_M4_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0474" size="4" name="CLK_M4_USB1_STAT" access="ReadOnly" description="CLK_M4_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x047C" size="4" name="CLK_M4_EMCDIV_STAT" access="ReadOnly" description="CLK_M4_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0484" size="4" name="CLK_M4_FLASHA_STAT" access="ReadOnly" description="CLK_M4_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048C" size="4" name="CLK_M4_FLASHB_STAT" access="ReadOnly" description="CLK_M4_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0494" size="4" name="CLK_M4_M0APP_STAT" access="ReadOnly" description="CLK_M4_MOAPP clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x049C" size="4" name="CLK_M4_ADCHS_STAT" access="ReadOnly" description="CLK_M4_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A4" size="4" name="CLK_M4_EEPROM_STAT" access="ReadOnly" description="CLK_M4_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504" size="4" name="CLK_M4_WWDT_STAT" access="ReadOnly" description="CLK_M4_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050C" size="4" name="CLK_M4_USART0_STAT" access="ReadOnly" description="CLK_M4_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0514" size="4" name="CLK_M4_UART1_STAT" access="ReadOnly" description="CLK_M4_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x051C" size="4" name="CLK_M4_SSP0_STAT" access="ReadOnly" description="CLK_M4_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0524" size="4" name="CLK_M4_TIMER0_STAT" access="ReadOnly" description="CLK_M4_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x052C" size="4" name="CLK_M4_TIMER1_STAT" access="ReadOnly" description="CLK_M4_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0534" size="4" name="CLK_M4_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x053C" size="4" name="CLK_M4_CREG_STAT" access="ReadOnly" description="CLK_M4_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x604" size="4" name="CLK_M4_RITIMER_STAT" access="ReadOnly" description="CLK_M4_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060C" size="4" name="CLK_M4_USART2_STAT" access="ReadOnly" description="CLK_M4_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0614" size="4" name="CLK_M4_USART3_STAT" access="ReadOnly" description="CLK_M4_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x061C" size="4" name="CLK_M4_TIMER2_STAT" access="ReadOnly" description="CLK_M4_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0624" size="4" name="CLK_M4_TIMER3_STAT" access="ReadOnly" description="CLK_M4_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x062C" size="4" name="CLK_M4_SSP1_STAT" access="ReadOnly" description="CLK_M4_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0634" size="4" name="CLK_M4_QEI_STAT" access="ReadOnly" description="CLK_M4_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_PERIPH_BUS_STAT" access="ReadOnly" description="CLK_PERIPH_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0714" size="4" name="CLK_PERIPH_CORE_STAT" access="ReadOnly" description="CLK_CORE_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x071C" size="4" name="CLK_PERIPH_SGPIO_STAT" access="ReadOnly" description="CLK_CORE_SGPIO_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xA04" size="4" name="CLK_SPI_STAT" access="ReadOnly" description="CLK_SPI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xB04" size="4" name="CLK_ADCHS_STAT" access="ReadOnly" description="CLK_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
-    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
-      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="13" size="1" name="M4_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="24" size="1" name="M0APP_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="25" size="1" name="SGPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="SPI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="1" name="ADCHS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="M4_RST" description="Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-    </Register>
-    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="M0APP_RST" description="Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SGPIO_RST" description="Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="SPI_RST" description="Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="ADCHS_RST" description="Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="M4_RST" description="Current status of the M4_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="24" size="1" name="M0APP_RST" description="Current status of the M0APP_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="25" size="1" name="SGPIO_RST" description="Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="SPI_RST" description="Current status of the SPI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="ADCHS_RST" description="Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x430" size="4" name="RESET_EXT_STAT12" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E0" size="4" name="RESET_EXT_STAT56" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E4" size="4" name="RESET_EXT_STAT57" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E8" size="4" name="RESET_EXT_STAT58" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04F0" size="4" name="RESET_EXT_STAT60" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
-        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
-        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
-        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
-        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
-        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
-        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
-    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
-        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
-        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
-      </BitField>
-      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
-        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
-        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
-      </BitField>
-      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
-        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
-        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
-        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
-        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
-      </BitField>
-      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
-        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
-        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
-      </BitField>
-      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
-      </BitField>
-    </Register>
-    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
-      </BitField>
-      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
-      </BitField>
-      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DAC" description="Select DAC">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
-        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
-      </BitField>
-      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
-      <BitField start="20" size="12" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
-      <BitField start="1" size="31" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
-    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="SGPIO3_DIV" start="0x1" description="SGPIO3_DIV" />
-        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
-        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
-        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
-        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO12_DIV" start="0x1" description="SGPIO12_DIV" />
-        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
-        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
-        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
-        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
-        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
-        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
-        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
-        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
-        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="SGPIO3_DIV" start="0x2" description="SGPIO3_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="SGPIO12" start="0x2" description="SGPIO12" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
-        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
-        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="ADCHS_TRIGGER_IN" access="Read/Write" description="ADCHS trigger input multiplexer (GIMA output 24)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0xA to 0xF are reserved.">
-        <Enum name="GPIO6_28" start="0x0" description="GPIO6[28]" />
-        <Enum name="GPIO5_3" start="0x1" description="GPIO5[3]" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO12" start="0x3" description="SGPIO12" />
-        <Enum name="RESERVED" start="0x4" description="Reserved" />
-        <Enum name="MCOB2" start="0x5" description="MCOB2" />
-        <Enum name="CTOUT_0_OR_T0_MAT0" start="0x6" description="CTOUT_0 or T0_MAT0" />
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x7" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T0_MAT0" start="0x8" description="T0_MAT0" />
-        <Enum name="T2_MAT0" start="0x9" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
-        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time">
-        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
-        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
-        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
-        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
-        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
-        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
-        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
-        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
-        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
-        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADCHS" start="0x400F0000" description="12-bit Analog-to-Digital Converter  High-Speed (ADCHS)">
-    <Register start="+0x0000" size="4" name="FLUSH" access="WriteOnly" description="Flushes FIFO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFO_FLUSH" description="1= fifo is cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="DMA_REQ" access="Read/Write" description="Set or clear DMA write request" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMA_REQ_WR" description="1 = Dma_req_wr is set (initially used to fill second table),  0 = Dma_req_wr is cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0008" size="4" name="FIFO_STS" access="ReadOnly" description="Indicates FIFO fill level status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="LEVEL" description="0 = FIFO is empty  1...15 = FIFO is partially full  16 = FIFO is full" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000C" size="4" name="FIFO_CFG" access="Read/Write" description="Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PACKED_READ" description="0 = one sample is packed in one 32-bit read cycle  1 = two samples are packed in one 32-bit read cycle" />
-      <BitField start="1" size="5" name="LEVEL" description="When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0010" size="4" name="TRIGGER" access="WriteOnly" description="Enable software trigger to start descriptor processing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SW_TRIGGER" description="Auto cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="DSCR_STS" access="Read/Write" description="Indicates active descriptor table and descriptor entry" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACT_TABLE" description="0 = table 0 is active  1 = table 1 is active." />
-      <BitField start="1" size="3" name="ACT_DESCRIPTOR" description="ID of the descriptor that is active." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="POWER_DOWN" access="Read/Write" description="Set or clear power down mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD_CTRL" description="0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set.   1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x001C" size="4" name="CONFIG" access="Read/Write" description="Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." reset_value="0x00002400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TRIGGER__MASK" description="00 = triggers off  01 = software trigger only  10 = external trigger only  11 = both triggers allowed" />
-      <BitField start="2" size="2" name="TRIGGER_MODE" description="00 = rising external trigger  01 = falling external trigger  10 = low external trigger  11 = high external trigger" />
-      <BitField start="4" size="1" name="TRIGGER_SYNC" description="0  = do not synchronize external  trigger input  1 = synchronize external  trigger input" />
-      <BitField start="5" size="1" name="CHANNEL_ID_EN" description="0 = do not add channel ID to FIFO output data  1 = add channel ID to FIFO output data" />
-      <BitField start="6" size="8" name="RECOVERY_TIME" description="ADC recovery time from power down" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0020" size="4" name="THR_A" access="Read/Write" description="Configures window comparator A levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="THR_LOW_A" description="Low Compare Threshold Register A:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="16" size="12" name="THR_HIGH_A" description="High Compare Threshold Register A:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0024" size="4" name="THR_B" access="Read/Write" description="Configures window comparator B levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="THR_LOW_B" description="Low Compare Threshold Register B:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="16" size="12" name="THR_HIGH_B" description="High Compare Threshold Register B:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0028+0" size="4" name="LAST_SAMPLE[0]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+4" size="4" name="LAST_SAMPLE[1]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+8" size="4" name="LAST_SAMPLE[2]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+12" size="4" name="LAST_SAMPLE[3]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+16" size="4" name="LAST_SAMPLE[4]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+20" size="4" name="LAST_SAMPLE[5]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0104" size="4" name="ADC_SPEED" access="Read/Write" description="ADC speed control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DGEC0" description="Speed0" />
-      <BitField start="4" size="4" name="DGEC1" description="Speed1" />
-      <BitField start="8" size="4" name="DGEC2" description="Speed2" />
-      <BitField start="12" size="4" name="DGEC3" description="Speed3" />
-      <BitField start="16" size="4" name="DGEC4" description="Speed4" />
-      <BitField start="20" size="4" name="DGEC5" description="Speed5" />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="POWER_CONTROL" access="Read/Write" description="Configures ADC power vs. speed, DC-in biasing, output format and power gating." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CRS" description="current setting for power versus speed programming" />
-      <BitField start="4" size="6" name="DCINNEG" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_neg side" />
-      <BitField start="10" size="6" name="DCINPOS" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_pos side" />
-      <BitField start="16" size="1" name="TWOS" description="Output data format selection  0 = offset binary  1 = two's complement" />
-      <BitField start="17" size="1" name="POWER_SWITCH" description="0 = ADC is powered down 1 = ADC is active" />
-      <BitField start="18" size="1" name="BGAP_SWITCH" description="0 = ADC band gap reference is powered down  1 = ADC band gap reference is active" />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0200+0" size="4" name="FIFO_OUTPUT[0]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+4" size="4" name="FIFO_OUTPUT[1]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+8" size="4" name="FIFO_OUTPUT[2]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+12" size="4" name="FIFO_OUTPUT[3]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+16" size="4" name="FIFO_OUTPUT[4]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+20" size="4" name="FIFO_OUTPUT[5]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+24" size="4" name="FIFO_OUTPUT[6]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+28" size="4" name="FIFO_OUTPUT[7]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+32" size="4" name="FIFO_OUTPUT[8]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+36" size="4" name="FIFO_OUTPUT[9]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+40" size="4" name="FIFO_OUTPUT[10]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+44" size="4" name="FIFO_OUTPUT[11]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+48" size="4" name="FIFO_OUTPUT[12]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+52" size="4" name="FIFO_OUTPUT[13]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+56" size="4" name="FIFO_OUTPUT[14]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+60" size="4" name="FIFO_OUTPUT[15]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0300+0" size="4" name="DESCRIPTOR0_[0]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+4" size="4" name="DESCRIPTOR0_[1]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+8" size="4" name="DESCRIPTOR0_[2]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+12" size="4" name="DESCRIPTOR0_[3]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+16" size="4" name="DESCRIPTOR0_[4]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+20" size="4" name="DESCRIPTOR0_[5]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+24" size="4" name="DESCRIPTOR0_[6]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+28" size="4" name="DESCRIPTOR0_[7]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+0" size="4" name="DESCRIPTOR1_[0]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+4" size="4" name="DESCRIPTOR1_[1]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+8" size="4" name="DESCRIPTOR1_[2]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+12" size="4" name="DESCRIPTOR1_[3]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+16" size="4" name="DESCRIPTOR1_[4]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+20" size="4" name="DESCRIPTOR1_[5]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+24" size="4" name="DESCRIPTOR1_[6]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+28" size="4" name="DESCRIPTOR1_[7]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0F00" size="4" name="CLR_EN0" access="WriteOnly" description="Interrupt 0 clear mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CEN0" description="Interrupt clear enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F04" size="4" name="SET_EN0" access="WriteOnly" description="Interrupt 0 set mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SEN0" description="Interrupt set enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F08" size="4" name="MASK0" access="ReadOnly" description="Interrupt 0 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="M0" description="Interrupt enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F0C" size="4" name="STATUS0" access="ReadOnly" description="Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFO_FULL" description="0: number of samples in FIFO less than or equal to FIFO_LEVEL  1: number of samples in FIFO is more than FIFO_LEVEL" />
-      <BitField start="1" size="1" name="FIFO_EMPTY" description="0: FIFO is not empty   1: FIFO is empty" />
-      <BitField start="2" size="1" name="FIFO_OVERFLOW" description="FIFO was full; conversion sample is not stored  and lost" />
-      <BitField start="3" size="1" name="DSCR_DONE" description="The descriptor INTERRUPT field was enabled and its sample is converted." />
-      <BitField start="4" size="1" name="DSCR_ERROR" description="The ADC was not fully woken up when a sample was converted and the conversion results is unreliable" />
-      <BitField start="5" size="1" name="ADC_OVF" description="Converted sample value was over range of the 12 bit output code." />
-      <BitField start="6" size="1" name="ADC_UNF" description="Converted sample value was under range of the 12 bit output code." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F10" size="4" name="CLR_STAT0" access="WriteOnly" description="Interrupt 0 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CSTAT0" description="Interrupt clear status" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F14" size="4" name="SET_STAT0" access="WriteOnly" description="Interrupt 0 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SSTAT0" description="Interrupt set status" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F20" size="4" name="CLR_EN1" access="WriteOnly" description="Interrupt 1 mask clear enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="CEN1" description="Interrupt clear enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F24" size="4" name="SET_EN1" access="WriteOnly" description="Interrupt 1 mask set enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SEN1" description="Interrupt set enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F28" size="4" name="MASK1" access="ReadOnly" description="Interrupt 1 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="M1" description="Interrupt enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F2C" size="4" name="STATUS1" access="ReadOnly" description="Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="THCMP_BRANGE0" description="Input channel 0 result below  range" />
-      <BitField start="1" size="1" name="THCMP_ARANGE0" description="Input channel 0 result above range" />
-      <BitField start="2" size="1" name="THCMP_DCROSS0" description="Input channel 0 result  downward threshold crossing detected" />
-      <BitField start="3" size="1" name="THCMP_UCROSS0" description="Input channel 0 result upward threshold crossing detected" />
-      <BitField start="4" size="1" name="OVERRUN_0" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [0]  before it has been read" />
-      <BitField start="5" size="1" name="THCMP_BRANGE1" description="Input channel 1 result below  range" />
-      <BitField start="6" size="1" name="THCMP_ARANGE1" description="Input channel 1 result above range" />
-      <BitField start="7" size="1" name="THCMP_DCROSS1" description="Input channel 1 result  downward threshold crossing detected" />
-      <BitField start="8" size="1" name="THCMP_UCROSS1" description="Input channel 1 result upward threshold crossing detected" />
-      <BitField start="9" size="1" name="OVERRUN_1" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [1]  before it has been read" />
-      <BitField start="10" size="1" name="THCMP_BRANGE2" description="Input channel 2 result below  range" />
-      <BitField start="11" size="1" name="THCMP_ARANGE2" description="Input channel 2 result above range" />
-      <BitField start="12" size="1" name="THCMP_DCROSS2" description="Input channel 2 result  downward threshold crossing detected" />
-      <BitField start="13" size="1" name="THCMP_UCROSS2" description="Input channel 2 result upward threshold crossing detected" />
-      <BitField start="14" size="1" name="OVERRUN_2" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [2]  before it has been read" />
-      <BitField start="15" size="1" name="THCMP_BRANGE3" description="Input channel 3 result below  range" />
-      <BitField start="16" size="1" name="THCMP_ARANGE3" description="Input channel 3 result above range" />
-      <BitField start="17" size="1" name="THCMP_DCROSS3" description="Input channel 3 result  downward threshold crossing detected" />
-      <BitField start="18" size="1" name="THCMP_UCROSS3" description="Input channel 3 result upward threshold crossing detected" />
-      <BitField start="19" size="1" name="OVERRUN_3" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [3]  before it has been read" />
-      <BitField start="20" size="1" name="THCMP_BRANGE4" description="Input channel 4 result below  range" />
-      <BitField start="21" size="1" name="THCMP_ARANGE4" description="Input channel 4 result above range" />
-      <BitField start="22" size="1" name="THCMP_DCROSS4" description="Input channel 4 result  downward threshold crossing detected" />
-      <BitField start="23" size="1" name="THCMP_UCROSS4" description="Input channel 4 result upward threshold crossing detected" />
-      <BitField start="24" size="1" name="OVERRUN_4" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [4]  before it has been read" />
-      <BitField start="25" size="1" name="THCMP_BRANGE5" description="Input channel 5 result below  range" />
-      <BitField start="26" size="1" name="THCMP_ARANGE5" description="Input channel 5 result above range" />
-      <BitField start="27" size="1" name="THCMP_DCROSS5" description="Input channel 5 result  downward threshold crossing detected" />
-      <BitField start="28" size="1" name="THCMP_UCROSS5" description="Input channel 5 result upward threshold crossing detected" />
-      <BitField start="29" size="1" name="OVERRUN_5" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [5]  before it has been read" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F30" size="4" name="CLR_STAT1" access="WriteOnly" description="Interrupt 1 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="CSTAT1" description="Interrupt clear status" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F34" size="4" name="SET_STAT1" access="WriteOnly" description="Interrupt 1 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SSTAT1" description="Interrupt set status" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI" start="0x40100000" description="SPI ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
-        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
-      </BitField>
-      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
-        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
-        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
-      </BitField>
-      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
-        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
-        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
-      </BitField>
-      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
-        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
-        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
-      </BitField>
-      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
-        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
-        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
-      </BitField>
-      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
-        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
-        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
-      </BitField>
-      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
-        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
-        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
-        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
-        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
-        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
-        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
-        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
-        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
-        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
-      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="TCR" access="Read/Write" description="SPI Test Control register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="7" name="TEST" description="SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="TSR" access="Read/Write" description="SPI Test Status register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SGPIO" start="0x40101000" description="Serial GPIO (SGPIO)">
-    <Register start="+0x0000+0" size="4" name="OUT_MUX_CFG[0]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+4" size="4" name="OUT_MUX_CFG[1]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+8" size="4" name="OUT_MUX_CFG[2]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+12" size="4" name="OUT_MUX_CFG[3]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+16" size="4" name="OUT_MUX_CFG[4]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+20" size="4" name="OUT_MUX_CFG[5]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+24" size="4" name="OUT_MUX_CFG[6]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+28" size="4" name="OUT_MUX_CFG[7]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+32" size="4" name="OUT_MUX_CFG[8]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+36" size="4" name="OUT_MUX_CFG[9]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+40" size="4" name="OUT_MUX_CFG[10]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+44" size="4" name="OUT_MUX_CFG[11]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+48" size="4" name="OUT_MUX_CFG[12]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+52" size="4" name="OUT_MUX_CFG[13]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+56" size="4" name="OUT_MUX_CFG[14]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+60" size="4" name="OUT_MUX_CFG[15]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040+0" size="4" name="SGPIO_MUX_CFG[0]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+4" size="4" name="SGPIO_MUX_CFG[1]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+8" size="4" name="SGPIO_MUX_CFG[2]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+12" size="4" name="SGPIO_MUX_CFG[3]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+16" size="4" name="SGPIO_MUX_CFG[4]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+20" size="4" name="SGPIO_MUX_CFG[5]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+24" size="4" name="SGPIO_MUX_CFG[6]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+28" size="4" name="SGPIO_MUX_CFG[7]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+32" size="4" name="SGPIO_MUX_CFG[8]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+36" size="4" name="SGPIO_MUX_CFG[9]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+40" size="4" name="SGPIO_MUX_CFG[10]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+44" size="4" name="SGPIO_MUX_CFG[11]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+48" size="4" name="SGPIO_MUX_CFG[12]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+52" size="4" name="SGPIO_MUX_CFG[13]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+56" size="4" name="SGPIO_MUX_CFG[14]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+60" size="4" name="SGPIO_MUX_CFG[15]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0080+0" size="4" name="SLICE_MUX_CFG[0]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+4" size="4" name="SLICE_MUX_CFG[1]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+8" size="4" name="SLICE_MUX_CFG[2]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+12" size="4" name="SLICE_MUX_CFG[3]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+16" size="4" name="SLICE_MUX_CFG[4]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+20" size="4" name="SLICE_MUX_CFG[5]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+24" size="4" name="SLICE_MUX_CFG[6]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+28" size="4" name="SLICE_MUX_CFG[7]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+32" size="4" name="SLICE_MUX_CFG[8]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+36" size="4" name="SLICE_MUX_CFG[9]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+40" size="4" name="SLICE_MUX_CFG[10]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+44" size="4" name="SLICE_MUX_CFG[11]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+48" size="4" name="SLICE_MUX_CFG[12]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+52" size="4" name="SLICE_MUX_CFG[13]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+56" size="4" name="SLICE_MUX_CFG[14]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+60" size="4" name="SLICE_MUX_CFG[15]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C0+0" size="4" name="REG[0]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+4" size="4" name="REG[1]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+8" size="4" name="REG[2]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+12" size="4" name="REG[3]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+16" size="4" name="REG[4]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+20" size="4" name="REG[5]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+24" size="4" name="REG[6]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+28" size="4" name="REG[7]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+32" size="4" name="REG[8]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+36" size="4" name="REG[9]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+40" size="4" name="REG[10]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+44" size="4" name="REG[11]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+48" size="4" name="REG[12]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+52" size="4" name="REG[13]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+56" size="4" name="REG[14]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+60" size="4" name="REG[15]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x0100+0" size="4" name="REG_SS[0]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+4" size="4" name="REG_SS[1]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+8" size="4" name="REG_SS[2]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+12" size="4" name="REG_SS[3]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+16" size="4" name="REG_SS[4]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+20" size="4" name="REG_SS[5]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+24" size="4" name="REG_SS[6]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+28" size="4" name="REG_SS[7]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+32" size="4" name="REG_SS[8]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+36" size="4" name="REG_SS[9]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+40" size="4" name="REG_SS[10]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+44" size="4" name="REG_SS[11]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+48" size="4" name="REG_SS[12]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+52" size="4" name="REG_SS[13]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+56" size="4" name="REG_SS[14]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+60" size="4" name="REG_SS[15]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0140+0" size="4" name="PRESET[0]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+4" size="4" name="PRESET[1]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+8" size="4" name="PRESET[2]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+12" size="4" name="PRESET[3]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+16" size="4" name="PRESET[4]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+20" size="4" name="PRESET[5]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+24" size="4" name="PRESET[6]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+28" size="4" name="PRESET[7]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+32" size="4" name="PRESET[8]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+36" size="4" name="PRESET[9]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+40" size="4" name="PRESET[10]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+44" size="4" name="PRESET[11]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+48" size="4" name="PRESET[12]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+52" size="4" name="PRESET[13]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+56" size="4" name="PRESET[14]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+60" size="4" name="PRESET[15]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+0" size="4" name="COUNT[0]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+4" size="4" name="COUNT[1]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+8" size="4" name="COUNT[2]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+12" size="4" name="COUNT[3]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+16" size="4" name="COUNT[4]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+20" size="4" name="COUNT[5]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+24" size="4" name="COUNT[6]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+28" size="4" name="COUNT[7]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+32" size="4" name="COUNT[8]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+36" size="4" name="COUNT[9]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+40" size="4" name="COUNT[10]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+44" size="4" name="COUNT[11]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+48" size="4" name="COUNT[12]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+52" size="4" name="COUNT[13]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+56" size="4" name="COUNT[14]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+60" size="4" name="COUNT[15]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+0" size="4" name="POS[0]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+4" size="4" name="POS[1]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+8" size="4" name="POS[2]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+12" size="4" name="POS[3]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+16" size="4" name="POS[4]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+20" size="4" name="POS[5]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+24" size="4" name="POS[6]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+28" size="4" name="POS[7]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+32" size="4" name="POS[8]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+36" size="4" name="POS[9]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+40" size="4" name="POS[10]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+44" size="4" name="POS[11]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+48" size="4" name="POS[12]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+52" size="4" name="POS[13]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+56" size="4" name="POS[14]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+60" size="4" name="POS[15]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0200" size="4" name="MASK_A" access="Read/Write" description="Mask for pattern match function of slice A" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_A" description="Mask for pattern match function of slice A  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0204" size="4" name="MASK_H" access="Read/Write" description="Mask for pattern match function of slice H" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_H" description="Mask for pattern match function of slice H  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0208" size="4" name="MASK_I" access="Read/Write" description="Mask for pattern match function of slice I" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_I" description="Mask for pattern match function of slice I  0 = No effect . 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x020C" size="4" name="MASK_P" access="Read/Write" description="Mask for pattern match function of slice P" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_P" description="Mask for pattern match function of slice P  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0210" size="4" name="GPIO_INREG" access="ReadOnly" description="GPIO input status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_INi" description="Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0214" size="4" name="GPIO_OUTREG" access="Read/Write" description="GPIO output control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_OUT" description="GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0218" size="4" name="GPIO_OENREG" access="Read/Write" description="GPIO OE control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_OE" description="Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x021C" size="4" name="CTRL_ENABLE" access="Read/Write" description="Enables the slice COUNT counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTRL_EN" description="Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0220" size="4" name="CTRL_DISABLE" access="Read/Write" description="Disables the slice POS counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTRL_DIS" description="Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F00" size="4" name="CLR_EN_0" access="WriteOnly" description="Shift clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_SCI" description="1 = Shift clock interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F04" size="4" name="SET_EN_0" access="WriteOnly" description="Shift clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_SCI" description="1 = Shift clock interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F08" size="4" name="ENABLE_0" access="ReadOnly" description="Shift clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_SCI" description="1 = Shift clock interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F0C" size="4" name="STATUS_0" access="ReadOnly" description="Shift clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_SCI" description="Shift clock interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F10" size="4" name="CLR_STATUS_0" access="WriteOnly" description="Shift clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_SCI" description="Shift clock interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F14" size="4" name="SET_STATUS_0" access="WriteOnly" description="Shift clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_SCI" description="Shift clock interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F20" size="4" name="CLR_EN_1" access="WriteOnly" description="Exchange clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN_CCI" description="1 = Exchange clock interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F24" size="4" name="SET_EN_1" access="WriteOnly" description="Exchange clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_CCI" description="1 = Exchange clock interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F28" size="4" name="ENABLE_1" access="ReadOnly" description="Exchange clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_CCI" description="Exchange clock interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F2C" size="4" name="STATUS_1" access="ReadOnly" description="Exchange clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_CCI" description="Exchange clock interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F30" size="4" name="CLR_STATUS_1" access="WriteOnly" description="Exchange clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_CCI" description="Exchange clock interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F34" size="4" name="SET_STATUS_1" access="WriteOnly" description="Exchange clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_CCI" description="Exchange clock interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F40" size="4" name="CLR_EN_2" access="WriteOnly" description="Pattern match interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN2_PMI" description="1 = Match interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F44" size="4" name="SET_EN_2" access="WriteOnly" description="Pattern match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_PMI" description="1 = Match interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F48" size="4" name="ENABLE_2" access="ReadOnly" description="Pattern match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_PMI" description="Match interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F4C" size="4" name="STATUS_2" access="ReadOnly" description="Pattern match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_PMI" description="Match interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F50" size="4" name="CLR_STATUS_2" access="WriteOnly" description="Pattern match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_PMI" description="Match interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F54" size="4" name="SET_STATUS_2" access="WriteOnly" description="Pattern match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_PMI" description="Match interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F60" size="4" name="CLR_EN_3" access="WriteOnly" description="Input interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN_INPI" description="1 = Input interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F64" size="4" name="SET_EN_3" access="WriteOnly" description="Input bit match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_INPI" description="1 = Input interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F68" size="4" name="ENABLE_3" access="ReadOnly" description="Input bit match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE3_INPI" description="Input interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F6C" size="4" name="STATUS_3" access="ReadOnly" description="Input bit match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_INPI" description="Input interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F70" size="4" name="CLR_STATUS_3" access="WriteOnly" description="Input bit match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_INPI" description="Input interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F74" size="4" name="SET_STATUS_3" access="WriteOnly" description="Input bit match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_INPI" description="Shift interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="DAC" start="5" size="3" />
-      <BitField name="DMA" start="21" size="3" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="FLASH" start="5" size="3" />
-      <BitField name="ETHERNET" start="13" size="3" />
-      <BitField name="SDIO" start="21" size="3" />
-      <BitField name="LCD" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="USB0" start="5" size="3" />
-      <BitField name="USB1" start="13" size="3" />
-      <BitField name="SCT" start="21" size="3" />
-      <BitField name="RITIMER" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TIMER0" start="5" size="3" />
-      <BitField name="TIMER1" start="13" size="3" />
-      <BitField name="TIMER2" start="21" size="3" />
-      <BitField name="TIMER3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="MCPWM" start="5" size="3" />
-      <BitField name="ADC0" start="13" size="3" />
-      <BitField name="I2C0" start="21" size="3" />
-      <BitField name="I2C1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SPI_INT" start="5" size="3" />
-      <BitField name="ADC1" start="13" size="3" />
-      <BitField name="SSP0" start="21" size="3" />
-      <BitField name="SSP1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USART0" start="5" size="3" />
-      <BitField name="UART1" start="13" size="3" />
-      <BitField name="USART2" start="21" size="3" />
-      <BitField name="USART3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="I2S0" start="5" size="3" />
-      <BitField name="I2S1" start="13" size="3" />
-      <BitField name="SPIFI" start="21" size="3" />
-      <BitField name="SGPIO_IINT" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PIN_INT0" start="5" size="3" />
-      <BitField name="PIN_INT1" start="13" size="3" />
-      <BitField name="PIN_INT2" start="21" size="3" />
-      <BitField name="PIN_INT3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="PIN_INT4" start="5" size="3" />
-      <BitField name="PIN_INT5" start="13" size="3" />
-      <BitField name="PIN_INT6" start="21" size="3" />
-      <BitField name="PIN_INT7" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="GINT0" start="5" size="3" />
-      <BitField name="GINT1" start="13" size="3" />
-      <BitField name="EVENTROUTER" start="21" size="3" />
-      <BitField name="C_CAN1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="ADCHS" start="13" size="3" />
-      <BitField name="ATIMER" start="21" size="3" />
-      <BitField name="RTC" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
-      <BitField name="WWDT" start="13" size="3" />
-      <BitField name="C_CAN0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
-      <BitField name="QEI" start="5" size="3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FPU" description="Floating Point Unit">
-    <Register name="CPACR" start="0xE000ED88" description="Coprocessor Access Control Register">
-      <BitField name="CP11" start="22" size="2" description="Access privileges for coprocessor 11" />
-      <BitField name="CP10" start="20" size="2" description="Access privileges for coprocessor 10" />
-    </Register>
-    <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register">
-      <BitField name="ASPEN" start="31" size="1" description="Automatic State Preservation" />
-      <BitField name="LSPEN" start="30" size="1" description="Lazy State Preservation Enabled" />
-      <BitField name="MONRDY" start="8" size="1" description="Monitor Ready" />
-      <BitField name="BFRDY" start="6" size="1" description="BusFault Ready" />
-      <BitField name="MMRDY" start="5" size="1" description="MemManage Ready" />
-      <BitField name="HFRDY" start="4" size="1" description="HardFault Ready" />
-      <BitField name="THREAD" start="3" size="1" description="Thread Mode Allocated Stack Frame" />
-      <BitField name="USER" start="1" size="1" description="User Allocated Stack Frame" />
-      <BitField name="LSPACT" start="0" size="1" description="Lazy State Preservation Active" />
-    </Register>
-    <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register">
-      <BitField name="ADDRESSS" start="3" size="29" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" />
-    </Register>
-    <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Status Control Register">
-      <BitField name="N" start="31" size="1" description="Negative condition code flag" />
-      <BitField name="Z" start="30" size="1" description="Zero condition code flag" />
-      <BitField name="C" start="29" size="1" description="Carry condition code flag" />
-      <BitField name="V" start="28" size="1" description="Overflow condition code flag" />
-      <BitField name="AHP" start="26" size="1" description="Alternative half-precision control bit" />
-      <BitField name="DN" start="25" size="1" description="Default NaN mode control bit" />
-      <BitField name="FZ" start="24" size="1" description="Flush-to-zero mode control bit" />
-      <BitField name="RMode" start="22" size="2" description="Rounding Mode control field" />
-      <BitField name="IDC" start="7" size="1" description="Input Denormal cumulative exception bit" />
-      <BitField name="IXC" start="4" size="1" description="Inexact cumulative exception bit" />
-      <BitField name="UFC" start="3" size="1" description="Underflow cumulative exception bit" />
-      <BitField name="OFC" start="2" size="1" description="Overflow cumulative exception bit" />
-      <BitField name="DZC" start="1" size="1" description="Division by Zero cumulative exception bit" />
-      <BitField name="IOC" start="0" size="1" description="Invalid Operation cumulative exception bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Vectors.s b/examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Vectors.s
deleted file mode 100644
index ab223b8a..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/LPC43xx_Vectors.s
+++ /dev/null
@@ -1,540 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak USB0_IRQHandler
-  .thumb_set USB0_IRQHandler,Dummy_Handler
-
-  .weak USB1_IRQHandler
-  .thumb_set USB1_IRQHandler,Dummy_Handler
-
-  .weak SCT_IRQHandler
-  .thumb_set SCT_IRQHandler,Dummy_Handler
-
-  .weak RITIMER_IRQHandler
-  .thumb_set RITIMER_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak ADC0_IRQHandler
-  .thumb_set ADC0_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak SPI_INT_IRQHandler
-  .thumb_set SPI_INT_IRQHandler,Dummy_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak USART0_IRQHandler
-  .thumb_set USART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Dummy_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Dummy_Handler
-
-  .weak I2S0_IRQHandler
-  .thumb_set I2S0_IRQHandler,Dummy_Handler
-
-  .weak I2S1_IRQHandler
-  .thumb_set I2S1_IRQHandler,Dummy_Handler
-
-  .weak SPIFI_IRQHandler
-  .thumb_set SPIFI_IRQHandler,Dummy_Handler
-
-  .weak SGPIO_IINT_IRQHandler
-  .thumb_set SGPIO_IINT_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak EVENTROUTER_IRQHandler
-  .thumb_set EVENTROUTER_IRQHandler,Dummy_Handler
-
-  .weak C_CAN1_IRQHandler
-  .thumb_set C_CAN1_IRQHandler,Dummy_Handler
-
-  .weak ADCHS_IRQHandler
-  .thumb_set ADCHS_IRQHandler,Dummy_Handler
-
-  .weak ATIMER_IRQHandler
-  .thumb_set ATIMER_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak C_CAN0_IRQHandler
-  .thumb_set C_CAN0_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak DAC_IRQHandler
-DAC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDIO_IRQHandler
-SDIO_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB0_IRQHandler
-USB0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB1_IRQHandler
-USB1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SCT_IRQHandler
-SCT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RITIMER_IRQHandler
-RITIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC0_IRQHandler
-ADC0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI_INT_IRQHandler
-SPI_INT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC1_IRQHandler
-ADC1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART0_IRQHandler
-USART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_IRQHandler
-USART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART3_IRQHandler
-USART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S0_IRQHandler
-I2S0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S1_IRQHandler
-I2S1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPIFI_IRQHandler
-SPIFI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SGPIO_IINT_IRQHandler
-SGPIO_IINT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EVENTROUTER_IRQHandler
-EVENTROUTER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN1_IRQHandler
-C_CAN1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADCHS_IRQHandler
-ADCHS_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ATIMER_IRQHandler
-ATIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN0_IRQHandler
-C_CAN0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word DAC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word DMA_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word FLASH_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDIO_IRQHandler
-  .word LCD_IRQHandler
-  .word USB0_IRQHandler
-  .word USB1_IRQHandler
-  .word SCT_IRQHandler
-  .word RITIMER_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word MCPWM_IRQHandler
-  .word ADC0_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word SPI_INT_IRQHandler
-  .word ADC1_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word USART0_IRQHandler
-  .word UART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word I2S0_IRQHandler
-  .word I2S1_IRQHandler
-  .word SPIFI_IRQHandler
-  .word SGPIO_IINT_IRQHandler
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word EVENTROUTER_IRQHandler
-  .word C_CAN1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word ADCHS_IRQHandler
-  .word ATIMER_IRQHandler
-  .word RTC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word WWDT_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word C_CAN0_IRQHandler
-  .word QEI_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/lpc43xx/flash_placement.xml b/examples/device/cdc_msc/ses/lpc43xx/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/lpc43xx/lpc43xx.emProject b/examples/device/cdc_msc/ses/lpc43xx/lpc43xx.emProject
deleted file mode 100644
index f751a432..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/lpc43xx.emProject
+++ /dev/null
@@ -1,136 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc43xx" target="8" version="2">
-  <project Name="lpc43xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4357 Cortex-M4"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 1a000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC4357_M4"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_LPC43XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/config_43xx;$(rootDir)/src;$(lpcDir)//inc"
-      debug_register_definition_file="LPC43xx_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="LPC4357 Cortex-M4_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x1a000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../.."
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/LPC4300_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="ea4357">
-          <file file_name="../../../../../hw/bsp/ea4357/pca9532.c" />
-          <file file_name="../../../../../hw/bsp/ea4357/pca9532.h" />
-          <file file_name="../../../../../hw/bsp/ea4357/ea4357.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_43xx">
-              <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/arm_common_tables.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/arm_math.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/cguccu_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/chip.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/chip_clocks.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/chip_lpc18xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/chip_lpc43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/clock_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/cmsis.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/cmsis_18xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/cmsis_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/cmsis_43xx_m0app.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cm0.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cm0plus.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cm3.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cm4.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cm4_simd.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cmFunc.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_cmInstr.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_sc000.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/core_sc300.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/creg_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/fpu_init.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/gpio_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/i2c_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/i2cm_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/lpc_types.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/packing.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/uart_18xx_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/usbhs_18xx_43xx.h" />
-                <folder Name="config_43xx">
-                  <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h" />
-                  <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/inc/config_43xx/sys_config.h" />
-                </folder>
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/chip_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/clock_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/fpu_init.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/gpio_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/i2c_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/i2cm_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/sysinit_18xx_43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_43xx/src/uart_18xx_43xx.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC4300_Startup.s" />
-      <file file_name="LPC4300_Target.js" />
-      <file file_name="LPC4357 Cortex-M4_MemoryMap.xml" />
-      <file file_name="LPC43xx_Registers.xml" />
-      <file file_name="LPC43xx_Vectors.s" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <configuration Name="EA4357" c_preprocessor_definitions="BOARD_EA4357" />
-  </project>
-  <configuration Name="EA4357" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/lpc43xx/thumb_crt0.s b/examples/device/cdc_msc/ses/lpc43xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/lpc43xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/nrf5x/flash_placement.xml b/examples/device/cdc_msc/ses/nrf5x/flash_placement.xml
deleted file mode 100644
index 951d2371..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml b/examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml
deleted file mode 100644
index cc4056c0..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="nRF52840_xxAA">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00100000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20000000" size="0x00040000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_s140v6_MemoryMap.xml b/examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_s140v6_MemoryMap.xml
deleted file mode 100644
index 48aad06a..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/nRF52840_xxAA_s140v6_MemoryMap.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="nRF52840_xxAA_s140v6">
-  <MemorySegment name="FLASH" start="0x00026000" size="0x000C7000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20004000" size="0x0003C000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/nrf5x/nRF_Target.js b/examples/device/cdc_msc/ses/nrf5x/nRF_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/nRF_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/nrf5x/nrf52840_Registers.xml b/examples/device/cdc_msc/ses/nrf5x/nrf52840_Registers.xml
deleted file mode 100644
index 39f861f9..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/nrf52840_Registers.xml
+++ /dev/null
@@ -1,22310 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="nrf52840" description="nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller ">
-  <RegisterGroup name="FICR" start="0x10000000" description="Factory information configuration registers">
-    <Register start="+0x010" size="4" name="CODEPAGESIZE" access="ReadOnly" description="Code memory page size" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CODEPAGESIZE" description="Code memory page size" />
-    </Register>
-    <Register start="+0x014" size="4" name="CODESIZE" access="ReadOnly" description="Code memory size" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CODESIZE" description="Code memory size in number of pages" />
-    </Register>
-    <Register start="+0x060+0" size="4" name="DEVICEID[0]" access="ReadOnly" description="Description collection[0]:  Device identifier" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEID" description="64 bit unique device identifier" />
-    </Register>
-    <Register start="+0x060+4" size="4" name="DEVICEID[1]" access="ReadOnly" description="Description collection[0]:  Device identifier" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEID" description="64 bit unique device identifier" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="ER[0]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="ER[1]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="ER[2]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="ER[3]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x090+0" size="4" name="IR[0]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x090+4" size="4" name="IR[1]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x090+8" size="4" name="IR[2]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x090+12" size="4" name="IR[3]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="DEVICEADDRTYPE" access="ReadOnly" description="Device address type" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEVICEADDRTYPE" description="Device address type">
-        <Enum name="Public" start="0" description="Public address" />
-        <Enum name="Random" start="1" description="Random address" />
-      </BitField>
-    </Register>
-    <Register start="+0x0A4+0" size="4" name="DEVICEADDR[0]" access="ReadOnly" description="Description collection[0]:  Device address 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEADDR" description="48 bit device address" />
-    </Register>
-    <Register start="+0x0A4+4" size="4" name="DEVICEADDR[1]" access="ReadOnly" description="Description collection[0]:  Device address 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEADDR" description="48 bit device address" />
-    </Register>
-    <Register start="+0x100+0x000" size="4" name="INFO.PART" access="ReadOnly" description="Part code" reset_value="0x00052840" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PART" description="Part code">
-        <Enum name="N52840" start="0x52840" description="nRF52840" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x004" size="4" name="INFO.VARIANT" access="ReadOnly" description="Part variant (hardware version and production configuration)" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VARIANT" description="Part variant (hardware version and production configuration). Encoded as ASCII.">
-        <Enum name="AAAA" start="0x41414141" description="AAAA" />
-        <Enum name="AAAB" start="0x41414142" description="AAAB" />
-        <Enum name="AABA" start="0x41414241" description="AABA" />
-        <Enum name="AABB" start="0x41414242" description="AABB" />
-        <Enum name="AAB0" start="0x41414230" description="AAB0" />
-        <Enum name="ABBA" start="0x41424241" description="ABBA" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x008" size="4" name="INFO.PACKAGE" access="ReadOnly" description="Package option" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PACKAGE" description="Package option">
-        <Enum name="QI" start="0x2004" description="QIxx - 73-pin aQFN" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x00C" size="4" name="INFO.RAM" access="ReadOnly" description="RAM variant" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RAM" description="RAM variant">
-        <Enum name="K16" start="0x10" description="16 kByte RAM" />
-        <Enum name="K32" start="0x20" description="32 kByte RAM" />
-        <Enum name="K64" start="0x40" description="64 kByte RAM" />
-        <Enum name="K128" start="0x80" description="128 kByte RAM" />
-        <Enum name="K256" start="0x100" description="256 kByte RAM" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x010" size="4" name="INFO.FLASH" access="ReadOnly" description="Flash variant" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FLASH" description="Flash variant">
-        <Enum name="K128" start="0x80" description="128 kByte FLASH" />
-        <Enum name="K256" start="0x100" description="256 kByte FLASH" />
-        <Enum name="K512" start="0x200" description="512 kByte FLASH" />
-        <Enum name="K1024" start="0x400" description="1 MByte FLASH" />
-        <Enum name="K2048" start="0x800" description="2 MByte FLASH" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x014+0" size="4" name="INFO.UNUSED0[0]" access="Read/Write" description="Description collection[0]: Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0x014+4" size="4" name="INFO.UNUSED0[1]" access="Read/Write" description="Description collection[0]: Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0x014+8" size="4" name="INFO.UNUSED0[2]" access="Read/Write" description="Description collection[0]: Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x404+0x000" size="4" name="TEMP.A0" access="ReadOnly" description="Slope definition A0" reset_value="0xFFFFF320" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x004" size="4" name="TEMP.A1" access="ReadOnly" description="Slope definition A1" reset_value="0xFFFFF343" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x008" size="4" name="TEMP.A2" access="ReadOnly" description="Slope definition A2" reset_value="0xFFFFF35D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x00C" size="4" name="TEMP.A3" access="ReadOnly" description="Slope definition A3" reset_value="0xFFFFF400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x010" size="4" name="TEMP.A4" access="ReadOnly" description="Slope definition A4" reset_value="0xFFFFF452" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x014" size="4" name="TEMP.A5" access="ReadOnly" description="Slope definition A5" reset_value="0xFFFFF37B" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x018" size="4" name="TEMP.B0" access="ReadOnly" description="Y-intercept B0" reset_value="0xFFFF3FCC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x01C" size="4" name="TEMP.B1" access="ReadOnly" description="Y-intercept B1" reset_value="0xFFFF3F98" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x020" size="4" name="TEMP.B2" access="ReadOnly" description="Y-intercept B2" reset_value="0xFFFF3F98" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x024" size="4" name="TEMP.B3" access="ReadOnly" description="Y-intercept B3" reset_value="0xFFFF0012" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x028" size="4" name="TEMP.B4" access="ReadOnly" description="Y-intercept B4" reset_value="0xFFFF004D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x02C" size="4" name="TEMP.B5" access="ReadOnly" description="Y-intercept B5" reset_value="0xFFFF3E10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x030" size="4" name="TEMP.T0" access="ReadOnly" description="Segment end T0" reset_value="0xFFFFFFE2" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x034" size="4" name="TEMP.T1" access="ReadOnly" description="Segment end T1" reset_value="0xFFFFFF00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x038" size="4" name="TEMP.T2" access="ReadOnly" description="Segment end T2" reset_value="0xFFFFFF14" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x03C" size="4" name="TEMP.T3" access="ReadOnly" description="Segment end T3" reset_value="0xFFFFFF19" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x040" size="4" name="TEMP.T4" access="ReadOnly" description="Segment end T4" reset_value="0xFFFFFF50" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x450+0x000" size="4" name="NFC.TAGHEADER0" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFF5F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MFGID" description="Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F" />
-      <BitField start="8" size="8" name="UD1" description="Unique identifier byte 1" />
-      <BitField start="16" size="8" name="UD2" description="Unique identifier byte 2" />
-      <BitField start="24" size="8" name="UD3" description="Unique identifier byte 3" />
-    </Register>
-    <Register start="+0x450+0x004" size="4" name="NFC.TAGHEADER1" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="UD4" description="Unique identifier byte 4" />
-      <BitField start="8" size="8" name="UD5" description="Unique identifier byte 5" />
-      <BitField start="16" size="8" name="UD6" description="Unique identifier byte 6" />
-      <BitField start="24" size="8" name="UD7" description="Unique identifier byte 7" />
-    </Register>
-    <Register start="+0x450+0x008" size="4" name="NFC.TAGHEADER2" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="UD8" description="Unique identifier byte 8" />
-      <BitField start="8" size="8" name="UD9" description="Unique identifier byte 9" />
-      <BitField start="16" size="8" name="UD10" description="Unique identifier byte 10" />
-      <BitField start="24" size="8" name="UD11" description="Unique identifier byte 11" />
-    </Register>
-    <Register start="+0x450+0x00C" size="4" name="NFC.TAGHEADER3" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="UD12" description="Unique identifier byte 12" />
-      <BitField start="8" size="8" name="UD13" description="Unique identifier byte 13" />
-      <BitField start="16" size="8" name="UD14" description="Unique identifier byte 14" />
-      <BitField start="24" size="8" name="UD15" description="Unique identifier byte 15" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UICR" start="0x10001000" description="User information configuration registers">
-    <Register start="+0x000" size="4" name="UNUSED0" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="UNUSED1" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="UNUSED2" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="UNUSED3" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014+0" size="4" name="NRFFW[0]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+4" size="4" name="NRFFW[1]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+8" size="4" name="NRFFW[2]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+12" size="4" name="NRFFW[3]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+16" size="4" name="NRFFW[4]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+20" size="4" name="NRFFW[5]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+24" size="4" name="NRFFW[6]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+28" size="4" name="NRFFW[7]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+32" size="4" name="NRFFW[8]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+36" size="4" name="NRFFW[9]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+40" size="4" name="NRFFW[10]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+44" size="4" name="NRFFW[11]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+48" size="4" name="NRFFW[12]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+52" size="4" name="NRFFW[13]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+56" size="4" name="NRFFW[14]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x050+0" size="4" name="NRFHW[0]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+4" size="4" name="NRFHW[1]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+8" size="4" name="NRFHW[2]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+12" size="4" name="NRFHW[3]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+16" size="4" name="NRFHW[4]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+20" size="4" name="NRFHW[5]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+24" size="4" name="NRFHW[6]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+28" size="4" name="NRFHW[7]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+32" size="4" name="NRFHW[8]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+36" size="4" name="NRFHW[9]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+40" size="4" name="NRFHW[10]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+44" size="4" name="NRFHW[11]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="CUSTOMER[0]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="CUSTOMER[1]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="CUSTOMER[2]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="CUSTOMER[3]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="CUSTOMER[4]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="CUSTOMER[5]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="CUSTOMER[6]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="CUSTOMER[7]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="CUSTOMER[8]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="CUSTOMER[9]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="CUSTOMER[10]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="CUSTOMER[11]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="CUSTOMER[12]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="CUSTOMER[13]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="CUSTOMER[14]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="CUSTOMER[15]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="CUSTOMER[16]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+68" size="4" name="CUSTOMER[17]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+72" size="4" name="CUSTOMER[18]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+76" size="4" name="CUSTOMER[19]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+80" size="4" name="CUSTOMER[20]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+84" size="4" name="CUSTOMER[21]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+88" size="4" name="CUSTOMER[22]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+92" size="4" name="CUSTOMER[23]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+96" size="4" name="CUSTOMER[24]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+100" size="4" name="CUSTOMER[25]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+104" size="4" name="CUSTOMER[26]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+108" size="4" name="CUSTOMER[27]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+112" size="4" name="CUSTOMER[28]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+116" size="4" name="CUSTOMER[29]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+120" size="4" name="CUSTOMER[30]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+124" size="4" name="CUSTOMER[31]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PSELRESET[0]" access="Read/Write" description="Description collection[0]:  Mapping of the nRESET function" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number of PORT onto which nRESET is exposed" />
-      <BitField start="5" size="1" name="PORT" description="Port number onto which nRESET is exposed" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x200+4" size="4" name="PSELRESET[1]" access="Read/Write" description="Description collection[0]:  Mapping of the nRESET function" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number of PORT onto which nRESET is exposed" />
-      <BitField start="5" size="1" name="PORT" description="Port number onto which nRESET is exposed" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x208" size="4" name="APPROTECT" access="Read/Write" description="Access port protection" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PALL" description="Enable or disable access port protection.">
-        <Enum name="Disabled" start="0xFF" description="Disable" />
-        <Enum name="Enabled" start="0x00" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x20C" size="4" name="NFCPINS" access="Read/Write" description="Setting of pins dedicated to NFC functionality: NFC antenna or GPIO" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PROTECT" description="Setting of pins dedicated to NFC functionality">
-        <Enum name="Disabled" start="0" description="Operation as GPIO pins. Same protection as normal GPIO pins" />
-        <Enum name="NFC" start="1" description="Operation as NFC antenna pins. Configures the protection for NFC operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x210" size="4" name="DEBUGCTRL" access="Read/Write" description="Processor debug control" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPUNIDEN" description="Configure CPU non-intrusive debug features">
-        <Enum name="Enabled" start="0xFF" description="Enable CPU ITM and ETM functionality (default behavior)" />
-        <Enum name="Disabled" start="0x00" description="Disable CPU ITM and ETM functionality" />
-      </BitField>
-      <BitField start="8" size="8" name="CPUFPBEN" description="Configure CPU flash patch and breakpoint (FPB) unit behavior">
-        <Enum name="Enabled" start="0xFF" description="Enable CPU FPB unit (default behavior)" />
-        <Enum name="Disabled" start="0x00" description="Disable CPU FPB unit. Writes into the FPB registers will be ignored." />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="EXTSUPPLY" access="Read/Write" description="Enable external circuitry to be supplied from VDD pin. Applicable in high voltage mode only." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTSUPPLY" description="Enable external circuitry to be supplied from VDD pin (output of REG0 stage)">
-        <Enum name="Disabled" start="0" description="No current can be drawn from the VDD pin" />
-        <Enum name="Enabled" start="1" description="It is allowed to supply external circuitry from the VDD pin" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="REGOUT0" access="Read/Write" description="GPIO reference voltage / external output supply voltage in high voltage mode" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="VOUT" description="Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.">
-        <Enum name="1V8" start="0" description="1.8 V" />
-        <Enum name="2V1" start="1" description="2.1 V" />
-        <Enum name="2V4" start="2" description="2.4 V" />
-        <Enum name="2V7" start="3" description="2.7 V" />
-        <Enum name="3V0" start="4" description="3.0 V" />
-        <Enum name="3V3" start="5" description="3.3 V" />
-        <Enum name="DEFAULT" start="7" description="Default voltage: 1.8 V" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="POWER" start="0x40000000" description="Power control">
-    <Register start="+0x078" size="4" name="TASKS_CONSTLAT" access="WriteOnly" description="Enable constant latency mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x07C" size="4" name="TASKS_LOWPWR" access="WriteOnly" description="Enable low power mode (variable latency)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_POFWARN" access="Read/Write" description="Power failure warning" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_SLEEPENTER" access="Read/Write" description="CPU entered WFI/WFE sleep" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_SLEEPEXIT" access="Read/Write" description="CPU exited WFI/WFE sleep" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_USBDETECTED" access="Read/Write" description="Voltage supply detected on VBUS" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_USBREMOVED" access="Read/Write" description="Voltage supply removed from VBUS" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_USBPWRRDY" access="Read/Write" description="USB 3.3 V supply ready" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="POFWARN" description="Write '1' to Enable interrupt for POFWARN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SLEEPENTER" description="Write '1' to Enable interrupt for SLEEPENTER event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="SLEEPEXIT" description="Write '1' to Enable interrupt for SLEEPEXIT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="USBDETECTED" description="Write '1' to Enable interrupt for USBDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="USBREMOVED" description="Write '1' to Enable interrupt for USBREMOVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="USBPWRRDY" description="Write '1' to Enable interrupt for USBPWRRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="POFWARN" description="Write '1' to Disable interrupt for POFWARN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SLEEPENTER" description="Write '1' to Disable interrupt for SLEEPENTER event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="SLEEPEXIT" description="Write '1' to Disable interrupt for SLEEPEXIT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="USBDETECTED" description="Write '1' to Disable interrupt for USBDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="USBREMOVED" description="Write '1' to Disable interrupt for USBREMOVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="USBPWRRDY" description="Write '1' to Disable interrupt for USBPWRRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RESETREAS" access="Read/Write" description="Reset reason" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESETPIN" description="Reset from pin-reset detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="1" size="1" name="DOG" description="Reset from watchdog detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="2" size="1" name="SREQ" description="Reset from soft reset detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="3" size="1" name="LOCKUP" description="Reset from CPU lock-up detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="16" size="1" name="OFF" description="Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="17" size="1" name="LPCOMP" description="Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="18" size="1" name="DIF" description="Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="19" size="1" name="NFC" description="Reset due to wake up from System OFF mode by NFC field detect">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="20" size="1" name="VBUS" description="Reset due to wake up from System OFF mode by Vbus rising into valid range">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-    </Register>
-    <Register start="+0x428" size="4" name="RAMSTATUS" access="ReadOnly" description="Deprecated register -  RAM status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAMBLOCK0" description="RAM block 0 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="RAMBLOCK1" description="RAM block 1 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="RAMBLOCK2" description="RAM block 2 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="RAMBLOCK3" description="RAM block 3 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x438" size="4" name="USBREGSTATUS" access="ReadOnly" description="USB supply status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VBUSDETECT" description="VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)">
-        <Enum name="NoVbus" start="0" description="VBUS voltage below valid threshold" />
-        <Enum name="VbusPresent" start="1" description="VBUS voltage above valid threshold" />
-      </BitField>
-      <BitField start="1" size="1" name="OUTPUTRDY" description="USB supply output settling time elapsed">
-        <Enum name="NotReady" start="0" description="USBREG output settling time not elapsed" />
-        <Enum name="Ready" start="1" description="USBREG output settling time elapsed (same information as USBPWRRDY event)" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="SYSTEMOFF" access="WriteOnly" description="System OFF register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYSTEMOFF" description="Enable System OFF mode">
-        <Enum name="Enter" start="1" description="Enable System OFF mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="POFCON" access="Read/Write" description="Power failure comparator configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POF" description="Enable or disable power failure comparator">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="4" name="THRESHOLD" description="Power failure comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only).">
-        <Enum name="V17" start="4" description="Set threshold to 1.7 V" />
-        <Enum name="V18" start="5" description="Set threshold to 1.8 V" />
-        <Enum name="V19" start="6" description="Set threshold to 1.9 V" />
-        <Enum name="V20" start="7" description="Set threshold to 2.0 V" />
-        <Enum name="V21" start="8" description="Set threshold to 2.1 V" />
-        <Enum name="V22" start="9" description="Set threshold to 2.2 V" />
-        <Enum name="V23" start="10" description="Set threshold to 2.3 V" />
-        <Enum name="V24" start="11" description="Set threshold to 2.4 V" />
-        <Enum name="V25" start="12" description="Set threshold to 2.5 V" />
-        <Enum name="V26" start="13" description="Set threshold to 2.6 V" />
-        <Enum name="V27" start="14" description="Set threshold to 2.7 V" />
-        <Enum name="V28" start="15" description="Set threshold to 2.8 V" />
-      </BitField>
-      <BitField start="8" size="4" name="THRESHOLDVDDH" description="Power failure comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).">
-        <Enum name="V27" start="0" description="Set threshold to 2.7 V" />
-        <Enum name="V28" start="1" description="Set threshold to 2.8 V" />
-        <Enum name="V29" start="2" description="Set threshold to 2.9 V" />
-        <Enum name="V30" start="3" description="Set threshold to 3.0 V" />
-        <Enum name="V31" start="4" description="Set threshold to 3.1 V" />
-        <Enum name="V32" start="5" description="Set threshold to 3.2 V" />
-        <Enum name="V33" start="6" description="Set threshold to 3.3 V" />
-        <Enum name="V34" start="7" description="Set threshold to 3.4 V" />
-        <Enum name="V35" start="8" description="Set threshold to 3.5 V" />
-        <Enum name="V36" start="9" description="Set threshold to 3.6 V" />
-        <Enum name="V37" start="10" description="Set threshold to 3.7 V" />
-        <Enum name="V38" start="11" description="Set threshold to 3.8 V" />
-        <Enum name="V39" start="12" description="Set threshold to 3.9 V" />
-        <Enum name="V40" start="13" description="Set threshold to 4.0 V" />
-        <Enum name="V41" start="14" description="Set threshold to 4.1 V" />
-        <Enum name="V42" start="15" description="Set threshold to 4.2 V" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="GPREGRET" access="Read/Write" description="General purpose retention register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="GPREGRET" description="General purpose retention register" />
-    </Register>
-    <Register start="+0x520" size="4" name="GPREGRET2" access="Read/Write" description="General purpose retention register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="GPREGRET" description="General purpose retention register" />
-    </Register>
-    <Register start="+0x578" size="4" name="DCDCEN" access="Read/Write" description="Enable DC/DC converter for REG1 stage." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCDCEN" description="Enable DC/DC converter for REG1 stage.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x580" size="4" name="DCDCEN0" access="Read/Write" description="Enable DC/DC converter for REG0 stage." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCDCEN" description="Enable DC/DC converter for REG0 stage.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x640" size="4" name="MAINREGSTATUS" access="ReadOnly" description="Main supply status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAINREGSTATUS" description="Main supply status">
-        <Enum name="Normal" start="0" description="Normal voltage mode. Voltage supplied on VDD." />
-        <Enum name="High" start="1" description="High voltage mode. Voltage supplied on VDDH." />
-      </BitField>
-    </Register>
-    <Register start="+0x900+0*16+0x000" size="4" name="RAM[0].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+0*16+0x004" size="4" name="RAM[0].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+0*16+0x008" size="4" name="RAM[0].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+1*16+0x000" size="4" name="RAM[1].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+1*16+0x004" size="4" name="RAM[1].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+1*16+0x008" size="4" name="RAM[1].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+2*16+0x000" size="4" name="RAM[2].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+2*16+0x004" size="4" name="RAM[2].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+2*16+0x008" size="4" name="RAM[2].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+3*16+0x000" size="4" name="RAM[3].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+3*16+0x004" size="4" name="RAM[3].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+3*16+0x008" size="4" name="RAM[3].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+4*16+0x000" size="4" name="RAM[4].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+4*16+0x004" size="4" name="RAM[4].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+4*16+0x008" size="4" name="RAM[4].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+5*16+0x000" size="4" name="RAM[5].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+5*16+0x004" size="4" name="RAM[5].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+5*16+0x008" size="4" name="RAM[5].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+6*16+0x000" size="4" name="RAM[6].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+6*16+0x004" size="4" name="RAM[6].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+6*16+0x008" size="4" name="RAM[6].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+7*16+0x000" size="4" name="RAM[7].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+7*16+0x004" size="4" name="RAM[7].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+7*16+0x008" size="4" name="RAM[7].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+8*16+0x000" size="4" name="RAM[8].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+8*16+0x004" size="4" name="RAM[8].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+8*16+0x008" size="4" name="RAM[8].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CLOCK" start="0x40000000" description="Clock control">
-    <Register start="+0x000" size="4" name="TASKS_HFCLKSTART" access="WriteOnly" description="Start HFCLK crystal oscillator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_HFCLKSTOP" access="WriteOnly" description="Stop HFCLK crystal oscillator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_LFCLKSTART" access="WriteOnly" description="Start LFCLK source" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_LFCLKSTOP" access="WriteOnly" description="Stop LFCLK source" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_CAL" access="WriteOnly" description="Start calibration of LFRC or LFULP oscillator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_CTSTART" access="WriteOnly" description="Start calibration timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x018" size="4" name="TASKS_CTSTOP" access="WriteOnly" description="Stop calibration timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_HFCLKSTARTED" access="Read/Write" description="HFCLK oscillator started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_LFCLKSTARTED" access="Read/Write" description="LFCLK started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_DONE" access="Read/Write" description="Calibration of LFCLK RC oscillator complete event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_CTTO" access="Read/Write" description="Calibration timer timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HFCLKSTARTED" description="Write '1' to Enable interrupt for HFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="LFCLKSTARTED" description="Write '1' to Enable interrupt for LFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DONE" description="Write '1' to Enable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CTTO" description="Write '1' to Enable interrupt for CTTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HFCLKSTARTED" description="Write '1' to Disable interrupt for HFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="LFCLKSTARTED" description="Write '1' to Disable interrupt for LFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DONE" description="Write '1' to Disable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CTTO" description="Write '1' to Disable interrupt for CTTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x408" size="4" name="HFCLKRUN" access="ReadOnly" description="Status indicating that HFCLKSTART task has been triggered" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="HFCLKSTART task triggered or not">
-        <Enum name="NotTriggered" start="0" description="Task not triggered" />
-        <Enum name="Triggered" start="1" description="Task triggered" />
-      </BitField>
-    </Register>
-    <Register start="+0x40C" size="4" name="HFCLKSTAT" access="ReadOnly" description="HFCLK status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SRC" description="Source of HFCLK">
-        <Enum name="RC" start="0" description="64 MHz internal oscillator (HFINT)" />
-        <Enum name="Xtal" start="1" description="64 MHz crystal oscillator (HFXO)" />
-      </BitField>
-      <BitField start="16" size="1" name="STATE" description="HFCLK state">
-        <Enum name="NotRunning" start="0" description="HFCLK not running" />
-        <Enum name="Running" start="1" description="HFCLK running" />
-      </BitField>
-    </Register>
-    <Register start="+0x414" size="4" name="LFCLKRUN" access="ReadOnly" description="Status indicating that LFCLKSTART task has been triggered" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="LFCLKSTART task triggered or not">
-        <Enum name="NotTriggered" start="0" description="Task not triggered" />
-        <Enum name="Triggered" start="1" description="Task triggered" />
-      </BitField>
-    </Register>
-    <Register start="+0x418" size="4" name="LFCLKSTAT" access="ReadOnly" description="LFCLK status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Source of LFCLK">
-        <Enum name="RC" start="0" description="32.768 kHz RC oscillator" />
-        <Enum name="Xtal" start="1" description="32.768 kHz crystal oscillator" />
-        <Enum name="Synth" start="2" description="32.768 kHz synthesized from HFCLK" />
-      </BitField>
-      <BitField start="16" size="1" name="STATE" description="LFCLK state">
-        <Enum name="NotRunning" start="0" description="LFCLK not running" />
-        <Enum name="Running" start="1" description="LFCLK running" />
-      </BitField>
-    </Register>
-    <Register start="+0x41C" size="4" name="LFCLKSRCCOPY" access="ReadOnly" description="Copy of LFCLKSRC register, set when LFCLKSTART task was triggered" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Clock source">
-        <Enum name="RC" start="0" description="32.768 kHz RC oscillator" />
-        <Enum name="Xtal" start="1" description="32.768 kHz crystal oscillator" />
-        <Enum name="Synth" start="2" description="32.768 kHz synthesized from HFCLK" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="LFCLKSRC" access="Read/Write" description="Clock source for the LFCLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Clock source">
-        <Enum name="RC" start="0" description="32.768 kHz RC oscillator" />
-        <Enum name="Xtal" start="1" description="32.768 kHz crystal oscillator" />
-        <Enum name="Synth" start="2" description="32.768 kHz synthesized from HFCLK" />
-      </BitField>
-      <BitField start="16" size="1" name="BYPASS" description="Enable or disable bypass of LFCLK crystal oscillator with external clock source">
-        <Enum name="Disabled" start="0" description="Disable (use with Xtal or low-swing external source)" />
-        <Enum name="Enabled" start="1" description="Enable (use with rail-to-rail external source)" />
-      </BitField>
-      <BitField start="17" size="1" name="EXTERNAL" description="Enable or disable external source for LFCLK">
-        <Enum name="Disabled" start="0" description="Disable external source (use with Xtal)" />
-        <Enum name="Enabled" start="1" description="Enable use of external source instead of Xtal (SRC needs to be set to Xtal)" />
-      </BitField>
-    </Register>
-    <Register start="+0x528" size="4" name="HFXODEBOUNCE" access="Read/Write" description="HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="HFXODEBOUNCE" description="HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us." />
-    </Register>
-    <Register start="+0x538" size="4" name="CTIV" access="Read/Write" description="Calibration timer interval" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CTIV" description="Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds." />
-    </Register>
-    <Register start="+0x55C" size="4" name="TRACECONFIG" access="Read/Write" description="Clocking options for the Trace Port debug interface" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TRACEPORTSPEED" description="Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.">
-        <Enum name="32MHz" start="0" description="32 MHz Trace Port clock (TRACECLK = 16 MHz)" />
-        <Enum name="16MHz" start="1" description="16 MHz Trace Port clock (TRACECLK = 8 MHz)" />
-        <Enum name="8MHz" start="2" description="8 MHz Trace Port clock (TRACECLK = 4 MHz)" />
-        <Enum name="4MHz" start="3" description="4 MHz Trace Port clock (TRACECLK = 2 MHz)" />
-      </BitField>
-      <BitField start="16" size="2" name="TRACEMUX" description="Pin multiplexing of trace signals. See pin assignment chapter for more details.">
-        <Enum name="GPIO" start="0" description="No trace signals routed to pins. All pins can be used as regular GPIOs." />
-        <Enum name="Serial" start="1" description="SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs." />
-        <Enum name="Parallel" start="2" description="All trace signals (TRACECLK and TRACEDATA[n]) routed to pins." />
-      </BitField>
-    </Register>
-    <Register start="+0x5B4" size="4" name="LFRCMODE" access="Read/Write" description="LFRC mode configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Set LFRC mode">
-        <Enum name="Normal" start="0" description="Normal mode" />
-        <Enum name="ULP" start="1" description="Ultra-low power mode (ULP)" />
-      </BitField>
-      <BitField start="16" size="1" name="STATUS" description="Active LFRC mode. This field is read only.">
-        <Enum name="Normal" start="0" description="Normal mode" />
-        <Enum name="ULP" start="1" description="Ultra-low power mode (ULP)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RADIO" start="0x40001000" description="2.4 GHz Radio">
-    <Register start="+0x000" size="4" name="TASKS_TXEN" access="WriteOnly" description="Enable RADIO in TX mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_RXEN" access="WriteOnly" description="Enable RADIO in RX mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_START" access="WriteOnly" description="Start RADIO" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RADIO" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_DISABLE" access="WriteOnly" description="Disable RADIO" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_RSSISTART" access="WriteOnly" description="Start the RSSI and take one single sample of the receive signal strength." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x018" size="4" name="TASKS_RSSISTOP" access="WriteOnly" description="Stop the RSSI measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_BCSTART" access="WriteOnly" description="Start the bit counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_BCSTOP" access="WriteOnly" description="Stop the bit counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x024" size="4" name="TASKS_EDSTART" access="WriteOnly" description="Start the Energy Detect measurement used in IEEE 802.15.4 mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_EDSTOP" access="WriteOnly" description="Stop the Energy Detect measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x02C" size="4" name="TASKS_CCASTART" access="WriteOnly" description="Start the Clear Channel Assessment used in IEEE 802.15.4 mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030" size="4" name="TASKS_CCASTOP" access="WriteOnly" description="Stop the Clear Channel Assessment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="RADIO has ramped up and is ready to be started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_ADDRESS" access="Read/Write" description="Address sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_PAYLOAD" access="Read/Write" description="Packet payload sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_END" access="Read/Write" description="Packet sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_DISABLED" access="Read/Write" description="RADIO has been disabled" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_DEVMATCH" access="Read/Write" description="A device address match occurred on the last received packet" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_DEVMISS" access="Read/Write" description="No device address match occurred on the last received packet" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_RSSIEND" access="Read/Write" description="Sampling of receive signal strength complete." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_BCMATCH" access="Read/Write" description="Bit counter reached bit count value." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130" size="4" name="EVENTS_CRCOK" access="Read/Write" description="Packet received with CRC ok" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x134" size="4" name="EVENTS_CRCERROR" access="Read/Write" description="Packet received with CRC error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_FRAMESTART" access="Read/Write" description="IEEE 802.15.4 length field received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x13C" size="4" name="EVENTS_EDEND" access="Read/Write" description="Sampling of Energy Detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140" size="4" name="EVENTS_EDSTOPPED" access="Read/Write" description="The sampling of Energy Detection has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_CCAIDLE" access="Read/Write" description="Wireless medium in idle - clear to send" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_CCABUSY" access="Read/Write" description="Wireless medium busy - do not send" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_CCASTOPPED" access="Read/Write" description="The CCA has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_RATEBOOST" access="Read/Write" description="Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x154" size="4" name="EVENTS_TXREADY" access="Read/Write" description="RADIO has ramped up and is ready to be started TX path" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_RXREADY" access="Read/Write" description="RADIO has ramped up and is ready to be started RX path" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_MHRMATCH" access="Read/Write" description="MAC Header match found." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x16C" size="4" name="EVENTS_PHYEND" access="Read/Write" description="Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY_START" description="Shortcut between READY event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="END_DISABLE" description="Shortcut between END event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="DISABLED_TXEN" description="Shortcut between DISABLED event and TXEN task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="DISABLED_RXEN" description="Shortcut between DISABLED event and RXEN task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="ADDRESS_RSSISTART" description="Shortcut between ADDRESS event and RSSISTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="ADDRESS_BCSTART" description="Shortcut between ADDRESS event and BCSTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="DISABLED_RSSISTOP" description="Shortcut between DISABLED event and RSSISTOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="RXREADY_CCASTART" description="Shortcut between RXREADY event and CCASTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="CCAIDLE_TXEN" description="Shortcut between CCAIDLE event and TXEN task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="CCABUSY_DISABLE" description="Shortcut between CCABUSY event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="14" size="1" name="FRAMESTART_BCSTART" description="Shortcut between FRAMESTART event and BCSTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="15" size="1" name="READY_EDSTART" description="Shortcut between READY event and EDSTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="16" size="1" name="EDEND_DISABLE" description="Shortcut between EDEND event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="17" size="1" name="CCAIDLE_STOP" description="Shortcut between CCAIDLE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="18" size="1" name="TXREADY_START" description="Shortcut between TXREADY event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="19" size="1" name="RXREADY_START" description="Shortcut between RXREADY event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="20" size="1" name="PHYEND_DISABLE" description="Shortcut between PHYEND event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="21" size="1" name="PHYEND_START" description="Shortcut between PHYEND event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS" description="Write '1' to Enable interrupt for ADDRESS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="PAYLOAD" description="Write '1' to Enable interrupt for PAYLOAD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DISABLED" description="Write '1' to Enable interrupt for DISABLED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DEVMATCH" description="Write '1' to Enable interrupt for DEVMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DEVMISS" description="Write '1' to Enable interrupt for DEVMISS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RSSIEND" description="Write '1' to Enable interrupt for RSSIEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="BCMATCH" description="Write '1' to Enable interrupt for BCMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CRCOK" description="Write '1' to Enable interrupt for CRCOK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CRCERROR" description="Write '1' to Enable interrupt for CRCERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="FRAMESTART" description="Write '1' to Enable interrupt for FRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="EDEND" description="Write '1' to Enable interrupt for EDEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="EDSTOPPED" description="Write '1' to Enable interrupt for EDSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CCAIDLE" description="Write '1' to Enable interrupt for CCAIDLE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CCABUSY" description="Write '1' to Enable interrupt for CCABUSY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CCASTOPPED" description="Write '1' to Enable interrupt for CCASTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="RATEBOOST" description="Write '1' to Enable interrupt for RATEBOOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="TXREADY" description="Write '1' to Enable interrupt for TXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="RXREADY" description="Write '1' to Enable interrupt for RXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="MHRMATCH" description="Write '1' to Enable interrupt for MHRMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PHYEND" description="Write '1' to Enable interrupt for PHYEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS" description="Write '1' to Disable interrupt for ADDRESS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="PAYLOAD" description="Write '1' to Disable interrupt for PAYLOAD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DISABLED" description="Write '1' to Disable interrupt for DISABLED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DEVMATCH" description="Write '1' to Disable interrupt for DEVMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DEVMISS" description="Write '1' to Disable interrupt for DEVMISS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RSSIEND" description="Write '1' to Disable interrupt for RSSIEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="BCMATCH" description="Write '1' to Disable interrupt for BCMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CRCOK" description="Write '1' to Disable interrupt for CRCOK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CRCERROR" description="Write '1' to Disable interrupt for CRCERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="FRAMESTART" description="Write '1' to Disable interrupt for FRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="EDEND" description="Write '1' to Disable interrupt for EDEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="EDSTOPPED" description="Write '1' to Disable interrupt for EDSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CCAIDLE" description="Write '1' to Disable interrupt for CCAIDLE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CCABUSY" description="Write '1' to Disable interrupt for CCABUSY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CCASTOPPED" description="Write '1' to Disable interrupt for CCASTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="RATEBOOST" description="Write '1' to Disable interrupt for RATEBOOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="TXREADY" description="Write '1' to Disable interrupt for TXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="RXREADY" description="Write '1' to Disable interrupt for RXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="MHRMATCH" description="Write '1' to Disable interrupt for MHRMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PHYEND" description="Write '1' to Disable interrupt for PHYEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="CRCSTATUS" access="ReadOnly" description="CRC status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCSTATUS" description="CRC status of packet received">
-        <Enum name="CRCError" start="0" description="Packet received with CRC error" />
-        <Enum name="CRCOk" start="1" description="Packet received with CRC ok" />
-      </BitField>
-    </Register>
-    <Register start="+0x408" size="4" name="RXMATCH" access="ReadOnly" description="Received address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXMATCH" description="Received address" />
-    </Register>
-    <Register start="+0x40C" size="4" name="RXCRC" access="ReadOnly" description="CRC field of previously received packet" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RXCRC" description="CRC field of previously received packet" />
-    </Register>
-    <Register start="+0x410" size="4" name="DAI" access="ReadOnly" description="Device address match index" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DAI" description="Device address match index" />
-    </Register>
-    <Register start="+0x414" size="4" name="PDUSTAT" access="ReadOnly" description="Payload status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDUSTAT" description="Status on payload length vs. PCNF1.MAXLEN">
-        <Enum name="LessThan" start="0" description="Payload less than PCNF1.MAXLEN" />
-        <Enum name="GreaterThan" start="1" description="Payload greater than PCNF1.MAXLEN" />
-      </BitField>
-      <BitField start="1" size="2" name="CISTAT" description="Status on what rate packet is received with in Long Range">
-        <Enum name="LR125kbit" start="0" description="Frame is received at 125kbps" />
-        <Enum name="LR500kbit" start="1" description="Frame is received at 500kbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PACKETPTR" access="Read/Write" description="Packet pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PACKETPTR" description="Packet pointer" />
-    </Register>
-    <Register start="+0x508" size="4" name="FREQUENCY" access="Read/Write" description="Frequency" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="FREQUENCY" description="Radio channel frequency" />
-      <BitField start="8" size="1" name="MAP" description="Channel map selection.">
-        <Enum name="Default" start="0" description="Channel map between 2400 MHZ .. 2500 MHz" />
-        <Enum name="Low" start="1" description="Channel map between 2360 MHZ .. 2460 MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="TXPOWER" access="Read/Write" description="Output power" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXPOWER" description="RADIO output power.">
-        <Enum name="Pos8dBm" start="0x8" description="+8 dBm" />
-        <Enum name="Pos7dBm" start="0x7" description="+7 dBm" />
-        <Enum name="Pos6dBm" start="0x6" description="+6 dBm" />
-        <Enum name="Pos5dBm" start="0x5" description="+5 dBm" />
-        <Enum name="Pos4dBm" start="0x4" description="+4 dBm" />
-        <Enum name="Pos3dBm" start="0x3" description="+3 dBm" />
-        <Enum name="Pos2dBm" start="0x2" description="+2 dBm" />
-        <Enum name="0dBm" start="0x0" description="0 dBm" />
-        <Enum name="Neg4dBm" start="0xFC" description="-4 dBm" />
-        <Enum name="Neg8dBm" start="0xF8" description="-8 dBm" />
-        <Enum name="Neg12dBm" start="0xF4" description="-12 dBm" />
-        <Enum name="Neg16dBm" start="0xF0" description="-16 dBm" />
-        <Enum name="Neg20dBm" start="0xEC" description="-20 dBm" />
-        <Enum name="Neg30dBm" start="0xD8" description="Deprecated enumerator -  -40 dBm" />
-        <Enum name="Neg40dBm" start="0xD8" description="-40 dBm" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="MODE" access="Read/Write" description="Data rate and modulation" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MODE" description="Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.">
-        <Enum name="Nrf_1Mbit" start="0" description="1 Mbit/s Nordic proprietary radio mode" />
-        <Enum name="Nrf_2Mbit" start="1" description="2 Mbit/s Nordic proprietary radio mode" />
-        <Enum name="Nrf_250Kbit" start="2" description="Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode" />
-        <Enum name="Ble_1Mbit" start="3" description="1 Mbit/s Bluetooth Low Energy" />
-        <Enum name="Ble_2Mbit" start="4" description="2 Mbit/s Bluetooth Low Energy" />
-        <Enum name="Ble_LR125Kbit" start="5" description="Long range 125 kbit/s (TX Only - RX supports both)" />
-        <Enum name="Ble_LR500Kbit" start="6" description="Long range 500 kbit/s (TX Only - RX supports both)" />
-        <Enum name="Ieee802154_250Kbit" start="15" description="IEEE 802.15.4-2006 250 kbit/s" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="PCNF0" access="Read/Write" description="Packet configuration register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="LFLEN" description="Length on air of LENGTH field in number of bits." />
-      <BitField start="8" size="1" name="S0LEN" description="Length on air of S0 field in number of bytes." />
-      <BitField start="16" size="4" name="S1LEN" description="Length on air of S1 field in number of bits." />
-      <BitField start="20" size="1" name="S1INCL" description="Include or exclude S1 field in RAM">
-        <Enum name="Automatic" start="0" description="Include S1 field in RAM only if S1LEN &amp;gt; 0" />
-        <Enum name="Include" start="1" description="Always include S1 field in RAM independent of S1LEN" />
-      </BitField>
-      <BitField start="22" size="2" name="CILEN" description="Length of Code Indicator - Long Range" />
-      <BitField start="24" size="2" name="PLEN" description="Length of preamble on air. Decision point: TASKS_START task">
-        <Enum name="8bit" start="0" description="8-bit preamble" />
-        <Enum name="16bit" start="1" description="16-bit preamble" />
-        <Enum name="32bitZero" start="2" description="32-bit zero preamble - used for IEEE 802.15.4" />
-        <Enum name="LongRange" start="3" description="Preamble - used for BTLE Long Range" />
-      </BitField>
-      <BitField start="26" size="1" name="CRCINC" description="Indicates if LENGTH field contains CRC or not">
-        <Enum name="Exclude" start="0" description="LENGTH does not contain CRC" />
-        <Enum name="Include" start="1" description="LENGTH includes CRC" />
-      </BitField>
-      <BitField start="29" size="2" name="TERMLEN" description="Length of TERM field in Long Range operation" />
-    </Register>
-    <Register start="+0x518" size="4" name="PCNF1" access="Read/Write" description="Packet configuration register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXLEN" description="Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN." />
-      <BitField start="8" size="8" name="STATLEN" description="Static length in number of bytes" />
-      <BitField start="16" size="3" name="BALEN" description="Base address length in number of bytes" />
-      <BitField start="24" size="1" name="ENDIAN" description="On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.">
-        <Enum name="Little" start="0" description="Least Significant bit on air first" />
-        <Enum name="Big" start="1" description="Most significant bit on air first" />
-      </BitField>
-      <BitField start="25" size="1" name="WHITEEN" description="Enable or disable packet whitening">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="BASE0" access="Read/Write" description="Base address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASE0" description="Base address 0" />
-    </Register>
-    <Register start="+0x520" size="4" name="BASE1" access="Read/Write" description="Base address 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASE1" description="Base address 1" />
-    </Register>
-    <Register start="+0x524" size="4" name="PREFIX0" access="Read/Write" description="Prefixes bytes for logical addresses 0-3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AP0" description="Address prefix 0." />
-      <BitField start="8" size="8" name="AP1" description="Address prefix 1." />
-      <BitField start="16" size="8" name="AP2" description="Address prefix 2." />
-      <BitField start="24" size="8" name="AP3" description="Address prefix 3." />
-    </Register>
-    <Register start="+0x528" size="4" name="PREFIX1" access="Read/Write" description="Prefixes bytes for logical addresses 4-7" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AP4" description="Address prefix 4." />
-      <BitField start="8" size="8" name="AP5" description="Address prefix 5." />
-      <BitField start="16" size="8" name="AP6" description="Address prefix 6." />
-      <BitField start="24" size="8" name="AP7" description="Address prefix 7." />
-    </Register>
-    <Register start="+0x52C" size="4" name="TXADDRESS" access="Read/Write" description="Transmit address select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="TXADDRESS" description="Transmit address select" />
-    </Register>
-    <Register start="+0x530" size="4" name="RXADDRESSES" access="Read/Write" description="Receive address select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADDR0" description="Enable or disable reception on logical address 0.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDR1" description="Enable or disable reception on logical address 1.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="ADDR2" description="Enable or disable reception on logical address 2.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="ADDR3" description="Enable or disable reception on logical address 3.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ADDR4" description="Enable or disable reception on logical address 4.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="ADDR5" description="Enable or disable reception on logical address 5.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="ADDR6" description="Enable or disable reception on logical address 6.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="ADDR7" description="Enable or disable reception on logical address 7.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x534" size="4" name="CRCCNF" access="Read/Write" description="CRC configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LEN" description="CRC length in number of bytes.">
-        <Enum name="Disabled" start="0" description="CRC length is zero and CRC calculation is disabled" />
-        <Enum name="One" start="1" description="CRC length is one byte and CRC calculation is enabled" />
-        <Enum name="Two" start="2" description="CRC length is two bytes and CRC calculation is enabled" />
-        <Enum name="Three" start="3" description="CRC length is three bytes and CRC calculation is enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="SKIPADDR" description="Include or exclude packet address field out of CRC calculation.">
-        <Enum name="Include" start="0" description="CRC calculation includes address field" />
-        <Enum name="Skip" start="1" description="CRC calculation does not include address field. The CRC calculation will start at the first byte after the address." />
-        <Enum name="Ieee802154" start="2" description="CRC calculation as per 802.15.4 standard. Starting at first byte after length field." />
-      </BitField>
-    </Register>
-    <Register start="+0x538" size="4" name="CRCPOLY" access="Read/Write" description="CRC polynomial" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CRCPOLY" description="CRC polynomial" />
-    </Register>
-    <Register start="+0x53C" size="4" name="CRCINIT" access="Read/Write" description="CRC initial value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CRCINIT" description="CRC initial value" />
-    </Register>
-    <Register start="+0x544" size="4" name="TIFS" access="Read/Write" description="Inter Frame Spacing in us" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="TIFS" description="Inter Frame Spacing in us" />
-    </Register>
-    <Register start="+0x548" size="4" name="RSSISAMPLE" access="ReadOnly" description="RSSI sample" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RSSISAMPLE" description="RSSI sample" />
-    </Register>
-    <Register start="+0x550" size="4" name="STATE" access="ReadOnly" description="Current radio state" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="STATE" description="Current radio state">
-        <Enum name="Disabled" start="0" description="RADIO is in the Disabled state" />
-        <Enum name="RxRu" start="1" description="RADIO is in the RXRU state" />
-        <Enum name="RxIdle" start="2" description="RADIO is in the RXIDLE state" />
-        <Enum name="Rx" start="3" description="RADIO is in the RX state" />
-        <Enum name="RxDisable" start="4" description="RADIO is in the RXDISABLED state" />
-        <Enum name="TxRu" start="9" description="RADIO is in the TXRU state" />
-        <Enum name="TxIdle" start="10" description="RADIO is in the TXIDLE state" />
-        <Enum name="Tx" start="11" description="RADIO is in the TX state" />
-        <Enum name="TxDisable" start="12" description="RADIO is in the TXDISABLED state" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="DATAWHITEIV" access="Read/Write" description="Data whitening initial value" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DATAWHITEIV" description="Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'." />
-    </Register>
-    <Register start="+0x560" size="4" name="BCC" access="Read/Write" description="Bit counter compare" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BCC" description="Bit counter compare" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="DAB[0]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="DAB[1]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="DAB[2]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="DAB[3]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="DAB[4]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="DAB[5]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="DAB[6]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="DAB[7]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x620+0" size="4" name="DAP[0]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+4" size="4" name="DAP[1]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+8" size="4" name="DAP[2]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+12" size="4" name="DAP[3]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+16" size="4" name="DAP[4]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+20" size="4" name="DAP[5]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+24" size="4" name="DAP[6]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+28" size="4" name="DAP[7]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x640" size="4" name="DACNF" access="Read/Write" description="Device address match configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable or disable device address matching using device address 0">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ENA1" description="Enable or disable device address matching using device address 1">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ENA2" description="Enable or disable device address matching using device address 2">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="ENA3" description="Enable or disable device address matching using device address 3">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENA4" description="Enable or disable device address matching using device address 4">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="ENA5" description="Enable or disable device address matching using device address 5">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="ENA6" description="Enable or disable device address matching using device address 6">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ENA7" description="Enable or disable device address matching using device address 7">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TXADD0" description="TxAdd for device address 0" />
-      <BitField start="9" size="1" name="TXADD1" description="TxAdd for device address 1" />
-      <BitField start="10" size="1" name="TXADD2" description="TxAdd for device address 2" />
-      <BitField start="11" size="1" name="TXADD3" description="TxAdd for device address 3" />
-      <BitField start="12" size="1" name="TXADD4" description="TxAdd for device address 4" />
-      <BitField start="13" size="1" name="TXADD5" description="TxAdd for device address 5" />
-      <BitField start="14" size="1" name="TXADD6" description="TxAdd for device address 6" />
-      <BitField start="15" size="1" name="TXADD7" description="TxAdd for device address 7" />
-    </Register>
-    <Register start="+0x644" size="4" name="MHRMATCHCONF" access="Read/Write" description="Search Pattern Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x648" size="4" name="MHRMATCHMAS" access="Read/Write" description="Pattern mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x650" size="4" name="MODECNF0" access="Read/Write" description="Radio mode configuration register 0" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RU" description="Radio ramp-up time">
-        <Enum name="Default" start="0" description="Default ramp-up time (tRXEN), compatible with firmware written for nRF51" />
-        <Enum name="Fast" start="1" description="Fast ramp-up (tRXEN,FAST), see electrical specification for more information" />
-      </BitField>
-      <BitField start="8" size="2" name="DTX" description="Default TX value">
-        <Enum name="B1" start="0" description="Transmit '1'" />
-        <Enum name="B0" start="1" description="Transmit '0'" />
-        <Enum name="Center" start="2" description="Transmit center frequency" />
-      </BitField>
-    </Register>
-    <Register start="+0x660" size="4" name="SFD" access="Read/Write" description="IEEE 802.15.4 Start of Frame Delimiter" reset_value="0x000000A7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SFD" description="IEEE 802.15.4 Start of Frame Delimiter. Note, the least significant 4-bits of the SFD cannot all be zeros." />
-    </Register>
-    <Register start="+0x664" size="4" name="EDCNT" access="Read/Write" description="IEEE 802.15.4 Energy Detect Loop Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="21" name="EDCNT" description="IEEE 802.15.4 Energy Detect Loop Count" />
-    </Register>
-    <Register start="+0x668" size="4" name="EDSAMPLE" access="Read/Write" description="IEEE 802.15.4 Energy Detect Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EDLVL" description="IEEE 802.15.4 Energy Detect Level" />
-    </Register>
-    <Register start="+0x66C" size="4" name="CCACTRL" access="Read/Write" description="IEEE 802.15.4 Clear Channel Assessment Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CCAMODE" description="CCA Mode Of Operation">
-        <Enum name="EdMode" start="0" description="Energy Above Threshold" />
-        <Enum name="CarrierMode" start="1" description="Carrier Seen" />
-        <Enum name="CarrierAndEdMode" start="2" description="Energy Above Threshold AND Carrier Seen" />
-        <Enum name="CarrierOrEdMode" start="3" description="Energy Above Threshold OR Carrier Seen" />
-        <Enum name="EdModeTest1" start="4" description="Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging." />
-      </BitField>
-      <BitField start="8" size="8" name="CCAEDTHRES" description="CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode." />
-      <BitField start="16" size="8" name="CCACORRTHRES" description="CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode." />
-      <BitField start="24" size="8" name="CCACORRCNT" description="Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled." />
-    </Register>
-    <Register start="+0xFFC" size="4" name="POWER" access="Read/Write" description="Peripheral power control" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER" description="Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.">
-        <Enum name="Disabled" start="0" description="Peripheral is powered off" />
-        <Enum name="Enabled" start="1" description="Peripheral is powered on" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UARTE0" start="0x40002000" description="UART with EasyDMA 0">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPRX" access="WriteOnly" description="Stop UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOPTX" access="WriteOnly" description="Stop UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x02C" size="4" name="TASKS_FLUSHRX" access="WriteOnly" description="Flush RX FIFO into RX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_CTS" access="Read/Write" description="CTS is activated (set low). Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_NCTS" access="Read/Write" description="CTS is deactivated (set high). Not Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDRDY" access="Read/Write" description="Data received in RXD (but potentially not yet transferred to Data RAM)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="Receive buffer is filled up" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDRDY" access="Read/Write" description="Data sent from TXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="Last TX byte transmitted" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="Error detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_RXTO" access="Read/Write" description="Receiver timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="UART receiver has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="UART transmitter has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_TXSTOPPED" access="Read/Write" description="Transmitter stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="ENDRX_STARTRX" description="Shortcut between ENDRX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDRX_STOPRX" description="Shortcut between ENDRX event and STOPRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Enable or disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Enable or disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Enable or disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Enable or disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Enable or disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Enable or disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Enable or disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Enable or disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Enable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Enable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Enable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Enable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Enable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Enable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x480" size="4" name="ERRORSRC" access="Read/Write" description="Error source Note : this register is read / write one to clear." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="PARITY" description="Parity error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="FRAMING" description="Framing error occurred">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="3" size="1" name="BREAK" description="Break condition">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable UARTE">
-        <Enum name="Disabled" start="0" description="Disable UARTE" />
-        <Enum name="Enabled" start="8" description="Enable UARTE" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="BAUDRATE" access="Read/Write" description="Baud rate. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BAUDRATE" description="Baud rate">
-        <Enum name="Baud1200" start="0x0004F000" description="1200 baud (actual rate: 1205)" />
-        <Enum name="Baud2400" start="0x0009D000" description="2400 baud (actual rate: 2396)" />
-        <Enum name="Baud4800" start="0x0013B000" description="4800 baud (actual rate: 4808)" />
-        <Enum name="Baud9600" start="0x00275000" description="9600 baud (actual rate: 9598)" />
-        <Enum name="Baud14400" start="0x003AF000" description="14400 baud (actual rate: 14401)" />
-        <Enum name="Baud19200" start="0x004EA000" description="19200 baud (actual rate: 19208)" />
-        <Enum name="Baud28800" start="0x0075C000" description="28800 baud (actual rate: 28777)" />
-        <Enum name="Baud31250" start="0x00800000" description="31250 baud" />
-        <Enum name="Baud38400" start="0x009D0000" description="38400 baud (actual rate: 38369)" />
-        <Enum name="Baud56000" start="0x00E50000" description="56000 baud (actual rate: 55944)" />
-        <Enum name="Baud57600" start="0x00EB0000" description="57600 baud (actual rate: 57554)" />
-        <Enum name="Baud76800" start="0x013A9000" description="76800 baud (actual rate: 76923)" />
-        <Enum name="Baud115200" start="0x01D60000" description="115200 baud (actual rate: 115108)" />
-        <Enum name="Baud230400" start="0x03B00000" description="230400 baud (actual rate: 231884)" />
-        <Enum name="Baud250000" start="0x04000000" description="250000 baud" />
-        <Enum name="Baud460800" start="0x07400000" description="460800 baud (actual rate: 457143)" />
-        <Enum name="Baud921600" start="0x0F000000" description="921600 baud (actual rate: 941176)" />
-        <Enum name="Baud1M" start="0x10000000" description="1Mega baud" />
-      </BitField>
-    </Register>
-    <Register start="+0x56C" size="4" name="CONFIG" access="Read/Write" description="Configuration of parity and hardware flow control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HWFC" description="Hardware flow control">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="3" name="PARITY" description="Parity">
-        <Enum name="Excluded" start="0x0" description="Exclude parity bit" />
-        <Enum name="Included" start="0x7" description="Include even parity bit" />
-      </BitField>
-      <BitField start="4" size="1" name="STOP" description="Stop bits">
-        <Enum name="One" start="0" description="One stop bit" />
-        <Enum name="Two" start="1" description="Two stop bits" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.RTS" access="Read/Write" description="Pin select for RTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.TXD" access="Read/Write" description="Pin select for TXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.CTS" access="Read/Write" description="Pin select for CTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.RXD" access="Read/Write" description="Pin select for RXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x40002000" description="Universal Asynchronous Receiver/Transmitter">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPRX" access="WriteOnly" description="Stop UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOPTX" access="WriteOnly" description="Stop UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_CTS" access="Read/Write" description="CTS is activated (set low). Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_NCTS" access="Read/Write" description="CTS is deactivated (set high). Not Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDRDY" access="Read/Write" description="Data received in RXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDRDY" access="Read/Write" description="Data sent from TXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="Error detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_RXTO" access="Read/Write" description="Receiver timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="CTS_STARTRX" description="Shortcut between CTS event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="NCTS_STOPRX" description="Shortcut between NCTS event and STOPRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Enable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Enable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Enable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Enable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Enable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x480" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="PARITY" description="Parity error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="FRAMING" description="Framing error occurred">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="3" size="1" name="BREAK" description="Break condition">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable UART">
-        <Enum name="Disabled" start="0" description="Disable UART" />
-        <Enum name="Enabled" start="4" description="Enable UART" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received in previous transfers, double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="WriteOnly" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to be transferred" />
-    </Register>
-    <Register start="+0x524" size="4" name="BAUDRATE" access="Read/Write" description="Baud rate. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BAUDRATE" description="Baud rate">
-        <Enum name="Baud1200" start="0x0004F000" description="1200 baud (actual rate: 1205)" />
-        <Enum name="Baud2400" start="0x0009D000" description="2400 baud (actual rate: 2396)" />
-        <Enum name="Baud4800" start="0x0013B000" description="4800 baud (actual rate: 4808)" />
-        <Enum name="Baud9600" start="0x00275000" description="9600 baud (actual rate: 9598)" />
-        <Enum name="Baud14400" start="0x003B0000" description="14400 baud (actual rate: 14414)" />
-        <Enum name="Baud19200" start="0x004EA000" description="19200 baud (actual rate: 19208)" />
-        <Enum name="Baud28800" start="0x0075F000" description="28800 baud (actual rate: 28829)" />
-        <Enum name="Baud31250" start="0x00800000" description="31250 baud" />
-        <Enum name="Baud38400" start="0x009D5000" description="38400 baud (actual rate: 38462)" />
-        <Enum name="Baud56000" start="0x00E50000" description="56000 baud (actual rate: 55944)" />
-        <Enum name="Baud57600" start="0x00EBF000" description="57600 baud (actual rate: 57762)" />
-        <Enum name="Baud76800" start="0x013A9000" description="76800 baud (actual rate: 76923)" />
-        <Enum name="Baud115200" start="0x01D7E000" description="115200 baud (actual rate: 115942)" />
-        <Enum name="Baud230400" start="0x03AFB000" description="230400 baud (actual rate: 231884)" />
-        <Enum name="Baud250000" start="0x04000000" description="250000 baud" />
-        <Enum name="Baud460800" start="0x075F7000" description="460800 baud (actual rate: 470588)" />
-        <Enum name="Baud921600" start="0x0EBED000" description="921600 baud (actual rate: 941176)" />
-        <Enum name="Baud1M" start="0x10000000" description="1Mega baud" />
-      </BitField>
-    </Register>
-    <Register start="+0x56C" size="4" name="CONFIG" access="Read/Write" description="Configuration of parity and hardware flow control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HWFC" description="Hardware flow control">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="3" name="PARITY" description="Parity">
-        <Enum name="Excluded" start="0x0" description="Exclude parity bit" />
-        <Enum name="Included" start="0x7" description="Include parity bit" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.RTS" access="Read/Write" description="Pin select for RTS" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.TXD" access="Read/Write" description="Pin select for TXD" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.CTS" access="Read/Write" description="Pin select for CTS" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.RXD" access="Read/Write" description="Pin select for RXD" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM0" start="0x40003000" description="Serial Peripheral Interface Master with EasyDMA 0">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIS0" start="0x40003000" description="SPI Slave 0">
-    <Register start="+0x024" size="4" name="TASKS_ACQUIRE" access="WriteOnly" description="Acquire SPI semaphore" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_RELEASE" access="WriteOnly" description="Release SPI semaphore, enabling the SPI slave to acquire it" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="Granted transaction completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_ACQUIRED" access="Read/Write" description="Semaphore acquired" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="END_ACQUIRE" description="Shortcut between END event and ACQUIRE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Enable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Disable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="SEMSTAT" access="ReadOnly" description="Semaphore status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEMSTAT" description="Semaphore status">
-        <Enum name="Free" start="0" description="Semaphore is free" />
-        <Enum name="CPU" start="1" description="Semaphore is assigned to CPU" />
-        <Enum name="SPIS" start="2" description="Semaphore is assigned to SPI slave" />
-        <Enum name="CPUPending" start="3" description="Semaphore is assigned to SPI but a handover to the CPU is pending" />
-      </BitField>
-    </Register>
-    <Register start="+0x440" size="4" name="STATUS" access="Read/Write" description="Status from last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI slave">
-        <Enum name="Disabled" start="0" description="Disable SPI slave" />
-        <Enum name="Enabled" start="2" description="Enable SPI slave" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x55C" size="4" name="DEF" access="Read/Write" description="Default character. Character clocked out in case of an ignored transaction." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEF" description="Default character. Character clocked out in case of an ignored transaction." />
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character clocked out after an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes received in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes received in the last granted transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transmitted in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transmitted in last granted transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIM0" start="0x40003000" description="I2C compatible Two-Wire Master Interface with EasyDMA 0">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction. Must be issued while the TWI master is not suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_LASTRX" access="Read/Write" description="Byte boundary, starting to receive the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160" size="4" name="EVENTS_LASTTX" access="Read/Write" description="Byte boundary, starting to transmit the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="LASTTX_STARTRX" description="Shortcut between LASTTX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="LASTTX_SUSPEND" description="Shortcut between LASTTX event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="LASTTX_STOP" description="Shortcut between LASTTX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="LASTRX_STARTTX" description="Shortcut between LASTRX event and STARTTX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="LASTRX_STOP" description="Shortcut between LASTRX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Enable or disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Enable or disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Enable or disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Enable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Enable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIM">
-        <Enum name="Disabled" start="0" description="Disable TWIM" />
-        <Enum name="Enabled" start="6" description="Enable TWIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06400000" description="400 kbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIS0" start="0x40003000" description="I2C compatible Two-Wire Slave Interface with EasyDMA 0">
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030" size="4" name="TASKS_PREPARERX" access="WriteOnly" description="Prepare the TWI slave to respond to a write command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x034" size="4" name="TASKS_PREPARETX" access="WriteOnly" description="Prepare the TWI slave to respond to a read command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x164" size="4" name="EVENTS_WRITE" access="Read/Write" description="Write command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x168" size="4" name="EVENTS_READ" access="Read/Write" description="Read command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="1" name="WRITE_SUSPEND" description="Shortcut between WRITE event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="14" size="1" name="READ_SUSPEND" description="Shortcut between READ event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Enable or disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Enable or disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Enable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Enable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D0" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK sent after receiving a data byte">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="3" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D4" size="4" name="MATCH" access="ReadOnly" description="Status register indicating which address had a match" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH" description="Which of the addresses in {ADDRESS} matched the incoming address" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIS" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIS">
-        <Enum name="Disabled" start="0" description="Disable TWIS" />
-        <Enum name="Enabled" start="9" description="Enable TWIS" />
-      </BitField>
-    </Register>
-    <Register start="+0x588+0" size="4" name="ADDRESS[0]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x588+4" size="4" name="ADDRESS[1]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x594" size="4" name="CONFIG" access="Read/Write" description="Configuration register for the address match mechanism" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADDRESS0" description="Enable or disable address matching on ADDRESS[0]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS1" description="Enable or disable address matching on ADDRESS[1]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in RXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in RXD buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last RXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last RXD transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in TXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in TXD buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last TXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last TXD transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI0" start="0x40003000" description="Serial Peripheral Interface 0">
-    <Register start="+0x108" size="4" name="EVENTS_READY" access="Read/Write" description="TXD byte sent and RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI">
-        <Enum name="Disabled" start="0" description="Disable SPI" />
-        <Enum name="Enabled" start="1" description="Enable SPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received. Double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to send. Double buffered" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWI0" start="0x40003000" description="I2C compatible Two-Wire Interface 0">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDREADY" access="Read/Write" description="TWI RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDSENT" access="Read/Write" description="TWI TXD byte sent" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_BB" access="Read/Write" description="TWI byte boundary, generated before each byte that is sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="TWI entered the suspended state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BB_SUSPEND" description="Shortcut between BB event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="BB_STOP" description="Shortcut between BB event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Enable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Enable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Enable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Disable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Disable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Disable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: no overrun occured" />
-        <Enum name="Present" start="1" description="Read: overrun occured" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWI">
-        <Enum name="Disabled" start="0" description="Disable TWI" />
-        <Enum name="Enabled" start="5" description="Enable TWI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RXD register" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TXD register" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06680000" description="400 kbps (actual rate 410.256 kbps)" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM1" start="0x40004000" description="Serial Peripheral Interface Master with EasyDMA 1">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIS1" start="0x40004000" description="SPI Slave 1">
-    <Register start="+0x024" size="4" name="TASKS_ACQUIRE" access="WriteOnly" description="Acquire SPI semaphore" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_RELEASE" access="WriteOnly" description="Release SPI semaphore, enabling the SPI slave to acquire it" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="Granted transaction completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_ACQUIRED" access="Read/Write" description="Semaphore acquired" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="END_ACQUIRE" description="Shortcut between END event and ACQUIRE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Enable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Disable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="SEMSTAT" access="ReadOnly" description="Semaphore status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEMSTAT" description="Semaphore status">
-        <Enum name="Free" start="0" description="Semaphore is free" />
-        <Enum name="CPU" start="1" description="Semaphore is assigned to CPU" />
-        <Enum name="SPIS" start="2" description="Semaphore is assigned to SPI slave" />
-        <Enum name="CPUPending" start="3" description="Semaphore is assigned to SPI but a handover to the CPU is pending" />
-      </BitField>
-    </Register>
-    <Register start="+0x440" size="4" name="STATUS" access="Read/Write" description="Status from last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI slave">
-        <Enum name="Disabled" start="0" description="Disable SPI slave" />
-        <Enum name="Enabled" start="2" description="Enable SPI slave" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x55C" size="4" name="DEF" access="Read/Write" description="Default character. Character clocked out in case of an ignored transaction." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEF" description="Default character. Character clocked out in case of an ignored transaction." />
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character clocked out after an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes received in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes received in the last granted transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transmitted in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transmitted in last granted transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIM1" start="0x40004000" description="I2C compatible Two-Wire Master Interface with EasyDMA 1">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction. Must be issued while the TWI master is not suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_LASTRX" access="Read/Write" description="Byte boundary, starting to receive the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160" size="4" name="EVENTS_LASTTX" access="Read/Write" description="Byte boundary, starting to transmit the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="LASTTX_STARTRX" description="Shortcut between LASTTX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="LASTTX_SUSPEND" description="Shortcut between LASTTX event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="LASTTX_STOP" description="Shortcut between LASTTX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="LASTRX_STARTTX" description="Shortcut between LASTRX event and STARTTX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="LASTRX_STOP" description="Shortcut between LASTRX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Enable or disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Enable or disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Enable or disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Enable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Enable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIM">
-        <Enum name="Disabled" start="0" description="Disable TWIM" />
-        <Enum name="Enabled" start="6" description="Enable TWIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06400000" description="400 kbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIS1" start="0x40004000" description="I2C compatible Two-Wire Slave Interface with EasyDMA 1">
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030" size="4" name="TASKS_PREPARERX" access="WriteOnly" description="Prepare the TWI slave to respond to a write command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x034" size="4" name="TASKS_PREPARETX" access="WriteOnly" description="Prepare the TWI slave to respond to a read command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x164" size="4" name="EVENTS_WRITE" access="Read/Write" description="Write command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x168" size="4" name="EVENTS_READ" access="Read/Write" description="Read command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="1" name="WRITE_SUSPEND" description="Shortcut between WRITE event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="14" size="1" name="READ_SUSPEND" description="Shortcut between READ event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Enable or disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Enable or disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Enable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Enable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D0" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK sent after receiving a data byte">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="3" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D4" size="4" name="MATCH" access="ReadOnly" description="Status register indicating which address had a match" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH" description="Which of the addresses in {ADDRESS} matched the incoming address" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIS" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIS">
-        <Enum name="Disabled" start="0" description="Disable TWIS" />
-        <Enum name="Enabled" start="9" description="Enable TWIS" />
-      </BitField>
-    </Register>
-    <Register start="+0x588+0" size="4" name="ADDRESS[0]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x588+4" size="4" name="ADDRESS[1]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x594" size="4" name="CONFIG" access="Read/Write" description="Configuration register for the address match mechanism" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADDRESS0" description="Enable or disable address matching on ADDRESS[0]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS1" description="Enable or disable address matching on ADDRESS[1]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in RXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in RXD buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last RXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last RXD transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in TXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in TXD buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last TXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last TXD transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI1" start="0x40004000" description="Serial Peripheral Interface 1">
-    <Register start="+0x108" size="4" name="EVENTS_READY" access="Read/Write" description="TXD byte sent and RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI">
-        <Enum name="Disabled" start="0" description="Disable SPI" />
-        <Enum name="Enabled" start="1" description="Enable SPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received. Double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to send. Double buffered" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWI1" start="0x40004000" description="I2C compatible Two-Wire Interface 1">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDREADY" access="Read/Write" description="TWI RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDSENT" access="Read/Write" description="TWI TXD byte sent" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_BB" access="Read/Write" description="TWI byte boundary, generated before each byte that is sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="TWI entered the suspended state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BB_SUSPEND" description="Shortcut between BB event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="BB_STOP" description="Shortcut between BB event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Enable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Enable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Enable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Disable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Disable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Disable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: no overrun occured" />
-        <Enum name="Present" start="1" description="Read: overrun occured" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWI">
-        <Enum name="Disabled" start="0" description="Disable TWI" />
-        <Enum name="Enabled" start="5" description="Enable TWI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RXD register" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TXD register" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06680000" description="400 kbps (actual rate 410.256 kbps)" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NFCT" start="0x40005000" description="NFC-A compatible radio">
-    <Register start="+0x000" size="4" name="TASKS_ACTIVATE" access="WriteOnly" description="Activate NFCT peripheral for incoming and outgoing frames, change state to activated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_DISABLE" access="WriteOnly" description="Disable NFCT peripheral" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_SENSE" access="WriteOnly" description="Enable NFC sense field mode, change state to sense mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start transmission of an outgoing frame, change state to transmit" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_ENABLERXDATA" access="WriteOnly" description="Initializes the EasyDMA for receive." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x024" size="4" name="TASKS_GOIDLE" access="WriteOnly" description="Force state machine to IDLE state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_GOSLEEP" access="WriteOnly" description="Force state machine to SLEEP_A state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="The NFCT peripheral is ready to receive and send frames" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_FIELDDETECTED" access="Read/Write" description="Remote NFC field detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_FIELDLOST" access="Read/Write" description="Remote NFC field lost" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_TXFRAMESTART" access="Read/Write" description="Marks the start of the first symbol of a transmitted frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_TXFRAMEEND" access="Read/Write" description="Marks the end of the last transmitted on-air symbol of a frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_RXFRAMESTART" access="Read/Write" description="Marks the end of the first symbol of a received frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_RXFRAMEEND" access="Read/Write" description="Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_ERROR" access="Read/Write" description="NFC error reported. The ERRORSTATUS register contains details on the source of the error." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_RXERROR" access="Read/Write" description="NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x12C" size="4" name="EVENTS_ENDRX" access="Read/Write" description="RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130" size="4" name="EVENTS_ENDTX" access="Read/Write" description="Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_AUTOCOLRESSTARTED" access="Read/Write" description="Auto collision resolution process has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_COLLISION" access="Read/Write" description="NFC auto collision resolution error reported." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_SELECTED" access="Read/Write" description="NFC auto collision resolution successfully completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_STARTED" access="Read/Write" description="EasyDMA is ready to receive or send frames." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIELDDETECTED_ACTIVATE" description="Shortcut between FIELDDETECTED event and ACTIVATE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDLOST_SENSE" description="Shortcut between FIELDLOST event and SENSE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="TXFRAMEEND_ENABLERXDATA" description="Shortcut between TXFRAMEEND event and ENABLERXDATA task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Enable or disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDDETECTED" description="Enable or disable interrupt for FIELDDETECTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="FIELDLOST" description="Enable or disable interrupt for FIELDLOST event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TXFRAMESTART" description="Enable or disable interrupt for TXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TXFRAMEEND" description="Enable or disable interrupt for TXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="RXFRAMESTART" description="Enable or disable interrupt for RXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="RXFRAMEEND" description="Enable or disable interrupt for RXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="RXERROR" description="Enable or disable interrupt for RXERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDRX" description="Enable or disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDTX" description="Enable or disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="AUTOCOLRESSTARTED" description="Enable or disable interrupt for AUTOCOLRESSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COLLISION" description="Enable or disable interrupt for COLLISION event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="SELECTED" description="Enable or disable interrupt for SELECTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDDETECTED" description="Write '1' to Enable interrupt for FIELDDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="FIELDLOST" description="Write '1' to Enable interrupt for FIELDLOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TXFRAMESTART" description="Write '1' to Enable interrupt for TXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TXFRAMEEND" description="Write '1' to Enable interrupt for TXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RXFRAMESTART" description="Write '1' to Enable interrupt for RXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXFRAMEEND" description="Write '1' to Enable interrupt for RXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="RXERROR" description="Write '1' to Enable interrupt for RXERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="AUTOCOLRESSTARTED" description="Write '1' to Enable interrupt for AUTOCOLRESSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COLLISION" description="Write '1' to Enable interrupt for COLLISION event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="SELECTED" description="Write '1' to Enable interrupt for SELECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDDETECTED" description="Write '1' to Disable interrupt for FIELDDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="FIELDLOST" description="Write '1' to Disable interrupt for FIELDLOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TXFRAMESTART" description="Write '1' to Disable interrupt for TXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TXFRAMEEND" description="Write '1' to Disable interrupt for TXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RXFRAMESTART" description="Write '1' to Disable interrupt for RXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXFRAMEEND" description="Write '1' to Disable interrupt for RXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="RXERROR" description="Write '1' to Disable interrupt for RXERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="AUTOCOLRESSTARTED" description="Write '1' to Disable interrupt for AUTOCOLRESSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COLLISION" description="Write '1' to Disable interrupt for COLLISION event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="SELECTED" description="Write '1' to Disable interrupt for SELECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x404" size="4" name="ERRORSTATUS" access="Read/Write" description="NFC Error Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEDELAYTIMEOUT" description="No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX" />
-    </Register>
-    <Register start="+0x410" size="4" name="NFCTAGSTATE" access="ReadOnly" description="NfcTag state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="NFCTAGSTATE" description="NfcTag state">
-        <Enum name="Disabled" start="0" description="Disabled or sense" />
-        <Enum name="RampUp" start="2" description="RampUp" />
-        <Enum name="Idle" start="3" description="Idle" />
-        <Enum name="Receive" start="4" description="Receive" />
-        <Enum name="FrameDelay" start="5" description="FrameDelay" />
-        <Enum name="Transmit" start="6" description="Transmit" />
-      </BitField>
-    </Register>
-    <Register start="+0x43C" size="4" name="FIELDPRESENT" access="ReadOnly" description="Indicates the presence or not of a valid field" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIELDPRESENT" description="Indicates if a valid field is present. Available only in the activated state.">
-        <Enum name="NoField" start="0" description="No valid field detected" />
-        <Enum name="FieldPresent" start="1" description="Valid field detected" />
-      </BitField>
-      <BitField start="1" size="1" name="LOCKDETECT" description="Indicates if the low level has locked to the field">
-        <Enum name="NotLocked" start="0" description="Not locked to field" />
-        <Enum name="Locked" start="1" description="Locked to field" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="FRAMEDELAYMIN" access="Read/Write" description="Minimum frame delay" reset_value="0x00000480" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FRAMEDELAYMIN" description="Minimum frame delay in number of 13.56 MHz clocks" />
-    </Register>
-    <Register start="+0x508" size="4" name="FRAMEDELAYMAX" access="Read/Write" description="Maximum frame delay" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="20" name="FRAMEDELAYMAX" description="Maximum frame delay in number of 13.56 MHz clocks" />
-    </Register>
-    <Register start="+0x50C" size="4" name="FRAMEDELAYMODE" access="Read/Write" description="Configuration register for the Frame Delay Timer" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="FRAMEDELAYMODE" description="Configuration register for the Frame Delay Timer">
-        <Enum name="FreeRun" start="0" description="Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout." />
-        <Enum name="Window" start="1" description="Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX" />
-        <Enum name="ExactVal" start="2" description="Frame is transmitted exactly at FRAMEDELAYMAX" />
-        <Enum name="WindowGrid" start="3" description="Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PACKETPTR" access="Read/Write" description="Packet pointer for TXD and RXD data storage in Data RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address." />
-    </Register>
-    <Register start="+0x514" size="4" name="MAXLEN" access="Read/Write" description="Size of the RAM buffer allocated to TXD and RXD data storage each" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="MAXLEN" description="Size of the RAM buffer allocated to TXD and RXD data storage each" />
-    </Register>
-    <Register start="+0x590" size="4" name="NFCID1_LAST" access="Read/Write" description="Last NFCID1 part (4, 7 or 10 bytes ID)" reset_value="0x00006363" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="NFCID1_Z" description="NFCID1 byte Z (very last byte sent)" />
-      <BitField start="8" size="8" name="NFCID1_Y" description="NFCID1 byte Y" />
-      <BitField start="16" size="8" name="NFCID1_X" description="NFCID1 byte X" />
-      <BitField start="24" size="8" name="NFCID1_W" description="NFCID1 byte W" />
-    </Register>
-    <Register start="+0x594" size="4" name="NFCID1_2ND_LAST" access="Read/Write" description="Second last NFCID1 part (7 or 10 bytes ID)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="NFCID1_V" description="NFCID1 byte V" />
-      <BitField start="8" size="8" name="NFCID1_U" description="NFCID1 byte U" />
-      <BitField start="16" size="8" name="NFCID1_T" description="NFCID1 byte T" />
-    </Register>
-    <Register start="+0x598" size="4" name="NFCID1_3RD_LAST" access="Read/Write" description="Third last NFCID1 part (10 bytes ID)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="NFCID1_S" description="NFCID1 byte S" />
-      <BitField start="8" size="8" name="NFCID1_R" description="NFCID1 byte R" />
-      <BitField start="16" size="8" name="NFCID1_Q" description="NFCID1 byte Q" />
-    </Register>
-    <Register start="+0x59C" size="4" name="AUTOCOLRESCONFIG" access="Read/Write" description="Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled." reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Enables/disables auto collision resolution">
-        <Enum name="Enabled" start="0" description="Auto collision resolution enabled" />
-        <Enum name="Disabled" start="1" description="Auto collision resolution disabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x5A0" size="4" name="SENSRES" access="Read/Write" description="NFC-A SENS_RES auto-response settings" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="BITFRAMESDD" description="Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification">
-        <Enum name="SDD00000" start="0" description="SDD pattern 00000" />
-        <Enum name="SDD00001" start="1" description="SDD pattern 00001" />
-        <Enum name="SDD00010" start="2" description="SDD pattern 00010" />
-        <Enum name="SDD00100" start="4" description="SDD pattern 00100" />
-        <Enum name="SDD01000" start="8" description="SDD pattern 01000" />
-        <Enum name="SDD10000" start="16" description="SDD pattern 10000" />
-      </BitField>
-      <BitField start="5" size="1" name="RFU5" description="Reserved for future use. Shall be 0." />
-      <BitField start="6" size="2" name="NFCIDSIZE" description="NFCID1 size. This value is used by the auto collision resolution engine.">
-        <Enum name="NFCID1Single" start="0" description="NFCID1 size: single (4 bytes)" />
-        <Enum name="NFCID1Double" start="1" description="NFCID1 size: double (7 bytes)" />
-        <Enum name="NFCID1Triple" start="2" description="NFCID1 size: triple (10 bytes)" />
-      </BitField>
-      <BitField start="8" size="4" name="PLATFCONFIG" description="Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification" />
-      <BitField start="12" size="4" name="RFU74" description="Reserved for future use. Shall be 0." />
-    </Register>
-    <Register start="+0x5A4" size="4" name="SELRES" access="Read/Write" description="NFC-A SEL_RES auto-response settings" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RFU10" description="Reserved for future use. Shall be 0." />
-      <BitField start="2" size="1" name="CASCADE" description="Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)" />
-      <BitField start="3" size="2" name="RFU43" description="Reserved for future use. Shall be 0." />
-      <BitField start="5" size="2" name="PROTOCOL" description="Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification" />
-      <BitField start="7" size="1" name="RFU7" description="Reserved for future use. Shall be 0." />
-    </Register>
-    <Register start="+0x40C+0x000" size="4" name="FRAMESTATUS.RX" access="Read/Write" description="Result of last incoming frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERROR" description="No valid end of frame (EoF) detected">
-        <Enum name="CRCCorrect" start="0" description="Valid CRC detected" />
-        <Enum name="CRCError" start="1" description="CRC received does not match local check" />
-      </BitField>
-      <BitField start="2" size="1" name="PARITYSTATUS" description="Parity status of received frame">
-        <Enum name="ParityOK" start="0" description="Frame received with parity OK" />
-        <Enum name="ParityError" start="1" description="Frame received with parity error" />
-      </BitField>
-      <BitField start="3" size="1" name="OVERRUN" description="Overrun detected">
-        <Enum name="NoOverrun" start="0" description="No overrun detected" />
-        <Enum name="Overrun" start="1" description="Overrun error" />
-      </BitField>
-    </Register>
-    <Register start="+0x518+0x000" size="4" name="TXD.FRAMECONFIG" access="Read/Write" description="Configuration of outgoing frames" reset_value="0x00000017" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PARITY" description="Indicates if parity is added to the frame">
-        <Enum name="NoParity" start="0" description="Parity is not added to TX frames" />
-        <Enum name="Parity" start="1" description="Parity is added to TX frames" />
-      </BitField>
-      <BitField start="1" size="1" name="DISCARDMODE" description="Discarding unused bits at start or end of a frame">
-        <Enum name="DiscardEnd" start="0" description="Unused bits are discarded at end of frame (EoF)" />
-        <Enum name="DiscardStart" start="1" description="Unused bits are discarded at start of frame (SoF)" />
-      </BitField>
-      <BitField start="2" size="1" name="SOF" description="Adding SoF or not in TX frames">
-        <Enum name="NoSoF" start="0" description="SoF symbol not added" />
-        <Enum name="SoF" start="1" description="SoF symbol added" />
-      </BitField>
-      <BitField start="4" size="1" name="CRCMODETX" description="CRC mode for outgoing frames">
-        <Enum name="NoCRCTX" start="0" description="CRC is not added to the frame" />
-        <Enum name="CRC16TX" start="1" description="16 bit CRC added to the frame based on all the data read from RAM that is used in the frame" />
-      </BitField>
-    </Register>
-    <Register start="+0x518+0x004" size="4" name="TXD.AMOUNT" access="Read/Write" description="Size of outgoing frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="TXDATABITS" description="Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit)." />
-      <BitField start="3" size="9" name="TXDATABYTES" description="Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing" />
-    </Register>
-    <Register start="+0x520+0x000" size="4" name="RXD.FRAMECONFIG" access="Read/Write" description="Configuration of incoming frames" reset_value="0x00000015" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PARITY" description="Indicates if parity expected in RX frame">
-        <Enum name="NoParity" start="0" description="Parity is not expected in RX frames" />
-        <Enum name="Parity" start="1" description="Parity is expected in RX frames" />
-      </BitField>
-      <BitField start="2" size="1" name="SOF" description="SoF expected or not in RX frames">
-        <Enum name="NoSoF" start="0" description="SoF symbol is not expected in RX frames" />
-        <Enum name="SoF" start="1" description="SoF symbol is expected in RX frames" />
-      </BitField>
-      <BitField start="4" size="1" name="CRCMODERX" description="CRC mode for incoming frames">
-        <Enum name="NoCRCRX" start="0" description="CRC is not expected in RX frames" />
-        <Enum name="CRC16RX" start="1" description="Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0x004" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Size of last incoming frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDATABITS" description="Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing)." />
-      <BitField start="3" size="9" name="RXDATABYTES" description="Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOTE" start="0x40006000" description="GPIO Tasks and Events">
-    <Register start="+0x000+0" size="4" name="TASKS_OUT[0]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_OUT[1]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_OUT[2]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_OUT[3]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_OUT[4]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_OUT[5]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_OUT[6]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_OUT[7]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+0" size="4" name="TASKS_SET[0]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+4" size="4" name="TASKS_SET[1]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+8" size="4" name="TASKS_SET[2]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+12" size="4" name="TASKS_SET[3]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+16" size="4" name="TASKS_SET[4]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+20" size="4" name="TASKS_SET[5]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+24" size="4" name="TASKS_SET[6]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+28" size="4" name="TASKS_SET[7]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+0" size="4" name="TASKS_CLR[0]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+4" size="4" name="TASKS_CLR[1]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+8" size="4" name="TASKS_CLR[2]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+12" size="4" name="TASKS_CLR[3]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+16" size="4" name="TASKS_CLR[4]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+20" size="4" name="TASKS_CLR[5]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+24" size="4" name="TASKS_CLR[6]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+28" size="4" name="TASKS_CLR[7]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_IN[0]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_IN[1]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_IN[2]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_IN[3]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_IN[4]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_IN[5]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_IN[6]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_IN[7]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x17C" size="4" name="EVENTS_PORT" access="Read/Write" description="Event generated from multiple input GPIO pins with SENSE mechanism enabled" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IN0" description="Write '1' to Enable interrupt for IN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="IN1" description="Write '1' to Enable interrupt for IN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="IN2" description="Write '1' to Enable interrupt for IN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="IN3" description="Write '1' to Enable interrupt for IN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="IN4" description="Write '1' to Enable interrupt for IN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="IN5" description="Write '1' to Enable interrupt for IN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="IN6" description="Write '1' to Enable interrupt for IN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="IN7" description="Write '1' to Enable interrupt for IN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="PORT" description="Write '1' to Enable interrupt for PORT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IN0" description="Write '1' to Disable interrupt for IN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="IN1" description="Write '1' to Disable interrupt for IN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="IN2" description="Write '1' to Disable interrupt for IN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="IN3" description="Write '1' to Disable interrupt for IN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="IN4" description="Write '1' to Disable interrupt for IN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="IN5" description="Write '1' to Disable interrupt for IN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="IN6" description="Write '1' to Disable interrupt for IN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="IN7" description="Write '1' to Disable interrupt for IN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="PORT" description="Write '1' to Disable interrupt for PORT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0" size="4" name="CONFIG[0]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4" size="4" name="CONFIG[1]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+8" size="4" name="CONFIG[2]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+12" size="4" name="CONFIG[3]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+16" size="4" name="CONFIG[4]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+20" size="4" name="CONFIG[5]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+24" size="4" name="CONFIG[6]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+28" size="4" name="CONFIG[7]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SAADC" start="0x40007000" description="Analog to Digital Converter">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start the ADC and prepare the result buffer in RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_SAMPLE" access="WriteOnly" description="Take one ADC sample, if scan is enabled all channels are sampled" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop the ADC and terminate any on-going conversion" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CALIBRATEOFFSET" access="WriteOnly" description="Starts offset auto-calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_STARTED" access="Read/Write" description="The ADC has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="The ADC has filled up the Result buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_DONE" access="Read/Write" description="A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_RESULTDONE" access="Read/Write" description="A result is ready to get transferred to RAM." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_CALIBRATEDONE" access="Read/Write" description="Calibration is complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_STOPPED" access="Read/Write" description="The ADC has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="END" description="Enable or disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="DONE" description="Enable or disable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="RESULTDONE" description="Enable or disable interrupt for RESULTDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="CALIBRATEDONE" description="Enable or disable interrupt for CALIBRATEDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="CH0LIMITH" description="Enable or disable interrupt for CH[0].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="CH0LIMITL" description="Enable or disable interrupt for CH[0].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="CH1LIMITH" description="Enable or disable interrupt for CH[1].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="CH1LIMITL" description="Enable or disable interrupt for CH[1].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="CH2LIMITH" description="Enable or disable interrupt for CH[2].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="CH2LIMITL" description="Enable or disable interrupt for CH[2].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="CH3LIMITH" description="Enable or disable interrupt for CH[3].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="CH3LIMITL" description="Enable or disable interrupt for CH[3].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="CH4LIMITH" description="Enable or disable interrupt for CH[4].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="CH4LIMITL" description="Enable or disable interrupt for CH[4].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="CH5LIMITH" description="Enable or disable interrupt for CH[5].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="CH5LIMITL" description="Enable or disable interrupt for CH[5].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="CH6LIMITH" description="Enable or disable interrupt for CH[6].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="CH6LIMITL" description="Enable or disable interrupt for CH[6].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="CH7LIMITH" description="Enable or disable interrupt for CH[7].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="21" size="1" name="CH7LIMITL" description="Enable or disable interrupt for CH[7].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="DONE" description="Write '1' to Enable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RESULTDONE" description="Write '1' to Enable interrupt for RESULTDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CALIBRATEDONE" description="Write '1' to Enable interrupt for CALIBRATEDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH0LIMITH" description="Write '1' to Enable interrupt for CH[0].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH0LIMITL" description="Write '1' to Enable interrupt for CH[0].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH1LIMITH" description="Write '1' to Enable interrupt for CH[1].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH1LIMITL" description="Write '1' to Enable interrupt for CH[1].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH2LIMITH" description="Write '1' to Enable interrupt for CH[2].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH2LIMITL" description="Write '1' to Enable interrupt for CH[2].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH3LIMITH" description="Write '1' to Enable interrupt for CH[3].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH3LIMITL" description="Write '1' to Enable interrupt for CH[3].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH4LIMITH" description="Write '1' to Enable interrupt for CH[4].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH4LIMITL" description="Write '1' to Enable interrupt for CH[4].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH5LIMITH" description="Write '1' to Enable interrupt for CH[5].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH5LIMITL" description="Write '1' to Enable interrupt for CH[5].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH6LIMITH" description="Write '1' to Enable interrupt for CH[6].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH6LIMITL" description="Write '1' to Enable interrupt for CH[6].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH7LIMITH" description="Write '1' to Enable interrupt for CH[7].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH7LIMITL" description="Write '1' to Enable interrupt for CH[7].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="DONE" description="Write '1' to Disable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RESULTDONE" description="Write '1' to Disable interrupt for RESULTDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CALIBRATEDONE" description="Write '1' to Disable interrupt for CALIBRATEDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH0LIMITH" description="Write '1' to Disable interrupt for CH[0].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH0LIMITL" description="Write '1' to Disable interrupt for CH[0].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH1LIMITH" description="Write '1' to Disable interrupt for CH[1].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH1LIMITL" description="Write '1' to Disable interrupt for CH[1].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH2LIMITH" description="Write '1' to Disable interrupt for CH[2].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH2LIMITL" description="Write '1' to Disable interrupt for CH[2].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH3LIMITH" description="Write '1' to Disable interrupt for CH[3].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH3LIMITL" description="Write '1' to Disable interrupt for CH[3].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH4LIMITH" description="Write '1' to Disable interrupt for CH[4].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH4LIMITL" description="Write '1' to Disable interrupt for CH[4].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH5LIMITH" description="Write '1' to Disable interrupt for CH[5].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH5LIMITL" description="Write '1' to Disable interrupt for CH[5].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH6LIMITH" description="Write '1' to Disable interrupt for CH[6].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH6LIMITL" description="Write '1' to Disable interrupt for CH[6].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH7LIMITH" description="Write '1' to Disable interrupt for CH[7].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH7LIMITL" description="Write '1' to Disable interrupt for CH[7].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Status">
-        <Enum name="Ready" start="0" description="ADC is ready. No on-going conversion." />
-        <Enum name="Busy" start="1" description="ADC is busy. Conversion in progress." />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable or disable ADC" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable ADC">
-        <Enum name="Disabled" start="0" description="Disable ADC" />
-        <Enum name="Enabled" start="1" description="Enable ADC" />
-      </BitField>
-    </Register>
-    <Register start="+0x5F0" size="4" name="RESOLUTION" access="Read/Write" description="Resolution configuration" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="VAL" description="Set the resolution">
-        <Enum name="8bit" start="0" description="8 bit" />
-        <Enum name="10bit" start="1" description="10 bit" />
-        <Enum name="12bit" start="2" description="12 bit" />
-        <Enum name="14bit" start="3" description="14 bit" />
-      </BitField>
-    </Register>
-    <Register start="+0x5F4" size="4" name="OVERSAMPLE" access="Read/Write" description="Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OVERSAMPLE" description="Oversample control">
-        <Enum name="Bypass" start="0" description="Bypass oversampling" />
-        <Enum name="Over2x" start="1" description="Oversample 2x" />
-        <Enum name="Over4x" start="2" description="Oversample 4x" />
-        <Enum name="Over8x" start="3" description="Oversample 8x" />
-        <Enum name="Over16x" start="4" description="Oversample 16x" />
-        <Enum name="Over32x" start="5" description="Oversample 32x" />
-        <Enum name="Over64x" start="6" description="Oversample 64x" />
-        <Enum name="Over128x" start="7" description="Oversample 128x" />
-        <Enum name="Over256x" start="8" description="Oversample 256x" />
-      </BitField>
-    </Register>
-    <Register start="+0x5F8" size="4" name="SAMPLERATE" access="Read/Write" description="Controls normal or continuous sample rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="CC" description="Capture and compare value. Sample rate is 16 MHz/CC" />
-      <BitField start="12" size="1" name="MODE" description="Select mode for sample rate control">
-        <Enum name="Task" start="0" description="Rate is controlled from SAMPLE task" />
-        <Enum name="Timers" start="1" description="Rate is controlled from local timer (use CC to control the rate)" />
-      </BitField>
-    </Register>
-    <Register start="+0x118+0*8+0x000" size="4" name="EVENTS_CH[0].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+0*8+0x004" size="4" name="EVENTS_CH[0].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+1*8+0x000" size="4" name="EVENTS_CH[1].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+1*8+0x004" size="4" name="EVENTS_CH[1].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+2*8+0x000" size="4" name="EVENTS_CH[2].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+2*8+0x004" size="4" name="EVENTS_CH[2].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+3*8+0x000" size="4" name="EVENTS_CH[3].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+3*8+0x004" size="4" name="EVENTS_CH[3].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+4*8+0x000" size="4" name="EVENTS_CH[4].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+4*8+0x004" size="4" name="EVENTS_CH[4].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+5*8+0x000" size="4" name="EVENTS_CH[5].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+5*8+0x004" size="4" name="EVENTS_CH[5].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+6*8+0x000" size="4" name="EVENTS_CH[6].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+6*8+0x004" size="4" name="EVENTS_CH[6].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+7*8+0x000" size="4" name="EVENTS_CH[7].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+7*8+0x004" size="4" name="EVENTS_CH[7].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x510+0*16+0x000" size="4" name="CH[0].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0*16+0x004" size="4" name="CH[0].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0*16+0x008" size="4" name="CH[0].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0*16+0x00C" size="4" name="CH[0].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+1*16+0x000" size="4" name="CH[1].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+1*16+0x004" size="4" name="CH[1].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+1*16+0x008" size="4" name="CH[1].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+1*16+0x00C" size="4" name="CH[1].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+2*16+0x000" size="4" name="CH[2].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+2*16+0x004" size="4" name="CH[2].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+2*16+0x008" size="4" name="CH[2].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+2*16+0x00C" size="4" name="CH[2].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+3*16+0x000" size="4" name="CH[3].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+3*16+0x004" size="4" name="CH[3].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+3*16+0x008" size="4" name="CH[3].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+3*16+0x00C" size="4" name="CH[3].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+4*16+0x000" size="4" name="CH[4].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4*16+0x004" size="4" name="CH[4].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4*16+0x008" size="4" name="CH[4].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4*16+0x00C" size="4" name="CH[4].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+5*16+0x000" size="4" name="CH[5].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+5*16+0x004" size="4" name="CH[5].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+5*16+0x008" size="4" name="CH[5].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+5*16+0x00C" size="4" name="CH[5].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+6*16+0x000" size="4" name="CH[6].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+6*16+0x004" size="4" name="CH[6].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+6*16+0x008" size="4" name="CH[6].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+6*16+0x00C" size="4" name="CH[6].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+7*16+0x000" size="4" name="CH[7].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+7*16+0x004" size="4" name="CH[7].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+7*16+0x008" size="4" name="CH[7].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+7*16+0x00C" size="4" name="CH[7].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x62C+0x000" size="4" name="RESULT.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x62C+0x004" size="4" name="RESULT.MAXCNT" access="Read/Write" description="Maximum number of buffer words to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MAXCNT" description="Maximum number of buffer words to transfer" />
-    </Register>
-    <Register start="+0x62C+0x008" size="4" name="RESULT.AMOUNT" access="ReadOnly" description="Number of buffer words transferred since last START" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="AMOUNT" description="Number of buffer words transferred since last START. This register can be read after an END or STOPPED event." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40008000" description="Timer/Counter 0">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40009000" description="Timer/Counter 1">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x4000A000" description="Timer/Counter 2">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC0" start="0x4000B000" description="Real time counter 0">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_TRIGOVRFLW" access="WriteOnly" description="Set COUNTER to 0xFFFFF0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TICK" access="Read/Write" description="Event on COUNTER increment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_OVRFLW" access="Read/Write" description="Event on COUNTER overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x340" size="4" name="EVTEN" access="Read/Write" description="Enable or disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Enable or disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Enable or disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Enable or disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Enable or disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Enable or disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Enable or disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x344" size="4" name="EVTENSET" access="Read/Write" description="Enable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x348" size="4" name="EVTENCLR" access="Read/Write" description="Disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="COUNTER" access="ReadOnly" description="Current COUNTER value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNTER" description="Counter value" />
-    </Register>
-    <Register start="+0x508" size="4" name="PRESCALER" access="Read/Write" description="12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TEMP" start="0x4000C000" description="Temperature Sensor">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start temperature measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop temperature measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_DATARDY" access="Read/Write" description="Temperature measurement complete, data ready" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Write '1' to Enable interrupt for DATARDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Write '1' to Disable interrupt for DATARDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="TEMP" access="ReadOnly" description="Temperature in degC (0.25deg steps)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEMP" description="Temperature in degC (0.25deg steps)" />
-    </Register>
-    <Register start="+0x520" size="4" name="A0" access="Read/Write" description="Slope of 1st piece wise linear function" reset_value="0x00000326" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A0" description="Slope of 1st piece wise linear function" />
-    </Register>
-    <Register start="+0x524" size="4" name="A1" access="Read/Write" description="Slope of 2nd piece wise linear function" reset_value="0x00000348" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A1" description="Slope of 2nd piece wise linear function" />
-    </Register>
-    <Register start="+0x528" size="4" name="A2" access="Read/Write" description="Slope of 3rd piece wise linear function" reset_value="0x000003AA" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A2" description="Slope of 3rd piece wise linear function" />
-    </Register>
-    <Register start="+0x52C" size="4" name="A3" access="Read/Write" description="Slope of 4th piece wise linear function" reset_value="0x0000040E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A3" description="Slope of 4th piece wise linear function" />
-    </Register>
-    <Register start="+0x530" size="4" name="A4" access="Read/Write" description="Slope of 5th piece wise linear function" reset_value="0x000004BD" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A4" description="Slope of 5th piece wise linear function" />
-    </Register>
-    <Register start="+0x534" size="4" name="A5" access="Read/Write" description="Slope of 6th piece wise linear function" reset_value="0x000005A3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A5" description="Slope of 6th piece wise linear function" />
-    </Register>
-    <Register start="+0x540" size="4" name="B0" access="Read/Write" description="y-intercept of 1st piece wise linear function" reset_value="0x00003FEF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B0" description="y-intercept of 1st piece wise linear function" />
-    </Register>
-    <Register start="+0x544" size="4" name="B1" access="Read/Write" description="y-intercept of 2nd piece wise linear function" reset_value="0x00003FBE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B1" description="y-intercept of 2nd piece wise linear function" />
-    </Register>
-    <Register start="+0x548" size="4" name="B2" access="Read/Write" description="y-intercept of 3rd piece wise linear function" reset_value="0x00003FBE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B2" description="y-intercept of 3rd piece wise linear function" />
-    </Register>
-    <Register start="+0x54C" size="4" name="B3" access="Read/Write" description="y-intercept of 4th piece wise linear function" reset_value="0x00000012" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B3" description="y-intercept of 4th piece wise linear function" />
-    </Register>
-    <Register start="+0x550" size="4" name="B4" access="Read/Write" description="y-intercept of 5th piece wise linear function" reset_value="0x00000124" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B4" description="y-intercept of 5th piece wise linear function" />
-    </Register>
-    <Register start="+0x554" size="4" name="B5" access="Read/Write" description="y-intercept of 6th piece wise linear function" reset_value="0x0000027C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B5" description="y-intercept of 6th piece wise linear function" />
-    </Register>
-    <Register start="+0x560" size="4" name="T0" access="Read/Write" description="End point of 1st piece wise linear function" reset_value="0x000000E2" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T0" description="End point of 1st piece wise linear function" />
-    </Register>
-    <Register start="+0x564" size="4" name="T1" access="Read/Write" description="End point of 2nd piece wise linear function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T1" description="End point of 2nd piece wise linear function" />
-    </Register>
-    <Register start="+0x568" size="4" name="T2" access="Read/Write" description="End point of 3rd piece wise linear function" reset_value="0x00000019" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T2" description="End point of 3rd piece wise linear function" />
-    </Register>
-    <Register start="+0x56C" size="4" name="T3" access="Read/Write" description="End point of 4th piece wise linear function" reset_value="0x0000003C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T3" description="End point of 4th piece wise linear function" />
-    </Register>
-    <Register start="+0x570" size="4" name="T4" access="Read/Write" description="End point of 5th piece wise linear function" reset_value="0x00000050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T4" description="End point of 5th piece wise linear function" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RNG" start="0x4000D000" description="Random Number Generator">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Task starting the random number generator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Task stopping the random number generator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_VALRDY" access="Read/Write" description="Event being generated for every new random number written to the VALUE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VALRDY_STOP" description="Shortcut between VALRDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VALRDY" description="Write '1' to Enable interrupt for VALRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VALRDY" description="Write '1' to Disable interrupt for VALRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DERCEN" description="Bias correction">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="VALUE" access="ReadOnly" description="Output random number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="VALUE" description="Generated random number" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ECB" start="0x4000E000" description="AES ECB Mode Encryption">
-    <Register start="+0x000" size="4" name="TASKS_STARTECB" access="WriteOnly" description="Start ECB block encrypt" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPECB" access="WriteOnly" description="Abort a possible executing ECB operation" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_ENDECB" access="Read/Write" description="ECB block encrypt complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_ERRORECB" access="Read/Write" description="ECB block encrypt aborted because of a STOPECB task or due to an error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDECB" description="Write '1' to Enable interrupt for ENDECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ERRORECB" description="Write '1' to Enable interrupt for ERRORECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDECB" description="Write '1' to Disable interrupt for ENDECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ERRORECB" description="Write '1' to Disable interrupt for ERRORECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="ECBDATAPTR" access="Read/Write" description="ECB block encrypt memory pointers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ECBDATAPTR" description="Pointer to the ECB data structure (see Table 1 ECB data structure overview)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCM" start="0x4000F000" description="AES CCM Mode Encryption">
-    <Register start="+0x000" size="4" name="TASKS_KSGEN" access="WriteOnly" description="Start generation of key-stream. This operation will stop by itself when completed." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_CRYPT" access="WriteOnly" description="Start encryption/decryption. This operation will stop by itself when completed." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop encryption/decryption" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_RATEOVERRIDE" access="WriteOnly" description="Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_ENDKSGEN" access="Read/Write" description="Key-stream generation complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_ENDCRYPT" access="Read/Write" description="Encrypt/decrypt complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_ERROR" access="Read/Write" description="Deprecated register -  CCM error event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDKSGEN_CRYPT" description="Shortcut between ENDKSGEN event and CRYPT task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDKSGEN" description="Write '1' to Enable interrupt for ENDKSGEN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ENDCRYPT" description="Write '1' to Enable interrupt for ENDCRYPT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDKSGEN" description="Write '1' to Disable interrupt for ENDKSGEN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ENDCRYPT" description="Write '1' to Disable interrupt for ENDCRYPT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="MICSTATUS" access="ReadOnly" description="MIC check result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MICSTATUS" description="The result of the MIC check performed during the previous decryption operation">
-        <Enum name="CheckFailed" start="0" description="MIC check failed" />
-        <Enum name="CheckPassed" start="1" description="MIC check passed" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable CCM">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="2" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Operation mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.">
-        <Enum name="Encryption" start="0" description="AES CCM packet encryption mode" />
-        <Enum name="Decryption" start="1" description="AES CCM packet decryption mode" />
-      </BitField>
-      <BitField start="16" size="2" name="DATARATE" description="Radio data rate that the CCM shall run synchronous with">
-        <Enum name="1Mbit" start="0" description="1 Mbps" />
-        <Enum name="2Mbit" start="1" description="2 Mbps" />
-        <Enum name="125Kbps" start="2" description="125 Kbps" />
-        <Enum name="500Kbps" start="3" description="500 Kbps" />
-      </BitField>
-      <BitField start="24" size="1" name="LENGTH" description="Packet length configuration">
-        <Enum name="Default" start="0" description="Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated." />
-        <Enum name="Extended" start="1" description="Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated." />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="CNFPTR" access="Read/Write" description="Pointer to data structure holding AES key and NONCE vector" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CNFPTR" description="Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)" />
-    </Register>
-    <Register start="+0x50C" size="4" name="INPTR" access="Read/Write" description="Input pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INPTR" description="Input pointer" />
-    </Register>
-    <Register start="+0x510" size="4" name="OUTPTR" access="Read/Write" description="Output pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTPTR" description="Output pointer" />
-    </Register>
-    <Register start="+0x514" size="4" name="SCRATCHPTR" access="Read/Write" description="Pointer to data area used for temporary storage" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SCRATCHPTR" description="Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption." />
-    </Register>
-    <Register start="+0x518" size="4" name="MAXPACKETSIZE" access="Read/Write" description="Length of key-stream generated when MODE.LENGTH = Extended." reset_value="0x000000FB" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXPACKETSIZE" description="Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted." />
-    </Register>
-    <Register start="+0x51C" size="4" name="RATEOVERRIDE" access="Read/Write" description="Data rate override setting." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RATEOVERRIDE" description="Data rate override setting.">
-        <Enum name="1Mbit" start="0" description="1 Mbps" />
-        <Enum name="2Mbit" start="1" description="2 Mbps" />
-        <Enum name="125Kbps" start="2" description="125 Kbps" />
-        <Enum name="500Kbps" start="3" description="500 Kbps" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="AAR" start="0x4000F000" description="Accelerated Address Resolver">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start resolving addresses based on IRKs specified in the IRK data structure" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop resolving addresses" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_END" access="Read/Write" description="Address resolution procedure complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_RESOLVED" access="Read/Write" description="Address resolved" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_NOTRESOLVED" access="Read/Write" description="Address not resolved" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RESOLVED" description="Write '1' to Enable interrupt for RESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="NOTRESOLVED" description="Write '1' to Enable interrupt for NOTRESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RESOLVED" description="Write '1' to Disable interrupt for RESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="NOTRESOLVED" description="Write '1' to Disable interrupt for NOTRESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Resolution status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="STATUS" description="The IRK that was used last time an address was resolved" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable AAR" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable AAR">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="3" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="NIRK" access="Read/Write" description="Number of IRKs" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="NIRK" description="Number of Identity root keys available in the IRK data structure" />
-    </Register>
-    <Register start="+0x508" size="4" name="IRKPTR" access="Read/Write" description="Pointer to IRK data structure" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IRKPTR" description="Pointer to the IRK data structure" />
-    </Register>
-    <Register start="+0x510" size="4" name="ADDRPTR" access="Read/Write" description="Pointer to the resolvable address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRPTR" description="Pointer to the resolvable address (6-bytes)" />
-    </Register>
-    <Register start="+0x514" size="4" name="SCRATCHPTR" access="Read/Write" description="Pointer to data area used for temporary storage" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SCRATCHPTR" description="Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WDT" start="0x40010000" description="Watchdog Timer">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start the watchdog" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TIMEOUT" access="Read/Write" description="Watchdog timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMEOUT" description="Write '1' to Enable interrupt for TIMEOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMEOUT" description="Write '1' to Disable interrupt for TIMEOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RUNSTATUS" access="ReadOnly" description="Run status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUNSTATUS" description="Indicates whether or not the watchdog is running">
-        <Enum name="NotRunning" start="0" description="Watchdog not running" />
-        <Enum name="Running" start="1" description="Watchdog is running" />
-      </BitField>
-    </Register>
-    <Register start="+0x404" size="4" name="REQSTATUS" access="ReadOnly" description="Request status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RR0" description="Request status for RR[0] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[0] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[0] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="1" size="1" name="RR1" description="Request status for RR[1] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[1] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[1] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="2" size="1" name="RR2" description="Request status for RR[2] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[2] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[2] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="3" size="1" name="RR3" description="Request status for RR[3] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[3] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[3] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="4" size="1" name="RR4" description="Request status for RR[4] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[4] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[4] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="5" size="1" name="RR5" description="Request status for RR[5] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[5] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[5] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="6" size="1" name="RR6" description="Request status for RR[6] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[6] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[6] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="7" size="1" name="RR7" description="Request status for RR[7] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[7] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[7] register is enabled, and are not yet requesting reload" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CRV" access="Read/Write" description="Counter reload value" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRV" description="Counter reload value in number of cycles of the 32.768 kHz clock" />
-    </Register>
-    <Register start="+0x508" size="4" name="RREN" access="Read/Write" description="Enable register for reload request registers" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RR0" description="Enable or disable RR[0] register">
-        <Enum name="Disabled" start="0" description="Disable RR[0] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[0] register" />
-      </BitField>
-      <BitField start="1" size="1" name="RR1" description="Enable or disable RR[1] register">
-        <Enum name="Disabled" start="0" description="Disable RR[1] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[1] register" />
-      </BitField>
-      <BitField start="2" size="1" name="RR2" description="Enable or disable RR[2] register">
-        <Enum name="Disabled" start="0" description="Disable RR[2] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[2] register" />
-      </BitField>
-      <BitField start="3" size="1" name="RR3" description="Enable or disable RR[3] register">
-        <Enum name="Disabled" start="0" description="Disable RR[3] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[3] register" />
-      </BitField>
-      <BitField start="4" size="1" name="RR4" description="Enable or disable RR[4] register">
-        <Enum name="Disabled" start="0" description="Disable RR[4] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[4] register" />
-      </BitField>
-      <BitField start="5" size="1" name="RR5" description="Enable or disable RR[5] register">
-        <Enum name="Disabled" start="0" description="Disable RR[5] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[5] register" />
-      </BitField>
-      <BitField start="6" size="1" name="RR6" description="Enable or disable RR[6] register">
-        <Enum name="Disabled" start="0" description="Disable RR[6] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[6] register" />
-      </BitField>
-      <BitField start="7" size="1" name="RR7" description="Enable or disable RR[7] register">
-        <Enum name="Disabled" start="0" description="Disable RR[7] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[7] register" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEP" description="Configure the watchdog to either be paused, or kept running, while the CPU is sleeping">
-        <Enum name="Pause" start="0" description="Pause watchdog while the CPU is sleeping" />
-        <Enum name="Run" start="1" description="Keep the watchdog running while the CPU is sleeping" />
-      </BitField>
-      <BitField start="3" size="1" name="HALT" description="Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger">
-        <Enum name="Pause" start="0" description="Pause watchdog while the CPU is halted by the debugger" />
-        <Enum name="Run" start="1" description="Keep the watchdog running while the CPU is halted by the debugger" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+0" size="4" name="RR[0]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+4" size="4" name="RR[1]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+8" size="4" name="RR[2]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+12" size="4" name="RR[3]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+16" size="4" name="RR[4]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+20" size="4" name="RR[5]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+24" size="4" name="RR[6]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+28" size="4" name="RR[7]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC1" start="0x40011000" description="Real time counter 1">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_TRIGOVRFLW" access="WriteOnly" description="Set COUNTER to 0xFFFFF0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TICK" access="Read/Write" description="Event on COUNTER increment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_OVRFLW" access="Read/Write" description="Event on COUNTER overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x340" size="4" name="EVTEN" access="Read/Write" description="Enable or disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Enable or disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Enable or disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Enable or disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Enable or disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Enable or disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Enable or disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x344" size="4" name="EVTENSET" access="Read/Write" description="Enable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x348" size="4" name="EVTENCLR" access="Read/Write" description="Disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="COUNTER" access="ReadOnly" description="Current COUNTER value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNTER" description="Counter value" />
-    </Register>
-    <Register start="+0x508" size="4" name="PRESCALER" access="Read/Write" description="12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QDEC" start="0x40012000" description="Quadrature Decoder">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Task starting the quadrature decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Task stopping the quadrature decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_READCLRACC" access="WriteOnly" description="Read and clear ACC and ACCDBL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_RDCLRACC" access="WriteOnly" description="Read and clear ACC" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_RDCLRDBL" access="WriteOnly" description="Read and clear ACCDBL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_SAMPLERDY" access="Read/Write" description="Event being generated for every new sample value written to the SAMPLE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_REPORTRDY" access="Read/Write" description="Non-null report ready" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_ACCOF" access="Read/Write" description="ACC or ACCDBL register overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_DBLRDY" access="Read/Write" description="Double displacement(s) detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_STOPPED" access="Read/Write" description="QDEC has been stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REPORTRDY_READCLRACC" description="Shortcut between REPORTRDY event and READCLRACC task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SAMPLERDY_STOP" description="Shortcut between SAMPLERDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="REPORTRDY_RDCLRACC" description="Shortcut between REPORTRDY event and RDCLRACC task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="REPORTRDY_STOP" description="Shortcut between REPORTRDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="DBLRDY_RDCLRDBL" description="Shortcut between DBLRDY event and RDCLRDBL task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="DBLRDY_STOP" description="Shortcut between DBLRDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="SAMPLERDY_READCLRACC" description="Shortcut between SAMPLERDY event and READCLRACC task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SAMPLERDY" description="Write '1' to Enable interrupt for SAMPLERDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REPORTRDY" description="Write '1' to Enable interrupt for REPORTRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ACCOF" description="Write '1' to Enable interrupt for ACCOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DBLRDY" description="Write '1' to Enable interrupt for DBLRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SAMPLERDY" description="Write '1' to Disable interrupt for SAMPLERDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REPORTRDY" description="Write '1' to Disable interrupt for REPORTRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ACCOF" description="Write '1' to Disable interrupt for ACCOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DBLRDY" description="Write '1' to Disable interrupt for DBLRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable the quadrature decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable the quadrature decoder">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="LEDPOL" access="Read/Write" description="LED output pin polarity" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEDPOL" description="LED output pin polarity">
-        <Enum name="ActiveLow" start="0" description="Led active on output pin low" />
-        <Enum name="ActiveHigh" start="1" description="Led active on output pin high" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="SAMPLEPER" access="Read/Write" description="Sample period" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLEPER" description="Sample period. The SAMPLE register will be updated for every new sample">
-        <Enum name="128us" start="0" description="128 us" />
-        <Enum name="256us" start="1" description="256 us" />
-        <Enum name="512us" start="2" description="512 us" />
-        <Enum name="1024us" start="3" description="1024 us" />
-        <Enum name="2048us" start="4" description="2048 us" />
-        <Enum name="4096us" start="5" description="4096 us" />
-        <Enum name="8192us" start="6" description="8192 us" />
-        <Enum name="16384us" start="7" description="16384 us" />
-        <Enum name="32ms" start="8" description="32768 us" />
-        <Enum name="65ms" start="9" description="65536 us" />
-        <Enum name="131ms" start="10" description="131072 us" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="SAMPLE" access="ReadOnly" description="Motion sample value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLE" description="Last motion sample" />
-    </Register>
-    <Register start="+0x510" size="4" name="REPORTPER" access="Read/Write" description="Number of samples to be taken before REPORTRDY and DBLRDY events can be generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REPORTPER" description="Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated">
-        <Enum name="10Smpl" start="0" description="10 samples / report" />
-        <Enum name="40Smpl" start="1" description="40 samples / report" />
-        <Enum name="80Smpl" start="2" description="80 samples / report" />
-        <Enum name="120Smpl" start="3" description="120 samples / report" />
-        <Enum name="160Smpl" start="4" description="160 samples / report" />
-        <Enum name="200Smpl" start="5" description="200 samples / report" />
-        <Enum name="240Smpl" start="6" description="240 samples / report" />
-        <Enum name="280Smpl" start="7" description="280 samples / report" />
-        <Enum name="1Smpl" start="8" description="1 sample / report" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="ACC" access="ReadOnly" description="Register accumulating the valid transitions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACC" description="Register accumulating all valid samples (not double transition) read from the SAMPLE register" />
-    </Register>
-    <Register start="+0x518" size="4" name="ACCREAD" access="ReadOnly" description="Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACCREAD" description="Snapshot of the ACC register." />
-    </Register>
-    <Register start="+0x528" size="4" name="DBFEN" access="Read/Write" description="Enable input debounce filters" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBFEN" description="Enable input debounce filters">
-        <Enum name="Disabled" start="0" description="Debounce input filters disabled" />
-        <Enum name="Enabled" start="1" description="Debounce input filters enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x540" size="4" name="LEDPRE" access="Read/Write" description="Time period the LED is switched ON prior to sampling" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="LEDPRE" description="Period in us the LED is switched on prior to sampling" />
-    </Register>
-    <Register start="+0x544" size="4" name="ACCDBL" access="ReadOnly" description="Register accumulating the number of detected double transitions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ACCDBL" description="Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 )." />
-    </Register>
-    <Register start="+0x548" size="4" name="ACCDBLREAD" access="ReadOnly" description="Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ACCDBLREAD" description="Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered." />
-    </Register>
-    <Register start="+0x51C+0x000" size="4" name="PSEL.LED" access="Read/Write" description="Pin select for LED signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C+0x004" size="4" name="PSEL.A" access="Read/Write" description="Pin select for A signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C+0x008" size="4" name="PSEL.B" access="Read/Write" description="Pin select for B signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="COMP" start="0x40013000" description="Comparator">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_SAMPLE" access="WriteOnly" description="Sample comparator value" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="COMP is ready and output is valid" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_DOWN" access="Read/Write" description="Downward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_UP" access="Read/Write" description="Upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_CROSS" access="Read/Write" description="Downward or upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY_SAMPLE" description="Shortcut between READY event and SAMPLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="READY_STOP" description="Shortcut between READY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="DOWN_STOP" description="Shortcut between DOWN event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="UP_STOP" description="Shortcut between UP event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="CROSS_STOP" description="Shortcut between CROSS event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Enable or disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Enable or disable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Enable or disable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Enable or disable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Enable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Enable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Enable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Disable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Disable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Disable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RESULT" access="ReadOnly" description="Compare result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESULT" description="Result of last compare. Decision point SAMPLE task.">
-        <Enum name="Below" start="0" description="Input voltage is below the threshold (VIN+ &amp;lt; VIN-)" />
-        <Enum name="Above" start="1" description="Input voltage is above the threshold (VIN+ &amp;gt; VIN-)" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="COMP enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable COMP">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="2" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PSEL" access="Read/Write" description="Pin select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PSEL" description="Analog pin select">
-        <Enum name="AnalogInput0" start="0" description="AIN0 selected as analog input" />
-        <Enum name="AnalogInput1" start="1" description="AIN1 selected as analog input" />
-        <Enum name="AnalogInput2" start="2" description="AIN2 selected as analog input" />
-        <Enum name="AnalogInput3" start="3" description="AIN3 selected as analog input" />
-        <Enum name="AnalogInput4" start="4" description="AIN4 selected as analog input" />
-        <Enum name="AnalogInput5" start="5" description="AIN5 selected as analog input" />
-        <Enum name="AnalogInput6" start="6" description="AIN6 selected as analog input" />
-        <Enum name="AnalogInput7" start="7" description="AIN7 selected as analog input" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="REFSEL" access="Read/Write" description="Reference source select" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="REFSEL" description="Reference select">
-        <Enum name="Int1V2" start="0" description="VREF = internal 1.2 V reference (VDD &amp;gt;= 1.7 V)" />
-        <Enum name="Int1V8" start="1" description="VREF = internal 1.8 V reference (VDD &amp;gt;= VREF + 0.2 V)" />
-        <Enum name="Int2V4" start="2" description="VREF = internal 2.4 V reference (VDD &amp;gt;= VREF + 0.2 V)" />
-        <Enum name="VDD" start="4" description="VREF = VDD" />
-        <Enum name="ARef" start="5" description="VREF = AREF (VDD &amp;gt;= VREF &amp;gt;= AREFMIN)" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="EXTREFSEL" access="Read/Write" description="External reference select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTREFSEL" description="External analog reference select">
-        <Enum name="AnalogReference0" start="0" description="Use AIN0 as external analog reference" />
-        <Enum name="AnalogReference1" start="1" description="Use AIN1 as external analog reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x530" size="4" name="TH" access="Read/Write" description="Threshold configuration for hysteresis unit" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="THDOWN" description="VDOWN = (THDOWN+1)/64*VREF" />
-      <BitField start="8" size="6" name="THUP" description="VUP = (THUP+1)/64*VREF" />
-    </Register>
-    <Register start="+0x534" size="4" name="MODE" access="Read/Write" description="Mode configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SP" description="Speed and power mode">
-        <Enum name="Low" start="0" description="Low power mode" />
-        <Enum name="Normal" start="1" description="Normal mode" />
-        <Enum name="High" start="2" description="High speed mode" />
-      </BitField>
-      <BitField start="8" size="1" name="MAIN" description="Main operation mode">
-        <Enum name="SE" start="0" description="Single ended mode" />
-        <Enum name="Diff" start="1" description="Differential mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x538" size="4" name="HYST" access="Read/Write" description="Comparator hysteresis enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HYST" description="Comparator hysteresis">
-        <Enum name="NoHyst" start="0" description="Comparator hysteresis disabled" />
-        <Enum name="Hyst50mV" start="1" description="Comparator hysteresis enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x53C" size="4" name="ISOURCE" access="Read/Write" description="Current source select on analog input" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ISOURCE" description="Comparator hysteresis">
-        <Enum name="Off" start="0" description="Current source disabled" />
-        <Enum name="Ien2mA5" start="1" description="Current source enabled (+/- 2.5 uA)" />
-        <Enum name="Ien5mA" start="2" description="Current source enabled (+/- 5 uA)" />
-        <Enum name="Ien10mA" start="3" description="Current source enabled (+/- 10 uA)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LPCOMP" start="0x40013000" description="Low Power Comparator">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_SAMPLE" access="WriteOnly" description="Sample comparator value" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="LPCOMP is ready and output is valid" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_DOWN" access="Read/Write" description="Downward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_UP" access="Read/Write" description="Upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_CROSS" access="Read/Write" description="Downward or upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY_SAMPLE" description="Shortcut between READY event and SAMPLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="READY_STOP" description="Shortcut between READY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="DOWN_STOP" description="Shortcut between DOWN event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="UP_STOP" description="Shortcut between UP event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="CROSS_STOP" description="Shortcut between CROSS event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Enable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Enable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Enable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Disable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Disable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Disable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RESULT" access="ReadOnly" description="Compare result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESULT" description="Result of last compare. Decision point SAMPLE task.">
-        <Enum name="Below" start="0" description="Input voltage is below the reference threshold (VIN+ &amp;lt; VIN-)." />
-        <Enum name="Above" start="1" description="Input voltage is above the reference threshold (VIN+ &amp;gt; VIN-)." />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable LPCOMP" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable LPCOMP">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PSEL" access="Read/Write" description="Input pin select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PSEL" description="Analog pin select">
-        <Enum name="AnalogInput0" start="0" description="AIN0 selected as analog input" />
-        <Enum name="AnalogInput1" start="1" description="AIN1 selected as analog input" />
-        <Enum name="AnalogInput2" start="2" description="AIN2 selected as analog input" />
-        <Enum name="AnalogInput3" start="3" description="AIN3 selected as analog input" />
-        <Enum name="AnalogInput4" start="4" description="AIN4 selected as analog input" />
-        <Enum name="AnalogInput5" start="5" description="AIN5 selected as analog input" />
-        <Enum name="AnalogInput6" start="6" description="AIN6 selected as analog input" />
-        <Enum name="AnalogInput7" start="7" description="AIN7 selected as analog input" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="REFSEL" access="Read/Write" description="Reference select" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference select">
-        <Enum name="Ref1_8Vdd" start="0" description="VDD * 1/8 selected as reference" />
-        <Enum name="Ref2_8Vdd" start="1" description="VDD * 2/8 selected as reference" />
-        <Enum name="Ref3_8Vdd" start="2" description="VDD * 3/8 selected as reference" />
-        <Enum name="Ref4_8Vdd" start="3" description="VDD * 4/8 selected as reference" />
-        <Enum name="Ref5_8Vdd" start="4" description="VDD * 5/8 selected as reference" />
-        <Enum name="Ref6_8Vdd" start="5" description="VDD * 6/8 selected as reference" />
-        <Enum name="Ref7_8Vdd" start="6" description="VDD * 7/8 selected as reference" />
-        <Enum name="ARef" start="7" description="External analog reference selected" />
-        <Enum name="Ref1_16Vdd" start="8" description="VDD * 1/16 selected as reference" />
-        <Enum name="Ref3_16Vdd" start="9" description="VDD * 3/16 selected as reference" />
-        <Enum name="Ref5_16Vdd" start="10" description="VDD * 5/16 selected as reference" />
-        <Enum name="Ref7_16Vdd" start="11" description="VDD * 7/16 selected as reference" />
-        <Enum name="Ref9_16Vdd" start="12" description="VDD * 9/16 selected as reference" />
-        <Enum name="Ref11_16Vdd" start="13" description="VDD * 11/16 selected as reference" />
-        <Enum name="Ref13_16Vdd" start="14" description="VDD * 13/16 selected as reference" />
-        <Enum name="Ref15_16Vdd" start="15" description="VDD * 15/16 selected as reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="EXTREFSEL" access="Read/Write" description="External reference select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTREFSEL" description="External analog reference select">
-        <Enum name="AnalogReference0" start="0" description="Use AIN0 as external analog reference" />
-        <Enum name="AnalogReference1" start="1" description="Use AIN1 as external analog reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="ANADETECT" access="Read/Write" description="Analog detect configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ANADETECT" description="Analog detect configuration">
-        <Enum name="Cross" start="0" description="Generate ANADETECT on crossing, both upward crossing and downward crossing" />
-        <Enum name="Up" start="1" description="Generate ANADETECT on upward crossing only" />
-        <Enum name="Down" start="2" description="Generate ANADETECT on downward crossing only" />
-      </BitField>
-    </Register>
-    <Register start="+0x538" size="4" name="HYST" access="Read/Write" description="Comparator hysteresis enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HYST" description="Comparator hysteresis enable">
-        <Enum name="NoHyst" start="0" description="Comparator hysteresis disabled" />
-        <Enum name="Hyst50mV" start="1" description="Comparator hysteresis disabled (typ. 50 mV)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI0" start="0x40014000" description="Software interrupt 0">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU0" start="0x40014000" description="Event Generator Unit 0">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI1" start="0x40015000" description="Software interrupt 1">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU1" start="0x40015000" description="Event Generator Unit 1">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI2" start="0x40016000" description="Software interrupt 2">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU2" start="0x40016000" description="Event Generator Unit 2">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI3" start="0x40017000" description="Software interrupt 3">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU3" start="0x40017000" description="Event Generator Unit 3">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI4" start="0x40018000" description="Software interrupt 4">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU4" start="0x40018000" description="Event Generator Unit 4">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI5" start="0x40019000" description="Software interrupt 5">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU5" start="0x40019000" description="Event Generator Unit 5">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x4001A000" description="Timer/Counter 3">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER4" start="0x4001B000" description="Timer/Counter 4">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM0" start="0x4001C000" description="Pulse Width Modulation Unit 0">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PDM" start="0x4001D000" description="Pulse Density Modulation (Digital Microphone) Interface">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Starts continuous PDM transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PDM transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_STARTED" access="Read/Write" description="PDM transfer has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="PDM transfer has finished" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_END" access="Read/Write" description="The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="END" description="Enable or disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PDM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PDM module">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PDMCLKCTRL" access="Read/Write" description="PDM clock generator control" reset_value="0x08400000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQ" description="PDM_CLK frequency">
-        <Enum name="1000K" start="0x08000000" description="PDM_CLK = 32 MHz / 32 = 1.000 MHz" />
-        <Enum name="Default" start="0x08400000" description="PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64." />
-        <Enum name="1067K" start="0x08800000" description="PDM_CLK = 32 MHz / 30 = 1.067 MHz" />
-        <Enum name="1231K" start="0x09800000" description="PDM_CLK = 32 MHz / 26 = 1.231 MHz" />
-        <Enum name="1280K" start="0x0A000000" description="PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80." />
-        <Enum name="1333K" start="0x0A800000" description="PDM_CLK = 32 MHz / 24 = 1.333 MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="MODE" access="Read/Write" description="Defines the routing of the connected PDM microphones' signals" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OPERATION" description="Mono or stereo operation">
-        <Enum name="Stereo" start="0" description="Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]" />
-        <Enum name="Mono" start="1" description="Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]" />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Defines on which PDM_CLK edge Left (or mono) is sampled">
-        <Enum name="LeftFalling" start="0" description="Left (or mono) is sampled on falling edge of PDM_CLK" />
-        <Enum name="LeftRising" start="1" description="Left (or mono) is sampled on rising edge of PDM_CLK" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="GAINL" access="Read/Write" description="Left output gain adjustment" reset_value="0x00000028" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="GAINL" description="Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust">
-        <Enum name="MinGain" start="0x00" description="-20dB gain adjustment (minimum)" />
-        <Enum name="DefaultGain" start="0x28" description="0dB gain adjustment ('2500 RMS' requirement)" />
-        <Enum name="MaxGain" start="0x50" description="+20dB gain adjustment (maximum)" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="GAINR" access="Read/Write" description="Right output gain adjustment" reset_value="0x00000028" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="GAINR" description="Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)">
-        <Enum name="MinGain" start="0x00" description="-20dB gain adjustment (minimum)" />
-        <Enum name="DefaultGain" start="0x28" description="0dB gain adjustment ('2500 RMS' requirement)" />
-        <Enum name="MaxGain" start="0x50" description="+20dB gain adjustment (maximum)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="RATIO" access="Read/Write" description="Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RATIO" description="Selects the ratio between PDM_CLK and output sample rate">
-        <Enum name="Ratio64" start="0" description="Ratio of 64" />
-        <Enum name="Ratio80" start="1" description="Ratio of 80" />
-      </BitField>
-    </Register>
-    <Register start="+0x540+0x000" size="4" name="PSEL.CLK" access="Read/Write" description="Pin number configuration for PDM CLK signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x540+0x004" size="4" name="PSEL.DIN" access="Read/Write" description="Pin number configuration for PDM DIN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="SAMPLE.PTR" access="Read/Write" description="RAM address pointer to write samples to with EasyDMA" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLEPTR" description="Address to write PDM samples to over DMA" />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="SAMPLE.MAXCNT" access="Read/Write" description="Number of samples to allocate memory for in EasyDMA mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="BUFFSIZE" description="Length of DMA RAM allocation in number of samples" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVMC" start="0x4001E000" description="Non Volatile Memory Controller">
-    <Register start="+0x400" size="4" name="READY" access="ReadOnly" description="Ready flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVMC is ready or busy">
-        <Enum name="Busy" start="0" description="NVMC is busy (on-going write or erase operation)" />
-        <Enum name="Ready" start="1" description="NVMC is ready" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WEN" description="Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.">
-        <Enum name="Ren" start="0" description="Read only access" />
-        <Enum name="Wen" start="1" description="Write enabled" />
-        <Enum name="Een" start="2" description="Erase enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="ERASEPAGE" access="Read/Write" description="Register for erasing a page in code area" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ERASEPAGE" description="Register for starting erase of a page in code area" />
-    </Register>
-    <Register start="+0x508" size="4" name="ERASEPCR1" access="Read/Write" description="Deprecated register -  Register for erasing a page in code area. Equivalent to ERASEPAGE." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ERASEPCR1" description="Register for erasing a page in code area. Equivalent to ERASEPAGE." />
-    </Register>
-    <Register start="+0x50C" size="4" name="ERASEALL" access="Read/Write" description="Register for erasing all non-volatile user memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERASEALL" description="Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.">
-        <Enum name="NoOperation" start="0" description="No operation" />
-        <Enum name="Erase" start="1" description="Start chip erase" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="ERASEPCR0" access="Read/Write" description="Deprecated register -  Register for erasing a page in code area. Equivalent to ERASEPAGE." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ERASEPCR0" description="Register for starting erase of a page in code area. Equivalent to ERASEPAGE." />
-    </Register>
-    <Register start="+0x514" size="4" name="ERASEUICR" access="Read/Write" description="Register for erasing user information configuration registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERASEUICR" description="Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.">
-        <Enum name="NoOperation" start="0" description="No operation" />
-        <Enum name="Erase" start="1" description="Start erase of UICR" />
-      </BitField>
-    </Register>
-    <Register start="+0x540" size="4" name="ICACHECNF" access="Read/Write" description="I-code cache configuration register." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CACHEEN" description="Cache enable">
-        <Enum name="Disabled" start="0" description="Disable cache. Invalidates all cache entries." />
-        <Enum name="Enabled" start="1" description="Enable cache" />
-      </BitField>
-      <BitField start="8" size="1" name="CACHEPROFEN" description="Cache profiling enable">
-        <Enum name="Disabled" start="0" description="Disable cache profiling" />
-        <Enum name="Enabled" start="1" description="Enable cache profiling" />
-      </BitField>
-    </Register>
-    <Register start="+0x548" size="4" name="IHIT" access="Read/Write" description="I-code cache hit counter." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HITS" description="Number of cache hits" />
-    </Register>
-    <Register start="+0x54C" size="4" name="IMISS" access="Read/Write" description="I-code cache miss counter." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MISSES" description="Number of cache misses" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ACL (ACL[%s])" start="0x4001E000" description="Access control lists">
-    <Register start="+0x000" size="4" name="ADDR" access="Read/Write" description="Description cluster[0]:  Configure the word-aligned start address of region 0 to protect" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary." />
-    </Register>
-    <Register start="+0x004" size="4" name="SIZE" access="Read/Write" description="Description cluster[0]:  Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SIZE" description="Size of flash region 0 in bytes. Must be a multiple of the flash page size." />
-    </Register>
-    <Register start="+0x008" size="4" name="PERM" access="Read/Write" description="Description cluster[0]:  Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="WRITE" description="Configure write and erase permissions for region 0. Write '0' has no effect.">
-        <Enum name="Enable" start="0" description="Allow write and erase instructions to region 0" />
-        <Enum name="Disable" start="1" description="Block write and erase instructions to region 0" />
-      </BitField>
-      <BitField start="2" size="1" name="READ" description="Configure read permissions for region 0. Write '0' has no effect.">
-        <Enum name="Enable" start="0" description="Allow read instructions to region 0" />
-        <Enum name="Disable" start="1" description="Block read instructions to region 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="4" name="UNUSED0" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="PPI" start="0x4001F000" description="Programmable Peripheral Interconnect">
-    <Register start="+0x500" size="4" name="CHEN" access="Read/Write" description="Channel enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Enable or disable channel 0">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Enable or disable channel 1">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Enable or disable channel 2">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Enable or disable channel 3">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Enable or disable channel 4">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Enable or disable channel 5">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Enable or disable channel 6">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Enable or disable channel 7">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Enable or disable channel 8">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Enable or disable channel 9">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Enable or disable channel 10">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Enable or disable channel 11">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Enable or disable channel 12">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Enable or disable channel 13">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Enable or disable channel 14">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Enable or disable channel 15">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Enable or disable channel 16">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Enable or disable channel 17">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Enable or disable channel 18">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Enable or disable channel 19">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Enable or disable channel 20">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Enable or disable channel 21">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Enable or disable channel 22">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Enable or disable channel 23">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Enable or disable channel 24">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Enable or disable channel 25">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Enable or disable channel 26">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Enable or disable channel 27">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Enable or disable channel 28">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Enable or disable channel 29">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Enable or disable channel 30">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Enable or disable channel 31">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CHENSET" access="Read/Write" description="Channel enable set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Channel 0 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Channel 1 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Channel 2 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Channel 3 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Channel 4 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Channel 5 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Channel 6 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Channel 7 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Channel 8 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Channel 9 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Channel 10 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Channel 11 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Channel 12 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Channel 13 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Channel 14 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Channel 15 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Channel 16 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Channel 17 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Channel 18 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Channel 19 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Channel 20 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Channel 21 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Channel 22 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Channel 23 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Channel 24 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Channel 25 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Channel 26 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Channel 27 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Channel 28 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Channel 29 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Channel 30 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Channel 31 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="CHENCLR" access="Read/Write" description="Channel enable clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Channel 0 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Channel 1 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Channel 2 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Channel 3 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Channel 4 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Channel 5 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Channel 6 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Channel 7 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Channel 8 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Channel 9 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Channel 10 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Channel 11 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Channel 12 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Channel 13 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Channel 14 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Channel 15 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Channel 16 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Channel 17 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Channel 18 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Channel 19 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Channel 20 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Channel 21 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Channel 22 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Channel 23 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Channel 24 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Channel 25 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Channel 26 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Channel 27 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Channel 28 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Channel 29 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Channel 30 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Channel 31 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+0" size="4" name="CHG[0]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+4" size="4" name="CHG[1]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+8" size="4" name="CHG[2]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+12" size="4" name="CHG[3]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+16" size="4" name="CHG[4]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+20" size="4" name="CHG[5]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x000+0*8+0x000" size="4" name="TASKS_CHG[0].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+0*8+0x004" size="4" name="TASKS_CHG[0].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+1*8+0x000" size="4" name="TASKS_CHG[1].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+1*8+0x004" size="4" name="TASKS_CHG[1].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+2*8+0x000" size="4" name="TASKS_CHG[2].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+2*8+0x004" size="4" name="TASKS_CHG[2].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+3*8+0x000" size="4" name="TASKS_CHG[3].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+3*8+0x004" size="4" name="TASKS_CHG[3].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4*8+0x000" size="4" name="TASKS_CHG[4].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4*8+0x004" size="4" name="TASKS_CHG[4].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+5*8+0x000" size="4" name="TASKS_CHG[5].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+5*8+0x004" size="4" name="TASKS_CHG[5].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x510+0*8+0x000" size="4" name="CH[0].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+0*8+0x004" size="4" name="CH[0].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+1*8+0x000" size="4" name="CH[1].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+1*8+0x004" size="4" name="CH[1].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+2*8+0x000" size="4" name="CH[2].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+2*8+0x004" size="4" name="CH[2].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+3*8+0x000" size="4" name="CH[3].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+3*8+0x004" size="4" name="CH[3].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+4*8+0x000" size="4" name="CH[4].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+4*8+0x004" size="4" name="CH[4].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+5*8+0x000" size="4" name="CH[5].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+5*8+0x004" size="4" name="CH[5].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+6*8+0x000" size="4" name="CH[6].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+6*8+0x004" size="4" name="CH[6].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+7*8+0x000" size="4" name="CH[7].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+7*8+0x004" size="4" name="CH[7].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+8*8+0x000" size="4" name="CH[8].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+8*8+0x004" size="4" name="CH[8].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+9*8+0x000" size="4" name="CH[9].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+9*8+0x004" size="4" name="CH[9].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+10*8+0x000" size="4" name="CH[10].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+10*8+0x004" size="4" name="CH[10].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+11*8+0x000" size="4" name="CH[11].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+11*8+0x004" size="4" name="CH[11].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+12*8+0x000" size="4" name="CH[12].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+12*8+0x004" size="4" name="CH[12].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+13*8+0x000" size="4" name="CH[13].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+13*8+0x004" size="4" name="CH[13].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+14*8+0x000" size="4" name="CH[14].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+14*8+0x004" size="4" name="CH[14].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+15*8+0x000" size="4" name="CH[15].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+15*8+0x004" size="4" name="CH[15].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+16*8+0x000" size="4" name="CH[16].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+16*8+0x004" size="4" name="CH[16].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+17*8+0x000" size="4" name="CH[17].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+17*8+0x004" size="4" name="CH[17].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+18*8+0x000" size="4" name="CH[18].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+18*8+0x004" size="4" name="CH[18].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+19*8+0x000" size="4" name="CH[19].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+19*8+0x004" size="4" name="CH[19].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x910+0*4+0x000" size="4" name="FORK[0].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+1*4+0x000" size="4" name="FORK[1].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+2*4+0x000" size="4" name="FORK[2].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+3*4+0x000" size="4" name="FORK[3].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+4*4+0x000" size="4" name="FORK[4].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+5*4+0x000" size="4" name="FORK[5].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+6*4+0x000" size="4" name="FORK[6].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+7*4+0x000" size="4" name="FORK[7].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+8*4+0x000" size="4" name="FORK[8].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+9*4+0x000" size="4" name="FORK[9].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+10*4+0x000" size="4" name="FORK[10].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+11*4+0x000" size="4" name="FORK[11].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+12*4+0x000" size="4" name="FORK[12].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+13*4+0x000" size="4" name="FORK[13].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+14*4+0x000" size="4" name="FORK[14].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+15*4+0x000" size="4" name="FORK[15].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+16*4+0x000" size="4" name="FORK[16].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+17*4+0x000" size="4" name="FORK[17].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+18*4+0x000" size="4" name="FORK[18].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+19*4+0x000" size="4" name="FORK[19].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+20*4+0x000" size="4" name="FORK[20].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+21*4+0x000" size="4" name="FORK[21].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+22*4+0x000" size="4" name="FORK[22].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+23*4+0x000" size="4" name="FORK[23].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+24*4+0x000" size="4" name="FORK[24].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+25*4+0x000" size="4" name="FORK[25].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+26*4+0x000" size="4" name="FORK[26].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+27*4+0x000" size="4" name="FORK[27].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+28*4+0x000" size="4" name="FORK[28].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+29*4+0x000" size="4" name="FORK[29].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+30*4+0x000" size="4" name="FORK[30].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+31*4+0x000" size="4" name="FORK[31].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MWU" start="0x40020000" description="Memory Watch Unit">
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Enable or disable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Enable or disable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Enable or disable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Enable or disable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Enable or disable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Enable or disable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Enable or disable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Enable or disable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Enable or disable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Enable or disable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Enable or disable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Enable or disable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Enable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Enable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Enable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Enable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Enable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Enable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Enable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Enable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Enable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Enable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Enable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Enable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Disable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Disable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Disable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Disable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Disable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Disable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Disable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Disable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Disable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Disable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Disable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Disable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x320" size="4" name="NMIEN" access="Read/Write" description="Enable or disable non-maskable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Enable or disable non-maskable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Enable or disable non-maskable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Enable or disable non-maskable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Enable or disable non-maskable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Enable or disable non-maskable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Enable or disable non-maskable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Enable or disable non-maskable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Enable or disable non-maskable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Enable or disable non-maskable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Enable or disable non-maskable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Enable or disable non-maskable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Enable or disable non-maskable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x324" size="4" name="NMIENSET" access="Read/Write" description="Enable non-maskable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Enable non-maskable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Enable non-maskable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Enable non-maskable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Enable non-maskable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Enable non-maskable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Enable non-maskable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Enable non-maskable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Enable non-maskable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Enable non-maskable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Enable non-maskable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Enable non-maskable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Enable non-maskable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x328" size="4" name="NMIENCLR" access="Read/Write" description="Disable non-maskable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Disable non-maskable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Disable non-maskable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Disable non-maskable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Disable non-maskable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Disable non-maskable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Disable non-maskable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Disable non-maskable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Disable non-maskable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Disable non-maskable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Disable non-maskable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Disable non-maskable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Disable non-maskable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="REGIONEN" access="Read/Write" description="Enable/disable regions watch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RGN0WA" description="Enable/disable write access watch in region[0]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="1" size="1" name="RGN0RA" description="Enable/disable read access watch in region[0]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="2" size="1" name="RGN1WA" description="Enable/disable write access watch in region[1]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="3" size="1" name="RGN1RA" description="Enable/disable read access watch in region[1]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="4" size="1" name="RGN2WA" description="Enable/disable write access watch in region[2]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="5" size="1" name="RGN2RA" description="Enable/disable read access watch in region[2]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="6" size="1" name="RGN3WA" description="Enable/disable write access watch in region[3]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="7" size="1" name="RGN3RA" description="Enable/disable read access watch in region[3]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="24" size="1" name="PRGN0WA" description="Enable/disable write access watch in PREGION[0]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this PREGION" />
-      </BitField>
-      <BitField start="25" size="1" name="PRGN0RA" description="Enable/disable read access watch in PREGION[0]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this PREGION" />
-      </BitField>
-      <BitField start="26" size="1" name="PRGN1WA" description="Enable/disable write access watch in PREGION[1]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this PREGION" />
-      </BitField>
-      <BitField start="27" size="1" name="PRGN1RA" description="Enable/disable read access watch in PREGION[1]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this PREGION" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="REGIONENSET" access="Read/Write" description="Enable regions watch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RGN0WA" description="Enable write access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RGN0RA" description="Enable read access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RGN1WA" description="Enable write access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RGN1RA" description="Enable read access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="RGN2WA" description="Enable write access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RGN2RA" description="Enable read access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RGN3WA" description="Enable write access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RGN3RA" description="Enable read access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PRGN0WA" description="Enable write access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PRGN0RA" description="Enable read access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PRGN1WA" description="Enable write access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PRGN1RA" description="Enable read access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="REGIONENCLR" access="Read/Write" description="Disable regions watch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RGN0WA" description="Disable write access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RGN0RA" description="Disable read access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RGN1WA" description="Disable write access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RGN1RA" description="Disable read access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="RGN2WA" description="Disable write access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RGN2RA" description="Disable read access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RGN3WA" description="Disable write access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RGN3RA" description="Disable read access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PRGN0WA" description="Disable write access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PRGN0RA" description="Disable read access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PRGN1WA" description="Disable write access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PRGN1RA" description="Disable read access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0*8+0x000" size="4" name="EVENTS_REGION[0].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0*8+0x004" size="4" name="EVENTS_REGION[0].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+1*8+0x000" size="4" name="EVENTS_REGION[1].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+1*8+0x004" size="4" name="EVENTS_REGION[1].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+2*8+0x000" size="4" name="EVENTS_REGION[2].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+2*8+0x004" size="4" name="EVENTS_REGION[2].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+3*8+0x000" size="4" name="EVENTS_REGION[3].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+3*8+0x004" size="4" name="EVENTS_REGION[3].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+0*8+0x000" size="4" name="EVENTS_PREGION[0].WA" access="Read/Write" description="Description cluster[0]:  Write access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+0*8+0x004" size="4" name="EVENTS_PREGION[0].RA" access="Read/Write" description="Description cluster[0]:  Read access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+1*8+0x000" size="4" name="EVENTS_PREGION[1].WA" access="Read/Write" description="Description cluster[0]:  Write access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+1*8+0x004" size="4" name="EVENTS_PREGION[1].RA" access="Read/Write" description="Description cluster[0]:  Read access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x400+0*8+0x000" size="4" name="PERREGION[0].SUBSTATWA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x400+0*8+0x004" size="4" name="PERREGION[0].SUBSTATRA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x400+1*8+0x000" size="4" name="PERREGION[1].SUBSTATWA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x400+1*8+0x004" size="4" name="PERREGION[1].SUBSTATRA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+0*16+0x000" size="4" name="REGION[0].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+0*16+0x004" size="4" name="REGION[0].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x600+1*16+0x000" size="4" name="REGION[1].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+1*16+0x004" size="4" name="REGION[1].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x600+2*16+0x000" size="4" name="REGION[2].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+2*16+0x004" size="4" name="REGION[2].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x600+3*16+0x000" size="4" name="REGION[3].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+3*16+0x004" size="4" name="REGION[3].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x6C0+0*16+0x000" size="4" name="PREGION[0].START" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+0*16+0x004" size="4" name="PREGION[0].END" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+0*16+0x008" size="4" name="PREGION[0].SUBS" access="Read/Write" description="Description cluster[0]:  Subregions of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Include or exclude subregion 0 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Include or exclude subregion 1 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Include or exclude subregion 2 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Include or exclude subregion 3 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Include or exclude subregion 4 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Include or exclude subregion 5 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Include or exclude subregion 6 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Include or exclude subregion 7 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Include or exclude subregion 8 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Include or exclude subregion 9 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Include or exclude subregion 10 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Include or exclude subregion 11 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Include or exclude subregion 12 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Include or exclude subregion 13 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Include or exclude subregion 14 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Include or exclude subregion 15 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Include or exclude subregion 16 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Include or exclude subregion 17 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Include or exclude subregion 18 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Include or exclude subregion 19 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Include or exclude subregion 20 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Include or exclude subregion 21 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Include or exclude subregion 22 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Include or exclude subregion 23 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Include or exclude subregion 24 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Include or exclude subregion 25 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Include or exclude subregion 26 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Include or exclude subregion 27 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Include or exclude subregion 28 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Include or exclude subregion 29 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Include or exclude subregion 30 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Include or exclude subregion 31 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x6C0+1*16+0x000" size="4" name="PREGION[1].START" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+1*16+0x004" size="4" name="PREGION[1].END" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+1*16+0x008" size="4" name="PREGION[1].SUBS" access="Read/Write" description="Description cluster[0]:  Subregions of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Include or exclude subregion 0 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Include or exclude subregion 1 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Include or exclude subregion 2 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Include or exclude subregion 3 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Include or exclude subregion 4 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Include or exclude subregion 5 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Include or exclude subregion 6 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Include or exclude subregion 7 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Include or exclude subregion 8 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Include or exclude subregion 9 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Include or exclude subregion 10 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Include or exclude subregion 11 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Include or exclude subregion 12 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Include or exclude subregion 13 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Include or exclude subregion 14 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Include or exclude subregion 15 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Include or exclude subregion 16 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Include or exclude subregion 17 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Include or exclude subregion 18 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Include or exclude subregion 19 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Include or exclude subregion 20 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Include or exclude subregion 21 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Include or exclude subregion 22 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Include or exclude subregion 23 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Include or exclude subregion 24 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Include or exclude subregion 25 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Include or exclude subregion 26 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Include or exclude subregion 27 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Include or exclude subregion 28 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Include or exclude subregion 29 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Include or exclude subregion 30 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Include or exclude subregion 31 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40021000" description="Pulse Width Modulation Unit 1">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM2" start="0x40022000" description="Pulse Width Modulation Unit 2">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM2" start="0x40023000" description="Serial Peripheral Interface Master with EasyDMA 2">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIS2" start="0x40023000" description="SPI Slave 2">
-    <Register start="+0x024" size="4" name="TASKS_ACQUIRE" access="WriteOnly" description="Acquire SPI semaphore" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_RELEASE" access="WriteOnly" description="Release SPI semaphore, enabling the SPI slave to acquire it" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="Granted transaction completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_ACQUIRED" access="Read/Write" description="Semaphore acquired" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="END_ACQUIRE" description="Shortcut between END event and ACQUIRE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Enable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Disable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="SEMSTAT" access="ReadOnly" description="Semaphore status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEMSTAT" description="Semaphore status">
-        <Enum name="Free" start="0" description="Semaphore is free" />
-        <Enum name="CPU" start="1" description="Semaphore is assigned to CPU" />
-        <Enum name="SPIS" start="2" description="Semaphore is assigned to SPI slave" />
-        <Enum name="CPUPending" start="3" description="Semaphore is assigned to SPI but a handover to the CPU is pending" />
-      </BitField>
-    </Register>
-    <Register start="+0x440" size="4" name="STATUS" access="Read/Write" description="Status from last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI slave">
-        <Enum name="Disabled" start="0" description="Disable SPI slave" />
-        <Enum name="Enabled" start="2" description="Enable SPI slave" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x55C" size="4" name="DEF" access="Read/Write" description="Default character. Character clocked out in case of an ignored transaction." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEF" description="Default character. Character clocked out in case of an ignored transaction." />
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character clocked out after an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes received in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes received in the last granted transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transmitted in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transmitted in last granted transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI2" start="0x40023000" description="Serial Peripheral Interface 2">
-    <Register start="+0x108" size="4" name="EVENTS_READY" access="Read/Write" description="TXD byte sent and RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI">
-        <Enum name="Disabled" start="0" description="Disable SPI" />
-        <Enum name="Enabled" start="1" description="Enable SPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received. Double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to send. Double buffered" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC2" start="0x40024000" description="Real time counter 2">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_TRIGOVRFLW" access="WriteOnly" description="Set COUNTER to 0xFFFFF0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TICK" access="Read/Write" description="Event on COUNTER increment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_OVRFLW" access="Read/Write" description="Event on COUNTER overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x340" size="4" name="EVTEN" access="Read/Write" description="Enable or disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Enable or disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Enable or disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Enable or disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Enable or disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Enable or disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Enable or disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x344" size="4" name="EVTENSET" access="Read/Write" description="Enable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x348" size="4" name="EVTENCLR" access="Read/Write" description="Disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="COUNTER" access="ReadOnly" description="Current COUNTER value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNTER" description="Counter value" />
-    </Register>
-    <Register start="+0x508" size="4" name="PRESCALER" access="Read/Write" description="12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x40025000" description="Inter-IC Sound">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Starts continuous I2S transfer. Also starts MCK generator when this is enabled." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_RXPTRUPD" access="Read/Write" description="The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_STOPPED" access="Read/Write" description="I2S transfer stopped." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_TXPTRUPD" access="Read/Write" description="The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RXPTRUPD" description="Enable or disable interrupt for RXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TXPTRUPD" description="Enable or disable interrupt for TXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RXPTRUPD" description="Write '1' to Enable interrupt for RXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TXPTRUPD" description="Write '1' to Enable interrupt for TXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RXPTRUPD" description="Write '1' to Disable interrupt for RXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TXPTRUPD" description="Write '1' to Disable interrupt for TXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable I2S module." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable I2S module.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x000" size="4" name="CONFIG.MODE" access="Read/Write" description="I2S mode." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="I2S mode.">
-        <Enum name="Master" start="0" description="Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx." />
-        <Enum name="Slave" start="1" description="Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x004" size="4" name="CONFIG.RXEN" access="Read/Write" description="Reception (RX) enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXEN" description="Reception (RX) enable.">
-        <Enum name="Disabled" start="0" description="Reception disabled and now data will be written to the RXD.PTR address." />
-        <Enum name="Enabled" start="1" description="Reception enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x008" size="4" name="CONFIG.TXEN" access="Read/Write" description="Transmission (TX) enable." reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmission (TX) enable.">
-        <Enum name="Disabled" start="0" description="Transmission disabled and now data will be read from the RXD.TXD address." />
-        <Enum name="Enabled" start="1" description="Transmission enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x00C" size="4" name="CONFIG.MCKEN" access="Read/Write" description="Master clock generator enable." reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCKEN" description="Master clock generator enable.">
-        <Enum name="Disabled" start="0" description="Master clock generator disabled and PSEL.MCK not connected(available as GPIO)." />
-        <Enum name="Enabled" start="1" description="Master clock generator running and MCK output on PSEL.MCK." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x010" size="4" name="CONFIG.MCKFREQ" access="Read/Write" description="Master clock generator frequency." reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCKFREQ" description="Master clock generator frequency.">
-        <Enum name="32MDIV2" start="0x80000000" description="32 MHz / 2 = 16.0 MHz" />
-        <Enum name="32MDIV3" start="0x50000000" description="32 MHz / 3 = 10.6666667 MHz" />
-        <Enum name="32MDIV4" start="0x40000000" description="32 MHz / 4 = 8.0 MHz" />
-        <Enum name="32MDIV5" start="0x30000000" description="32 MHz / 5 = 6.4 MHz" />
-        <Enum name="32MDIV6" start="0x28000000" description="32 MHz / 6 = 5.3333333 MHz" />
-        <Enum name="32MDIV8" start="0x20000000" description="32 MHz / 8 = 4.0 MHz" />
-        <Enum name="32MDIV10" start="0x18000000" description="32 MHz / 10 = 3.2 MHz" />
-        <Enum name="32MDIV11" start="0x16000000" description="32 MHz / 11 = 2.9090909 MHz" />
-        <Enum name="32MDIV15" start="0x11000000" description="32 MHz / 15 = 2.1333333 MHz" />
-        <Enum name="32MDIV16" start="0x10000000" description="32 MHz / 16 = 2.0 MHz" />
-        <Enum name="32MDIV21" start="0x0C000000" description="32 MHz / 21 = 1.5238095" />
-        <Enum name="32MDIV23" start="0x0B000000" description="32 MHz / 23 = 1.3913043 MHz" />
-        <Enum name="32MDIV30" start="0x08800000" description="32 MHz / 30 = 1.0666667 MHz" />
-        <Enum name="32MDIV31" start="0x08400000" description="32 MHz / 31 = 1.0322581 MHz" />
-        <Enum name="32MDIV32" start="0x08000000" description="32 MHz / 32 = 1.0 MHz" />
-        <Enum name="32MDIV42" start="0x06000000" description="32 MHz / 42 = 0.7619048 MHz" />
-        <Enum name="32MDIV63" start="0x04100000" description="32 MHz / 63 = 0.5079365 MHz" />
-        <Enum name="32MDIV125" start="0x020C0000" description="32 MHz / 125 = 0.256 MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x014" size="4" name="CONFIG.RATIO" access="Read/Write" description="MCK / LRCK ratio." reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RATIO" description="MCK / LRCK ratio.">
-        <Enum name="32X" start="0" description="LRCK = MCK / 32" />
-        <Enum name="48X" start="1" description="LRCK = MCK / 48" />
-        <Enum name="64X" start="2" description="LRCK = MCK / 64" />
-        <Enum name="96X" start="3" description="LRCK = MCK / 96" />
-        <Enum name="128X" start="4" description="LRCK = MCK / 128" />
-        <Enum name="192X" start="5" description="LRCK = MCK / 192" />
-        <Enum name="256X" start="6" description="LRCK = MCK / 256" />
-        <Enum name="384X" start="7" description="LRCK = MCK / 384" />
-        <Enum name="512X" start="8" description="LRCK = MCK / 512" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x018" size="4" name="CONFIG.SWIDTH" access="Read/Write" description="Sample width." reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SWIDTH" description="Sample width.">
-        <Enum name="8Bit" start="0" description="8 bit." />
-        <Enum name="16Bit" start="1" description="16 bit." />
-        <Enum name="24Bit" start="2" description="24 bit." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x01C" size="4" name="CONFIG.ALIGN" access="Read/Write" description="Alignment of sample within a frame." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALIGN" description="Alignment of sample within a frame.">
-        <Enum name="Left" start="0" description="Left-aligned." />
-        <Enum name="Right" start="1" description="Right-aligned." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x020" size="4" name="CONFIG.FORMAT" access="Read/Write" description="Frame format." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FORMAT" description="Frame format.">
-        <Enum name="I2S" start="0" description="Original I2S format." />
-        <Enum name="Aligned" start="1" description="Alternate (left- or right-aligned) format." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x024" size="4" name="CONFIG.CHANNELS" access="Read/Write" description="Enable channels." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CHANNELS" description="Enable channels.">
-        <Enum name="Stereo" start="0" description="Stereo." />
-        <Enum name="Left" start="1" description="Left only." />
-        <Enum name="Right" start="2" description="Right only." />
-      </BitField>
-    </Register>
-    <Register start="+0x538+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Receive buffer RAM start address." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address." />
-    </Register>
-    <Register start="+0x540+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Transmit buffer RAM start address." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address." />
-    </Register>
-    <Register start="+0x550+0x000" size="4" name="RXTXD.MAXCNT" access="Read/Write" description="Size of RXD and TXD buffers." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="MAXCNT" description="Size of RXD and TXD buffers in number of 32 bit words." />
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="PSEL.MCK" access="Read/Write" description="Pin select for MCK signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x008" size="4" name="PSEL.LRCK" access="Read/Write" description="Pin select for LRCK signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x00C" size="4" name="PSEL.SDIN" access="Read/Write" description="Pin select for SDIN signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x010" size="4" name="PSEL.SDOUT" access="Read/Write" description="Pin select for SDOUT signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FPU" start="0x40026000" description="FPU">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="USBD" start="0x40027000" description="Universal Serial Bus device">
-    <Register start="+0x004+0" size="4" name="TASKS_STARTEPIN[0]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+4" size="4" name="TASKS_STARTEPIN[1]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+8" size="4" name="TASKS_STARTEPIN[2]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+12" size="4" name="TASKS_STARTEPIN[3]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+16" size="4" name="TASKS_STARTEPIN[4]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+20" size="4" name="TASKS_STARTEPIN[5]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+24" size="4" name="TASKS_STARTEPIN[6]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+28" size="4" name="TASKS_STARTEPIN[7]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x024" size="4" name="TASKS_STARTISOIN" access="WriteOnly" description="Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers values, and enables sending data on iso endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+0" size="4" name="TASKS_STARTEPOUT[0]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+4" size="4" name="TASKS_STARTEPOUT[1]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+8" size="4" name="TASKS_STARTEPOUT[2]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+12" size="4" name="TASKS_STARTEPOUT[3]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+16" size="4" name="TASKS_STARTEPOUT[4]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+20" size="4" name="TASKS_STARTEPOUT[5]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+24" size="4" name="TASKS_STARTEPOUT[6]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+28" size="4" name="TASKS_STARTEPOUT[7]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x048" size="4" name="TASKS_STARTISOOUT" access="WriteOnly" description="Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers values, and enables receiving of data on iso endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x04C" size="4" name="TASKS_EP0RCVOUT" access="WriteOnly" description="Allows OUT data stage on control endpoint 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x050" size="4" name="TASKS_EP0STATUS" access="WriteOnly" description="Allows status stage on control endpoint 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x054" size="4" name="TASKS_EP0STALL" access="WriteOnly" description="STALLs data and status stage on control endpoint 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x058" size="4" name="TASKS_DPDMDRIVE" access="WriteOnly" description="Forces D+ and D-lines to the state defined in the DPDMVALUE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x05C" size="4" name="TASKS_DPDMNODRIVE" access="WriteOnly" description="Stops forcing D+ and D- lines to any state (USB engine takes control)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_USBRESET" access="Read/Write" description="Signals that a USB reset condition has been detected on the USB lines" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STARTED" access="Read/Write" description="Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_ENDEPIN[0]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_ENDEPIN[1]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+8" size="4" name="EVENTS_ENDEPIN[2]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+12" size="4" name="EVENTS_ENDEPIN[3]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+16" size="4" name="EVENTS_ENDEPIN[4]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+20" size="4" name="EVENTS_ENDEPIN[5]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+24" size="4" name="EVENTS_ENDEPIN[6]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+28" size="4" name="EVENTS_ENDEPIN[7]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_EP0DATADONE" access="Read/Write" description="An acknowledged data transfer has taken place on the control endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x12C" size="4" name="EVENTS_ENDISOIN" access="Read/Write" description="The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+0" size="4" name="EVENTS_ENDEPOUT[0]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+4" size="4" name="EVENTS_ENDEPOUT[1]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+8" size="4" name="EVENTS_ENDEPOUT[2]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+12" size="4" name="EVENTS_ENDEPOUT[3]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+16" size="4" name="EVENTS_ENDEPOUT[4]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+20" size="4" name="EVENTS_ENDEPOUT[5]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+24" size="4" name="EVENTS_ENDEPOUT[6]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+28" size="4" name="EVENTS_ENDEPOUT[7]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_ENDISOOUT" access="Read/Write" description="The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x154" size="4" name="EVENTS_SOF" access="Read/Write" description="Signals that a SOF (start of frame) condition has been detected on the USB lines" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_USBEVENT" access="Read/Write" description="An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_EP0SETUP" access="Read/Write" description="A valid SETUP token has been received (and acknowledged) on the control endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160" size="4" name="EVENTS_EPDATA" access="Read/Write" description="A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x164" size="4" name="EVENTS_ACCESSFAULT" access="Read/Write" description="Access to an unavailable USB register has been attempted (software or EasyDMA). This event can  get fired even when USBD is not ENABLEd." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP0DATADONE_STARTEPIN0" description="Shortcut between EP0DATADONE event and STARTEPIN[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="EP0DATADONE_STARTEPOUT0" description="Shortcut between EP0DATADONE event and STARTEPOUT[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="EP0DATADONE_EP0STATUS" description="Shortcut between EP0DATADONE event and EP0STATUS task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPOUT0_EP0STATUS" description="Shortcut between ENDEPOUT[0] event and EP0STATUS task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPOUT0_EP0RCVOUT" description="Shortcut between ENDEPOUT[0] event and EP0RCVOUT task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USBRESET" description="Enable or disable interrupt for USBRESET event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="ENDEPIN0" description="Enable or disable interrupt for ENDEPIN[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPIN1" description="Enable or disable interrupt for ENDEPIN[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPIN2" description="Enable or disable interrupt for ENDEPIN[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="ENDEPIN3" description="Enable or disable interrupt for ENDEPIN[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDEPIN4" description="Enable or disable interrupt for ENDEPIN[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="ENDEPIN5" description="Enable or disable interrupt for ENDEPIN[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDEPIN6" description="Enable or disable interrupt for ENDEPIN[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ENDEPIN7" description="Enable or disable interrupt for ENDEPIN[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="EP0DATADONE" description="Enable or disable interrupt for EP0DATADONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDISOIN" description="Enable or disable interrupt for ENDISOIN event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDEPOUT0" description="Enable or disable interrupt for ENDEPOUT[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="ENDEPOUT1" description="Enable or disable interrupt for ENDEPOUT[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="ENDEPOUT2" description="Enable or disable interrupt for ENDEPOUT[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="ENDEPOUT3" description="Enable or disable interrupt for ENDEPOUT[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="ENDEPOUT4" description="Enable or disable interrupt for ENDEPOUT[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="ENDEPOUT5" description="Enable or disable interrupt for ENDEPOUT[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="ENDEPOUT6" description="Enable or disable interrupt for ENDEPOUT[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="ENDEPOUT7" description="Enable or disable interrupt for ENDEPOUT[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="ENDISOOUT" description="Enable or disable interrupt for ENDISOOUT event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="21" size="1" name="SOF" description="Enable or disable interrupt for SOF event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="USBEVENT" description="Enable or disable interrupt for USBEVENT event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="EP0SETUP" description="Enable or disable interrupt for EP0SETUP event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="EPDATA" description="Enable or disable interrupt for EPDATA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="ACCESSFAULT" description="Enable or disable interrupt for ACCESSFAULT event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USBRESET" description="Write '1' to Enable interrupt for USBRESET event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ENDEPIN0" description="Write '1' to Enable interrupt for ENDEPIN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPIN1" description="Write '1' to Enable interrupt for ENDEPIN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPIN2" description="Write '1' to Enable interrupt for ENDEPIN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="ENDEPIN3" description="Write '1' to Enable interrupt for ENDEPIN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDEPIN4" description="Write '1' to Enable interrupt for ENDEPIN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ENDEPIN5" description="Write '1' to Enable interrupt for ENDEPIN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDEPIN6" description="Write '1' to Enable interrupt for ENDEPIN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ENDEPIN7" description="Write '1' to Enable interrupt for ENDEPIN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="EP0DATADONE" description="Write '1' to Enable interrupt for EP0DATADONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDISOIN" description="Write '1' to Enable interrupt for ENDISOIN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDEPOUT0" description="Write '1' to Enable interrupt for ENDEPOUT[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="ENDEPOUT1" description="Write '1' to Enable interrupt for ENDEPOUT[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="ENDEPOUT2" description="Write '1' to Enable interrupt for ENDEPOUT[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="ENDEPOUT3" description="Write '1' to Enable interrupt for ENDEPOUT[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="ENDEPOUT4" description="Write '1' to Enable interrupt for ENDEPOUT[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="ENDEPOUT5" description="Write '1' to Enable interrupt for ENDEPOUT[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="ENDEPOUT6" description="Write '1' to Enable interrupt for ENDEPOUT[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="ENDEPOUT7" description="Write '1' to Enable interrupt for ENDEPOUT[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="ENDISOOUT" description="Write '1' to Enable interrupt for ENDISOOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="SOF" description="Write '1' to Enable interrupt for SOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="USBEVENT" description="Write '1' to Enable interrupt for USBEVENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="EP0SETUP" description="Write '1' to Enable interrupt for EP0SETUP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="EPDATA" description="Write '1' to Enable interrupt for EPDATA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="ACCESSFAULT" description="Write '1' to Enable interrupt for ACCESSFAULT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USBRESET" description="Write '1' to Disable interrupt for USBRESET event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ENDEPIN0" description="Write '1' to Disable interrupt for ENDEPIN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPIN1" description="Write '1' to Disable interrupt for ENDEPIN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPIN2" description="Write '1' to Disable interrupt for ENDEPIN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="ENDEPIN3" description="Write '1' to Disable interrupt for ENDEPIN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDEPIN4" description="Write '1' to Disable interrupt for ENDEPIN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ENDEPIN5" description="Write '1' to Disable interrupt for ENDEPIN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDEPIN6" description="Write '1' to Disable interrupt for ENDEPIN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ENDEPIN7" description="Write '1' to Disable interrupt for ENDEPIN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="EP0DATADONE" description="Write '1' to Disable interrupt for EP0DATADONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDISOIN" description="Write '1' to Disable interrupt for ENDISOIN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDEPOUT0" description="Write '1' to Disable interrupt for ENDEPOUT[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="ENDEPOUT1" description="Write '1' to Disable interrupt for ENDEPOUT[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="ENDEPOUT2" description="Write '1' to Disable interrupt for ENDEPOUT[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="ENDEPOUT3" description="Write '1' to Disable interrupt for ENDEPOUT[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="ENDEPOUT4" description="Write '1' to Disable interrupt for ENDEPOUT[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="ENDEPOUT5" description="Write '1' to Disable interrupt for ENDEPOUT[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="ENDEPOUT6" description="Write '1' to Disable interrupt for ENDEPOUT[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="ENDEPOUT7" description="Write '1' to Disable interrupt for ENDEPOUT[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="ENDISOOUT" description="Write '1' to Disable interrupt for ENDISOOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="SOF" description="Write '1' to Disable interrupt for SOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="USBEVENT" description="Write '1' to Disable interrupt for USBEVENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="EP0SETUP" description="Write '1' to Disable interrupt for EP0SETUP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="EPDATA" description="Write '1' to Disable interrupt for EPDATA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="ACCESSFAULT" description="Write '1' to Disable interrupt for ACCESSFAULT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="EVENTCAUSE" access="Read/Write" description="Details on event that caused the USBEVENT event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ISOOUTCRC" description="CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="No error detected" />
-        <Enum name="Detected" start="1" description="Error detected" />
-      </BitField>
-      <BitField start="8" size="1" name="SUSPEND" description="Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="Suspend not detected" />
-        <Enum name="Detected" start="1" description="Suspend detected" />
-      </BitField>
-      <BitField start="9" size="1" name="RESUME" description="Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="Resume not detected" />
-        <Enum name="Detected" start="1" description="Resume detected" />
-      </BitField>
-      <BitField start="11" size="1" name="READY" description="Wrapper has re-initialized SFRs to the proper values. MAC is ready for normal operation. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="USBEVENT was not issued due to USBD peripheral ready" />
-        <Enum name="Ready" start="1" description="USBD peripheral is ready" />
-      </BitField>
-    </Register>
-    <Register start="+0x404" size="4" name="BUSSTATE" access="ReadOnly" description="Provides the logic state of the D+ and D- lines" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DM" description="State of the D- line">
-        <Enum name="Low" start="0" description="Low" />
-        <Enum name="High" start="1" description="High" />
-      </BitField>
-      <BitField start="1" size="1" name="DP" description="State of the D+ line">
-        <Enum name="Low" start="0" description="Low" />
-        <Enum name="High" start="1" description="High" />
-      </BitField>
-    </Register>
-    <Register start="+0x468" size="4" name="EPSTATUS" access="Read/Write" description="Provides information on which endpoint's EasyDMA registers have been captured" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPIN0" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="1" size="1" name="EPIN1" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="2" size="1" name="EPIN2" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="3" size="1" name="EPIN3" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="4" size="1" name="EPIN4" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="5" size="1" name="EPIN5" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="6" size="1" name="EPIN6" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="7" size="1" name="EPIN7" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="8" size="1" name="EPIN8" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="16" size="1" name="EPOUT0" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="17" size="1" name="EPOUT1" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="18" size="1" name="EPOUT2" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="19" size="1" name="EPOUT3" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="20" size="1" name="EPOUT4" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="21" size="1" name="EPOUT5" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="22" size="1" name="EPOUT6" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="23" size="1" name="EPOUT7" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="24" size="1" name="EPOUT8" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-    </Register>
-    <Register start="+0x46C" size="4" name="EPDATASTATUS" access="Read/Write" description="Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="EPIN1" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="EPIN2" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="3" size="1" name="EPIN3" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="4" size="1" name="EPIN4" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="5" size="1" name="EPIN5" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="6" size="1" name="EPIN6" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="7" size="1" name="EPIN7" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="17" size="1" name="EPOUT1" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="18" size="1" name="EPOUT2" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="19" size="1" name="EPOUT3" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="20" size="1" name="EPOUT4" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="21" size="1" name="EPOUT5" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="22" size="1" name="EPOUT6" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="23" size="1" name="EPOUT7" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x470" size="4" name="USBADDR" access="ReadOnly" description="Device USB address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDR" description="Device USB address" />
-    </Register>
-    <Register start="+0x480" size="4" name="BMREQUESTTYPE" access="ReadOnly" description="SETUP data, byte 0, bmRequestType" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RECIPIENT" description="Data transfer type">
-        <Enum name="Device" start="0" description="Device" />
-        <Enum name="Interface" start="1" description="Interface" />
-        <Enum name="Endpoint" start="2" description="Endpoint" />
-        <Enum name="Other" start="3" description="Other" />
-      </BitField>
-      <BitField start="5" size="2" name="TYPE" description="Data transfer type">
-        <Enum name="Standard" start="0" description="Standard" />
-        <Enum name="Class" start="1" description="Class" />
-        <Enum name="Vendor" start="2" description="Vendor" />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECTION" description="Data transfer direction">
-        <Enum name="HostToDevice" start="0" description="Host-to-device" />
-        <Enum name="DeviceToHost" start="1" description="Device-to-host" />
-      </BitField>
-    </Register>
-    <Register start="+0x484" size="4" name="BREQUEST" access="ReadOnly" description="SETUP data, byte 1, bRequest" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BREQUEST" description="SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values.">
-        <Enum name="STD_GET_STATUS" start="0" description="Standard request GET_STATUS" />
-        <Enum name="STD_CLEAR_FEATURE" start="1" description="Standard request CLEAR_FEATURE" />
-        <Enum name="STD_SET_FEATURE" start="3" description="Standard request SET_FEATURE" />
-        <Enum name="STD_SET_ADDRESS" start="5" description="Standard request SET_ADDRESS" />
-        <Enum name="STD_GET_DESCRIPTOR" start="6" description="Standard request GET_DESCRIPTOR" />
-        <Enum name="STD_SET_DESCRIPTOR" start="7" description="Standard request SET_DESCRIPTOR" />
-        <Enum name="STD_GET_CONFIGURATION" start="8" description="Standard request GET_CONFIGURATION" />
-        <Enum name="STD_SET_CONFIGURATION" start="9" description="Standard request SET_CONFIGURATION" />
-        <Enum name="STD_GET_INTERFACE" start="10" description="Standard request GET_INTERFACE" />
-        <Enum name="STD_SET_INTERFACE" start="11" description="Standard request SET_INTERFACE" />
-        <Enum name="STD_SYNCH_FRAME" start="12" description="Standard request SYNCH_FRAME" />
-      </BitField>
-    </Register>
-    <Register start="+0x488" size="4" name="WVALUEL" access="ReadOnly" description="SETUP data, byte 2, LSB of wValue" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WVALUEL" description="SETUP data, byte 2, LSB of wValue" />
-    </Register>
-    <Register start="+0x48C" size="4" name="WVALUEH" access="ReadOnly" description="SETUP data, byte 3, MSB of wValue" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WVALUEH" description="SETUP data, byte 3, MSB of wValue" />
-    </Register>
-    <Register start="+0x490" size="4" name="WINDEXL" access="ReadOnly" description="SETUP data, byte 4, LSB of wIndex" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WINDEXL" description="SETUP data, byte 4, LSB of wIndex" />
-    </Register>
-    <Register start="+0x494" size="4" name="WINDEXH" access="ReadOnly" description="SETUP data, byte 5, MSB of wIndex" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WINDEXH" description="SETUP data, byte 5, MSB of wIndex" />
-    </Register>
-    <Register start="+0x498" size="4" name="WLENGTHL" access="ReadOnly" description="SETUP data, byte 6, LSB of wLength" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WLENGTHL" description="SETUP data, byte 6, LSB of wLength" />
-    </Register>
-    <Register start="+0x49C" size="4" name="WLENGTHH" access="ReadOnly" description="SETUP data, byte 7, MSB of wLength" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WLENGTHH" description="SETUP data, byte 7, MSB of wLength" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable USB" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable USB">
-        <Enum name="Disabled" start="0" description="USB peripheral is disabled" />
-        <Enum name="Enabled" start="1" description="USB peripheral is enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="USBPULLUP" access="Read/Write" description="Control of the USB pull-up" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONNECT" description="Control of the USB pull-up on the D+ line">
-        <Enum name="Disabled" start="0" description="Pull-up is disconnected" />
-        <Enum name="Enabled" start="1" description="Pull-up is connected to D+" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="DPDMVALUE" access="Read/Write" description="State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing)." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE" description="State at which the DPDMDRIVE task will force D+ and D-">
-        <Enum name="Resume" start="1" description="D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state)" />
-        <Enum name="J" start="2" description="D+ forced high, D- forced low (J state)" />
-        <Enum name="K" start="4" description="D+ forced low, D- forced high (K state)" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="DTOGGLE" access="Read/Write" description="Data toggle control and status." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EP" description="Select bulk endpoint number" />
-      <BitField start="7" size="1" name="IO" description="Selects IN or OUT endpoint">
-        <Enum name="Out" start="0" description="Selects OUT endpoint" />
-        <Enum name="In" start="1" description="Selects IN endpoint" />
-      </BitField>
-      <BitField start="8" size="2" name="VALUE" description="Data toggle value">
-        <Enum name="Nop" start="0" description="No action on data toggle when writing the register with this value" />
-        <Enum name="Data0" start="1" description="Data toggle is DATA0 on endpoint set by EP and IO" />
-        <Enum name="Data1" start="2" description="Data toggle is DATA1 on endpoint set by EP and IO" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="EPINEN" access="Read/Write" description="Endpoint IN enable" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IN0" description="Enable IN endpoint 0">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 0 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 0 (response to IN tokens)" />
-      </BitField>
-      <BitField start="1" size="1" name="IN1" description="Enable IN endpoint 1">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 1 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 1 (response to IN tokens)" />
-      </BitField>
-      <BitField start="2" size="1" name="IN2" description="Enable IN endpoint 2">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 2 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 2 (response to IN tokens)" />
-      </BitField>
-      <BitField start="3" size="1" name="IN3" description="Enable IN endpoint 3">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 3 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 3 (response to IN tokens)" />
-      </BitField>
-      <BitField start="4" size="1" name="IN4" description="Enable IN endpoint 4">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 4 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 4 (response to IN tokens)" />
-      </BitField>
-      <BitField start="5" size="1" name="IN5" description="Enable IN endpoint 5">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 5 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 5 (response to IN tokens)" />
-      </BitField>
-      <BitField start="6" size="1" name="IN6" description="Enable IN endpoint 6">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 6 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 6 (response to IN tokens)" />
-      </BitField>
-      <BitField start="7" size="1" name="IN7" description="Enable IN endpoint 7">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 7 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 7 (response to IN tokens)" />
-      </BitField>
-      <BitField start="8" size="1" name="ISOIN" description="Enable iso IN endpoint">
-        <Enum name="Disable" start="0" description="Disable iso IN endpoint 8" />
-        <Enum name="Enable" start="1" description="Enable iso IN endpoint 8" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="EPOUTEN" access="Read/Write" description="Endpoint OUT enable" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OUT0" description="Enable OUT endpoint 0">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 0 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 0 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="1" size="1" name="OUT1" description="Enable OUT endpoint 1">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 1 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 1 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="2" size="1" name="OUT2" description="Enable OUT endpoint 2">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 2 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 2 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="3" size="1" name="OUT3" description="Enable OUT endpoint 3">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 3 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 3 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="4" size="1" name="OUT4" description="Enable OUT endpoint 4">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 4 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 4 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="5" size="1" name="OUT5" description="Enable OUT endpoint 5">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 5 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 5 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="6" size="1" name="OUT6" description="Enable OUT endpoint 6">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 6 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 6 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="7" size="1" name="OUT7" description="Enable OUT endpoint 7">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 7 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 7 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="8" size="1" name="ISOOUT" description="Enable iso OUT endpoint 8">
-        <Enum name="Disable" start="0" description="Disable iso OUT endpoint 8" />
-        <Enum name="Enable" start="1" description="Enable iso OUT endpoint 8" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="EPSTALL" access="None" description="STALL endpoints" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EP" description="Select endpoint number" />
-      <BitField start="7" size="1" name="IO" description="Selects IN or OUT endpoint">
-        <Enum name="Out" start="0" description="Selects OUT endpoint" />
-        <Enum name="In" start="1" description="Selects IN endpoint" />
-      </BitField>
-      <BitField start="8" size="1" name="STALL" description="Stall selected endpoint">
-        <Enum name="UnStall" start="0" description="Don't stall selected endpoint" />
-        <Enum name="Stall" start="1" description="Stall selected endpoint" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="ISOSPLIT" access="Read/Write" description="Controls the split of ISO buffers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SPLIT" description="Controls the split of ISO buffers">
-        <Enum name="OneDir" start="0x0000" description="Full buffer dedicated to either iso IN or OUT" />
-        <Enum name="HalfIN" start="0x0080" description="Lower half for IN, upper half for OUT" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="FRAMECNTR" access="ReadOnly" description="Returns the current value of the start of frame counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="FRAMECNTR" description="Returns the current value of the start of frame counter" />
-    </Register>
-    <Register start="+0x52C" size="4" name="LOWPOWER" access="Read/Write" description="First silicon only: Controls USBD peripheral low-power mode during USB suspend" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOWPOWER" description="Controls USBD peripheral low-power mode during USB suspend">
-        <Enum name="ForceNormal" start="0" description="Software must write this value to exit low power mode and before performing a remote wake-up" />
-        <Enum name="LowPower" start="1" description="Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral" />
-      </BitField>
-    </Register>
-    <Register start="+0x530" size="4" name="ISOINCONFIG" access="Read/Write" description="Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESPONSE" description="Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent">
-        <Enum name="NoResp" start="0" description="Endpoint does not respond in that case" />
-        <Enum name="ZeroData" start="1" description="Endpoint responds with a zero-length data packet in that case" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+0" size="4" name="HALTED.EPIN[0]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+4" size="4" name="HALTED.EPIN[1]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+8" size="4" name="HALTED.EPIN[2]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+12" size="4" name="HALTED.EPIN[3]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+16" size="4" name="HALTED.EPIN[4]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+20" size="4" name="HALTED.EPIN[5]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+24" size="4" name="HALTED.EPIN[6]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+28" size="4" name="HALTED.EPIN[7]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+0" size="4" name="HALTED.EPOUT[0]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+4" size="4" name="HALTED.EPOUT[1]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+8" size="4" name="HALTED.EPOUT[2]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+12" size="4" name="HALTED.EPOUT[3]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+16" size="4" name="HALTED.EPOUT[4]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+20" size="4" name="HALTED.EPOUT[5]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+24" size="4" name="HALTED.EPOUT[6]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+28" size="4" name="HALTED.EPOUT[7]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x4A0+0x000+0" size="4" name="SIZE.EPOUT[0]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+4" size="4" name="SIZE.EPOUT[1]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+8" size="4" name="SIZE.EPOUT[2]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+12" size="4" name="SIZE.EPOUT[3]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+16" size="4" name="SIZE.EPOUT[4]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+20" size="4" name="SIZE.EPOUT[5]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+24" size="4" name="SIZE.EPOUT[6]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+28" size="4" name="SIZE.EPOUT[7]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x020" size="4" name="SIZE.ISOOUT" access="ReadOnly" description="Amount of bytes received last on this iso OUT data endpoint" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SIZE" description="Amount of bytes received last on this iso OUT data endpoint" />
-      <BitField start="16" size="1" name="ZERO" description="Zero-length data packet received">
-        <Enum name="Normal" start="0" description="No zero-length data received, use value in SIZE" />
-        <Enum name="ZeroData" start="1" description="Zero-length data received, ignore value in SIZE" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+0*20+0x000" size="4" name="EPIN[0].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+0*20+0x004" size="4" name="EPIN[0].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+0*20+0x008" size="4" name="EPIN[0].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+1*20+0x000" size="4" name="EPIN[1].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+1*20+0x004" size="4" name="EPIN[1].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+1*20+0x008" size="4" name="EPIN[1].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+2*20+0x000" size="4" name="EPIN[2].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+2*20+0x004" size="4" name="EPIN[2].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+2*20+0x008" size="4" name="EPIN[2].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+3*20+0x000" size="4" name="EPIN[3].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+3*20+0x004" size="4" name="EPIN[3].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+3*20+0x008" size="4" name="EPIN[3].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+4*20+0x000" size="4" name="EPIN[4].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+4*20+0x004" size="4" name="EPIN[4].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+4*20+0x008" size="4" name="EPIN[4].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+5*20+0x000" size="4" name="EPIN[5].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+5*20+0x004" size="4" name="EPIN[5].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+5*20+0x008" size="4" name="EPIN[5].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+6*20+0x000" size="4" name="EPIN[6].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+6*20+0x004" size="4" name="EPIN[6].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+6*20+0x008" size="4" name="EPIN[6].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+7*20+0x000" size="4" name="EPIN[7].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+7*20+0x004" size="4" name="EPIN[7].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+7*20+0x008" size="4" name="EPIN[7].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x6A0+0x000" size="4" name="ISOIN.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x6A0+0x004" size="4" name="ISOIN.MAXCNT" access="Read/Write" description="Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x6A0+0x008" size="4" name="ISOIN.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+0*20+0x000" size="4" name="EPOUT[0].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+0*20+0x004" size="4" name="EPOUT[0].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+0*20+0x008" size="4" name="EPOUT[0].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+1*20+0x000" size="4" name="EPOUT[1].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+1*20+0x004" size="4" name="EPOUT[1].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+1*20+0x008" size="4" name="EPOUT[1].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+2*20+0x000" size="4" name="EPOUT[2].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+2*20+0x004" size="4" name="EPOUT[2].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+2*20+0x008" size="4" name="EPOUT[2].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+3*20+0x000" size="4" name="EPOUT[3].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+3*20+0x004" size="4" name="EPOUT[3].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+3*20+0x008" size="4" name="EPOUT[3].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+4*20+0x000" size="4" name="EPOUT[4].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+4*20+0x004" size="4" name="EPOUT[4].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+4*20+0x008" size="4" name="EPOUT[4].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+5*20+0x000" size="4" name="EPOUT[5].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+5*20+0x004" size="4" name="EPOUT[5].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+5*20+0x008" size="4" name="EPOUT[5].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+6*20+0x000" size="4" name="EPOUT[6].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+6*20+0x004" size="4" name="EPOUT[6].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+6*20+0x008" size="4" name="EPOUT[6].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+7*20+0x000" size="4" name="EPOUT[7].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+7*20+0x004" size="4" name="EPOUT[7].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+7*20+0x008" size="4" name="EPOUT[7].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x7A0+0x000" size="4" name="ISOOUT.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x7A0+0x004" size="4" name="ISOOUT.MAXCNT" access="Read/Write" description="Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x7A0+0x008" size="4" name="ISOOUT.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UARTE1" start="0x40028000" description="UART with EasyDMA 1">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPRX" access="WriteOnly" description="Stop UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOPTX" access="WriteOnly" description="Stop UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x02C" size="4" name="TASKS_FLUSHRX" access="WriteOnly" description="Flush RX FIFO into RX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_CTS" access="Read/Write" description="CTS is activated (set low). Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_NCTS" access="Read/Write" description="CTS is deactivated (set high). Not Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDRDY" access="Read/Write" description="Data received in RXD (but potentially not yet transferred to Data RAM)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="Receive buffer is filled up" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDRDY" access="Read/Write" description="Data sent from TXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="Last TX byte transmitted" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="Error detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_RXTO" access="Read/Write" description="Receiver timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="UART receiver has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="UART transmitter has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_TXSTOPPED" access="Read/Write" description="Transmitter stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="ENDRX_STARTRX" description="Shortcut between ENDRX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDRX_STOPRX" description="Shortcut between ENDRX event and STOPRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Enable or disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Enable or disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Enable or disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Enable or disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Enable or disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Enable or disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Enable or disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Enable or disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Enable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Enable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Enable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Enable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Enable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Enable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x480" size="4" name="ERRORSRC" access="Read/Write" description="Error source Note : this register is read / write one to clear." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="PARITY" description="Parity error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="FRAMING" description="Framing error occurred">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="3" size="1" name="BREAK" description="Break condition">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable UARTE">
-        <Enum name="Disabled" start="0" description="Disable UARTE" />
-        <Enum name="Enabled" start="8" description="Enable UARTE" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="BAUDRATE" access="Read/Write" description="Baud rate. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BAUDRATE" description="Baud rate">
-        <Enum name="Baud1200" start="0x0004F000" description="1200 baud (actual rate: 1205)" />
-        <Enum name="Baud2400" start="0x0009D000" description="2400 baud (actual rate: 2396)" />
-        <Enum name="Baud4800" start="0x0013B000" description="4800 baud (actual rate: 4808)" />
-        <Enum name="Baud9600" start="0x00275000" description="9600 baud (actual rate: 9598)" />
-        <Enum name="Baud14400" start="0x003AF000" description="14400 baud (actual rate: 14401)" />
-        <Enum name="Baud19200" start="0x004EA000" description="19200 baud (actual rate: 19208)" />
-        <Enum name="Baud28800" start="0x0075C000" description="28800 baud (actual rate: 28777)" />
-        <Enum name="Baud31250" start="0x00800000" description="31250 baud" />
-        <Enum name="Baud38400" start="0x009D0000" description="38400 baud (actual rate: 38369)" />
-        <Enum name="Baud56000" start="0x00E50000" description="56000 baud (actual rate: 55944)" />
-        <Enum name="Baud57600" start="0x00EB0000" description="57600 baud (actual rate: 57554)" />
-        <Enum name="Baud76800" start="0x013A9000" description="76800 baud (actual rate: 76923)" />
-        <Enum name="Baud115200" start="0x01D60000" description="115200 baud (actual rate: 115108)" />
-        <Enum name="Baud230400" start="0x03B00000" description="230400 baud (actual rate: 231884)" />
-        <Enum name="Baud250000" start="0x04000000" description="250000 baud" />
-        <Enum name="Baud460800" start="0x07400000" description="460800 baud (actual rate: 457143)" />
-        <Enum name="Baud921600" start="0x0F000000" description="921600 baud (actual rate: 941176)" />
-        <Enum name="Baud1M" start="0x10000000" description="1Mega baud" />
-      </BitField>
-    </Register>
-    <Register start="+0x56C" size="4" name="CONFIG" access="Read/Write" description="Configuration of parity and hardware flow control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HWFC" description="Hardware flow control">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="3" name="PARITY" description="Parity">
-        <Enum name="Excluded" start="0x0" description="Exclude parity bit" />
-        <Enum name="Included" start="0x7" description="Include even parity bit" />
-      </BitField>
-      <BitField start="4" size="1" name="STOP" description="Stop bits">
-        <Enum name="One" start="0" description="One stop bit" />
-        <Enum name="Two" start="1" description="Two stop bits" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.RTS" access="Read/Write" description="Pin select for RTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.TXD" access="Read/Write" description="Pin select for TXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.CTS" access="Read/Write" description="Pin select for CTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.RXD" access="Read/Write" description="Pin select for RXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QSPI" start="0x40029000" description="External flash interface">
-    <Register start="+0x000" size="4" name="TASKS_ACTIVATE" access="WriteOnly" description="Activate QSPI interface" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_READSTART" access="WriteOnly" description="Start transfer from external flash memory to internal RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_WRITESTART" access="WriteOnly" description="Start transfer from internal RAM to external flash memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_ERASESTART" access="WriteOnly" description="Start external flash memory erase operation" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_DEACTIVATE" access="WriteOnly" description="Deactivate QSPI interface" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="QSPI peripheral is ready. This event will be generated as a response to any QSPI task." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Enable or disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable QSPI peripheral and acquire the pins selected in PSELn registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable QSPI">
-        <Enum name="Disabled" start="0" description="Disable QSPI" />
-        <Enum name="Enabled" start="1" description="Enable QSPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x540" size="4" name="XIPOFFSET" access="Read/Write" description="Address offset into the external memory for Execute in Place operation." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="XIPOFFSET" description="Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4." />
-    </Register>
-    <Register start="+0x544" size="4" name="IFCONFIG0" access="Read/Write" description="Interface configuration." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="READOC" description="Configure number of data lines and opcode used for reading.">
-        <Enum name="FASTREAD" start="0" description="Single data line SPI. FAST_READ (opcode 0x0B)." />
-        <Enum name="READ2O" start="1" description="Dual data line SPI. READ2O (opcode 0x3B)." />
-        <Enum name="READ2IO" start="2" description="Dual data line SPI. READ2IO (opcode 0xBB)." />
-        <Enum name="READ4O" start="3" description="Quad data line SPI. READ4O (opcode 0x6B)." />
-        <Enum name="READ4IO" start="4" description="Quad data line SPI. READ4IO (opcode 0xEB)." />
-      </BitField>
-      <BitField start="3" size="3" name="WRITEOC" description="Configure number of data lines and opcode used for writing.">
-        <Enum name="PP" start="0" description="Single data line SPI. PP (opcode 0x02)." />
-        <Enum name="PP2O" start="1" description="Dual data line SPI. PP2O (opcode 0xA2)." />
-        <Enum name="PP4O" start="2" description="Quad data line SPI. PP4O (opcode 0x32)." />
-        <Enum name="PP4IO" start="3" description="Quad data line SPI. PP4IO (opcode 0x38)." />
-      </BitField>
-      <BitField start="6" size="1" name="ADDRMODE" description="Addressing mode.">
-        <Enum name="24BIT" start="0" description="24-bit addressing." />
-        <Enum name="32BIT" start="1" description="32-bit addressing." />
-      </BitField>
-      <BitField start="7" size="1" name="DPMENABLE" description="Enable deep power-down mode (DPM) feature.">
-        <Enum name="Disable" start="0" description="Disable DPM feature." />
-        <Enum name="Enable" start="1" description="Enable DPM feature." />
-      </BitField>
-      <BitField start="12" size="1" name="PPSIZE" description="Page size for commands PP, PP2O, PP4O and PP4IO.">
-        <Enum name="256Bytes" start="0" description="256 bytes." />
-        <Enum name="512Bytes" start="1" description="512 bytes." />
-      </BitField>
-    </Register>
-    <Register start="+0x600" size="4" name="IFCONFIG1" access="Read/Write" description="Interface configuration." reset_value="0x00040480" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SCKDELAY" description="Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)." />
-      <BitField start="24" size="1" name="DPMEN" description="Enter/exit deep power-down mode (DPM) for external flash memory.">
-        <Enum name="Exit" start="0" description="Exit DPM." />
-        <Enum name="Enter" start="1" description="Enter DPM." />
-      </BitField>
-      <BitField start="25" size="1" name="SPIMODE" description="Select SPI mode.">
-        <Enum name="MODE0" start="0" description="Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0)." />
-        <Enum name="MODE3" start="1" description="Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1)." />
-      </BitField>
-      <BitField start="28" size="4" name="SCKFREQ" description="SCK frequency is given as 32 MHz / (SCKFREQ + 1)." />
-    </Register>
-    <Register start="+0x604" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="DPM" description="Deep power-down mode (DPM) status of external flash.">
-        <Enum name="Disabled" start="0" description="External flash is not in DPM." />
-        <Enum name="Enabled" start="1" description="External flash is in DPM." />
-      </BitField>
-      <BitField start="3" size="1" name="READY" description="Ready status.">
-        <Enum name="READY" start="1" description="QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM." />
-        <Enum name="BUSY" start="0" description="QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM." />
-      </BitField>
-      <BitField start="24" size="8" name="SREG" description="Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte." />
-    </Register>
-    <Register start="+0x614" size="4" name="DPMDUR" access="Read/Write" description="Set the duration required to enter/exit deep power-down mode (DPM)." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENTER" description="Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns." />
-      <BitField start="16" size="16" name="EXIT" description="Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns." />
-    </Register>
-    <Register start="+0x624" size="4" name="ADDRCONF" access="Read/Write" description="Extended address configuration." reset_value="0x000000B7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="OPCODE" description="Opcode that enters the 32-bit addressing mode." />
-      <BitField start="8" size="8" name="BYTE0" description="Byte 0 following opcode." />
-      <BitField start="16" size="8" name="BYTE1" description="Byte 1 following byte 0." />
-      <BitField start="24" size="2" name="MODE" description="Extended addressing mode.">
-        <Enum name="NoInstr" start="0" description="Do not send any instruction." />
-        <Enum name="Opcode" start="1" description="Send opcode." />
-        <Enum name="OpByte0" start="2" description="Send opcode, byte0." />
-        <Enum name="All" start="3" description="Send opcode, byte0, byte1." />
-      </BitField>
-      <BitField start="26" size="1" name="WIPWAIT" description="Wait for write complete before sending command.">
-        <Enum name="Disable" start="0" description="No wait." />
-        <Enum name="Enable" start="1" description="Wait." />
-      </BitField>
-      <BitField start="27" size="1" name="WREN" description="Send WREN (write enable opcode 0x06) before instruction.">
-        <Enum name="Disable" start="0" description="Do not send WREN." />
-        <Enum name="Enable" start="1" description="Send WREN." />
-      </BitField>
-    </Register>
-    <Register start="+0x634" size="4" name="CINSTRCONF" access="Read/Write" description="Custom instruction configuration register." reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="OPCODE" description="Opcode of Custom instruction." />
-      <BitField start="8" size="4" name="LENGTH" description="Length of custom instruction in number of bytes.">
-        <Enum name="1B" start="1" description="Send opcode only." />
-        <Enum name="2B" start="2" description="Send opcode, CINSTRDAT0.BYTE0." />
-        <Enum name="3B" start="3" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT0.BYTE1." />
-        <Enum name="4B" start="4" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT0.BYTE2." />
-        <Enum name="5B" start="5" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT0.BYTE3." />
-        <Enum name="6B" start="6" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE4." />
-        <Enum name="7B" start="7" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE5." />
-        <Enum name="8B" start="8" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE6." />
-        <Enum name="9B" start="9" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE7." />
-      </BitField>
-      <BitField start="12" size="1" name="LIO2" description="Level of the IO2 pin (if connected) during transmission of custom instruction." />
-      <BitField start="13" size="1" name="LIO3" description="Level of the IO3 pin (if connected) during transmission of custom instruction." />
-      <BitField start="14" size="1" name="WIPWAIT" description="Wait for write complete before sending command.">
-        <Enum name="Disable" start="0" description="No wait." />
-        <Enum name="Enable" start="1" description="Wait." />
-      </BitField>
-      <BitField start="15" size="1" name="WREN" description="Send WREN (write enable opcode 0x06) before instruction.">
-        <Enum name="Disable" start="0" description="Do not send WREN." />
-        <Enum name="Enable" start="1" description="Send WREN." />
-      </BitField>
-      <BitField start="16" size="1" name="LFEN" description="Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.">
-        <Enum name="Disable" start="0" description="Long frame mode disabled" />
-        <Enum name="Enable" start="1" description="Long frame mode enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="LFSTOP" description="Stop (finalize) long frame transaction">
-        <Enum name="Stop" start="1" description="Stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x638" size="4" name="CINSTRDAT0" access="Read/Write" description="Custom instruction data register 0." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BYTE0" description="Data byte 0" />
-      <BitField start="8" size="8" name="BYTE1" description="Data byte 1" />
-      <BitField start="16" size="8" name="BYTE2" description="Data byte 2" />
-      <BitField start="24" size="8" name="BYTE3" description="Data byte 3" />
-    </Register>
-    <Register start="+0x63C" size="4" name="CINSTRDAT1" access="Read/Write" description="Custom instruction data register 1." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BYTE4" description="Data byte 4" />
-      <BitField start="8" size="8" name="BYTE5" description="Data byte 5" />
-      <BitField start="16" size="8" name="BYTE6" description="Data byte 6" />
-      <BitField start="24" size="8" name="BYTE7" description="Data byte 7" />
-    </Register>
-    <Register start="+0x640" size="4" name="IFTIMING" access="Read/Write" description="SPI interface timing." reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="3" name="RXDELAY" description="Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x504+0x000" size="4" name="READ.SRC" access="Read/Write" description="Flash memory source address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRC" description="Word-aligned flash memory source address." />
-    </Register>
-    <Register start="+0x504+0x004" size="4" name="READ.DST" access="Read/Write" description="RAM destination address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DST" description="Word-aligned RAM destination address." />
-    </Register>
-    <Register start="+0x504+0x008" size="4" name="READ.CNT" access="Read/Write" description="Read transfer length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="21" name="CNT" description="Read transfer length in number of bytes. The length must be a multiple of 4 bytes." />
-    </Register>
-    <Register start="+0x510+0x000" size="4" name="WRITE.DST" access="Read/Write" description="Flash destination address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DST" description="Word-aligned flash destination address." />
-    </Register>
-    <Register start="+0x510+0x004" size="4" name="WRITE.SRC" access="Read/Write" description="RAM source address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRC" description="Word-aligned RAM source address." />
-    </Register>
-    <Register start="+0x510+0x008" size="4" name="WRITE.CNT" access="Read/Write" description="Write transfer length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="21" name="CNT" description="Write transfer length in number of bytes. The length must be a multiple of 4 bytes." />
-    </Register>
-    <Register start="+0x51C+0x000" size="4" name="ERASE.PTR" access="Read/Write" description="Start address of flash block to be erased" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Word-aligned start address of block to be erased." />
-    </Register>
-    <Register start="+0x51C+0x004" size="4" name="ERASE.LEN" access="Read/Write" description="Size of block to be erased." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LEN" description="LEN">
-        <Enum name="4KB" start="0" description="Erase 4 kB block (flash command 0x20)" />
-        <Enum name="64KB" start="1" description="Erase 64 kB block (flash command 0xD8)" />
-        <Enum name="All" start="2" description="Erase all (flash command 0xC7)" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for serial clock SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x004" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for chip select signal CSN." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x00C" size="4" name="PSEL.IO0" access="Read/Write" description="Pin select for serial data MOSI/IO0." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x010" size="4" name="PSEL.IO1" access="Read/Write" description="Pin select for serial data MISO/IO1." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x014" size="4" name="PSEL.IO2" access="Read/Write" description="Pin select for serial data IO2." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x018" size="4" name="PSEL.IO3" access="Read/Write" description="Pin select for serial data IO3." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM3" start="0x4002D000" description="Pulse Width Modulation Unit 3">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM3" start="0x4002F000" description="Serial Peripheral Interface Master with EasyDMA 3">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="P0" start="0x50000000" description="GPIO Port 1">
-    <Register start="+0x504" size="4" name="OUT" access="Read/Write" description="Write GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="OUTSET" access="Read/Write" description="Set individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="OUTCLR" access="Read/Write" description="Clear individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="IN" access="ReadOnly" description="Read GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="DIR" access="Read/Write" description="Direction of GPIO pins" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="DIRSET" access="Read/Write" description="DIR set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as output pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as output pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as output pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as output pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as output pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as output pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as output pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as output pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as output pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as output pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as output pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as output pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as output pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as output pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as output pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as output pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as output pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as output pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as output pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as output pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as output pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as output pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as output pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as output pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as output pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as output pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as output pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as output pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as output pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as output pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as output pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as output pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="DIRCLR" access="Read/Write" description="DIR clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as input pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as input pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as input pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as input pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as input pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as input pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as input pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as input pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as input pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as input pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as input pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as input pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as input pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as input pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as input pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as input pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as input pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as input pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as input pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as input pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as input pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as input pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as input pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as input pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as input pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as input pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as input pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as input pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as input pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as input pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as input pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as input pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="LATCH" access="Read/Write" description="Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="DETECTMODE" access="Read/Write" description="Select between default DETECT signal behaviour and LDETECT mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETECTMODE" description="Select between default DETECT signal behaviour and LDETECT mode">
-        <Enum name="Default" start="0" description="DETECT directly connected to PIN DETECT signals" />
-        <Enum name="LDETECT" start="1" description="Use the latched LDETECT behaviour" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+0" size="4" name="PIN_CNF[0]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+4" size="4" name="PIN_CNF[1]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+8" size="4" name="PIN_CNF[2]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+12" size="4" name="PIN_CNF[3]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+16" size="4" name="PIN_CNF[4]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+20" size="4" name="PIN_CNF[5]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+24" size="4" name="PIN_CNF[6]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+28" size="4" name="PIN_CNF[7]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+32" size="4" name="PIN_CNF[8]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+36" size="4" name="PIN_CNF[9]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+40" size="4" name="PIN_CNF[10]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+44" size="4" name="PIN_CNF[11]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+48" size="4" name="PIN_CNF[12]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+52" size="4" name="PIN_CNF[13]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+56" size="4" name="PIN_CNF[14]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+60" size="4" name="PIN_CNF[15]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+64" size="4" name="PIN_CNF[16]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+68" size="4" name="PIN_CNF[17]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+72" size="4" name="PIN_CNF[18]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+76" size="4" name="PIN_CNF[19]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+80" size="4" name="PIN_CNF[20]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+84" size="4" name="PIN_CNF[21]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+88" size="4" name="PIN_CNF[22]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+92" size="4" name="PIN_CNF[23]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+96" size="4" name="PIN_CNF[24]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+100" size="4" name="PIN_CNF[25]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+104" size="4" name="PIN_CNF[26]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+108" size="4" name="PIN_CNF[27]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+112" size="4" name="PIN_CNF[28]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+116" size="4" name="PIN_CNF[29]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+120" size="4" name="PIN_CNF[30]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+124" size="4" name="PIN_CNF[31]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="P1" start="0x50000300" description="GPIO Port 2">
-    <Register start="+0x504" size="4" name="OUT" access="Read/Write" description="Write GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="OUTSET" access="Read/Write" description="Set individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="OUTCLR" access="Read/Write" description="Clear individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="IN" access="ReadOnly" description="Read GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="DIR" access="Read/Write" description="Direction of GPIO pins" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="DIRSET" access="Read/Write" description="DIR set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as output pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as output pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as output pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as output pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as output pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as output pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as output pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as output pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as output pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as output pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as output pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as output pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as output pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as output pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as output pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as output pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as output pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as output pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as output pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as output pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as output pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as output pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as output pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as output pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as output pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as output pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as output pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as output pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as output pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as output pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as output pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as output pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="DIRCLR" access="Read/Write" description="DIR clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as input pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as input pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as input pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as input pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as input pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as input pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as input pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as input pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as input pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as input pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as input pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as input pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as input pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as input pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as input pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as input pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as input pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as input pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as input pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as input pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as input pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as input pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as input pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as input pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as input pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as input pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as input pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as input pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as input pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as input pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as input pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as input pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="LATCH" access="Read/Write" description="Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="DETECTMODE" access="Read/Write" description="Select between default DETECT signal behaviour and LDETECT mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETECTMODE" description="Select between default DETECT signal behaviour and LDETECT mode">
-        <Enum name="Default" start="0" description="DETECT directly connected to PIN DETECT signals" />
-        <Enum name="LDETECT" start="1" description="Use the latched LDETECT behaviour" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+0" size="4" name="PIN_CNF[0]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+4" size="4" name="PIN_CNF[1]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+8" size="4" name="PIN_CNF[2]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+12" size="4" name="PIN_CNF[3]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+16" size="4" name="PIN_CNF[4]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+20" size="4" name="PIN_CNF[5]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+24" size="4" name="PIN_CNF[6]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+28" size="4" name="PIN_CNF[7]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+32" size="4" name="PIN_CNF[8]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+36" size="4" name="PIN_CNF[9]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+40" size="4" name="PIN_CNF[10]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+44" size="4" name="PIN_CNF[11]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+48" size="4" name="PIN_CNF[12]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+52" size="4" name="PIN_CNF[13]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+56" size="4" name="PIN_CNF[14]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+60" size="4" name="PIN_CNF[15]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+64" size="4" name="PIN_CNF[16]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+68" size="4" name="PIN_CNF[17]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+72" size="4" name="PIN_CNF[18]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+76" size="4" name="PIN_CNF[19]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+80" size="4" name="PIN_CNF[20]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+84" size="4" name="PIN_CNF[21]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+88" size="4" name="PIN_CNF[22]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+92" size="4" name="PIN_CNF[23]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+96" size="4" name="PIN_CNF[24]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+100" size="4" name="PIN_CNF[25]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+104" size="4" name="PIN_CNF[26]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+108" size="4" name="PIN_CNF[27]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+112" size="4" name="PIN_CNF[28]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+116" size="4" name="PIN_CNF[29]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+120" size="4" name="PIN_CNF[30]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+124" size="4" name="PIN_CNF[31]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CRYPTOCELL" start="0x5002A000" description="ARM CryptoCell register interface">
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Control power and clock for ARM CryptoCell subsystem" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable the CryptoCell subsystem">
-        <Enum name="Disabled" start="0" description="CryptoCell subsystem disabled" />
-        <Enum name="Enabled" start="1" description="CryptoCell subsystem enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="POWER_CLOCK" start="5" size="3" />
-      <BitField name="RADIO" start="13" size="3" />
-      <BitField name="UARTE0_UART0" start="21" size="3" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="5" size="3" />
-      <BitField name="NFCT" start="13" size="3" />
-      <BitField name="GPIOTE" start="21" size="3" />
-      <BitField name="SAADC" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="TIMER0" start="5" size="3" />
-      <BitField name="TIMER1" start="13" size="3" />
-      <BitField name="TIMER2" start="21" size="3" />
-      <BitField name="RTC0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TEMP" start="5" size="3" />
-      <BitField name="RNG" start="13" size="3" />
-      <BitField name="ECB" start="21" size="3" />
-      <BitField name="CCM_AAR" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="WDT" start="5" size="3" />
-      <BitField name="RTC1" start="13" size="3" />
-      <BitField name="QDEC" start="21" size="3" />
-      <BitField name="COMP_LPCOMP" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SWI0_EGU0" start="5" size="3" />
-      <BitField name="SWI1_EGU1" start="13" size="3" />
-      <BitField name="SWI2_EGU2" start="21" size="3" />
-      <BitField name="SWI3_EGU3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="SWI4_EGU4" start="5" size="3" />
-      <BitField name="SWI5_EGU5" start="13" size="3" />
-      <BitField name="TIMER3" start="21" size="3" />
-      <BitField name="TIMER4" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="PWM0" start="5" size="3" />
-      <BitField name="PDM" start="13" size="3" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="MWU" start="5" size="3" />
-      <BitField name="PWM1" start="13" size="3" />
-      <BitField name="PWM2" start="21" size="3" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="RTC2" start="5" size="3" />
-      <BitField name="I2S" start="13" size="3" />
-      <BitField name="FPU" start="21" size="3" />
-      <BitField name="USBD" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="UARTE1" start="5" size="3" />
-      <BitField name="QSPI" start="13" size="3" />
-      <BitField name="CRYPTOCELL" start="21" size="3" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="PWM3" start="13" size="3" />
-      <BitField name="SPIM3" start="29" size="3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/nrf5x/nrf5x.emProject b/examples/device/cdc_msc/ses/nrf5x/nrf5x.emProject
deleted file mode 100644
index 94419913..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/nrf5x.emProject
+++ /dev/null
@@ -1,132 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="nrf5x" target="8" version="2">
-  <project Name="nrf5x">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="nRF52840_xxAA"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00100000;RAM;0x20000000;0x00040000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="nRF52840_xxAA"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_additional_options="-Wno-error=undef;-Wno-error=unused-parameter;-Wno-error=cast-align;-Wno-error=cast-function-type"
-      c_preprocessor_definitions="NRF52840_XXAA;__nRF_FAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_NRF5X;CFG_TUSB_DEBUG=1"
-      c_user_include_directories="../../src;$(rootDir)/lib/CMSIS_5/CMSIS/Core/Include;$(rootDir)/hw;$(rootDir)/src;$(nrfxDir)/..;$(nrfxDir);$(nrfxDir)/mdk;$(nrfxDir)/hal;$(nrfxDir)/drivers/include;$(nrfxDir)/drivers/src"
-      debug_register_definition_file="nrf52840_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="nRF52840_xxAA_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      macros="DeviceFamily=nRF;Target=nRF52840_xxAA;Placement=Flash;rootDir=../../../../..;nrfxDir=../../../../../hw/mcu/nordic/nrfx"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/nRF_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <file file_name="../../../../../hw/bsp/board.c" />
-        <folder Name="feather_nrf52840_express">
-          <file file_name="../../../../../hw/bsp/feather_nrf52840_express/feather_nrf52840_express.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nordic">
-          <folder Name="nrfx">
-            <folder Name="drivers">
-              <folder Name="include">
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/include/nrfx_power_clock.h" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/include/nrfx_power.h" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/include/nrfx_qspi.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/src/nrfx_qspi.c" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c" />
-              </folder>
-            </folder>
-            <folder Name="hal">
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/hal/nrf_power.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/hal/nrf_qspi.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/hal/nrf_usbd.h" />
-            </folder>
-            <folder Name="mdk">
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf51_to_nrf52840.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52840_bitfields.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52840.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52840_peripherals.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52_to_nrf52840.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/ses_startup_nrf52840.s" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/ses_startup_nrf_common.s" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/system_nrf52840.c" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/system_nrf52840.h" />
-            </folder>
-          </folder>
-          <file file_name="../../../../../hw/mcu/nordic/nrfx_config.h" />
-          <file file_name="../../../../../hw/mcu/nordic/nrfx_glue.h" />
-        </folder>
-      </folder>
-      <configuration
-        Name="pca10056 s140v6"
-        build_treat_warnings_as_errors="No" />
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="nrf52840_Registers.xml" />
-      <file file_name="nRF52840_xxAA_MemoryMap.xml" />
-      <file file_name="nRF_Target.js" />
-      <file file_name="thumb_crt0.s" />
-      <file file_name="nRF52840_xxAA_s140v6_MemoryMap.xml" />
-    </folder>
-    <configuration
-      Name="pca10056"
-      build_treat_warnings_as_errors="No"
-      c_preprocessor_definitions=""
-      linker_memory_map_file="nRF52840_xxAA_MemoryMap.xml" />
-    <configuration
-      Name="pca10056 s140v6"
-      build_treat_warnings_as_errors="No"
-      c_preprocessor_definitions="SOFTDEVICE_PRESENT;S140;NO_VTOR_CONFIG;BOARD_PCA10056"
-      c_user_include_directories="$(nrfxDir)/../nrf5x/s140_nrf52_6.1.1_API/include;$(nrfxDir)/../nrf5x/s140_nrf52_6.1.1_API/include/nrf52"
-      debug_start_from_entry_point_symbol="No"
-      linker_memory_map_file="nRF52840_xxAA_s140v6_MemoryMap.xml" />
-    <folder Name="SEGGER_RTT">
-      <folder Name="RTT">
-        <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.c" />
-        <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.h" />
-        <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h" />
-        <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c" />
-      </folder>
-    </folder>
-  </project>
-  <configuration Name="pca10056" />
-  <configuration Name="pca10056 s140v6" />
-  <configuration Name="Feather nRF52840" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/nrf5x/thumb_crt0.s b/examples/device/cdc_msc/ses/nrf5x/thumb_crt0.s
deleted file mode 100644
index 71820cb5..00000000
--- a/examples/device/cdc_msc/ses/nrf5x/thumb_crt0.s
+++ /dev/null
@@ -1,420 +0,0 @@
-// SEGGER Embedded Studio, runtime support.
-//
-// Copyright (c) 2014-2017 SEGGER Microcontroller GmbH & Co KG
-// Copyright (c) 2001-2017 Rowley Associates Limited.
-//
-// This file may be distributed under the terms of the License Agreement
-// provided with this software.
-//
-// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
-// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .align 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER __heap_lock
-  bx lr
-HELPER __heap_unlock
-  bx lr
-HELPER __printf_lock
-  bx lr
-HELPER __printf_unlock
-  bx lr
-HELPER __scanf_lock
-  bx lr
-HELPER __scanf_unlock
-  bx lr
-HELPER __debug_io_lock
-  bx lr
-HELPER __debug_io_unlock
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __cxa_pure_virtual
-  b .
-HELPER __cxa_guard_acquire
-  ldr r3, [r0]
-#if defined(__thumb__) && !defined(__thumb2__)
-  movs r0, #1
-  tst r3, r0
-#else
-  tst r3, #1
-#endif
-  beq 1f
-  movs r0, #0
-  bx lr
-1:
-  movs r0, #1
-  bx lr
-HELPER __cxa_guard_release
-  movs r3, #1
-  str r3, [r0]
-  bx lr
-HELPER __cxa_guard_abort
-  bx lr
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_MemoryMap.xml b/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_MemoryMap.xml
deleted file mode 100644
index 2143d305..00000000
--- a/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_MemoryMap.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="ATSAMD21G18A">
-  <MemorySegment name="FLASH" start="0x00002000" size="0x0003E000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20000000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Registers.xml b/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Registers.xml
deleted file mode 100644
index 2e0fa061..00000000
--- a/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Registers.xml
+++ /dev/null
@@ -1,9587 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="ATSAMD21G18A" description="Atmel ATSAMD21G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G18A.aspx for more)">
-  <RegisterGroup name="AC" start="0x42004400" description="Analog Comparators">
-    <Register start="+0x10+0" size="4" name="AC_COMPCTRL0" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable" />
-      <BitField start="1" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="2" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="LOW" start="0x0" description="Low speed" />
-        <Enum name="HIGH" start="0x1" description="High speed" />
-      </BitField>
-      <BitField start="5" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="2" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-      <BitField start="19" size="1" name="HYST" description="Hysteresis Enable" />
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-    </Register>
-    <Register start="+0x10+4" size="4" name="AC_COMPCTRL1" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable" />
-      <BitField start="1" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="2" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="LOW" start="0x0" description="Low speed" />
-        <Enum name="HIGH" start="0x1" description="High speed" />
-      </BitField>
-      <BitField start="5" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="2" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-      <BitField start="19" size="1" name="HYST" description="Hysteresis Enable" />
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-    </Register>
-    <Register start="+0x00" size="1" name="AC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="LPMUX" description="Low-Power Mux" />
-    </Register>
-    <Register start="+0x01" size="1" name="AC_CTRLB" access="WriteOnly" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START0" description="Comparator 0 Start Comparison" />
-      <BitField start="1" size="1" name="START1" description="Comparator 1 Start Comparison" />
-    </Register>
-    <Register start="+0x02" size="2" name="AC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPEO0" description="Comparator 0 Event Output Enable" />
-      <BitField start="1" size="1" name="COMPEO1" description="Comparator 1 Event Output Enable" />
-      <BitField start="4" size="1" name="WINEO0" description="Window 0 Event Output Enable" />
-      <BitField start="8" size="1" name="COMPEI0" description="Comparator 0 Event Input" />
-      <BitField start="9" size="1" name="COMPEI1" description="Comparator 1 Event Input" />
-    </Register>
-    <Register start="+0x04" size="1" name="AC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="AC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="AC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0" />
-    </Register>
-    <Register start="+0x20+0" size="1" name="AC_SCALER0" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x20+1" size="1" name="AC_SCALER1" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x08" size="1" name="AC_STATUSA" access="ReadOnly" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATE0" description="Comparator 0 Current State" />
-      <BitField start="1" size="1" name="STATE1" description="Comparator 1 Current State" />
-      <BitField start="4" size="2" name="WSTATE0" description="Window 0 Current State">
-        <Enum name="ABOVE" start="0x0" description="Signal is above window" />
-        <Enum name="INSIDE" start="0x1" description="Signal is inside window" />
-        <Enum name="BELOW" start="0x2" description="Signal is below window" />
-      </BitField>
-    </Register>
-    <Register start="+0x09" size="1" name="AC_STATUSB" access="ReadOnly" description="Status B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY0" description="Comparator 0 Ready" />
-      <BitField start="1" size="1" name="READY1" description="Comparator 1 Ready" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-    <Register start="+0x0A" size="1" name="AC_STATUSC" access="ReadOnly" description="Status C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATE0" description="Comparator 0 Current State" />
-      <BitField start="1" size="1" name="STATE1" description="Comparator 1 Current State" />
-      <BitField start="4" size="2" name="WSTATE0" description="Window 0 Current State">
-        <Enum name="ABOVE" start="0x0" description="Signal is above window" />
-        <Enum name="INSIDE" start="0x1" description="Signal is inside window" />
-        <Enum name="BELOW" start="0x2" description="Signal is below window" />
-      </BitField>
-    </Register>
-    <Register start="+0x0C" size="1" name="AC_WINCTRL" access="Read/Write" description="Window Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WEN0" description="Window 0 Mode Enable" />
-      <BitField start="1" size="2" name="WINTSEL0" description="Window 0 Interrupt Selection">
-        <Enum name="ABOVE" start="0x0" description="Interrupt on signal above window" />
-        <Enum name="INSIDE" start="0x1" description="Interrupt on signal inside window" />
-        <Enum name="BELOW" start="0x2" description="Interrupt on signal below window" />
-        <Enum name="OUTSIDE" start="0x3" description="Interrupt on signal outside window" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x42004000" description="Analog Digital Converter">
-    <Register start="+0x02" size="1" name="ADC_AVGCTRL" access="Read/Write" description="Average Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLENUM" description="Number of Samples to be Collected">
-        <Enum name="1" start="0x0" description="1 sample" />
-        <Enum name="2" start="0x1" description="2 samples" />
-        <Enum name="4" start="0x2" description="4 samples" />
-        <Enum name="8" start="0x3" description="8 samples" />
-        <Enum name="16" start="0x4" description="16 samples" />
-        <Enum name="32" start="0x5" description="32 samples" />
-        <Enum name="64" start="0x6" description="64 samples" />
-        <Enum name="128" start="0x7" description="128 samples" />
-        <Enum name="256" start="0x8" description="256 samples" />
-        <Enum name="512" start="0x9" description="512 samples" />
-        <Enum name="1024" start="0xa" description="1024 samples" />
-      </BitField>
-      <BitField start="4" size="3" name="ADJRES" description="Adjusting Result / Division Coefficient" />
-    </Register>
-    <Register start="+0x28" size="2" name="ADC_CALIB" access="Read/Write" description="Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LINEARITY_CAL" description="Linearity Calibration Value" />
-      <BitField start="8" size="3" name="BIAS_CAL" description="Bias Calibration Value" />
-    </Register>
-    <Register start="+0x00" size="1" name="ADC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x04" size="2" name="ADC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIFFMODE" description="Differential Mode" />
-      <BitField start="1" size="1" name="LEFTADJ" description="Left-Adjusted Result" />
-      <BitField start="2" size="1" name="FREERUN" description="Free Running Mode" />
-      <BitField start="3" size="1" name="CORREN" description="Digital Correction Logic Enabled" />
-      <BitField start="4" size="2" name="RESSEL" description="Conversion Result Resolution">
-        <Enum name="12BIT" start="0x0" description="12-bit result" />
-        <Enum name="16BIT" start="0x1" description="For averaging mode output" />
-        <Enum name="10BIT" start="0x2" description="10-bit result" />
-        <Enum name="8BIT" start="0x3" description="8-bit result" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler Configuration">
-        <Enum name="DIV4" start="0x0" description="Peripheral clock divided by 4" />
-        <Enum name="DIV8" start="0x1" description="Peripheral clock divided by 8" />
-        <Enum name="DIV16" start="0x2" description="Peripheral clock divided by 16" />
-        <Enum name="DIV32" start="0x3" description="Peripheral clock divided by 32" />
-        <Enum name="DIV64" start="0x4" description="Peripheral clock divided by 64" />
-        <Enum name="DIV128" start="0x5" description="Peripheral clock divided by 128" />
-        <Enum name="DIV256" start="0x6" description="Peripheral clock divided by 256" />
-        <Enum name="DIV512" start="0x7" description="Peripheral clock divided by 512" />
-      </BitField>
-    </Register>
-    <Register start="+0x2A" size="1" name="ADC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x14" size="1" name="ADC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTEI" description="Start Conversion Event In" />
-      <BitField start="1" size="1" name="SYNCEI" description="Synchronization Event In" />
-      <BitField start="4" size="1" name="RESRDYEO" description="Result Ready Event Out" />
-      <BitField start="5" size="1" name="WINMONEO" description="Window Monitor Event Out" />
-    </Register>
-    <Register start="+0x24" size="2" name="ADC_GAINCORR" access="Read/Write" description="Gain Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="GAINCORR" description="Gain Correction Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="ADC_INPUTCTRL" access="Read/Write" description="Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MUXPOS" description="Positive Mux Input Selection">
-        <Enum name="PIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="PIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="PIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="PIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="PIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="PIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="PIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="PIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="PIN8" start="0x8" description="ADC AIN8 Pin" />
-        <Enum name="PIN9" start="0x9" description="ADC AIN9 Pin" />
-        <Enum name="PIN10" start="0xa" description="ADC AIN10 Pin" />
-        <Enum name="PIN11" start="0xb" description="ADC AIN11 Pin" />
-        <Enum name="PIN12" start="0xc" description="ADC AIN12 Pin" />
-        <Enum name="PIN13" start="0xd" description="ADC AIN13 Pin" />
-        <Enum name="PIN14" start="0xe" description="ADC AIN14 Pin" />
-        <Enum name="PIN15" start="0xf" description="ADC AIN15 Pin" />
-        <Enum name="PIN16" start="0x10" description="ADC AIN16 Pin" />
-        <Enum name="PIN17" start="0x11" description="ADC AIN17 Pin" />
-        <Enum name="PIN18" start="0x12" description="ADC AIN18 Pin" />
-        <Enum name="PIN19" start="0x13" description="ADC AIN19 Pin" />
-        <Enum name="TEMP" start="0x18" description="Temperature Reference" />
-        <Enum name="BANDGAP" start="0x19" description="Bandgap Voltage" />
-        <Enum name="SCALEDCOREVCC" start="0x1a" description="1/4  Scaled Core Supply" />
-        <Enum name="SCALEDIOVCC" start="0x1b" description="1/4  Scaled I/O Supply" />
-        <Enum name="DAC" start="0x1c" description="DAC Output" />
-      </BitField>
-      <BitField start="8" size="5" name="MUXNEG" description="Negative Mux Input Selection">
-        <Enum name="PIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="PIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="PIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="PIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="PIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="PIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="PIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="PIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="GND" start="0x18" description="Internal Ground" />
-        <Enum name="IOGND" start="0x19" description="I/O Ground" />
-      </BitField>
-      <BitField start="16" size="4" name="INPUTSCAN" description="Number of Input Channels Included in Scan" />
-      <BitField start="20" size="4" name="INPUTOFFSET" description="Positive Mux Setting Offset" />
-      <BitField start="24" size="4" name="GAIN" description="Gain Factor Selection">
-        <Enum name="1X" start="0x0" description="1x" />
-        <Enum name="2X" start="0x1" description="2x" />
-        <Enum name="4X" start="0x2" description="4x" />
-        <Enum name="8X" start="0x3" description="8x" />
-        <Enum name="16X" start="0x4" description="16x" />
-        <Enum name="DIV2" start="0xf" description="1/2x" />
-      </BitField>
-    </Register>
-    <Register start="+0x16" size="1" name="ADC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x17" size="1" name="ADC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="ADC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-    </Register>
-    <Register start="+0x26" size="2" name="ADC_OFFSETCORR" access="Read/Write" description="Offset Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="OFFSETCORR" description="Offset Correction Value" />
-    </Register>
-    <Register start="+0x01" size="1" name="ADC_REFCTRL" access="Read/Write" description="Reference Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference Selection">
-        <Enum name="INT1V" start="0x0" description="1.0V voltage reference" />
-        <Enum name="INTVCC0" start="0x1" description="1/1.48 VDDANA" />
-        <Enum name="INTVCC1" start="0x2" description="1/2 VDDANA (only for VDDANA &gt; 2.0V)" />
-        <Enum name="AREFA" start="0x3" description="External reference" />
-        <Enum name="AREFB" start="0x4" description="External reference" />
-      </BitField>
-      <BitField start="7" size="1" name="REFCOMP" description="Reference Buffer Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x1A" size="2" name="ADC_RESULT" access="ReadOnly" description="Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Result Conversion Value" />
-    </Register>
-    <Register start="+0x03" size="1" name="ADC_SAMPCTRL" access="Read/Write" description="Sampling Time Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SAMPLEN" description="Sampling Time Length" />
-    </Register>
-    <Register start="+0x19" size="1" name="ADC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-    <Register start="+0x0C" size="1" name="ADC_SWTRIG" access="Read/Write" description="Software Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSH" description="ADC Conversion Flush" />
-      <BitField start="1" size="1" name="START" description="ADC Start Conversion" />
-    </Register>
-    <Register start="+0x08" size="1" name="ADC_WINCTRL" access="Read/Write" description="Window Monitor Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WINMODE" description="Window Monitor Mode">
-        <Enum name="DISABLE" start="0x0" description="No window mode (default)" />
-        <Enum name="MODE1" start="0x1" description="Mode 1: RESULT &gt; WINLT" />
-        <Enum name="MODE2" start="0x2" description="Mode 2: RESULT &lt; WINUT" />
-        <Enum name="MODE3" start="0x3" description="Mode 3: WINLT &lt; RESULT &lt; WINUT" />
-        <Enum name="MODE4" start="0x4" description="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C" size="2" name="ADC_WINLT" access="Read/Write" description="Window Monitor Lower Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINLT" description="Window Lower Threshold" />
-    </Register>
-    <Register start="+0x20" size="2" name="ADC_WINUT" access="Read/Write" description="Window Monitor Upper Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINUT" description="Window Upper Threshold" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x42004800" description="Digital Analog Converter">
-    <Register start="+0x0" size="1" name="DAC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x1" size="1" name="DAC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOEN" description="External Output Enable" />
-      <BitField start="1" size="1" name="IOEN" description="Internal Output Enable" />
-      <BitField start="2" size="1" name="LEFTADJ" description="Left Adjusted Data" />
-      <BitField start="3" size="1" name="VPD" description="Voltage Pump Disable" />
-      <BitField start="4" size="1" name="BDWP" description="Bypass DATABUF Write Protection" />
-      <BitField start="6" size="2" name="REFSEL" description="Reference Selection">
-        <Enum name="INT1V" start="0x0" description="Internal 1.0V reference" />
-        <Enum name="AVCC" start="0x1" description="AVCC" />
-        <Enum name="VREFP" start="0x2" description="External reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x8" size="2" name="DAC_DATA" access="Read/Write" description="Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Data value to be converted" />
-    </Register>
-    <Register start="+0xC" size="2" name="DAC_DATABUF" access="Read/Write" description="Data Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATABUF" description="Data Buffer" />
-    </Register>
-    <Register start="+0x2" size="1" name="DAC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTEI" description="Start Conversion Event Input" />
-      <BitField start="1" size="1" name="EMPTYEO" description="Data Buffer Empty Event Output" />
-    </Register>
-    <Register start="+0x4" size="1" name="DAC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN" description="Underrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EMPTY" description="Data Buffer Empty Interrupt Enable" />
-      <BitField start="2" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x5" size="1" name="DAC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN" description="Underrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EMPTY" description="Data Buffer Empty Interrupt Enable" />
-      <BitField start="2" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x6" size="1" name="DAC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN" description="Underrun" />
-      <BitField start="1" size="1" name="EMPTY" description="Data Buffer Empty" />
-      <BitField start="2" size="1" name="SYNCRDY" description="Synchronization Ready" />
-    </Register>
-    <Register start="+0x7" size="1" name="DAC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMAC" start="0x41004800" description="Direct Memory Access Controller">
-    <Register start="+0x30" size="4" name="DMAC_ACTIVE" access="ReadOnly" description="Active Channel and Levels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LVLEX0" description="Level 0 Channel Trigger Request Executing" />
-      <BitField start="1" size="1" name="LVLEX1" description="Level 1 Channel Trigger Request Executing" />
-      <BitField start="2" size="1" name="LVLEX2" description="Level 2 Channel Trigger Request Executing" />
-      <BitField start="3" size="1" name="LVLEX3" description="Level 3 Channel Trigger Request Executing" />
-      <BitField start="8" size="5" name="ID" description="Active Channel ID" />
-      <BitField start="15" size="1" name="ABUSY" description="Active Channel Busy" />
-      <BitField start="16" size="16" name="BTCNT" description="Active Channel Block Transfer Count" />
-    </Register>
-    <Register start="+0x34" size="4" name="DMAC_BASEADDR" access="Read/Write" description="Descriptor Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASEADDR" description="Descriptor Memory Base Address" />
-    </Register>
-    <Register start="+0x28" size="4" name="DMAC_BUSYCH" access="ReadOnly" description="Busy Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSYCH0" description="Busy Channel 0" />
-      <BitField start="1" size="1" name="BUSYCH1" description="Busy Channel 1" />
-      <BitField start="2" size="1" name="BUSYCH2" description="Busy Channel 2" />
-      <BitField start="3" size="1" name="BUSYCH3" description="Busy Channel 3" />
-      <BitField start="4" size="1" name="BUSYCH4" description="Busy Channel 4" />
-      <BitField start="5" size="1" name="BUSYCH5" description="Busy Channel 5" />
-      <BitField start="6" size="1" name="BUSYCH6" description="Busy Channel 6" />
-      <BitField start="7" size="1" name="BUSYCH7" description="Busy Channel 7" />
-      <BitField start="8" size="1" name="BUSYCH8" description="Busy Channel 8" />
-      <BitField start="9" size="1" name="BUSYCH9" description="Busy Channel 9" />
-      <BitField start="10" size="1" name="BUSYCH10" description="Busy Channel 10" />
-      <BitField start="11" size="1" name="BUSYCH11" description="Busy Channel 11" />
-    </Register>
-    <Register start="+0x40" size="1" name="DMAC_CHCTRLA" access="Read/Write" description="Channel Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-    </Register>
-    <Register start="+0x44" size="4" name="DMAC_CHCTRLB" access="Read/Write" description="Channel Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-      </BitField>
-      <BitField start="3" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="4" size="1" name="EVOE" description="Channel Event Output Enable" />
-      <BitField start="5" size="2" name="LVL" description="Channel Arbitration Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-      </BitField>
-      <BitField start="8" size="6" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="22" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BEAT" start="0x2" description="One trigger required for each beat transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x3F" size="1" name="DMAC_CHID" access="Read/Write" description="Channel ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Channel ID" />
-    </Register>
-    <Register start="+0x4C" size="1" name="DMAC_CHINTENCLR" access="Read/Write" description="Channel Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D" size="1" name="DMAC_CHINTENSET" access="Read/Write" description="Channel Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4E" size="1" name="DMAC_CHINTFLAG" access="Read/Write" description="Channel Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4F" size="1" name="DMAC_CHSTATUS" access="ReadOnly" description="Channel Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-    </Register>
-    <Register start="+0x08" size="4" name="DMAC_CRCCHKSUM" access="Read/Write" description="CRC Checksum" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCCHKSUM" description="CRC Checksum" />
-    </Register>
-    <Register start="+0x02" size="2" name="DMAC_CRCCTRL" access="Read/Write" description="CRC Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRCBEATSIZE" description="CRC Beat Size">
-        <Enum name="BYTE" start="0x0" description="8-bit bus transfer" />
-        <Enum name="HWORD" start="0x1" description="16-bit bus transfer" />
-        <Enum name="WORD" start="0x2" description="32-bit bus transfer" />
-      </BitField>
-      <BitField start="2" size="2" name="CRCPOLY" description="CRC Polynomial Type">
-        <Enum name="CRC16" start="0x0" description="CRC-16 (CRC-CCITT)" />
-        <Enum name="CRC32" start="0x1" description="CRC32 (IEEE 802.3)" />
-      </BitField>
-      <BitField start="8" size="6" name="CRCSRC" description="CRC Input Source">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="IO" start="0x1" description="I/O interface" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="DMAC_CRCDATAIN" access="Read/Write" description="CRC Data Input" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCDATAIN" description="CRC Data Input" />
-    </Register>
-    <Register start="+0x0C" size="1" name="DMAC_CRCSTATUS" access="Read/Write" description="CRC Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCBUSY" description="CRC Module Busy" />
-      <BitField start="1" size="1" name="CRCZERO" description="CRC Zero" />
-    </Register>
-    <Register start="+0x00" size="2" name="DMAC_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="DMAENABLE" description="DMA Enable" />
-      <BitField start="2" size="1" name="CRCENABLE" description="CRC Enable" />
-      <BitField start="8" size="1" name="LVLEN0" description="Priority Level 0 Enable" />
-      <BitField start="9" size="1" name="LVLEN1" description="Priority Level 1 Enable" />
-      <BitField start="10" size="1" name="LVLEN2" description="Priority Level 2 Enable" />
-      <BitField start="11" size="1" name="LVLEN3" description="Priority Level 3 Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="DMAC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x20" size="2" name="DMAC_INTPEND" access="Read/Write" description="Interrupt Pending" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Channel ID" />
-      <BitField start="8" size="1" name="TERR" description="Transfer Error" />
-      <BitField start="9" size="1" name="TCMPL" description="Transfer Complete" />
-      <BitField start="10" size="1" name="SUSP" description="Channel Suspend" />
-      <BitField start="13" size="1" name="FERR" description="Fetch Error" />
-      <BitField start="14" size="1" name="BUSY" description="Busy" />
-      <BitField start="15" size="1" name="PEND" description="Pending" />
-    </Register>
-    <Register start="+0x24" size="4" name="DMAC_INTSTATUS" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHINT0" description="Channel 0 Pending Interrupt" />
-      <BitField start="1" size="1" name="CHINT1" description="Channel 1 Pending Interrupt" />
-      <BitField start="2" size="1" name="CHINT2" description="Channel 2 Pending Interrupt" />
-      <BitField start="3" size="1" name="CHINT3" description="Channel 3 Pending Interrupt" />
-      <BitField start="4" size="1" name="CHINT4" description="Channel 4 Pending Interrupt" />
-      <BitField start="5" size="1" name="CHINT5" description="Channel 5 Pending Interrupt" />
-      <BitField start="6" size="1" name="CHINT6" description="Channel 6 Pending Interrupt" />
-      <BitField start="7" size="1" name="CHINT7" description="Channel 7 Pending Interrupt" />
-      <BitField start="8" size="1" name="CHINT8" description="Channel 8 Pending Interrupt" />
-      <BitField start="9" size="1" name="CHINT9" description="Channel 9 Pending Interrupt" />
-      <BitField start="10" size="1" name="CHINT10" description="Channel 10 Pending Interrupt" />
-      <BitField start="11" size="1" name="CHINT11" description="Channel 11 Pending Interrupt" />
-    </Register>
-    <Register start="+0x2C" size="4" name="DMAC_PENDCH" access="ReadOnly" description="Pending Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PENDCH0" description="Pending Channel 0" />
-      <BitField start="1" size="1" name="PENDCH1" description="Pending Channel 1" />
-      <BitField start="2" size="1" name="PENDCH2" description="Pending Channel 2" />
-      <BitField start="3" size="1" name="PENDCH3" description="Pending Channel 3" />
-      <BitField start="4" size="1" name="PENDCH4" description="Pending Channel 4" />
-      <BitField start="5" size="1" name="PENDCH5" description="Pending Channel 5" />
-      <BitField start="6" size="1" name="PENDCH6" description="Pending Channel 6" />
-      <BitField start="7" size="1" name="PENDCH7" description="Pending Channel 7" />
-      <BitField start="8" size="1" name="PENDCH8" description="Pending Channel 8" />
-      <BitField start="9" size="1" name="PENDCH9" description="Pending Channel 9" />
-      <BitField start="10" size="1" name="PENDCH10" description="Pending Channel 10" />
-      <BitField start="11" size="1" name="PENDCH11" description="Pending Channel 11" />
-    </Register>
-    <Register start="+0x14" size="4" name="DMAC_PRICTRL0" access="Read/Write" description="Priority Control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="LVLPRI0" description="Level 0 Channel Priority Number" />
-      <BitField start="7" size="1" name="RRLVLEN0" description="Level 0 Round-Robin Scheduling Enable" />
-      <BitField start="8" size="4" name="LVLPRI1" description="Level 1 Channel Priority Number" />
-      <BitField start="15" size="1" name="RRLVLEN1" description="Level 1 Round-Robin Scheduling Enable" />
-      <BitField start="16" size="4" name="LVLPRI2" description="Level 2 Channel Priority Number" />
-      <BitField start="23" size="1" name="RRLVLEN2" description="Level 2 Round-Robin Scheduling Enable" />
-      <BitField start="24" size="4" name="LVLPRI3" description="Level 3 Channel Priority Number" />
-      <BitField start="31" size="1" name="RRLVLEN3" description="Level 3 Round-Robin Scheduling Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="DMAC_QOSCTRL" access="Read/Write" description="QOS Control" reset_value="0x15" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WRBQOS" description="Write-Back Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="2" size="2" name="FQOS" description="Fetch Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="4" size="2" name="DQOS" description="Data Transfer Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-    </Register>
-    <Register start="+0x10" size="4" name="DMAC_SWTRIGCTRL" access="Read/Write" description="Software Trigger Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWTRIG0" description="Channel 0 Software Trigger" />
-      <BitField start="1" size="1" name="SWTRIG1" description="Channel 1 Software Trigger" />
-      <BitField start="2" size="1" name="SWTRIG2" description="Channel 2 Software Trigger" />
-      <BitField start="3" size="1" name="SWTRIG3" description="Channel 3 Software Trigger" />
-      <BitField start="4" size="1" name="SWTRIG4" description="Channel 4 Software Trigger" />
-      <BitField start="5" size="1" name="SWTRIG5" description="Channel 5 Software Trigger" />
-      <BitField start="6" size="1" name="SWTRIG6" description="Channel 6 Software Trigger" />
-      <BitField start="7" size="1" name="SWTRIG7" description="Channel 7 Software Trigger" />
-      <BitField start="8" size="1" name="SWTRIG8" description="Channel 8 Software Trigger" />
-      <BitField start="9" size="1" name="SWTRIG9" description="Channel 9 Software Trigger" />
-      <BitField start="10" size="1" name="SWTRIG10" description="Channel 10 Software Trigger" />
-      <BitField start="11" size="1" name="SWTRIG11" description="Channel 11 Software Trigger" />
-    </Register>
-    <Register start="+0x38" size="4" name="DMAC_WRBADDR" access="Read/Write" description="Write-Back Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WRBADDR" description="Write-Back Memory Base Address" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DSU" start="0x41002000" description="Device Service Unit">
-    <Register start="+0x0004" size="4" name="DSU_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="30" name="ADDR" description="Address" />
-    </Register>
-    <Register start="+0x1FF0" size="4" name="DSU_CID0" access="ReadOnly" description="Component Identification 0" reset_value="0x0000000D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB0" description="Preamble Byte 0" />
-    </Register>
-    <Register start="+0x1FF4" size="4" name="DSU_CID1" access="ReadOnly" description="Component Identification 1" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PREAMBLE" description="Preamble" />
-      <BitField start="4" size="4" name="CCLASS" description="Component Class" />
-    </Register>
-    <Register start="+0x1FF8" size="4" name="DSU_CID2" access="ReadOnly" description="Component Identification 2" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB2" description="Preamble Byte 2" />
-    </Register>
-    <Register start="+0x1FFC" size="4" name="DSU_CID3" access="ReadOnly" description="Component Identification 3" reset_value="0x000000B1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB3" description="Preamble Byte 3" />
-    </Register>
-    <Register start="+0x0000" size="1" name="DSU_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="2" size="1" name="CRC" description="32-bit Cyclic Redundancy Check" />
-      <BitField start="3" size="1" name="MBIST" description="Memory Built-In Self-Test" />
-      <BitField start="4" size="1" name="CE" description="Chip Erase" />
-    </Register>
-    <Register start="+0x000C" size="4" name="DSU_DATA" access="Read/Write" description="Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+0" size="4" name="DSU_DCC0" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+4" size="4" name="DSU_DCC1" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0018" size="4" name="DSU_DID" access="ReadOnly" description="Device Identification" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEVSEL" description="Device Select" />
-      <BitField start="8" size="4" name="REVISION" description="Revision" />
-      <BitField start="12" size="4" name="DIE" description="Die Identification" />
-      <BitField start="16" size="6" name="SERIES" description="Product Series" />
-      <BitField start="23" size="5" name="FAMILY" description="Product Family" />
-      <BitField start="28" size="4" name="PROCESSOR" description="Processor" />
-    </Register>
-    <Register start="+0x1008" size="4" name="DSU_END" access="ReadOnly" description="Coresight ROM Table End" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End Marker" />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="DSU_ENTRY0" access="ReadOnly" description="Coresight ROM Table Entry n" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRES" description="Entry Present" />
-      <BitField start="1" size="1" name="FMT" description="Format" />
-      <BitField start="12" size="20" name="ADDOFF" description="Address Offset" />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="DSU_ENTRY1" access="ReadOnly" description="Coresight ROM Table Entry n" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRES" description="Entry Present" />
-      <BitField start="1" size="1" name="FMT" description="Format" />
-      <BitField start="12" size="20" name="ADDOFF" description="Address Offset" />
-    </Register>
-    <Register start="+0x0008" size="4" name="DSU_LENGTH" access="Read/Write" description="Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="30" name="LENGTH" description="Length" />
-    </Register>
-    <Register start="+0x1FCC" size="4" name="DSU_MEMTYPE" access="ReadOnly" description="Coresight ROM Table Memory Type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SMEMP" description="System Memory Present" />
-    </Register>
-    <Register start="+0x1FE0" size="4" name="DSU_PID0" access="ReadOnly" description="Peripheral Identification 0" reset_value="0x000000D0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PARTNBL" description="Part Number Low" />
-    </Register>
-    <Register start="+0x1FE4" size="4" name="DSU_PID1" access="ReadOnly" description="Peripheral Identification 1" reset_value="0x000000FC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PARTNBH" description="Part Number High" />
-      <BitField start="4" size="4" name="JEPIDCL" description="Low part of the JEP-106 Identity Code" />
-    </Register>
-    <Register start="+0x1FE8" size="4" name="DSU_PID2" access="ReadOnly" description="Peripheral Identification 2" reset_value="0x00000009" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="JEPIDCH" description="JEP-106 Identity Code High" />
-      <BitField start="3" size="1" name="JEPU" description="JEP-106 Identity Code is used" />
-      <BitField start="4" size="4" name="REVISION" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FEC" size="4" name="DSU_PID3" access="ReadOnly" description="Peripheral Identification 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CUSMOD" description="ARM CUSMOD" />
-      <BitField start="4" size="4" name="REVAND" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FD0" size="4" name="DSU_PID4" access="ReadOnly" description="Peripheral Identification 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="JEPCC" description="JEP-106 Continuation Code" />
-      <BitField start="4" size="4" name="FKBC" description="4KB Count" />
-    </Register>
-    <Register start="+0x0001" size="1" name="DSU_STATUSA" access="Read/Write" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Done" />
-      <BitField start="1" size="1" name="CRSTEXT" description="CPU Reset Phase Extension" />
-      <BitField start="2" size="1" name="BERR" description="Bus Error" />
-      <BitField start="3" size="1" name="FAIL" description="Failure" />
-      <BitField start="4" size="1" name="PERR" description="Protection Error" />
-    </Register>
-    <Register start="+0x0002" size="1" name="DSU_STATUSB" access="ReadOnly" description="Status B" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PROT" description="Protected" />
-      <BitField start="1" size="1" name="DBGPRES" description="Debugger Present" />
-      <BitField start="2" size="1" name="DCCD0" description="Debug Communication Channel 0 Dirty" />
-      <BitField start="3" size="1" name="DCCD1" description="Debug Communication Channel 1 Dirty" />
-      <BitField start="4" size="1" name="HPE" description="Hot-Plugging Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EIC" start="0x40001800" description="External Interrupt Controller">
-    <Register start="+0x18+0" size="4" name="EIC_CONFIG0" access="Read/Write" description="Configuration n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense 0 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter 0 Enable" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense 1 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter 1 Enable" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense 2 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter 2 Enable" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense 3 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter 3 Enable" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense 4 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter 4 Enable" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense 5 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter 5 Enable" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense 6 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter 6 Enable" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense 7 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter 7 Enable" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="EIC_CONFIG1" access="Read/Write" description="Configuration n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense 0 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter 0 Enable" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense 1 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter 1 Enable" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense 2 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter 2 Enable" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense 3 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter 3 Enable" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense 4 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter 4 Enable" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense 5 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter 5 Enable" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense 6 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter 6 Enable" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense 7 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter 7 Enable" />
-    </Register>
-    <Register start="+0x00" size="1" name="EIC_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="EIC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINTEO0" description="External Interrupt 0 Event Output Enable" />
-      <BitField start="1" size="1" name="EXTINTEO1" description="External Interrupt 1 Event Output Enable" />
-      <BitField start="2" size="1" name="EXTINTEO2" description="External Interrupt 2 Event Output Enable" />
-      <BitField start="3" size="1" name="EXTINTEO3" description="External Interrupt 3 Event Output Enable" />
-      <BitField start="4" size="1" name="EXTINTEO4" description="External Interrupt 4 Event Output Enable" />
-      <BitField start="5" size="1" name="EXTINTEO5" description="External Interrupt 5 Event Output Enable" />
-      <BitField start="6" size="1" name="EXTINTEO6" description="External Interrupt 6 Event Output Enable" />
-      <BitField start="7" size="1" name="EXTINTEO7" description="External Interrupt 7 Event Output Enable" />
-      <BitField start="8" size="1" name="EXTINTEO8" description="External Interrupt 8 Event Output Enable" />
-      <BitField start="9" size="1" name="EXTINTEO9" description="External Interrupt 9 Event Output Enable" />
-      <BitField start="10" size="1" name="EXTINTEO10" description="External Interrupt 10 Event Output Enable" />
-      <BitField start="11" size="1" name="EXTINTEO11" description="External Interrupt 11 Event Output Enable" />
-      <BitField start="12" size="1" name="EXTINTEO12" description="External Interrupt 12 Event Output Enable" />
-      <BitField start="13" size="1" name="EXTINTEO13" description="External Interrupt 13 Event Output Enable" />
-      <BitField start="14" size="1" name="EXTINTEO14" description="External Interrupt 14 Event Output Enable" />
-      <BitField start="15" size="1" name="EXTINTEO15" description="External Interrupt 15 Event Output Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="EIC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0 Enable" />
-      <BitField start="1" size="1" name="EXTINT1" description="External Interrupt 1 Enable" />
-      <BitField start="2" size="1" name="EXTINT2" description="External Interrupt 2 Enable" />
-      <BitField start="3" size="1" name="EXTINT3" description="External Interrupt 3 Enable" />
-      <BitField start="4" size="1" name="EXTINT4" description="External Interrupt 4 Enable" />
-      <BitField start="5" size="1" name="EXTINT5" description="External Interrupt 5 Enable" />
-      <BitField start="6" size="1" name="EXTINT6" description="External Interrupt 6 Enable" />
-      <BitField start="7" size="1" name="EXTINT7" description="External Interrupt 7 Enable" />
-      <BitField start="8" size="1" name="EXTINT8" description="External Interrupt 8 Enable" />
-      <BitField start="9" size="1" name="EXTINT9" description="External Interrupt 9 Enable" />
-      <BitField start="10" size="1" name="EXTINT10" description="External Interrupt 10 Enable" />
-      <BitField start="11" size="1" name="EXTINT11" description="External Interrupt 11 Enable" />
-      <BitField start="12" size="1" name="EXTINT12" description="External Interrupt 12 Enable" />
-      <BitField start="13" size="1" name="EXTINT13" description="External Interrupt 13 Enable" />
-      <BitField start="14" size="1" name="EXTINT14" description="External Interrupt 14 Enable" />
-      <BitField start="15" size="1" name="EXTINT15" description="External Interrupt 15 Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="EIC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0 Enable" />
-      <BitField start="1" size="1" name="EXTINT1" description="External Interrupt 1 Enable" />
-      <BitField start="2" size="1" name="EXTINT2" description="External Interrupt 2 Enable" />
-      <BitField start="3" size="1" name="EXTINT3" description="External Interrupt 3 Enable" />
-      <BitField start="4" size="1" name="EXTINT4" description="External Interrupt 4 Enable" />
-      <BitField start="5" size="1" name="EXTINT5" description="External Interrupt 5 Enable" />
-      <BitField start="6" size="1" name="EXTINT6" description="External Interrupt 6 Enable" />
-      <BitField start="7" size="1" name="EXTINT7" description="External Interrupt 7 Enable" />
-      <BitField start="8" size="1" name="EXTINT8" description="External Interrupt 8 Enable" />
-      <BitField start="9" size="1" name="EXTINT9" description="External Interrupt 9 Enable" />
-      <BitField start="10" size="1" name="EXTINT10" description="External Interrupt 10 Enable" />
-      <BitField start="11" size="1" name="EXTINT11" description="External Interrupt 11 Enable" />
-      <BitField start="12" size="1" name="EXTINT12" description="External Interrupt 12 Enable" />
-      <BitField start="13" size="1" name="EXTINT13" description="External Interrupt 13 Enable" />
-      <BitField start="14" size="1" name="EXTINT14" description="External Interrupt 14 Enable" />
-      <BitField start="15" size="1" name="EXTINT15" description="External Interrupt 15 Enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="EIC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0" />
-      <BitField start="1" size="1" name="EXTINT1" description="External Interrupt 1" />
-      <BitField start="2" size="1" name="EXTINT2" description="External Interrupt 2" />
-      <BitField start="3" size="1" name="EXTINT3" description="External Interrupt 3" />
-      <BitField start="4" size="1" name="EXTINT4" description="External Interrupt 4" />
-      <BitField start="5" size="1" name="EXTINT5" description="External Interrupt 5" />
-      <BitField start="6" size="1" name="EXTINT6" description="External Interrupt 6" />
-      <BitField start="7" size="1" name="EXTINT7" description="External Interrupt 7" />
-      <BitField start="8" size="1" name="EXTINT8" description="External Interrupt 8" />
-      <BitField start="9" size="1" name="EXTINT9" description="External Interrupt 9" />
-      <BitField start="10" size="1" name="EXTINT10" description="External Interrupt 10" />
-      <BitField start="11" size="1" name="EXTINT11" description="External Interrupt 11" />
-      <BitField start="12" size="1" name="EXTINT12" description="External Interrupt 12" />
-      <BitField start="13" size="1" name="EXTINT13" description="External Interrupt 13" />
-      <BitField start="14" size="1" name="EXTINT14" description="External Interrupt 14" />
-      <BitField start="15" size="1" name="EXTINT15" description="External Interrupt 15" />
-    </Register>
-    <Register start="+0x02" size="1" name="EIC_NMICTRL" access="Read/Write" description="Non-Maskable Interrupt Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="NMISENSE" description="Non-Maskable Interrupt Sense">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="NMIFILTEN" description="Non-Maskable Interrupt Filter Enable" />
-    </Register>
-    <Register start="+0x03" size="1" name="EIC_NMIFLAG" access="Read/Write" description="Non-Maskable Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMI" description="Non-Maskable Interrupt" />
-    </Register>
-    <Register start="+0x01" size="1" name="EIC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-    <Register start="+0x14" size="4" name="EIC_WAKEUP" access="Read/Write" description="Wake-Up Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUPEN0" description="External Interrupt 0 Wake-up Enable" />
-      <BitField start="1" size="1" name="WAKEUPEN1" description="External Interrupt 1 Wake-up Enable" />
-      <BitField start="2" size="1" name="WAKEUPEN2" description="External Interrupt 2 Wake-up Enable" />
-      <BitField start="3" size="1" name="WAKEUPEN3" description="External Interrupt 3 Wake-up Enable" />
-      <BitField start="4" size="1" name="WAKEUPEN4" description="External Interrupt 4 Wake-up Enable" />
-      <BitField start="5" size="1" name="WAKEUPEN5" description="External Interrupt 5 Wake-up Enable" />
-      <BitField start="6" size="1" name="WAKEUPEN6" description="External Interrupt 6 Wake-up Enable" />
-      <BitField start="7" size="1" name="WAKEUPEN7" description="External Interrupt 7 Wake-up Enable" />
-      <BitField start="8" size="1" name="WAKEUPEN8" description="External Interrupt 8 Wake-up Enable" />
-      <BitField start="9" size="1" name="WAKEUPEN9" description="External Interrupt 9 Wake-up Enable" />
-      <BitField start="10" size="1" name="WAKEUPEN10" description="External Interrupt 10 Wake-up Enable" />
-      <BitField start="11" size="1" name="WAKEUPEN11" description="External Interrupt 11 Wake-up Enable" />
-      <BitField start="12" size="1" name="WAKEUPEN12" description="External Interrupt 12 Wake-up Enable" />
-      <BitField start="13" size="1" name="WAKEUPEN13" description="External Interrupt 13 Wake-up Enable" />
-      <BitField start="14" size="1" name="WAKEUPEN14" description="External Interrupt 14 Wake-up Enable" />
-      <BitField start="15" size="1" name="WAKEUPEN15" description="External Interrupt 15 Wake-up Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVSYS" start="0x42000400" description="Event System Interface">
-    <Register start="+0x04" size="4" name="EVSYS_CHANNEL" access="Read/Write" description="Channel" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CHANNEL" description="Channel Selection" />
-      <BitField start="8" size="1" name="SWEVT" description="Software Event" />
-      <BitField start="16" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="24" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="26" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-    </Register>
-    <Register start="+0x0C" size="4" name="EVSYS_CHSTATUS" access="ReadOnly" description="Channel Status" reset_value="0x000F00FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USRRDY0" description="Channel 0 User Ready" />
-      <BitField start="1" size="1" name="USRRDY1" description="Channel 1 User Ready" />
-      <BitField start="2" size="1" name="USRRDY2" description="Channel 2 User Ready" />
-      <BitField start="3" size="1" name="USRRDY3" description="Channel 3 User Ready" />
-      <BitField start="4" size="1" name="USRRDY4" description="Channel 4 User Ready" />
-      <BitField start="5" size="1" name="USRRDY5" description="Channel 5 User Ready" />
-      <BitField start="6" size="1" name="USRRDY6" description="Channel 6 User Ready" />
-      <BitField start="7" size="1" name="USRRDY7" description="Channel 7 User Ready" />
-      <BitField start="8" size="1" name="CHBUSY0" description="Channel 0 Busy" />
-      <BitField start="9" size="1" name="CHBUSY1" description="Channel 1 Busy" />
-      <BitField start="10" size="1" name="CHBUSY2" description="Channel 2 Busy" />
-      <BitField start="11" size="1" name="CHBUSY3" description="Channel 3 Busy" />
-      <BitField start="12" size="1" name="CHBUSY4" description="Channel 4 Busy" />
-      <BitField start="13" size="1" name="CHBUSY5" description="Channel 5 Busy" />
-      <BitField start="14" size="1" name="CHBUSY6" description="Channel 6 Busy" />
-      <BitField start="15" size="1" name="CHBUSY7" description="Channel 7 Busy" />
-      <BitField start="16" size="1" name="USRRDY8" description="Channel 8 User Ready" />
-      <BitField start="17" size="1" name="USRRDY9" description="Channel 9 User Ready" />
-      <BitField start="18" size="1" name="USRRDY10" description="Channel 10 User Ready" />
-      <BitField start="19" size="1" name="USRRDY11" description="Channel 11 User Ready" />
-      <BitField start="24" size="1" name="CHBUSY8" description="Channel 8 Busy" />
-      <BitField start="25" size="1" name="CHBUSY9" description="Channel 9 Busy" />
-      <BitField start="26" size="1" name="CHBUSY10" description="Channel 10 Busy" />
-      <BitField start="27" size="1" name="CHBUSY11" description="Channel 11 Busy" />
-    </Register>
-    <Register start="+0x00" size="1" name="EVSYS_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="4" size="1" name="GCLKREQ" description="Generic Clock Requests" />
-    </Register>
-    <Register start="+0x10" size="4" name="EVSYS_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR0" description="Channel 0 Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="OVR1" description="Channel 1 Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="OVR2" description="Channel 2 Overrun Interrupt Enable" />
-      <BitField start="3" size="1" name="OVR3" description="Channel 3 Overrun Interrupt Enable" />
-      <BitField start="4" size="1" name="OVR4" description="Channel 4 Overrun Interrupt Enable" />
-      <BitField start="5" size="1" name="OVR5" description="Channel 5 Overrun Interrupt Enable" />
-      <BitField start="6" size="1" name="OVR6" description="Channel 6 Overrun Interrupt Enable" />
-      <BitField start="7" size="1" name="OVR7" description="Channel 7 Overrun Interrupt Enable" />
-      <BitField start="8" size="1" name="EVD0" description="Channel 0 Event Detection Interrupt Enable" />
-      <BitField start="9" size="1" name="EVD1" description="Channel 1 Event Detection Interrupt Enable" />
-      <BitField start="10" size="1" name="EVD2" description="Channel 2 Event Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="EVD3" description="Channel 3 Event Detection Interrupt Enable" />
-      <BitField start="12" size="1" name="EVD4" description="Channel 4 Event Detection Interrupt Enable" />
-      <BitField start="13" size="1" name="EVD5" description="Channel 5 Event Detection Interrupt Enable" />
-      <BitField start="14" size="1" name="EVD6" description="Channel 6 Event Detection Interrupt Enable" />
-      <BitField start="15" size="1" name="EVD7" description="Channel 7 Event Detection Interrupt Enable" />
-      <BitField start="16" size="1" name="OVR8" description="Channel 8 Overrun Interrupt Enable" />
-      <BitField start="17" size="1" name="OVR9" description="Channel 9 Overrun Interrupt Enable" />
-      <BitField start="18" size="1" name="OVR10" description="Channel 10 Overrun Interrupt Enable" />
-      <BitField start="19" size="1" name="OVR11" description="Channel 11 Overrun Interrupt Enable" />
-      <BitField start="24" size="1" name="EVD8" description="Channel 8 Event Detection Interrupt Enable" />
-      <BitField start="25" size="1" name="EVD9" description="Channel 9 Event Detection Interrupt Enable" />
-      <BitField start="26" size="1" name="EVD10" description="Channel 10 Event Detection Interrupt Enable" />
-      <BitField start="27" size="1" name="EVD11" description="Channel 11 Event Detection Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="4" name="EVSYS_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR0" description="Channel 0 Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="OVR1" description="Channel 1 Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="OVR2" description="Channel 2 Overrun Interrupt Enable" />
-      <BitField start="3" size="1" name="OVR3" description="Channel 3 Overrun Interrupt Enable" />
-      <BitField start="4" size="1" name="OVR4" description="Channel 4 Overrun Interrupt Enable" />
-      <BitField start="5" size="1" name="OVR5" description="Channel 5 Overrun Interrupt Enable" />
-      <BitField start="6" size="1" name="OVR6" description="Channel 6 Overrun Interrupt Enable" />
-      <BitField start="7" size="1" name="OVR7" description="Channel 7 Overrun Interrupt Enable" />
-      <BitField start="8" size="1" name="EVD0" description="Channel 0 Event Detection Interrupt Enable" />
-      <BitField start="9" size="1" name="EVD1" description="Channel 1 Event Detection Interrupt Enable" />
-      <BitField start="10" size="1" name="EVD2" description="Channel 2 Event Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="EVD3" description="Channel 3 Event Detection Interrupt Enable" />
-      <BitField start="12" size="1" name="EVD4" description="Channel 4 Event Detection Interrupt Enable" />
-      <BitField start="13" size="1" name="EVD5" description="Channel 5 Event Detection Interrupt Enable" />
-      <BitField start="14" size="1" name="EVD6" description="Channel 6 Event Detection Interrupt Enable" />
-      <BitField start="15" size="1" name="EVD7" description="Channel 7 Event Detection Interrupt Enable" />
-      <BitField start="16" size="1" name="OVR8" description="Channel 8 Overrun Interrupt Enable" />
-      <BitField start="17" size="1" name="OVR9" description="Channel 9 Overrun Interrupt Enable" />
-      <BitField start="18" size="1" name="OVR10" description="Channel 10 Overrun Interrupt Enable" />
-      <BitField start="19" size="1" name="OVR11" description="Channel 11 Overrun Interrupt Enable" />
-      <BitField start="24" size="1" name="EVD8" description="Channel 8 Event Detection Interrupt Enable" />
-      <BitField start="25" size="1" name="EVD9" description="Channel 9 Event Detection Interrupt Enable" />
-      <BitField start="26" size="1" name="EVD10" description="Channel 10 Event Detection Interrupt Enable" />
-      <BitField start="27" size="1" name="EVD11" description="Channel 11 Event Detection Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="4" name="EVSYS_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR0" description="Channel 0 Overrun" />
-      <BitField start="1" size="1" name="OVR1" description="Channel 1 Overrun" />
-      <BitField start="2" size="1" name="OVR2" description="Channel 2 Overrun" />
-      <BitField start="3" size="1" name="OVR3" description="Channel 3 Overrun" />
-      <BitField start="4" size="1" name="OVR4" description="Channel 4 Overrun" />
-      <BitField start="5" size="1" name="OVR5" description="Channel 5 Overrun" />
-      <BitField start="6" size="1" name="OVR6" description="Channel 6 Overrun" />
-      <BitField start="7" size="1" name="OVR7" description="Channel 7 Overrun" />
-      <BitField start="8" size="1" name="EVD0" description="Channel 0 Event Detection" />
-      <BitField start="9" size="1" name="EVD1" description="Channel 1 Event Detection" />
-      <BitField start="10" size="1" name="EVD2" description="Channel 2 Event Detection" />
-      <BitField start="11" size="1" name="EVD3" description="Channel 3 Event Detection" />
-      <BitField start="12" size="1" name="EVD4" description="Channel 4 Event Detection" />
-      <BitField start="13" size="1" name="EVD5" description="Channel 5 Event Detection" />
-      <BitField start="14" size="1" name="EVD6" description="Channel 6 Event Detection" />
-      <BitField start="15" size="1" name="EVD7" description="Channel 7 Event Detection" />
-      <BitField start="16" size="1" name="OVR8" description="Channel 8 Overrun" />
-      <BitField start="17" size="1" name="OVR9" description="Channel 9 Overrun" />
-      <BitField start="18" size="1" name="OVR10" description="Channel 10 Overrun" />
-      <BitField start="19" size="1" name="OVR11" description="Channel 11 Overrun" />
-      <BitField start="24" size="1" name="EVD8" description="Channel 8 Event Detection" />
-      <BitField start="25" size="1" name="EVD9" description="Channel 9 Event Detection" />
-      <BitField start="26" size="1" name="EVD10" description="Channel 10 Event Detection" />
-      <BitField start="27" size="1" name="EVD11" description="Channel 11 Event Detection" />
-    </Register>
-    <Register start="+0x08" size="2" name="EVSYS_USER" access="Read/Write" description="User Multiplexer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="USER" description="User Multiplexer Selection" />
-      <BitField start="8" size="5" name="CHANNEL" description="Channel Event Selection">
-        <Enum name="0" start="0x0" description="No Channel Output Selected" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GCLK" start="0x40000C00" description="Generic Clock Generator">
-    <Register start="+0x2" size="2" name="GCLK_CLKCTRL" access="Read/Write" description="Generic Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ID" description="Generic Clock Selection ID">
-        <Enum name="DFLL48" start="0x0" description="DFLL48" />
-        <Enum name="FDPLL" start="0x1" description="FDPLL" />
-        <Enum name="FDPLL32K" start="0x2" description="FDPLL32K" />
-        <Enum name="WDT" start="0x3" description="WDT" />
-        <Enum name="RTC" start="0x4" description="RTC" />
-        <Enum name="EIC" start="0x5" description="EIC" />
-        <Enum name="USB" start="0x6" description="USB" />
-        <Enum name="EVSYS_0" start="0x7" description="EVSYS_0" />
-        <Enum name="EVSYS_1" start="0x8" description="EVSYS_1" />
-        <Enum name="EVSYS_2" start="0x9" description="EVSYS_2" />
-        <Enum name="EVSYS_3" start="0xa" description="EVSYS_3" />
-        <Enum name="EVSYS_4" start="0xb" description="EVSYS_4" />
-        <Enum name="EVSYS_5" start="0xc" description="EVSYS_5" />
-        <Enum name="EVSYS_6" start="0xd" description="EVSYS_6" />
-        <Enum name="EVSYS_7" start="0xe" description="EVSYS_7" />
-        <Enum name="EVSYS_8" start="0xf" description="EVSYS_8" />
-        <Enum name="EVSYS_9" start="0x10" description="EVSYS_9" />
-        <Enum name="EVSYS_10" start="0x11" description="EVSYS_10" />
-        <Enum name="EVSYS_11" start="0x12" description="EVSYS_11" />
-        <Enum name="SERCOMX_SLOW" start="0x13" description="SERCOMX_SLOW" />
-        <Enum name="SERCOM0_CORE" start="0x14" description="SERCOM0_CORE" />
-        <Enum name="SERCOM1_CORE" start="0x15" description="SERCOM1_CORE" />
-        <Enum name="SERCOM2_CORE" start="0x16" description="SERCOM2_CORE" />
-        <Enum name="SERCOM3_CORE" start="0x17" description="SERCOM3_CORE" />
-        <Enum name="SERCOM4_CORE" start="0x18" description="SERCOM4_CORE" />
-        <Enum name="SERCOM5_CORE" start="0x19" description="SERCOM5_CORE" />
-        <Enum name="TCC0_TCC1" start="0x1a" description="TCC0_TCC1" />
-        <Enum name="TCC2_TC3" start="0x1b" description="TCC2_TC3" />
-        <Enum name="TC4_TC5" start="0x1c" description="TC4_TC5" />
-        <Enum name="TC6_TC7" start="0x1d" description="TC6_TC7" />
-        <Enum name="ADC" start="0x1e" description="ADC" />
-        <Enum name="AC_DIG" start="0x1f" description="AC_DIG" />
-        <Enum name="AC_ANA" start="0x20" description="AC_ANA" />
-        <Enum name="DAC" start="0x21" description="DAC" />
-        <Enum name="PTC" start="0x22" description="PTC" />
-        <Enum name="I2S_0" start="0x23" description="I2S_0" />
-        <Enum name="I2S_1" start="0x24" description="I2S_1" />
-      </BitField>
-      <BitField start="8" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-      </BitField>
-      <BitField start="14" size="1" name="CLKEN" description="Clock Enable" />
-      <BitField start="15" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x0" size="1" name="GCLK_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-    </Register>
-    <Register start="+0x4" size="4" name="GCLK_GENCTRL" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Generic Clock Generator Selection" />
-      <BitField start="8" size="5" name="SRC" description="Source Select">
-        <Enum name="XOSC" start="0x0" description="XOSC oscillator output" />
-        <Enum name="GCLKIN" start="0x1" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x2" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x3" description="OSCULP32K oscillator output" />
-        <Enum name="OSC32K" start="0x4" description="OSC32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="OSC8M" start="0x6" description="OSC8M oscillator output" />
-        <Enum name="DFLL48M" start="0x7" description="DFLL48M output" />
-        <Enum name="FDPLL" start="0x8" description="FDPLL output" />
-      </BitField>
-      <BitField start="16" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="17" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="18" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="19" size="1" name="OE" description="Output Enable" />
-      <BitField start="20" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="21" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x8" size="4" name="GCLK_GENDIV" access="Read/Write" description="Generic Clock Generator Division" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Generic Clock Generator Selection" />
-      <BitField start="8" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x1" size="1" name="GCLK_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="HMATRIX" start="0x41007000" description="HSB Matrix">
-    <Register start="+0x080+0" size="4" name="HMATRIXB_PRAS0" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+8" size="4" name="HMATRIXB_PRAS1" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+16" size="4" name="HMATRIXB_PRAS2" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+24" size="4" name="HMATRIXB_PRAS3" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+32" size="4" name="HMATRIXB_PRAS4" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+40" size="4" name="HMATRIXB_PRAS5" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+48" size="4" name="HMATRIXB_PRAS6" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+56" size="4" name="HMATRIXB_PRAS7" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+64" size="4" name="HMATRIXB_PRAS8" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+72" size="4" name="HMATRIXB_PRAS9" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+80" size="4" name="HMATRIXB_PRAS10" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+88" size="4" name="HMATRIXB_PRAS11" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+96" size="4" name="HMATRIXB_PRAS12" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+104" size="4" name="HMATRIXB_PRAS13" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+112" size="4" name="HMATRIXB_PRAS14" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+120" size="4" name="HMATRIXB_PRAS15" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+0" size="4" name="HMATRIXB_PRBS0" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+8" size="4" name="HMATRIXB_PRBS1" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+16" size="4" name="HMATRIXB_PRBS2" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+24" size="4" name="HMATRIXB_PRBS3" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+32" size="4" name="HMATRIXB_PRBS4" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+40" size="4" name="HMATRIXB_PRBS5" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+48" size="4" name="HMATRIXB_PRBS6" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+56" size="4" name="HMATRIXB_PRBS7" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+64" size="4" name="HMATRIXB_PRBS8" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+72" size="4" name="HMATRIXB_PRBS9" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+80" size="4" name="HMATRIXB_PRBS10" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+88" size="4" name="HMATRIXB_PRBS11" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+96" size="4" name="HMATRIXB_PRBS12" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+104" size="4" name="HMATRIXB_PRBS13" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+112" size="4" name="HMATRIXB_PRBS14" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+120" size="4" name="HMATRIXB_PRBS15" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="HMATRIXB_SFR0" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+4" size="4" name="HMATRIXB_SFR1" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+8" size="4" name="HMATRIXB_SFR2" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+12" size="4" name="HMATRIXB_SFR3" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+16" size="4" name="HMATRIXB_SFR4" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+20" size="4" name="HMATRIXB_SFR5" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+24" size="4" name="HMATRIXB_SFR6" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+28" size="4" name="HMATRIXB_SFR7" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+32" size="4" name="HMATRIXB_SFR8" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+36" size="4" name="HMATRIXB_SFR9" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+40" size="4" name="HMATRIXB_SFR10" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+44" size="4" name="HMATRIXB_SFR11" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+48" size="4" name="HMATRIXB_SFR12" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+52" size="4" name="HMATRIXB_SFR13" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+56" size="4" name="HMATRIXB_SFR14" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+60" size="4" name="HMATRIXB_SFR15" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x42005000" description="Inter-IC Sound Interface">
-    <Register start="+0x04+0" size="4" name="I2S_CLKCTRL0" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="11" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="12" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="16" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="18" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="19" size="5" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="5" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-      <BitField start="29" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="30" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="31" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-    </Register>
-    <Register start="+0x04+4" size="4" name="I2S_CLKCTRL1" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="11" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="12" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="16" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="18" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="19" size="5" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="5" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-      <BitField start="29" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="30" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="31" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-    </Register>
-    <Register start="+0x00" size="1" name="I2S_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable" />
-      <BitField start="4" size="1" name="SEREN0" description="Serializer 0 Enable" />
-      <BitField start="5" size="1" name="SEREN1" description="Serializer 1 Enable" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="I2S_DATA0" access="Read/Write" description="Data n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="I2S_DATA1" access="Read/Write" description="Data n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-    <Register start="+0x0C" size="2" name="I2S_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="2" name="I2S_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="2" name="I2S_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="I2S_SERCTRL0" access="Read/Write" description="Serializer n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SERMODE" description="Serializer Mode">
-        <Enum name="RX" start="0x0" description="Receive" />
-        <Enum name="TX" start="0x1" description="Transmit" />
-        <Enum name="PDM2" start="0x2" description="Receive one PDM data on each serial clock edge" />
-      </BitField>
-      <BitField start="2" size="2" name="TXDEFAULT" description="Line Default Line when Slot Disabled">
-        <Enum name="ZERO" start="0x0" description="Output Default Value is 0" />
-        <Enum name="ONE" start="0x1" description="Output Default Value is 1" />
-        <Enum name="HIZ" start="0x3" description="Output Default Value is high impedance" />
-      </BitField>
-      <BitField start="4" size="1" name="TXSAME" description="Transmit Data when Underrun">
-        <Enum name="ZERO" start="0x0" description="Zero data transmitted in case of underrun" />
-        <Enum name="SAME" start="0x1" description="Last data transmitted in case of underrun" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Unit Selection">
-        <Enum name="CLK0" start="0x0" description="Use Clock Unit 0" />
-        <Enum name="CLK1" start="0x1" description="Use Clock Unit 1" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-      <BitField start="26" size="1" name="RXLOOP" description="Loop-back Test Mode" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="I2S_SERCTRL1" access="Read/Write" description="Serializer n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SERMODE" description="Serializer Mode">
-        <Enum name="RX" start="0x0" description="Receive" />
-        <Enum name="TX" start="0x1" description="Transmit" />
-        <Enum name="PDM2" start="0x2" description="Receive one PDM data on each serial clock edge" />
-      </BitField>
-      <BitField start="2" size="2" name="TXDEFAULT" description="Line Default Line when Slot Disabled">
-        <Enum name="ZERO" start="0x0" description="Output Default Value is 0" />
-        <Enum name="ONE" start="0x1" description="Output Default Value is 1" />
-        <Enum name="HIZ" start="0x3" description="Output Default Value is high impedance" />
-      </BitField>
-      <BitField start="4" size="1" name="TXSAME" description="Transmit Data when Underrun">
-        <Enum name="ZERO" start="0x0" description="Zero data transmitted in case of underrun" />
-        <Enum name="SAME" start="0x1" description="Last data transmitted in case of underrun" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Unit Selection">
-        <Enum name="CLK0" start="0x0" description="Use Clock Unit 0" />
-        <Enum name="CLK1" start="0x1" description="Use Clock Unit 1" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-      <BitField start="26" size="1" name="RXLOOP" description="Loop-back Test Mode" />
-    </Register>
-    <Register start="+0x18" size="2" name="I2S_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Status" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Status" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable Synchronization Status" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable Synchronization Status" />
-      <BitField start="4" size="1" name="SEREN0" description="Serializer 0 Enable Synchronization Status" />
-      <BitField start="5" size="1" name="SEREN1" description="Serializer 1 Enable Synchronization Status" />
-      <BitField start="8" size="1" name="DATA0" description="Data 0 Synchronization Status" />
-      <BitField start="9" size="1" name="DATA1" description="Data 1 Synchronization Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MTB" start="0x41006000" description="Cortex-M0+ Micro-Trace Buffer">
-    <Register start="+0xFB8" size="4" name="MTB_AUTHSTATUS" access="ReadOnly" description="MTB Authentication Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="MTB_BASE" access="ReadOnly" description="MTB Base" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFF0" size="4" name="MTB_CID0" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFF4" size="4" name="MTB_CID1" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFF8" size="4" name="MTB_CID2" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFFC" size="4" name="MTB_CID3" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFA4" size="4" name="MTB_CLAIMCLR" access="Read/Write" description="MTB Claim Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFA0" size="4" name="MTB_CLAIMSET" access="Read/Write" description="MTB Claim Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFBC" size="4" name="MTB_DEVARCH" access="ReadOnly" description="MTB Device Architecture" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFC8" size="4" name="MTB_DEVID" access="ReadOnly" description="MTB Device Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFCC" size="4" name="MTB_DEVTYPE" access="ReadOnly" description="MTB Device Type" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="MTB_FLOW" access="Read/Write" description="MTB Flow" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUTOSTOP" description="Auto Stop Tracing" />
-      <BitField start="1" size="1" name="AUTOHALT" description="Auto Halt Request" />
-      <BitField start="3" size="29" name="WATERMARK" description="Watermark value" />
-    </Register>
-    <Register start="+0xF00" size="4" name="MTB_ITCTRL" access="Read/Write" description="MTB Integration Mode Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFB0" size="4" name="MTB_LOCKACCESS" access="Read/Write" description="MTB Lock Access" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFB4" size="4" name="MTB_LOCKSTATUS" access="ReadOnly" description="MTB Lock Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="MTB_MASTER" access="Read/Write" description="MTB Master" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MASK" description="Maximum Value of the Trace Buffer in SRAM" />
-      <BitField start="5" size="1" name="TSTARTEN" description="Trace Start Input Enable" />
-      <BitField start="6" size="1" name="TSTOPEN" description="Trace Stop Input Enable" />
-      <BitField start="7" size="1" name="SFRWPRIV" description="Special Function Register Write Privilege" />
-      <BitField start="8" size="1" name="RAMPRIV" description="SRAM Privilege" />
-      <BitField start="9" size="1" name="HALTREQ" description="Halt Request" />
-      <BitField start="31" size="1" name="EN" description="Main Trace Enable" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="MTB_PID0" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFE4" size="4" name="MTB_PID1" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFE8" size="4" name="MTB_PID2" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFEC" size="4" name="MTB_PID3" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFD0" size="4" name="MTB_PID4" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFD4" size="4" name="MTB_PID5" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFD8" size="4" name="MTB_PID6" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFDC" size="4" name="MTB_PID7" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000" size="4" name="MTB_POSITION" access="Read/Write" description="MTB Position" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="WRAP" description="Pointer Value Wraps" />
-      <BitField start="3" size="29" name="POINTER" description="Trace Packet Location Pointer" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVMCTRL" start="0x41004000" description="Non-Volatile Memory Controller">
-    <Register start="+0x1C" size="4" name="NVMCTRL_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="ADDR" description="NVM Address" />
-    </Register>
-    <Register start="+0x00" size="2" name="NVMCTRL_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CMD" description="Command">
-        <Enum name="ER" start="0x2" description="Erase Row - Erases the row addressed by the ADDR register." />
-        <Enum name="WP" start="0x4" description="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." />
-        <Enum name="EAR" start="0x5" description="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." />
-        <Enum name="WAP" start="0x6" description="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." />
-        <Enum name="SF" start="0xa" description="Security Flow Command" />
-        <Enum name="WL" start="0xf" description="Write lockbits" />
-        <Enum name="LR" start="0x40" description="Lock Region - Locks the region containing the address location in the ADDR register." />
-        <Enum name="UR" start="0x41" description="Unlock Region - Unlocks the region containing the address location in the ADDR register." />
-        <Enum name="SPRM" start="0x42" description="Sets the power reduction mode." />
-        <Enum name="CPRM" start="0x43" description="Clears the power reduction mode." />
-        <Enum name="PBC" start="0x44" description="Page Buffer Clear - Clears the page buffer." />
-        <Enum name="SSB" start="0x45" description="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." />
-        <Enum name="INVALL" start="0x46" description="Invalidates all cache lines." />
-      </BitField>
-      <BitField start="8" size="8" name="CMDEX" description="Command Execution">
-        <Enum name="KEY" start="0xa5" description="Execution Key" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="NVMCTRL_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="4" name="RWS" description="NVM Read Wait States">
-        <Enum name="SINGLE" start="0x0" description="Single Auto Wait State" />
-        <Enum name="HALF" start="0x1" description="Half Auto Wait State" />
-        <Enum name="DUAL" start="0x2" description="Dual Auto Wait State" />
-      </BitField>
-      <BitField start="7" size="1" name="MANW" description="Manual Write" />
-      <BitField start="8" size="2" name="SLEEPPRM" description="Power Reduction Mode during Sleep">
-        <Enum name="WAKEONACCESS" start="0x0" description="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." />
-        <Enum name="WAKEUPINSTANT" start="0x1" description="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." />
-        <Enum name="DISABLED" start="0x3" description="Auto power reduction disabled." />
-      </BitField>
-      <BitField start="16" size="2" name="READMODE" description="NVMCTRL Read Mode">
-        <Enum name="NO_MISS_PENALTY" start="0x0" description="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." />
-        <Enum name="LOW_POWER" start="0x1" description="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." />
-        <Enum name="DETERMINISTIC" start="0x2" description="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." />
-      </BitField>
-      <BitField start="18" size="1" name="CACHEDIS" description="Cache Disable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="NVMCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVM Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="ERROR" description="Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="1" name="NVMCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVM Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="ERROR" description="Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="1" name="NVMCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVM Ready" />
-      <BitField start="1" size="1" name="ERROR" description="Error" />
-    </Register>
-    <Register start="+0x20" size="2" name="NVMCTRL_LOCK" access="Read/Write" description="Lock Section" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOCK" description="Region Lock Bits" />
-    </Register>
-    <Register start="+0x08" size="4" name="NVMCTRL_PARAM" access="Read/Write" description="NVM Parameter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NVMP" description="NVM Pages" />
-      <BitField start="16" size="3" name="PSZ" description="Page Size">
-        <Enum name="8" start="0x0" description="8 bytes" />
-        <Enum name="16" start="0x1" description="16 bytes" />
-        <Enum name="32" start="0x2" description="32 bytes" />
-        <Enum name="64" start="0x3" description="64 bytes" />
-        <Enum name="128" start="0x4" description="128 bytes" />
-        <Enum name="256" start="0x5" description="256 bytes" />
-        <Enum name="512" start="0x6" description="512 bytes" />
-        <Enum name="1024" start="0x7" description="1024 bytes" />
-      </BitField>
-    </Register>
-    <Register start="+0x18" size="2" name="NVMCTRL_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PRM" description="Power Reduction Mode" />
-      <BitField start="1" size="1" name="LOAD" description="NVM Page Buffer Active Loading" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error Status" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error Status" />
-      <BitField start="4" size="1" name="NVME" description="NVM Error" />
-      <BitField start="8" size="1" name="SB" description="Security Bit Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC0" start="0x40000000" description="Peripheral Access Controller 0">
-    <Register start="+0x0" size="4" name="PAC_WPCLR" access="Read/Write" description="Write Protection Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Clear" />
-    </Register>
-    <Register start="+0x4" size="4" name="PAC_WPSET" access="Read/Write" description="Write Protection Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Set" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC1" start="0x41000000" description="Peripheral Access Controller 1">
-    <Register start="+0x0" size="4" name="PAC_WPCLR" access="Read/Write" description="Write Protection Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Clear" />
-    </Register>
-    <Register start="+0x4" size="4" name="PAC_WPSET" access="Read/Write" description="Write Protection Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Set" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC2" start="0x42000000" description="Peripheral Access Controller 2">
-    <Register start="+0x0" size="4" name="PAC_WPCLR" access="Read/Write" description="Write Protection Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Clear" />
-    </Register>
-    <Register start="+0x4" size="4" name="PAC_WPSET" access="Read/Write" description="Write Protection Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Set" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PM" start="0x40000400" description="Power Manager">
-    <Register start="+0x14" size="4" name="PM_AHBMASK" access="Read/Write" description="AHB Mask" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HPB0_" description="HPB0 AHB Clock Mask" />
-      <BitField start="1" size="1" name="HPB1_" description="HPB1 AHB Clock Mask" />
-      <BitField start="2" size="1" name="HPB2_" description="HPB2 AHB Clock Mask" />
-      <BitField start="3" size="1" name="DSU_" description="DSU AHB Clock Mask" />
-      <BitField start="4" size="1" name="NVMCTRL_" description="NVMCTRL AHB Clock Mask" />
-      <BitField start="5" size="1" name="DMAC_" description="DMAC AHB Clock Mask" />
-      <BitField start="6" size="1" name="USB_" description="USB AHB Clock Mask" />
-    </Register>
-    <Register start="+0x18" size="4" name="PM_APBAMASK" access="Read/Write" description="APBA Mask" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC0_" description="PAC0 APB Clock Enable" />
-      <BitField start="1" size="1" name="PM_" description="PM APB Clock Enable" />
-      <BitField start="2" size="1" name="SYSCTRL_" description="SYSCTRL APB Clock Enable" />
-      <BitField start="3" size="1" name="GCLK_" description="GCLK APB Clock Enable" />
-      <BitField start="4" size="1" name="WDT_" description="WDT APB Clock Enable" />
-      <BitField start="5" size="1" name="RTC_" description="RTC APB Clock Enable" />
-      <BitField start="6" size="1" name="EIC_" description="EIC APB Clock Enable" />
-    </Register>
-    <Register start="+0x09" size="1" name="PM_APBASEL" access="Read/Write" description="APBA Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="APBADIV" description="APBA Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C" size="4" name="PM_APBBMASK" access="Read/Write" description="APBB Mask" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC1_" description="PAC1 APB Clock Enable" />
-      <BitField start="1" size="1" name="DSU_" description="DSU APB Clock Enable" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL APB Clock Enable" />
-      <BitField start="3" size="1" name="PORT_" description="PORT APB Clock Enable" />
-      <BitField start="4" size="1" name="DMAC_" description="DMAC APB Clock Enable" />
-      <BitField start="5" size="1" name="USB_" description="USB APB Clock Enable" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX APB Clock Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="PM_APBBSEL" access="Read/Write" description="APBB Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="APBBDIV" description="APBB Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x20" size="4" name="PM_APBCMASK" access="Read/Write" description="APBC Mask" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC2_" description="PAC2 APB Clock Enable" />
-      <BitField start="1" size="1" name="EVSYS_" description="EVSYS APB Clock Enable" />
-      <BitField start="2" size="1" name="SERCOM0_" description="SERCOM0 APB Clock Enable" />
-      <BitField start="3" size="1" name="SERCOM1_" description="SERCOM1 APB Clock Enable" />
-      <BitField start="4" size="1" name="SERCOM2_" description="SERCOM2 APB Clock Enable" />
-      <BitField start="5" size="1" name="SERCOM3_" description="SERCOM3 APB Clock Enable" />
-      <BitField start="6" size="1" name="SERCOM4_" description="SERCOM4 APB Clock Enable" />
-      <BitField start="7" size="1" name="SERCOM5_" description="SERCOM5 APB Clock Enable" />
-      <BitField start="8" size="1" name="TCC0_" description="TCC0 APB Clock Enable" />
-      <BitField start="9" size="1" name="TCC1_" description="TCC1 APB Clock Enable" />
-      <BitField start="10" size="1" name="TCC2_" description="TCC2 APB Clock Enable" />
-      <BitField start="11" size="1" name="TC3_" description="TC3 APB Clock Enable" />
-      <BitField start="12" size="1" name="TC4_" description="TC4 APB Clock Enable" />
-      <BitField start="13" size="1" name="TC5_" description="TC5 APB Clock Enable" />
-      <BitField start="16" size="1" name="ADC_" description="ADC APB Clock Enable" />
-      <BitField start="17" size="1" name="AC_" description="AC APB Clock Enable" />
-      <BitField start="18" size="1" name="DAC_" description="DAC APB Clock Enable" />
-      <BitField start="19" size="1" name="PTC_" description="PTC APB Clock Enable" />
-      <BitField start="20" size="1" name="I2S_" description="I2S APB Clock Enable" />
-    </Register>
-    <Register start="+0x0B" size="1" name="PM_APBCSEL" access="Read/Write" description="APBC Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="APBCDIV" description="APBC Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="1" name="PM_CPUSEL" access="Read/Write" description="CPU Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CPUDIV" description="CPU Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x00" size="1" name="PM_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x34" size="1" name="PM_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x35" size="1" name="PM_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x36" size="1" name="PM_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready" />
-    </Register>
-    <Register start="+0x38" size="1" name="PM_RCAUSE" access="ReadOnly" description="Reset Cause" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POR" description="Power On Reset" />
-      <BitField start="1" size="1" name="BOD12" description="Brown Out 12 Detector Reset" />
-      <BitField start="2" size="1" name="BOD33" description="Brown Out 33 Detector Reset" />
-      <BitField start="4" size="1" name="EXT" description="External Reset" />
-      <BitField start="5" size="1" name="WDT" description="Watchdog Reset" />
-      <BitField start="6" size="1" name="SYST" description="System Reset Request" />
-    </Register>
-    <Register start="+0x01" size="1" name="PM_SLEEP" access="Read/Write" description="Sleep Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IDLE" description="Idle Mode Configuration">
-        <Enum name="CPU" start="0x0" description="The CPU clock domain is stopped" />
-        <Enum name="AHB" start="0x1" description="The CPU and AHB clock domains are stopped" />
-        <Enum name="APB" start="0x2" description="The CPU, AHB and APB clock domains are stopped" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PORT" start="0x41004400" description="Port Module">
-    <Register start="+0x24+0" size="4" name="PORT_CTRL0" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x24+128" size="4" name="PORT_CTRL1" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x00+0" size="4" name="PORT_DIR0" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x00+128" size="4" name="PORT_DIR1" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x04+0" size="4" name="PORT_DIRCLR0" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x04+128" size="4" name="PORT_DIRCLR1" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x08+0" size="4" name="PORT_DIRSET0" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x08+128" size="4" name="PORT_DIRSET1" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x0C+0" size="4" name="PORT_DIRTGL0" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x0C+128" size="4" name="PORT_DIRTGL1" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="PORT_IN0" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="Port Data Input Value" />
-    </Register>
-    <Register start="+0x20+128" size="4" name="PORT_IN1" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="Port Data Input Value" />
-    </Register>
-    <Register start="+0x10+0" size="4" name="PORT_OUT0" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="Port Data Output Value" />
-    </Register>
-    <Register start="+0x10+128" size="4" name="PORT_OUT1" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="Port Data Output Value" />
-    </Register>
-    <Register start="+0x14+0" size="4" name="PORT_OUTCLR0" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="Port Data Output Value Clear" />
-    </Register>
-    <Register start="+0x14+128" size="4" name="PORT_OUTCLR1" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="Port Data Output Value Clear" />
-    </Register>
-    <Register start="+0x18+0" size="4" name="PORT_OUTSET0" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="Port Data Output Value Set" />
-    </Register>
-    <Register start="+0x18+128" size="4" name="PORT_OUTSET1" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="Port Data Output Value Set" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="PORT_OUTTGL0" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="Port Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x1C+128" size="4" name="PORT_OUTTGL1" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="Port Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x40+0" size="1" name="PORT_PINCFG0_0" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+1" size="1" name="PORT_PINCFG0_1" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+2" size="1" name="PORT_PINCFG0_2" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+3" size="1" name="PORT_PINCFG0_3" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+4" size="1" name="PORT_PINCFG0_4" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+5" size="1" name="PORT_PINCFG0_5" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+6" size="1" name="PORT_PINCFG0_6" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+7" size="1" name="PORT_PINCFG0_7" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+8" size="1" name="PORT_PINCFG0_8" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+9" size="1" name="PORT_PINCFG0_9" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+10" size="1" name="PORT_PINCFG0_10" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+11" size="1" name="PORT_PINCFG0_11" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+12" size="1" name="PORT_PINCFG0_12" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+13" size="1" name="PORT_PINCFG0_13" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+14" size="1" name="PORT_PINCFG0_14" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+15" size="1" name="PORT_PINCFG0_15" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+16" size="1" name="PORT_PINCFG0_16" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+17" size="1" name="PORT_PINCFG0_17" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+18" size="1" name="PORT_PINCFG0_18" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+19" size="1" name="PORT_PINCFG0_19" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+20" size="1" name="PORT_PINCFG0_20" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+21" size="1" name="PORT_PINCFG0_21" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+22" size="1" name="PORT_PINCFG0_22" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+23" size="1" name="PORT_PINCFG0_23" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+24" size="1" name="PORT_PINCFG0_24" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+25" size="1" name="PORT_PINCFG0_25" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+26" size="1" name="PORT_PINCFG0_26" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+27" size="1" name="PORT_PINCFG0_27" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+28" size="1" name="PORT_PINCFG0_28" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+29" size="1" name="PORT_PINCFG0_29" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+30" size="1" name="PORT_PINCFG0_30" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+31" size="1" name="PORT_PINCFG0_31" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+0" size="1" name="PORT_PINCFG1_0" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+1" size="1" name="PORT_PINCFG1_1" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+2" size="1" name="PORT_PINCFG1_2" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+3" size="1" name="PORT_PINCFG1_3" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+4" size="1" name="PORT_PINCFG1_4" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+5" size="1" name="PORT_PINCFG1_5" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+6" size="1" name="PORT_PINCFG1_6" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+7" size="1" name="PORT_PINCFG1_7" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+8" size="1" name="PORT_PINCFG1_8" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+9" size="1" name="PORT_PINCFG1_9" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+10" size="1" name="PORT_PINCFG1_10" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+11" size="1" name="PORT_PINCFG1_11" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+12" size="1" name="PORT_PINCFG1_12" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+13" size="1" name="PORT_PINCFG1_13" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+14" size="1" name="PORT_PINCFG1_14" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+15" size="1" name="PORT_PINCFG1_15" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+16" size="1" name="PORT_PINCFG1_16" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+17" size="1" name="PORT_PINCFG1_17" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+18" size="1" name="PORT_PINCFG1_18" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+19" size="1" name="PORT_PINCFG1_19" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+20" size="1" name="PORT_PINCFG1_20" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+21" size="1" name="PORT_PINCFG1_21" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+22" size="1" name="PORT_PINCFG1_22" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+23" size="1" name="PORT_PINCFG1_23" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+24" size="1" name="PORT_PINCFG1_24" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+25" size="1" name="PORT_PINCFG1_25" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+26" size="1" name="PORT_PINCFG1_26" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+27" size="1" name="PORT_PINCFG1_27" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+28" size="1" name="PORT_PINCFG1_28" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+29" size="1" name="PORT_PINCFG1_29" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+30" size="1" name="PORT_PINCFG1_30" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+31" size="1" name="PORT_PINCFG1_31" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="PORT_PMUX0_0" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+1" size="1" name="PORT_PMUX0_1" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+2" size="1" name="PORT_PMUX0_2" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+3" size="1" name="PORT_PMUX0_3" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+4" size="1" name="PORT_PMUX0_4" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+5" size="1" name="PORT_PMUX0_5" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+6" size="1" name="PORT_PMUX0_6" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+7" size="1" name="PORT_PMUX0_7" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+8" size="1" name="PORT_PMUX0_8" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+9" size="1" name="PORT_PMUX0_9" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+10" size="1" name="PORT_PMUX0_10" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+11" size="1" name="PORT_PMUX0_11" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+12" size="1" name="PORT_PMUX0_12" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+13" size="1" name="PORT_PMUX0_13" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+14" size="1" name="PORT_PMUX0_14" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+15" size="1" name="PORT_PMUX0_15" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+0" size="1" name="PORT_PMUX1_0" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+1" size="1" name="PORT_PMUX1_1" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+2" size="1" name="PORT_PMUX1_2" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+3" size="1" name="PORT_PMUX1_3" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+4" size="1" name="PORT_PMUX1_4" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+5" size="1" name="PORT_PMUX1_5" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+6" size="1" name="PORT_PMUX1_6" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+7" size="1" name="PORT_PMUX1_7" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+8" size="1" name="PORT_PMUX1_8" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+9" size="1" name="PORT_PMUX1_9" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+10" size="1" name="PORT_PMUX1_10" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+11" size="1" name="PORT_PMUX1_11" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+12" size="1" name="PORT_PMUX1_12" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+13" size="1" name="PORT_PMUX1_13" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+14" size="1" name="PORT_PMUX1_14" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+15" size="1" name="PORT_PMUX1_15" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x28+0" size="4" name="PORT_WRCONFIG0" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-    <Register start="+0x28+128" size="4" name="PORT_WRCONFIG1" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE0)" start="0x40001400" description="Real-Time Counter">
-    <Register start="+0x18+0" size="4" name="RTC_COMP0" access="Read/Write" description="MODE0 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_COUNT" access="Read/Write" description="MODE0 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="RTC_CTRL" access="Read/Write" description="MODE0 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x0B" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x04" size="2" name="RTC_EVCTRL" access="Read/Write" description="MODE0 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x06" size="1" name="RTC_INTENCLR" access="Read/Write" description="MODE0 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="RTC_INTENSET" access="Read/Write" description="MODE0 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="RTC_INTFLAG" access="Read/Write" description="MODE0 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="7" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_READREQ" access="Read/Write" description="Read Request" reset_value="0x0010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0A" size="1" name="RTC_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE1)" start="0x40001400" description="Real-Time Counter">
-    <Register start="+0x18+0" size="2" name="RTC_COMP0" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="RTC_COMP1" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="RTC_COUNT" access="Read/Write" description="MODE1 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="RTC_CTRL" access="Read/Write" description="MODE1 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x0B" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x04" size="2" name="RTC_EVCTRL" access="Read/Write" description="MODE1 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="9" size="1" name="CMPEO1" description="Compare 1 Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x06" size="1" name="RTC_INTENCLR" access="Read/Write" description="MODE1 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="RTC_INTENSET" access="Read/Write" description="MODE1 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="RTC_INTFLAG" access="Read/Write" description="MODE1 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="1" size="1" name="CMP1" description="Compare 1" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="7" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x14" size="2" name="RTC_PER" access="Read/Write" description="MODE1 Counter Period" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PER" description="Counter Period" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_READREQ" access="Read/Write" description="Read Request" reset_value="0x0010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0A" size="1" name="RTC_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE2)" start="0x40001400" description="Real-Time Counter">
-    <Register start="+0x18+0" size="4" name="RTC_ALARM0" access="Read/Write" description="MODE2 Alarm n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour" />
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_CLOCK" access="Read/Write" description="MODE2 Clock Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="PM" start="0x10" description="Afternoon Hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x00" size="2" name="RTC_CTRL" access="Read/Write" description="MODE2 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="6" size="1" name="CLKREP" description="Clock Representation" />
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x0B" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x04" size="2" name="RTC_EVCTRL" access="Read/Write" description="MODE2 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="ALARMEO0" description="Alarm 0 Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x06" size="1" name="RTC_INTENCLR" access="Read/Write" description="MODE2 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="RTC_INTENSET" access="Read/Write" description="MODE2 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="RTC_INTFLAG" access="Read/Write" description="MODE2 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALARM0" description="Alarm 0" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="7" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="RTC_MASK0" access="Read/Write" description="MODE2 Alarm n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SEL" description="Alarm Mask Selection">
-        <Enum name="OFF" start="0x0" description="Alarm Disabled" />
-        <Enum name="SS" start="0x1" description="Match seconds only" />
-        <Enum name="MMSS" start="0x2" description="Match seconds and minutes only" />
-        <Enum name="HHMMSS" start="0x3" description="Match seconds, minutes, and hours only" />
-        <Enum name="DDHHMMSS" start="0x4" description="Match seconds, minutes, hours, and days only" />
-        <Enum name="MMDDHHMMSS" start="0x5" description="Match seconds, minutes, hours, days, and months only" />
-        <Enum name="YYMMDDHHMMSS" start="0x6" description="Match seconds, minutes, hours, days, months, and years" />
-      </BitField>
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_READREQ" access="Read/Write" description="Read Request" reset_value="0x0010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0A" size="1" name="RTC_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CM)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CS)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (SPI)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (USART)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CM)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CS)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (SPI)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (USART)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CM)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CS)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (SPI)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (USART)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CM)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CS)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (SPI)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (USART)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CM)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CS)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (SPI)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (USART)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CM)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CS)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (SPI)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (USART)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCTRL" start="0x40000800" description="System Control">
-    <Register start="+0x34" size="4" name="SYSCTRL_BOD33" access="Read/Write" description="3.3V Brown-Out Detector (BOD33) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="HYST" description="Hysteresis" />
-      <BitField start="3" size="2" name="ACTION" description="BOD33 Action">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RESET" start="0x1" description="The BOD33 generates a reset" />
-        <Enum name="INTERRUPT" start="0x2" description="The BOD33 generates an interrupt" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="1" name="MODE" description="Operation Mode" />
-      <BitField start="9" size="1" name="CEN" description="Clock Enable" />
-      <BitField start="12" size="4" name="PSEL" description="Prescaler Select">
-        <Enum name="DIV2" start="0x0" description="Divide clock by 2" />
-        <Enum name="DIV4" start="0x1" description="Divide clock by 4" />
-        <Enum name="DIV8" start="0x2" description="Divide clock by 8" />
-        <Enum name="DIV16" start="0x3" description="Divide clock by 16" />
-        <Enum name="DIV32" start="0x4" description="Divide clock by 32" />
-        <Enum name="DIV64" start="0x5" description="Divide clock by 64" />
-        <Enum name="DIV128" start="0x6" description="Divide clock by 128" />
-        <Enum name="DIV256" start="0x7" description="Divide clock by 256" />
-        <Enum name="DIV512" start="0x8" description="Divide clock by 512" />
-        <Enum name="DIV1K" start="0x9" description="Divide clock by 1024" />
-        <Enum name="DIV2K" start="0xa" description="Divide clock by 2048" />
-        <Enum name="DIV4K" start="0xb" description="Divide clock by 4096" />
-        <Enum name="DIV8K" start="0xc" description="Divide clock by 8192" />
-        <Enum name="DIV16K" start="0xd" description="Divide clock by 16384" />
-        <Enum name="DIV32K" start="0xe" description="Divide clock by 32768" />
-        <Enum name="DIV64K" start="0xf" description="Divide clock by 65536" />
-      </BitField>
-      <BitField start="16" size="6" name="LEVEL" description="BOD33 Threshold Level" />
-    </Register>
-    <Register start="+0x24" size="2" name="SYSCTRL_DFLLCTRL" access="Read/Write" description="DFLL48M Control" reset_value="0x0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DFLL Enable" />
-      <BitField start="2" size="1" name="MODE" description="Operating Mode Selection" />
-      <BitField start="3" size="1" name="STABLE" description="Stable DFLL Frequency" />
-      <BitField start="4" size="1" name="LLAW" description="Lose Lock After Wake" />
-      <BitField start="5" size="1" name="USBCRM" description="USB Clock Recovery Mode" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="1" name="CCDIS" description="Chill Cycle Disable" />
-      <BitField start="9" size="1" name="QLDIS" description="Quick Lock Disable" />
-      <BitField start="10" size="1" name="BPLCKC" description="Bypass Coarse Lock" />
-      <BitField start="11" size="1" name="WAITLOCK" description="Wait Lock" />
-    </Register>
-    <Register start="+0x2C" size="4" name="SYSCTRL_DFLLMUL" access="Read/Write" description="DFLL48M Multiplier" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MUL" description="DFLL Multiply Factor" />
-      <BitField start="16" size="10" name="FSTEP" description="Fine Maximum Step" />
-      <BitField start="26" size="6" name="CSTEP" description="Coarse Maximum Step" />
-    </Register>
-    <Register start="+0x30" size="1" name="SYSCTRL_DFLLSYNC" access="Read/Write" description="DFLL48M Synchronization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="READREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x28" size="4" name="SYSCTRL_DFLLVAL" access="Read/Write" description="DFLL48M Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="FINE" description="Fine Value" />
-      <BitField start="10" size="6" name="COARSE" description="Coarse Value" />
-      <BitField start="16" size="16" name="DIFF" description="Multiplication Ratio Difference" />
-    </Register>
-    <Register start="+0x44" size="1" name="SYSCTRL_DPLLCTRLA" access="Read/Write" description="DPLL Control A" reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Clock Activation" />
-    </Register>
-    <Register start="+0x4C" size="4" name="SYSCTRL_DPLLCTRLB" access="Read/Write" description="DPLL Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="FILTER" description="Proportional Integral Filter Selection">
-        <Enum name="DEFAULT" start="0x0" description="Default filter mode" />
-        <Enum name="LBFILT" start="0x1" description="Low bandwidth filter" />
-        <Enum name="HBFILT" start="0x2" description="High bandwidth filter" />
-        <Enum name="HDFILT" start="0x3" description="High damping filter" />
-      </BitField>
-      <BitField start="2" size="1" name="LPEN" description="Low-Power Enable" />
-      <BitField start="3" size="1" name="WUF" description="Wake Up Fast" />
-      <BitField start="4" size="2" name="REFCLK" description="Reference Clock Selection">
-        <Enum name="REF0" start="0x0" description="CLK_DPLL_REF0 clock reference" />
-        <Enum name="REF1" start="0x1" description="CLK_DPLL_REF1 clock reference" />
-        <Enum name="GCLK" start="0x2" description="GCLK_DPLL clock reference" />
-      </BitField>
-      <BitField start="8" size="3" name="LTIME" description="Lock Time">
-        <Enum name="DEFAULT" start="0x0" description="No time-out" />
-        <Enum name="8MS" start="0x4" description="Time-out if no lock within 8 ms" />
-        <Enum name="9MS" start="0x5" description="Time-out if no lock within 9 ms" />
-        <Enum name="10MS" start="0x6" description="Time-out if no lock within 10 ms" />
-        <Enum name="11MS" start="0x7" description="Time-out if no lock within 11 ms" />
-      </BitField>
-      <BitField start="12" size="1" name="LBYPASS" description="Lock Bypass" />
-      <BitField start="16" size="11" name="DIV" description="Clock Divider" />
-    </Register>
-    <Register start="+0x48" size="4" name="SYSCTRL_DPLLRATIO" access="Read/Write" description="DPLL Ratio Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="LDR" description="Loop Divider Ratio" />
-      <BitField start="16" size="4" name="LDRFRAC" description="Loop Divider Ratio Fractional Part" />
-    </Register>
-    <Register start="+0x50" size="1" name="SYSCTRL_DPLLSTATUS" access="ReadOnly" description="DPLL Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="DPLL Lock Status" />
-      <BitField start="1" size="1" name="CLKRDY" description="Output Clock Ready" />
-      <BitField start="2" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="3" size="1" name="DIV" description="Divider Enable" />
-    </Register>
-    <Register start="+0x00" size="4" name="SYSCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready Interrupt Enable" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready Interrupt Enable" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready Interrupt Enable" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout Interrupt Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SYSCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready Interrupt Enable" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready Interrupt Enable" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready Interrupt Enable" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SYSCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout" />
-    </Register>
-    <Register start="+0x18" size="4" name="SYSCTRL_OSC32K" access="Read/Write" description="32kHz Internal Oscillator (OSC32K) Control" reset_value="0x003F0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="EN32K" description="32kHz Output Enable" />
-      <BitField start="3" size="1" name="EN1K" description="1kHz Output Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="STARTUP" description="Oscillator Start-Up Time" />
-      <BitField start="12" size="1" name="WRTLOCK" description="Write Lock" />
-      <BitField start="16" size="7" name="CALIB" description="Oscillator Calibration" />
-    </Register>
-    <Register start="+0x20" size="4" name="SYSCTRL_OSC8M" access="Read/Write" description="8MHz Internal Oscillator (OSC8M) Control" reset_value="0x87070382" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="2" name="PRESC" description="Oscillator Prescaler">
-        <Enum name="0" start="0x0" description="1" />
-        <Enum name="1" start="0x1" description="2" />
-        <Enum name="2" start="0x2" description="4" />
-        <Enum name="3" start="0x3" description="8" />
-      </BitField>
-      <BitField start="16" size="12" name="CALIB" description="Oscillator Calibration" />
-      <BitField start="30" size="2" name="FRANGE" description="Oscillator Frequency Range">
-        <Enum name="0" start="0x0" description="4 to 6MHz" />
-        <Enum name="1" start="0x1" description="6 to 8MHz" />
-        <Enum name="2" start="0x2" description="8 to 11MHz" />
-        <Enum name="3" start="0x3" description="11 to 15MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C" size="1" name="SYSCTRL_OSCULP32K" access="Read/Write" description="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control" reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="CALIB" description="Oscillator Calibration" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SYSCTRL_PCLKSR" access="ReadOnly" description="Power and Clocks Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout" />
-    </Register>
-    <Register start="+0x40" size="4" name="SYSCTRL_VREF" access="Read/Write" description="Voltage References System (VREF) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="TSEN" description="Temperature Sensor Enable" />
-      <BitField start="2" size="1" name="BGOUTEN" description="Bandgap Output Enable" />
-      <BitField start="16" size="11" name="CALIB" description="Bandgap Voltage Generator Calibration" />
-    </Register>
-    <Register start="+0x3C" size="2" name="SYSCTRL_VREG" access="Read/Write" description="Voltage Regulator System (VREG) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="13" size="1" name="FORCELDO" description="Force LDO Voltage Regulator" />
-    </Register>
-    <Register start="+0x10" size="2" name="SYSCTRL_XOSC" access="Read/Write" description="External Multipurpose Crystal Oscillator (XOSC) Control" reset_value="0x0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="GAIN" description="Oscillator Gain">
-        <Enum name="0" start="0x0" description="2MHz" />
-        <Enum name="1" start="0x1" description="4MHz" />
-        <Enum name="2" start="0x2" description="8MHz" />
-        <Enum name="3" start="0x3" description="16MHz" />
-        <Enum name="4" start="0x4" description="30MHz" />
-      </BitField>
-      <BitField start="11" size="1" name="AMPGC" description="Automatic Amplitude Gain Control" />
-      <BitField start="12" size="4" name="STARTUP" description="Start-Up Time" />
-    </Register>
-    <Register start="+0x14" size="2" name="SYSCTRL_XOSC32K" access="Read/Write" description="32kHz External Crystal Oscillator (XOSC32K) Control" reset_value="0x0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="3" size="1" name="EN32K" description="32kHz Output Enable" />
-      <BitField start="4" size="1" name="EN1K" description="1kHz Output Enable" />
-      <BitField start="5" size="1" name="AAMPEN" description="Automatic Amplitude Control Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="STARTUP" description="Oscillator Start-Up Time" />
-      <BitField start="12" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT8)" start="0x42002C00" description="Basic Timer Counter 3">
-    <Register start="+0x18+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period Value" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT16)" start="0x42002C00" description="Basic Timer Counter 3">
-    <Register start="+0x18+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT32)" start="0x42002C00" description="Basic Timer Counter 3">
-    <Register start="+0x18+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT8)" start="0x42003000" description="Basic Timer Counter 4">
-    <Register start="+0x18+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period Value" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT16)" start="0x42003000" description="Basic Timer Counter 4">
-    <Register start="+0x18+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT32)" start="0x42003000" description="Basic Timer Counter 4">
-    <Register start="+0x18+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT8)" start="0x42003400" description="Basic Timer Counter 5">
-    <Register start="+0x18+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period Value" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT16)" start="0x42003400" description="Basic Timer Counter 5">
-    <Register start="+0x18+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT32)" start="0x42003400" description="Basic Timer Counter 5">
-    <Register start="+0x18+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC0" start="0x42002000" description="Timer Counter Control 0">
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTB" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBV" description="Pattern Buffer Valid" />
-      <BitField start="6" size="1" name="WAVEBV" description="Wave Buffer Valid" />
-      <BitField start="7" size="1" name="PERBV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="16" size="1" name="PATTB" description="Pattern Buffer Busy" />
-      <BitField start="17" size="1" name="WAVEB" description="Wave Buffer Busy" />
-      <BitField start="18" size="1" name="PERB" description="Period Buffer Busy" />
-      <BitField start="19" size="1" name="CCB0" description="Compare Channel Buffer 0 Busy" />
-      <BitField start="20" size="1" name="CCB1" description="Compare Channel Buffer 1 Busy" />
-      <BitField start="21" size="1" name="CCB2" description="Compare Channel Buffer 2 Busy" />
-      <BitField start="22" size="1" name="CCB3" description="Compare Channel Buffer 3 Busy" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x68" size="4" name="TCC_WAVEB" access="Read/Write" description="Waveform Control Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGENB" description="Waveform Generation Buffer">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMPB" description="Ramp Mode Buffer">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPERENB" description="Circular Period Enable Buffer" />
-      <BitField start="8" size="1" name="CICCENB0" description="Circular Channel 0 Enable Buffer" />
-      <BitField start="9" size="1" name="CICCENB1" description="Circular Channel 1 Enable Buffer" />
-      <BitField start="10" size="1" name="CICCENB2" description="Circular Channel 2 Enable Buffer" />
-      <BitField start="11" size="1" name="CICCENB3" description="Circular Channel 3 Enable Buffer" />
-      <BitField start="16" size="1" name="POLB0" description="Channel 0 Polarity Buffer" />
-      <BitField start="17" size="1" name="POLB1" description="Channel 1 Polarity Buffer" />
-      <BitField start="18" size="1" name="POLB2" description="Channel 2 Polarity Buffer" />
-      <BitField start="19" size="1" name="POLB3" description="Channel 3 Polarity Buffer" />
-      <BitField start="24" size="1" name="SWAPB0" description="Swap DTI Output Pair 0 Buffer" />
-      <BitField start="25" size="1" name="SWAPB1" description="Swap DTI Output Pair 1 Buffer" />
-      <BitField start="26" size="1" name="SWAPB2" description="Swap DTI Output Pair 2 Buffer" />
-      <BitField start="27" size="1" name="SWAPB3" description="Swap DTI Output Pair 3 Buffer" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC1" start="0x42002400" description="Timer Counter Control 1">
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTB" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBV" description="Pattern Buffer Valid" />
-      <BitField start="6" size="1" name="WAVEBV" description="Wave Buffer Valid" />
-      <BitField start="7" size="1" name="PERBV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="16" size="1" name="PATTB" description="Pattern Buffer Busy" />
-      <BitField start="17" size="1" name="WAVEB" description="Wave Buffer Busy" />
-      <BitField start="18" size="1" name="PERB" description="Period Buffer Busy" />
-      <BitField start="19" size="1" name="CCB0" description="Compare Channel Buffer 0 Busy" />
-      <BitField start="20" size="1" name="CCB1" description="Compare Channel Buffer 1 Busy" />
-      <BitField start="21" size="1" name="CCB2" description="Compare Channel Buffer 2 Busy" />
-      <BitField start="22" size="1" name="CCB3" description="Compare Channel Buffer 3 Busy" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x68" size="4" name="TCC_WAVEB" access="Read/Write" description="Waveform Control Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGENB" description="Waveform Generation Buffer">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMPB" description="Ramp Mode Buffer">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPERENB" description="Circular Period Enable Buffer" />
-      <BitField start="8" size="1" name="CICCENB0" description="Circular Channel 0 Enable Buffer" />
-      <BitField start="9" size="1" name="CICCENB1" description="Circular Channel 1 Enable Buffer" />
-      <BitField start="10" size="1" name="CICCENB2" description="Circular Channel 2 Enable Buffer" />
-      <BitField start="11" size="1" name="CICCENB3" description="Circular Channel 3 Enable Buffer" />
-      <BitField start="16" size="1" name="POLB0" description="Channel 0 Polarity Buffer" />
-      <BitField start="17" size="1" name="POLB1" description="Channel 1 Polarity Buffer" />
-      <BitField start="18" size="1" name="POLB2" description="Channel 2 Polarity Buffer" />
-      <BitField start="19" size="1" name="POLB3" description="Channel 3 Polarity Buffer" />
-      <BitField start="24" size="1" name="SWAPB0" description="Swap DTI Output Pair 0 Buffer" />
-      <BitField start="25" size="1" name="SWAPB1" description="Swap DTI Output Pair 1 Buffer" />
-      <BitField start="26" size="1" name="SWAPB2" description="Swap DTI Output Pair 2 Buffer" />
-      <BitField start="27" size="1" name="SWAPB3" description="Swap DTI Output Pair 3 Buffer" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC2" start="0x42002800" description="Timer Counter Control 2">
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTB" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBV" description="Pattern Buffer Valid" />
-      <BitField start="6" size="1" name="WAVEBV" description="Wave Buffer Valid" />
-      <BitField start="7" size="1" name="PERBV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="16" size="1" name="PATTB" description="Pattern Buffer Busy" />
-      <BitField start="17" size="1" name="WAVEB" description="Wave Buffer Busy" />
-      <BitField start="18" size="1" name="PERB" description="Period Buffer Busy" />
-      <BitField start="19" size="1" name="CCB0" description="Compare Channel Buffer 0 Busy" />
-      <BitField start="20" size="1" name="CCB1" description="Compare Channel Buffer 1 Busy" />
-      <BitField start="21" size="1" name="CCB2" description="Compare Channel Buffer 2 Busy" />
-      <BitField start="22" size="1" name="CCB3" description="Compare Channel Buffer 3 Busy" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x68" size="4" name="TCC_WAVEB" access="Read/Write" description="Waveform Control Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGENB" description="Waveform Generation Buffer">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMPB" description="Ramp Mode Buffer">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPERENB" description="Circular Period Enable Buffer" />
-      <BitField start="8" size="1" name="CICCENB0" description="Circular Channel 0 Enable Buffer" />
-      <BitField start="9" size="1" name="CICCENB1" description="Circular Channel 1 Enable Buffer" />
-      <BitField start="10" size="1" name="CICCENB2" description="Circular Channel 2 Enable Buffer" />
-      <BitField start="11" size="1" name="CICCENB3" description="Circular Channel 3 Enable Buffer" />
-      <BitField start="16" size="1" name="POLB0" description="Channel 0 Polarity Buffer" />
-      <BitField start="17" size="1" name="POLB1" description="Channel 1 Polarity Buffer" />
-      <BitField start="18" size="1" name="POLB2" description="Channel 2 Polarity Buffer" />
-      <BitField start="19" size="1" name="POLB3" description="Channel 3 Polarity Buffer" />
-      <BitField start="24" size="1" name="SWAPB0" description="Swap DTI Output Pair 0 Buffer" />
-      <BitField start="25" size="1" name="SWAPB1" description="Swap DTI Output Pair 1 Buffer" />
-      <BitField start="26" size="1" name="SWAPB2" description="Swap DTI Output Pair 2 Buffer" />
-      <BitField start="27" size="1" name="SWAPB3" description="Swap DTI Output Pair 3 Buffer" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (DEVICE)" start="0x41005000" description="Universal Serial Bus">
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="DEVICE Control B" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETACH" description="Detach" />
-      <BitField start="1" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration">
-        <Enum name="FS" start="0x0" description="FS : Full Speed" />
-        <Enum name="LS" start="0x1" description="LS : Low Speed" />
-        <Enum name="HS" start="0x2" description="HS : High Speed capable" />
-        <Enum name="HSTM" start="0x3" description="HSTM: High Speed Test Mode (force high-speed mode for test mode)" />
-      </BitField>
-      <BitField start="4" size="1" name="NREPLY" description="No Reply" />
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="7" size="1" name="TSTPCKT" description="Test packet mode" />
-      <BitField start="8" size="1" name="OPMODE2" description="Specific Operational Mode" />
-      <BitField start="9" size="1" name="GNAK" description="Global NAK" />
-      <BitField start="10" size="2" name="LPMHDSK" description="Link Power Management Handshake">
-        <Enum name="NO" start="0x0" description="No handshake. LPM is not supported" />
-        <Enum name="ACK" start="0x1" description="ACK" />
-        <Enum name="NYET" start="0x2" description="NYET" />
-        <Enum name="STALL" start="0x3" description="STALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_DADD" access="Read/Write" description="DEVICE Device Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DADD" description="Device Address" />
-      <BitField start="7" size="1" name="ADDEN" description="Device Address Enable" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_EPCFG0" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_EPCFG1" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_EPCFG2" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_EPCFG3" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_EPCFG4" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_EPCFG5" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_EPCFG6" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_EPCFG7" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_EPINTENCLR0" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_EPINTENCLR1" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_EPINTENCLR2" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_EPINTENCLR3" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_EPINTENCLR4" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_EPINTENCLR5" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_EPINTENCLR6" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_EPINTENCLR7" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_EPINTENSET0" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_EPINTENSET1" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_EPINTENSET2" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_EPINTENSET3" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_EPINTENSET4" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_EPINTENSET5" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_EPINTENSET6" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_EPINTENSET7" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_EPINTFLAG0" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_EPINTFLAG1" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_EPINTFLAG2" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_EPINTFLAG3" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_EPINTFLAG4" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_EPINTFLAG5" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_EPINTFLAG6" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_EPINTFLAG7" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_EPINTSMRY" access="ReadOnly" description="DEVICE End Point Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="End Point 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="End Point 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="End Point 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="End Point 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="End Point 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="End Point 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="End Point 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="End Point 7 Interrupt" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_EPSTATUS0" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_EPSTATUS1" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_EPSTATUS2" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_EPSTATUS3" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_EPSTATUS4" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_EPSTATUS5" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_EPSTATUS6" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_EPSTATUS7" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_EPSTATUSCLR0" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_EPSTATUSCLR1" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_EPSTATUSCLR2" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_EPSTATUSCLR3" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_EPSTATUSCLR4" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_EPSTATUSCLR5" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_EPSTATUSCLR6" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_EPSTATUSCLR7" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_EPSTATUSSET0" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_EPSTATUSSET1" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_EPSTATUSSET2" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_EPSTATUSSET3" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_EPSTATUSSET4" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_EPSTATUSSET5" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_EPSTATUSSET6" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_EPSTATUSSET7" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="ReadOnly" description="DEVICE Device Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-      <BitField start="15" size="1" name="FNCERR" description="Frame Number CRC Error" />
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="DEVICE Device Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="DEVICE Device Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="DEVICE Device Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x05" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="ReadOnly" description="DEVICE Status" reset_value="0x40" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status">
-        <Enum name="FS" start="0x0" description="Full-speed mode" />
-        <Enum name="HS" start="0x1" description="High-speed mode" />
-        <Enum name="LS" start="0x2" description="Low-speed mode" />
-      </BitField>
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status">
-        <Enum name="0" start="0x0" description="SE0/RESET" />
-        <Enum name="1" start="0x1" description="FS-J or LS-K State" />
-        <Enum name="2" start="0x2" description="FS-K or LS-J State" />
-      </BitField>
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (HOST)" start="0x41005000" description="Universal Serial Bus">
-    <Register start="+0x103+0" size="1" name="USB_BINTERVAL0" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+32" size="1" name="USB_BINTERVAL1" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+64" size="1" name="USB_BINTERVAL2" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+96" size="1" name="USB_BINTERVAL3" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+128" size="1" name="USB_BINTERVAL4" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+160" size="1" name="USB_BINTERVAL5" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+192" size="1" name="USB_BINTERVAL6" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+224" size="1" name="USB_BINTERVAL7" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="HOST Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RESUME" description="Send USB Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration for Host">
-        <Enum name="NORMAL" start="0x0" description="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." />
-        <Enum name="FS" start="0x3" description="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." />
-      </BitField>
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="8" size="1" name="SOFE" description="Start of Frame Generation Enable" />
-      <BitField start="9" size="1" name="BUSRESET" description="Send USB Reset" />
-      <BitField start="10" size="1" name="VBUSOK" description="VBUS is OK" />
-      <BitField start="11" size="1" name="L1RESUME" description="Send L1 Resume" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x012" size="1" name="USB_FLENHIGH" access="ReadOnly" description="HOST Host Frame Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FLENHIGH" description="Frame Length" />
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="Read/Write" description="HOST Host Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_HSOFC" access="Read/Write" description="HOST Host Start Of Frame Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FLENC" description="Frame Length Control" />
-      <BitField start="7" size="1" name="FLENCE" description="Frame Length Control Enable" />
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="HOST Host Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Disable" />
-      <BitField start="3" size="1" name="RST" description="BUS Reset Interrupt Disable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Disable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to Device Interrupt Disable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from Device Interrupt Disable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Disable" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection Interrupt Disable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Disable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="HOST Host Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to the Device Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume fromthe device Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="DCONN" description="Link Power Management Interrupt Enable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="HOST Host Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="DNRSM" description="Downstream" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from the Device" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_PCFG0" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_PCFG1" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_PCFG2" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_PCFG3" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_PCFG4" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_PCFG5" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_PCFG6" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_PCFG7" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_PINTENCLR0" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_PINTENCLR1" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_PINTENCLR2" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_PINTENCLR3" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_PINTENCLR4" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_PINTENCLR5" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_PINTENCLR6" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_PINTENCLR7" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_PINTENSET0" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_PINTENSET1" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_PINTENSET2" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_PINTENSET3" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_PINTENSET4" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_PINTENSET5" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_PINTENSET6" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_PINTENSET7" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_PINTFLAG0" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_PINTFLAG1" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_PINTFLAG2" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_PINTFLAG3" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_PINTFLAG4" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_PINTFLAG5" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_PINTFLAG6" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_PINTFLAG7" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_PINTSMRY" access="ReadOnly" description="HOST Pipe Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="Pipe 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="Pipe 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="Pipe 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="Pipe 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="Pipe 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="Pipe 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="Pipe 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="Pipe 7 Interrupt" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_PSTATUS0" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_PSTATUS1" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_PSTATUS2" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_PSTATUS3" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_PSTATUS4" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_PSTATUS5" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_PSTATUS6" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_PSTATUS7" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_PSTATUSCLR0" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_PSTATUSCLR1" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_PSTATUSCLR2" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_PSTATUSCLR3" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_PSTATUSCLR4" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_PSTATUSCLR5" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_PSTATUSCLR6" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_PSTATUSCLR7" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_PSTATUSSET0" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_PSTATUSSET1" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_PSTATUSSET2" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_PSTATUSSET3" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_PSTATUSSET4" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_PSTATUSSET5" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_PSTATUSSET6" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_PSTATUSSET7" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x05" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="Read/Write" description="HOST Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status" />
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status" />
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WDT" start="0x40001000" description="Watchdog Timer">
-    <Register start="+0x8" size="1" name="WDT_CLEAR" access="WriteOnly" description="Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLEAR" description="Watchdog Clear">
-        <Enum name="KEY" start="0xa5" description="Clear Key" />
-      </BitField>
-    </Register>
-    <Register start="+0x1" size="1" name="WDT_CONFIG" access="Read/Write" description="Configuration" reset_value="0xBB" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PER" description="Time-Out Period">
-        <Enum name="8" start="0x0" description="8 clock cycles" />
-        <Enum name="16" start="0x1" description="16 clock cycles" />
-        <Enum name="32" start="0x2" description="32 clock cycles" />
-        <Enum name="64" start="0x3" description="64 clock cycles" />
-        <Enum name="128" start="0x4" description="128 clock cycles" />
-        <Enum name="256" start="0x5" description="256 clock cycles" />
-        <Enum name="512" start="0x6" description="512 clock cycles" />
-        <Enum name="1K" start="0x7" description="1024 clock cycles" />
-        <Enum name="2K" start="0x8" description="2048 clock cycles" />
-        <Enum name="4K" start="0x9" description="4096 clock cycles" />
-        <Enum name="8K" start="0xa" description="8192 clock cycles" />
-        <Enum name="16K" start="0xb" description="16384 clock cycles" />
-      </BitField>
-      <BitField start="4" size="4" name="WINDOW" description="Window Mode Time-Out Period">
-        <Enum name="8" start="0x0" description="8 clock cycles" />
-        <Enum name="16" start="0x1" description="16 clock cycles" />
-        <Enum name="32" start="0x2" description="32 clock cycles" />
-        <Enum name="64" start="0x3" description="64 clock cycles" />
-        <Enum name="128" start="0x4" description="128 clock cycles" />
-        <Enum name="256" start="0x5" description="256 clock cycles" />
-        <Enum name="512" start="0x6" description="512 clock cycles" />
-        <Enum name="1K" start="0x7" description="1024 clock cycles" />
-        <Enum name="2K" start="0x8" description="2048 clock cycles" />
-        <Enum name="4K" start="0x9" description="4096 clock cycles" />
-        <Enum name="8K" start="0xa" description="8192 clock cycles" />
-        <Enum name="16K" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x0" size="1" name="WDT_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="WEN" description="Watchdog Timer Window Mode Enable" />
-      <BitField start="7" size="1" name="ALWAYSON" description="Always-On" />
-    </Register>
-    <Register start="+0x2" size="1" name="WDT_EWCTRL" access="Read/Write" description="Early Warning Interrupt Control" reset_value="0x0B" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EWOFFSET" description="Early Warning Interrupt Time Offset">
-        <Enum name="8" start="0x0" description="8 clock cycles" />
-        <Enum name="16" start="0x1" description="16 clock cycles" />
-        <Enum name="32" start="0x2" description="32 clock cycles" />
-        <Enum name="64" start="0x3" description="64 clock cycles" />
-        <Enum name="128" start="0x4" description="128 clock cycles" />
-        <Enum name="256" start="0x5" description="256 clock cycles" />
-        <Enum name="512" start="0x6" description="512 clock cycles" />
-        <Enum name="1K" start="0x7" description="1024 clock cycles" />
-        <Enum name="2K" start="0x8" description="2048 clock cycles" />
-        <Enum name="4K" start="0x9" description="4096 clock cycles" />
-        <Enum name="8K" start="0xa" description="8192 clock cycles" />
-        <Enum name="16K" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x4" size="1" name="WDT_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x5" size="1" name="WDT_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x6" size="1" name="WDT_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning" />
-    </Register>
-    <Register start="+0x7" size="1" name="WDT_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="PM" start="6" size="2" />
-      <BitField name="SYSCTRL" start="14" size="2" />
-      <BitField name="WDT" start="22" size="2" />
-      <BitField name="RTC" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="EIC" start="6" size="2" />
-      <BitField name="NVMCTRL" start="14" size="2" />
-      <BitField name="DMAC" start="22" size="2" />
-      <BitField name="USB" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="EVSYS" start="6" size="2" />
-      <BitField name="SERCOM0" start="14" size="2" />
-      <BitField name="SERCOM1" start="22" size="2" />
-      <BitField name="SERCOM2" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="SERCOM3" start="6" size="2" />
-      <BitField name="SERCOM4" start="14" size="2" />
-      <BitField name="SERCOM5" start="22" size="2" />
-      <BitField name="TCC0" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="TCC1" start="6" size="2" />
-      <BitField name="TCC2" start="14" size="2" />
-      <BitField name="TC3" start="22" size="2" />
-      <BitField name="TC4" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="TC5" start="6" size="2" />
-      <BitField name="ADC" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="AC" start="6" size="2" />
-      <BitField name="DAC" start="14" size="2" />
-      <BitField name="I2S" start="30" size="2" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="30" size="2" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="30" size="2" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="22" size="2" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Vectors.s b/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Vectors.s
deleted file mode 100644
index 5cecbd23..00000000
--- a/examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Vectors.s
+++ /dev/null
@@ -1,331 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak PM_Handler
-  .thumb_set PM_Handler,Dummy_Handler
-
-  .weak SYSCTRL_Handler
-  .thumb_set SYSCTRL_Handler,Dummy_Handler
-
-  .weak WDT_Handler
-  .thumb_set WDT_Handler,Dummy_Handler
-
-  .weak RTC_Handler
-  .thumb_set RTC_Handler,Dummy_Handler
-
-  .weak EIC_Handler
-  .thumb_set EIC_Handler,Dummy_Handler
-
-  .weak NVMCTRL_Handler
-  .thumb_set NVMCTRL_Handler,Dummy_Handler
-
-  .weak DMAC_Handler
-  .thumb_set DMAC_Handler,Dummy_Handler
-
-  .weak USB_Handler
-  .thumb_set USB_Handler,Dummy_Handler
-
-  .weak EVSYS_Handler
-  .thumb_set EVSYS_Handler,Dummy_Handler
-
-  .weak SERCOM0_Handler
-  .thumb_set SERCOM0_Handler,Dummy_Handler
-
-  .weak SERCOM1_Handler
-  .thumb_set SERCOM1_Handler,Dummy_Handler
-
-  .weak SERCOM2_Handler
-  .thumb_set SERCOM2_Handler,Dummy_Handler
-
-  .weak SERCOM3_Handler
-  .thumb_set SERCOM3_Handler,Dummy_Handler
-
-  .weak SERCOM4_Handler
-  .thumb_set SERCOM4_Handler,Dummy_Handler
-
-  .weak SERCOM5_Handler
-  .thumb_set SERCOM5_Handler,Dummy_Handler
-
-  .weak TCC0_Handler
-  .thumb_set TCC0_Handler,Dummy_Handler
-
-  .weak TCC1_Handler
-  .thumb_set TCC1_Handler,Dummy_Handler
-
-  .weak TCC2_Handler
-  .thumb_set TCC2_Handler,Dummy_Handler
-
-  .weak TC3_Handler
-  .thumb_set TC3_Handler,Dummy_Handler
-
-  .weak TC4_Handler
-  .thumb_set TC4_Handler,Dummy_Handler
-
-  .weak TC5_Handler
-  .thumb_set TC5_Handler,Dummy_Handler
-
-  .weak ADC_Handler
-  .thumb_set ADC_Handler,Dummy_Handler
-
-  .weak AC_Handler
-  .thumb_set AC_Handler,Dummy_Handler
-
-  .weak DAC_Handler
-  .thumb_set DAC_Handler,Dummy_Handler
-
-  .weak I2S_Handler
-  .thumb_set I2S_Handler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak PM_Handler
-PM_Handler:
-  b .
-
-  .thumb_func
-  .weak SYSCTRL_Handler
-SYSCTRL_Handler:
-  b .
-
-  .thumb_func
-  .weak WDT_Handler
-WDT_Handler:
-  b .
-
-  .thumb_func
-  .weak RTC_Handler
-RTC_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_Handler
-EIC_Handler:
-  b .
-
-  .thumb_func
-  .weak NVMCTRL_Handler
-NVMCTRL_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_Handler
-DMAC_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_Handler
-USB_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_Handler
-EVSYS_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_Handler
-SERCOM0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_Handler
-SERCOM1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_Handler
-SERCOM2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_Handler
-SERCOM3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_Handler
-SERCOM4_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_Handler
-SERCOM5_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_Handler
-TCC0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_Handler
-TCC1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_Handler
-TCC2_Handler:
-  b .
-
-  .thumb_func
-  .weak TC3_Handler
-TC3_Handler:
-  b .
-
-  .thumb_func
-  .weak TC4_Handler
-TC4_Handler:
-  b .
-
-  .thumb_func
-  .weak TC5_Handler
-TC5_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC_Handler
-ADC_Handler:
-  b .
-
-  .thumb_func
-  .weak AC_Handler
-AC_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_Handler
-DAC_Handler:
-  b .
-
-  .thumb_func
-  .weak I2S_Handler
-I2S_Handler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word PM_Handler
-  .word SYSCTRL_Handler
-  .word WDT_Handler
-  .word RTC_Handler
-  .word EIC_Handler
-  .word NVMCTRL_Handler
-  .word DMAC_Handler
-  .word USB_Handler
-  .word EVSYS_Handler
-  .word SERCOM0_Handler
-  .word SERCOM1_Handler
-  .word SERCOM2_Handler
-  .word SERCOM3_Handler
-  .word SERCOM4_Handler
-  .word SERCOM5_Handler
-  .word TCC0_Handler
-  .word TCC1_Handler
-  .word TCC2_Handler
-  .word TC3_Handler
-  .word TC4_Handler
-  .word TC5_Handler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word ADC_Handler
-  .word AC_Handler
-  .word DAC_Handler
-  .word Dummy_Handler /* Reserved */
-  .word I2S_Handler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/samd21/SAMD21_Startup.s b/examples/device/cdc_msc/ses/samd21/SAMD21_Startup.s
deleted file mode 100644
index c4b48d35..00000000
--- a/examples/device/cdc_msc/ses/samd21/SAMD21_Startup.s
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  ldr r1, =0x7
-  bics r0, r1
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/samd21/SAMD21_Target.js b/examples/device/cdc_msc/ses/samd21/SAMD21_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/samd21/SAMD21_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/samd21/flash_placement.xml b/examples/device/cdc_msc/ses/samd21/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/samd21/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/samd21/samd21.emProject b/examples/device/cdc_msc/ses/samd21/samd21.emProject
deleted file mode 100644
index 6740241a..00000000
--- a/examples/device/cdc_msc/ses/samd21/samd21.emProject
+++ /dev/null
@@ -1,108 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="samd21" target="8" version="2">
-  <project Name="samd21">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="nRF52840_xxAA"
-      arm_architecture="v6M"
-      arm_core_type="Cortex-M0+"
-      arm_endian="Little"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 20000000,00030000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="ATSAMD21G18A"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="__SAMD21G18A__;__SAMD21_FAMILY;__SAM_D21_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;CONF_XOSC32K_CONFIG=1;CONF_OSC32K_ENABLE=1;CONF_OSC32K_EN32K=1;CONF_XOSC32K_STARTUP=CONF_XOSC32K_STARTUP_TIME_2000092MCS;CONF_DFLL_ONDEMAND=0;CONF_DFLL_OVERWRITE_CALIBRATION=0;CFG_TUSB_MCU=OPT_MCU_SAMD21"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(asf4Dir)/hpl/pm"
-      debug_register_definition_file="ATSAMD21G18A_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
-      macros="DeviceFamily=SAMD21;Target=ATSAMD21G18A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd21"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/SAMD21_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="metro_m0_express">
-          <file file_name="../../../../../hw/bsp/metro_m0_express/metro_m0_express.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="microchip">
-          <folder Name="samd">
-            <folder Name="asf4">
-              <folder Name="samd21">
-                <folder Name="gcc">
-                  <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c" />
-                </folder>
-                <folder Name="hpl">
-                  <folder Name="gclk">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c" />
-                  </folder>
-                  <folder Name="pm">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c" />
-                  </folder>
-                  <folder Name="sysctrl">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c" />
-                  </folder>
-                </folder>
-                <folder Name="hal">
-                  <folder Name="src">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hal/src/hal_atomic.c" />
-                  </folder>
-                </folder>
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="ATSAMD21G18A_MemoryMap.xml" />
-      <file file_name="ATSAMD21G18A_Registers.xml" />
-      <file file_name="ATSAMD21G18A_Vectors.s" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="SAMD21_Startup.s" />
-      <file file_name="SAMD21_Target.js" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <configuration
-      Name="Metro M0 Express"
-      c_preprocessor_definitions="BOARD_METRO_M0_EXPRESS" />
-  </project>
-  <configuration Name="Metro M0 Express" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/samd21/thumb_crt0.s b/examples/device/cdc_msc/ses/samd21/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/samd21/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_MemoryMap.xml b/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_MemoryMap.xml
deleted file mode 100644
index 49d9a9cb..00000000
--- a/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="ATSAMD51J19A">
-  <MemorySegment name="FLASH" start="0x00004000" size="0x0007C000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20000000" size="0x00030000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x47000000" size="0x00002000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_Registers.xml b/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_Registers.xml
deleted file mode 100644
index 83fe837f..00000000
--- a/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_Registers.xml
+++ /dev/null
@@ -1,23643 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="ATSAMD51J19A" description="Atmel ATSAMD51J19A device: Cortex-M4 Microcontroller with 512KB Flash, 192KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD51J19A.aspx for more)">
-  <RegisterGroup name="AC" start="0x42002000" description="Analog Comparators">
-    <Register start="+0x00" size="1" name="AC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x01" size="1" name="AC_CTRLB" access="WriteOnly" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START0" description="Comparator 0 Start Comparison" />
-      <BitField start="1" size="1" name="START1" description="Comparator 1 Start Comparison" />
-    </Register>
-    <Register start="+0x02" size="2" name="AC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPEO0" description="Comparator 0 Event Output Enable" />
-      <BitField start="1" size="1" name="COMPEO1" description="Comparator 1 Event Output Enable" />
-      <BitField start="4" size="1" name="WINEO0" description="Window 0 Event Output Enable" />
-      <BitField start="8" size="1" name="COMPEI0" description="Comparator 0 Event Input Enable" />
-      <BitField start="9" size="1" name="COMPEI1" description="Comparator 1 Event Input Enable" />
-      <BitField start="12" size="1" name="INVEI0" description="Comparator 0 Input Event Invert Enable" />
-      <BitField start="13" size="1" name="INVEI1" description="Comparator 1 Input Event Invert Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="AC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="AC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="AC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0" />
-    </Register>
-    <Register start="+0x07" size="1" name="AC_STATUSA" access="ReadOnly" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATE0" description="Comparator 0 Current State" />
-      <BitField start="1" size="1" name="STATE1" description="Comparator 1 Current State" />
-      <BitField start="4" size="2" name="WSTATE0" description="Window 0 Current State">
-        <Enum name="ABOVE" start="0x0" description="Signal is above window" />
-        <Enum name="INSIDE" start="0x1" description="Signal is inside window" />
-        <Enum name="BELOW" start="0x2" description="Signal is below window" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="1" name="AC_STATUSB" access="ReadOnly" description="Status B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY0" description="Comparator 0 Ready" />
-      <BitField start="1" size="1" name="READY1" description="Comparator 1 Ready" />
-    </Register>
-    <Register start="+0x09" size="1" name="AC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x0A" size="1" name="AC_WINCTRL" access="Read/Write" description="Window Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WEN0" description="Window 0 Mode Enable" />
-      <BitField start="1" size="2" name="WINTSEL0" description="Window 0 Interrupt Selection">
-        <Enum name="ABOVE" start="0x0" description="Interrupt on signal above window" />
-        <Enum name="INSIDE" start="0x1" description="Interrupt on signal inside window" />
-        <Enum name="BELOW" start="0x2" description="Interrupt on signal below window" />
-        <Enum name="OUTSIDE" start="0x3" description="Interrupt on signal outside window" />
-      </BitField>
-    </Register>
-    <Register start="+0x0C+0" size="1" name="AC_SCALER0" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x0C+1" size="1" name="AC_SCALER1" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x10+0" size="4" name="AC_COMPCTRL0" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="3" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="3" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="VSCALE" start="0x4" description="VDD Scaler" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="HIGH" start="0x3" description="High speed" />
-      </BitField>
-      <BitField start="19" size="1" name="HYSTEN" description="Hysteresis Enable" />
-      <BitField start="20" size="2" name="HYST" description="Hysteresis Level">
-        <Enum name="HYST50" start="0x0" description="50mV" />
-        <Enum name="HYST100" start="0x1" description="100mV" />
-        <Enum name="HYST150" start="0x2" description="150mV" />
-      </BitField>
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-      <BitField start="28" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-    </Register>
-    <Register start="+0x10+4" size="4" name="AC_COMPCTRL1" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="3" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="3" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="VSCALE" start="0x4" description="VDD Scaler" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="HIGH" start="0x3" description="High speed" />
-      </BitField>
-      <BitField start="19" size="1" name="HYSTEN" description="Hysteresis Enable" />
-      <BitField start="20" size="2" name="HYST" description="Hysteresis Level">
-        <Enum name="HYST50" start="0x0" description="50mV" />
-        <Enum name="HYST100" start="0x1" description="100mV" />
-        <Enum name="HYST150" start="0x2" description="150mV" />
-      </BitField>
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-      <BitField start="28" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-    </Register>
-    <Register start="+0x20" size="4" name="AC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="WINCTRL" description="WINCTRL Synchronization Busy" />
-      <BitField start="3" size="1" name="COMPCTRL0" description="COMPCTRL 0 Synchronization Busy" />
-      <BitField start="4" size="1" name="COMPCTRL1" description="COMPCTRL 1 Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="2" name="AC_CALIB" access="Read/Write" description="Calibration" reset_value="0x0101" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BIAS0" description="COMP0/1 Bias Scaling" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x43001C00" description="Analog Digital Converter 0">
-    <Register start="+0x00" size="2" name="ADC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="3" size="2" name="DUALSEL" description="Dual Mode Trigger Selection">
-        <Enum name="BOTH" start="0x0" description="Start event or software trigger will start a conversion on both ADCs" />
-        <Enum name="INTERLEAVE" start="0x1" description="START event or software trigger will alternatingly start a conversion on ADC0 and ADC1" />
-      </BitField>
-      <BitField start="5" size="1" name="SLAVEEN" description="Slave Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler Configuration">
-        <Enum name="DIV2" start="0x0" description="Peripheral clock divided by 2" />
-        <Enum name="DIV4" start="0x1" description="Peripheral clock divided by 4" />
-        <Enum name="DIV8" start="0x2" description="Peripheral clock divided by 8" />
-        <Enum name="DIV16" start="0x3" description="Peripheral clock divided by 16" />
-        <Enum name="DIV32" start="0x4" description="Peripheral clock divided by 32" />
-        <Enum name="DIV64" start="0x5" description="Peripheral clock divided by 64" />
-        <Enum name="DIV128" start="0x6" description="Peripheral clock divided by 128" />
-        <Enum name="DIV256" start="0x7" description="Peripheral clock divided by 256" />
-      </BitField>
-      <BitField start="15" size="1" name="R2R" description="Rail to Rail Operation Enable" />
-    </Register>
-    <Register start="+0x02" size="1" name="ADC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSHEI" description="Flush Event Input Enable" />
-      <BitField start="1" size="1" name="STARTEI" description="Start Conversion Event Input Enable" />
-      <BitField start="2" size="1" name="FLUSHINV" description="Flush Event Invert Enable" />
-      <BitField start="3" size="1" name="STARTINV" description="Start Conversion Event Invert Enable" />
-      <BitField start="4" size="1" name="RESRDYEO" description="Result Ready Event Out" />
-      <BitField start="5" size="1" name="WINMONEO" description="Window Monitor Event Out" />
-    </Register>
-    <Register start="+0x03" size="1" name="ADC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x04" size="2" name="ADC_INPUTCTRL" access="Read/Write" description="Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MUXPOS" description="Positive Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="AIN8" start="0x8" description="ADC AIN8 Pin" />
-        <Enum name="AIN9" start="0x9" description="ADC AIN9 Pin" />
-        <Enum name="AIN10" start="0xa" description="ADC AIN10 Pin" />
-        <Enum name="AIN11" start="0xb" description="ADC AIN11 Pin" />
-        <Enum name="AIN12" start="0xc" description="ADC AIN12 Pin" />
-        <Enum name="AIN13" start="0xd" description="ADC AIN13 Pin" />
-        <Enum name="AIN14" start="0xe" description="ADC AIN14 Pin" />
-        <Enum name="AIN15" start="0xf" description="ADC AIN15 Pin" />
-        <Enum name="AIN16" start="0x10" description="ADC AIN16 Pin" />
-        <Enum name="AIN17" start="0x11" description="ADC AIN17 Pin" />
-        <Enum name="AIN18" start="0x12" description="ADC AIN18 Pin" />
-        <Enum name="AIN19" start="0x13" description="ADC AIN19 Pin" />
-        <Enum name="AIN20" start="0x14" description="ADC AIN20 Pin" />
-        <Enum name="AIN21" start="0x15" description="ADC AIN21 Pin" />
-        <Enum name="AIN22" start="0x16" description="ADC AIN22 Pin" />
-        <Enum name="AIN23" start="0x17" description="ADC AIN23 Pin" />
-        <Enum name="SCALEDCOREVCC" start="0x18" description="1/4 Scaled Core Supply" />
-        <Enum name="SCALEDVBAT" start="0x19" description="1/4 Scaled VBAT Supply" />
-        <Enum name="SCALEDIOVCC" start="0x1a" description="1/4 Scaled I/O Supply" />
-        <Enum name="BANDGAP" start="0x1b" description="Bandgap Voltage" />
-        <Enum name="PTAT" start="0x1c" description="Temperature Sensor" />
-        <Enum name="CTAT" start="0x1d" description="Temperature Sensor" />
-        <Enum name="DAC" start="0x1e" description="DAC Output" />
-        <Enum name="PTC" start="0x1f" description="PTC output (only on ADC0)" />
-      </BitField>
-      <BitField start="7" size="1" name="DIFFMODE" description="Differential Mode" />
-      <BitField start="8" size="5" name="MUXNEG" description="Negative Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="GND" start="0x18" description="Internal Ground" />
-      </BitField>
-      <BitField start="15" size="1" name="DSEQSTOP" description="Stop DMA Sequencing" />
-    </Register>
-    <Register start="+0x06" size="2" name="ADC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left-Adjusted Result" />
-      <BitField start="1" size="1" name="FREERUN" description="Free Running Mode" />
-      <BitField start="2" size="1" name="CORREN" description="Digital Correction Logic Enable" />
-      <BitField start="3" size="2" name="RESSEL" description="Conversion Result Resolution">
-        <Enum name="12BIT" start="0x0" description="12-bit result" />
-        <Enum name="16BIT" start="0x1" description="For averaging mode output" />
-        <Enum name="10BIT" start="0x2" description="10-bit result" />
-        <Enum name="8BIT" start="0x3" description="8-bit result" />
-      </BitField>
-      <BitField start="8" size="3" name="WINMODE" description="Window Monitor Mode">
-        <Enum name="DISABLE" start="0x0" description="No window mode (default)" />
-        <Enum name="MODE1" start="0x1" description="RESULT &gt; WINLT" />
-        <Enum name="MODE2" start="0x2" description="RESULT &lt; WINUT" />
-        <Enum name="MODE3" start="0x3" description="WINLT &lt; RESULT &lt; WINUT" />
-        <Enum name="MODE4" start="0x4" description="!(WINLT &lt; RESULT &lt; WINUT)" />
-      </BitField>
-      <BitField start="11" size="1" name="WINSS" description="Window Single Sample" />
-    </Register>
-    <Register start="+0x08" size="1" name="ADC_REFCTRL" access="Read/Write" description="Reference Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference Selection">
-        <Enum name="INTREF" start="0x0" description="Internal Bandgap Reference" />
-        <Enum name="INTVCC0" start="0x2" description="1/2 VDDANA" />
-        <Enum name="INTVCC1" start="0x3" description="VDDANA" />
-        <Enum name="AREFA" start="0x4" description="External Reference" />
-        <Enum name="AREFB" start="0x5" description="External Reference" />
-        <Enum name="AREFC" start="0x6" description="External Reference (only on ADC1)" />
-      </BitField>
-      <BitField start="7" size="1" name="REFCOMP" description="Reference Buffer Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="ADC_AVGCTRL" access="Read/Write" description="Average Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLENUM" description="Number of Samples to be Collected">
-        <Enum name="1" start="0x0" description="1 sample" />
-        <Enum name="2" start="0x1" description="2 samples" />
-        <Enum name="4" start="0x2" description="4 samples" />
-        <Enum name="8" start="0x3" description="8 samples" />
-        <Enum name="16" start="0x4" description="16 samples" />
-        <Enum name="32" start="0x5" description="32 samples" />
-        <Enum name="64" start="0x6" description="64 samples" />
-        <Enum name="128" start="0x7" description="128 samples" />
-        <Enum name="256" start="0x8" description="256 samples" />
-        <Enum name="512" start="0x9" description="512 samples" />
-        <Enum name="1024" start="0xa" description="1024 samples" />
-      </BitField>
-      <BitField start="4" size="3" name="ADJRES" description="Adjusting Result / Division Coefficient" />
-    </Register>
-    <Register start="+0x0B" size="1" name="ADC_SAMPCTRL" access="Read/Write" description="Sample Time Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SAMPLEN" description="Sampling Time Length" />
-      <BitField start="7" size="1" name="OFFCOMP" description="Comparator Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="ADC_WINLT" access="Read/Write" description="Window Monitor Lower Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINLT" description="Window Lower Threshold" />
-    </Register>
-    <Register start="+0x0E" size="2" name="ADC_WINUT" access="Read/Write" description="Window Monitor Upper Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINUT" description="Window Upper Threshold" />
-    </Register>
-    <Register start="+0x10" size="2" name="ADC_GAINCORR" access="Read/Write" description="Gain Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="GAINCORR" description="Gain Correction Value" />
-    </Register>
-    <Register start="+0x12" size="2" name="ADC_OFFSETCORR" access="Read/Write" description="Offset Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="OFFSETCORR" description="Offset Correction Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="ADC_SWTRIG" access="Read/Write" description="Software Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSH" description="ADC Conversion Flush" />
-      <BitField start="1" size="1" name="START" description="Start ADC Conversion" />
-    </Register>
-    <Register start="+0x2C" size="1" name="ADC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Disable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Disable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Disable" />
-    </Register>
-    <Register start="+0x2D" size="1" name="ADC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-    </Register>
-    <Register start="+0x2E" size="1" name="ADC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Flag" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Flag" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Flag" />
-    </Register>
-    <Register start="+0x2F" size="1" name="ADC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADCBUSY" description="ADC Busy Status" />
-      <BitField start="2" size="6" name="WCC" description="Window Comparator Counter" />
-    </Register>
-    <Register start="+0x30" size="4" name="ADC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="SWRST Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="ENABLE Synchronization Busy" />
-      <BitField start="2" size="1" name="INPUTCTRL" description="Input Control Synchronization Busy" />
-      <BitField start="3" size="1" name="CTRLB" description="Control B Synchronization Busy" />
-      <BitField start="4" size="1" name="REFCTRL" description="Reference Control Synchronization Busy" />
-      <BitField start="5" size="1" name="AVGCTRL" description="Average Control Synchronization Busy" />
-      <BitField start="6" size="1" name="SAMPCTRL" description="Sampling Time Control Synchronization Busy" />
-      <BitField start="7" size="1" name="WINLT" description="Window Monitor Lower Threshold Synchronization Busy" />
-      <BitField start="8" size="1" name="WINUT" description="Window Monitor Upper Threshold Synchronization Busy" />
-      <BitField start="9" size="1" name="GAINCORR" description="Gain Correction Synchronization Busy" />
-      <BitField start="10" size="1" name="OFFSETCORR" description="Offset Correction Synchronization Busy" />
-      <BitField start="11" size="1" name="SWTRIG" description="Software Trigger Synchronization Busy" />
-    </Register>
-    <Register start="+0x34" size="4" name="ADC_DSEQDATA" access="WriteOnly" description="DMA Sequencial Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="DMA Sequential Data" />
-    </Register>
-    <Register start="+0x38" size="4" name="ADC_DSEQCTRL" access="Read/Write" description="DMA Sequential Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="AUTOSTART" description="ADC Auto-Start Conversion" />
-    </Register>
-    <Register start="+0x3C" size="4" name="ADC_DSEQSTAT" access="ReadOnly" description="DMA Sequencial Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="BUSY" description="DMA Sequencing Busy" />
-    </Register>
-    <Register start="+0x40" size="2" name="ADC_RESULT" access="ReadOnly" description="Result Conversion Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Result Conversion Value" />
-    </Register>
-    <Register start="+0x44" size="2" name="ADC_RESS" access="ReadOnly" description="Last Sample Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESS" description="Last ADC conversion result" />
-    </Register>
-    <Register start="+0x48" size="2" name="ADC_CALIB" access="Read/Write" description="Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="BIASCOMP" description="Bias Comparator Scaling" />
-      <BitField start="4" size="3" name="BIASR2R" description="Bias R2R Ampli scaling" />
-      <BitField start="8" size="3" name="BIASREFBUF" description="Bias  Reference Buffer Scaling" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x43002000" description="Analog Digital Converter 1">
-    <Register start="+0x00" size="2" name="ADC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="3" size="2" name="DUALSEL" description="Dual Mode Trigger Selection">
-        <Enum name="BOTH" start="0x0" description="Start event or software trigger will start a conversion on both ADCs" />
-        <Enum name="INTERLEAVE" start="0x1" description="START event or software trigger will alternatingly start a conversion on ADC0 and ADC1" />
-      </BitField>
-      <BitField start="5" size="1" name="SLAVEEN" description="Slave Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler Configuration">
-        <Enum name="DIV2" start="0x0" description="Peripheral clock divided by 2" />
-        <Enum name="DIV4" start="0x1" description="Peripheral clock divided by 4" />
-        <Enum name="DIV8" start="0x2" description="Peripheral clock divided by 8" />
-        <Enum name="DIV16" start="0x3" description="Peripheral clock divided by 16" />
-        <Enum name="DIV32" start="0x4" description="Peripheral clock divided by 32" />
-        <Enum name="DIV64" start="0x5" description="Peripheral clock divided by 64" />
-        <Enum name="DIV128" start="0x6" description="Peripheral clock divided by 128" />
-        <Enum name="DIV256" start="0x7" description="Peripheral clock divided by 256" />
-      </BitField>
-      <BitField start="15" size="1" name="R2R" description="Rail to Rail Operation Enable" />
-    </Register>
-    <Register start="+0x02" size="1" name="ADC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSHEI" description="Flush Event Input Enable" />
-      <BitField start="1" size="1" name="STARTEI" description="Start Conversion Event Input Enable" />
-      <BitField start="2" size="1" name="FLUSHINV" description="Flush Event Invert Enable" />
-      <BitField start="3" size="1" name="STARTINV" description="Start Conversion Event Invert Enable" />
-      <BitField start="4" size="1" name="RESRDYEO" description="Result Ready Event Out" />
-      <BitField start="5" size="1" name="WINMONEO" description="Window Monitor Event Out" />
-    </Register>
-    <Register start="+0x03" size="1" name="ADC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x04" size="2" name="ADC_INPUTCTRL" access="Read/Write" description="Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MUXPOS" description="Positive Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="AIN8" start="0x8" description="ADC AIN8 Pin" />
-        <Enum name="AIN9" start="0x9" description="ADC AIN9 Pin" />
-        <Enum name="AIN10" start="0xa" description="ADC AIN10 Pin" />
-        <Enum name="AIN11" start="0xb" description="ADC AIN11 Pin" />
-        <Enum name="AIN12" start="0xc" description="ADC AIN12 Pin" />
-        <Enum name="AIN13" start="0xd" description="ADC AIN13 Pin" />
-        <Enum name="AIN14" start="0xe" description="ADC AIN14 Pin" />
-        <Enum name="AIN15" start="0xf" description="ADC AIN15 Pin" />
-        <Enum name="AIN16" start="0x10" description="ADC AIN16 Pin" />
-        <Enum name="AIN17" start="0x11" description="ADC AIN17 Pin" />
-        <Enum name="AIN18" start="0x12" description="ADC AIN18 Pin" />
-        <Enum name="AIN19" start="0x13" description="ADC AIN19 Pin" />
-        <Enum name="AIN20" start="0x14" description="ADC AIN20 Pin" />
-        <Enum name="AIN21" start="0x15" description="ADC AIN21 Pin" />
-        <Enum name="AIN22" start="0x16" description="ADC AIN22 Pin" />
-        <Enum name="AIN23" start="0x17" description="ADC AIN23 Pin" />
-        <Enum name="SCALEDCOREVCC" start="0x18" description="1/4 Scaled Core Supply" />
-        <Enum name="SCALEDVBAT" start="0x19" description="1/4 Scaled VBAT Supply" />
-        <Enum name="SCALEDIOVCC" start="0x1a" description="1/4 Scaled I/O Supply" />
-        <Enum name="BANDGAP" start="0x1b" description="Bandgap Voltage" />
-        <Enum name="PTAT" start="0x1c" description="Temperature Sensor" />
-        <Enum name="CTAT" start="0x1d" description="Temperature Sensor" />
-        <Enum name="DAC" start="0x1e" description="DAC Output" />
-        <Enum name="PTC" start="0x1f" description="PTC output (only on ADC0)" />
-      </BitField>
-      <BitField start="7" size="1" name="DIFFMODE" description="Differential Mode" />
-      <BitField start="8" size="5" name="MUXNEG" description="Negative Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="GND" start="0x18" description="Internal Ground" />
-      </BitField>
-      <BitField start="15" size="1" name="DSEQSTOP" description="Stop DMA Sequencing" />
-    </Register>
-    <Register start="+0x06" size="2" name="ADC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left-Adjusted Result" />
-      <BitField start="1" size="1" name="FREERUN" description="Free Running Mode" />
-      <BitField start="2" size="1" name="CORREN" description="Digital Correction Logic Enable" />
-      <BitField start="3" size="2" name="RESSEL" description="Conversion Result Resolution">
-        <Enum name="12BIT" start="0x0" description="12-bit result" />
-        <Enum name="16BIT" start="0x1" description="For averaging mode output" />
-        <Enum name="10BIT" start="0x2" description="10-bit result" />
-        <Enum name="8BIT" start="0x3" description="8-bit result" />
-      </BitField>
-      <BitField start="8" size="3" name="WINMODE" description="Window Monitor Mode">
-        <Enum name="DISABLE" start="0x0" description="No window mode (default)" />
-        <Enum name="MODE1" start="0x1" description="RESULT &gt; WINLT" />
-        <Enum name="MODE2" start="0x2" description="RESULT &lt; WINUT" />
-        <Enum name="MODE3" start="0x3" description="WINLT &lt; RESULT &lt; WINUT" />
-        <Enum name="MODE4" start="0x4" description="!(WINLT &lt; RESULT &lt; WINUT)" />
-      </BitField>
-      <BitField start="11" size="1" name="WINSS" description="Window Single Sample" />
-    </Register>
-    <Register start="+0x08" size="1" name="ADC_REFCTRL" access="Read/Write" description="Reference Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference Selection">
-        <Enum name="INTREF" start="0x0" description="Internal Bandgap Reference" />
-        <Enum name="INTVCC0" start="0x2" description="1/2 VDDANA" />
-        <Enum name="INTVCC1" start="0x3" description="VDDANA" />
-        <Enum name="AREFA" start="0x4" description="External Reference" />
-        <Enum name="AREFB" start="0x5" description="External Reference" />
-        <Enum name="AREFC" start="0x6" description="External Reference (only on ADC1)" />
-      </BitField>
-      <BitField start="7" size="1" name="REFCOMP" description="Reference Buffer Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="ADC_AVGCTRL" access="Read/Write" description="Average Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLENUM" description="Number of Samples to be Collected">
-        <Enum name="1" start="0x0" description="1 sample" />
-        <Enum name="2" start="0x1" description="2 samples" />
-        <Enum name="4" start="0x2" description="4 samples" />
-        <Enum name="8" start="0x3" description="8 samples" />
-        <Enum name="16" start="0x4" description="16 samples" />
-        <Enum name="32" start="0x5" description="32 samples" />
-        <Enum name="64" start="0x6" description="64 samples" />
-        <Enum name="128" start="0x7" description="128 samples" />
-        <Enum name="256" start="0x8" description="256 samples" />
-        <Enum name="512" start="0x9" description="512 samples" />
-        <Enum name="1024" start="0xa" description="1024 samples" />
-      </BitField>
-      <BitField start="4" size="3" name="ADJRES" description="Adjusting Result / Division Coefficient" />
-    </Register>
-    <Register start="+0x0B" size="1" name="ADC_SAMPCTRL" access="Read/Write" description="Sample Time Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SAMPLEN" description="Sampling Time Length" />
-      <BitField start="7" size="1" name="OFFCOMP" description="Comparator Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="ADC_WINLT" access="Read/Write" description="Window Monitor Lower Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINLT" description="Window Lower Threshold" />
-    </Register>
-    <Register start="+0x0E" size="2" name="ADC_WINUT" access="Read/Write" description="Window Monitor Upper Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINUT" description="Window Upper Threshold" />
-    </Register>
-    <Register start="+0x10" size="2" name="ADC_GAINCORR" access="Read/Write" description="Gain Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="GAINCORR" description="Gain Correction Value" />
-    </Register>
-    <Register start="+0x12" size="2" name="ADC_OFFSETCORR" access="Read/Write" description="Offset Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="OFFSETCORR" description="Offset Correction Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="ADC_SWTRIG" access="Read/Write" description="Software Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSH" description="ADC Conversion Flush" />
-      <BitField start="1" size="1" name="START" description="Start ADC Conversion" />
-    </Register>
-    <Register start="+0x2C" size="1" name="ADC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Disable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Disable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Disable" />
-    </Register>
-    <Register start="+0x2D" size="1" name="ADC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-    </Register>
-    <Register start="+0x2E" size="1" name="ADC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Flag" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Flag" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Flag" />
-    </Register>
-    <Register start="+0x2F" size="1" name="ADC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADCBUSY" description="ADC Busy Status" />
-      <BitField start="2" size="6" name="WCC" description="Window Comparator Counter" />
-    </Register>
-    <Register start="+0x30" size="4" name="ADC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="SWRST Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="ENABLE Synchronization Busy" />
-      <BitField start="2" size="1" name="INPUTCTRL" description="Input Control Synchronization Busy" />
-      <BitField start="3" size="1" name="CTRLB" description="Control B Synchronization Busy" />
-      <BitField start="4" size="1" name="REFCTRL" description="Reference Control Synchronization Busy" />
-      <BitField start="5" size="1" name="AVGCTRL" description="Average Control Synchronization Busy" />
-      <BitField start="6" size="1" name="SAMPCTRL" description="Sampling Time Control Synchronization Busy" />
-      <BitField start="7" size="1" name="WINLT" description="Window Monitor Lower Threshold Synchronization Busy" />
-      <BitField start="8" size="1" name="WINUT" description="Window Monitor Upper Threshold Synchronization Busy" />
-      <BitField start="9" size="1" name="GAINCORR" description="Gain Correction Synchronization Busy" />
-      <BitField start="10" size="1" name="OFFSETCORR" description="Offset Correction Synchronization Busy" />
-      <BitField start="11" size="1" name="SWTRIG" description="Software Trigger Synchronization Busy" />
-    </Register>
-    <Register start="+0x34" size="4" name="ADC_DSEQDATA" access="WriteOnly" description="DMA Sequencial Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="DMA Sequential Data" />
-    </Register>
-    <Register start="+0x38" size="4" name="ADC_DSEQCTRL" access="Read/Write" description="DMA Sequential Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="AUTOSTART" description="ADC Auto-Start Conversion" />
-    </Register>
-    <Register start="+0x3C" size="4" name="ADC_DSEQSTAT" access="ReadOnly" description="DMA Sequencial Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="BUSY" description="DMA Sequencing Busy" />
-    </Register>
-    <Register start="+0x40" size="2" name="ADC_RESULT" access="ReadOnly" description="Result Conversion Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Result Conversion Value" />
-    </Register>
-    <Register start="+0x44" size="2" name="ADC_RESS" access="ReadOnly" description="Last Sample Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESS" description="Last ADC conversion result" />
-    </Register>
-    <Register start="+0x48" size="2" name="ADC_CALIB" access="Read/Write" description="Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="BIASCOMP" description="Bias Comparator Scaling" />
-      <BitField start="4" size="3" name="BIASR2R" description="Bias R2R Ampli scaling" />
-      <BitField start="8" size="3" name="BIASREFBUF" description="Bias  Reference Buffer Scaling" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="AES" start="0x42002400" description="Advanced Encryption Standard">
-    <Register start="+0x00" size="4" name="AES_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="AESMODE" description="AES Modes of operation">
-        <Enum name="ECB" start="0x0" description="Electronic code book mode" />
-        <Enum name="CBC" start="0x1" description="Cipher block chaining mode" />
-        <Enum name="OFB" start="0x2" description="Output feedback mode" />
-        <Enum name="CFB" start="0x3" description="Cipher feedback mode" />
-        <Enum name="COUNTER" start="0x4" description="Counter mode" />
-        <Enum name="CCM" start="0x5" description="CCM mode" />
-        <Enum name="GCM" start="0x6" description="Galois counter mode" />
-      </BitField>
-      <BitField start="5" size="3" name="CFBS" description="Cipher Feedback Block Size">
-        <Enum name="128BIT" start="0x0" description="128-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="64BIT" start="0x1" description="64-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="32BIT" start="0x2" description="32-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="16BIT" start="0x3" description="16-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="8BIT" start="0x4" description="8-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-      </BitField>
-      <BitField start="8" size="2" name="KEYSIZE" description="Encryption Key Size">
-        <Enum name="128BIT" start="0x0" description="128-bit Key for Encryption / Decryption" />
-        <Enum name="192BIT" start="0x1" description="192-bit Key for Encryption / Decryption" />
-        <Enum name="256BIT" start="0x2" description="256-bit Key for Encryption / Decryption" />
-      </BitField>
-      <BitField start="10" size="1" name="CIPHER" description="Cipher Mode">
-        <Enum name="DEC" start="0x0" description="Decryption" />
-        <Enum name="ENC" start="0x1" description="Encryption" />
-      </BitField>
-      <BitField start="11" size="1" name="STARTMODE" description="Start Mode Select">
-        <Enum name="MANUAL" start="0x0" description="Start Encryption / Decryption in Manual mode" />
-        <Enum name="AUTO" start="0x1" description="Start Encryption / Decryption in Auto mode" />
-      </BitField>
-      <BitField start="12" size="1" name="LOD" description="Last Output Data Mode">
-        <Enum name="NONE" start="0x0" description="No effect" />
-        <Enum name="LAST" start="0x1" description="Start encryption in Last Output Data mode" />
-      </BitField>
-      <BitField start="13" size="1" name="KEYGEN" description="Last Key Generation">
-        <Enum name="NONE" start="0x0" description="No effect" />
-        <Enum name="LAST" start="0x1" description="Start Computation of the last NK words of the expanded key" />
-      </BitField>
-      <BitField start="14" size="1" name="XORKEY" description="XOR Key Operation">
-        <Enum name="NONE" start="0x0" description="No effect" />
-        <Enum name="XOR" start="0x1" description="The user keyword gets XORed with the previous keyword register content." />
-      </BitField>
-      <BitField start="16" size="4" name="CTYPE" description="Counter Measure Type" />
-    </Register>
-    <Register start="+0x04" size="1" name="AES_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start Encryption/Decryption" />
-      <BitField start="1" size="1" name="NEWMSG" description="New message" />
-      <BitField start="2" size="1" name="EOM" description="End of message" />
-      <BitField start="3" size="1" name="GFMUL" description="GF Multiplication" />
-    </Register>
-    <Register start="+0x05" size="1" name="AES_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENCCMP" description="Encryption Complete Interrupt Enable" />
-      <BitField start="1" size="1" name="GFMCMP" description="GF Multiplication Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="AES_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENCCMP" description="Encryption Complete Interrupt Enable" />
-      <BitField start="1" size="1" name="GFMCMP" description="GF Multiplication Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="AES_INTFLAG" access="Read/Write" description="Interrupt Flag Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENCCMP" description="Encryption Complete" />
-      <BitField start="1" size="1" name="GFMCMP" description="GF Multiplication Complete" />
-    </Register>
-    <Register start="+0x08" size="1" name="AES_DATABUFPTR" access="Read/Write" description="Data buffer pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="INDATAPTR" description="Input Data Pointer" />
-    </Register>
-    <Register start="+0x09" size="1" name="AES_DBGCTRL" access="Read/Write" description="Debug control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x0C+0" size="4" name="AES_KEYWORD0" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+4" size="4" name="AES_KEYWORD1" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+8" size="4" name="AES_KEYWORD2" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+12" size="4" name="AES_KEYWORD3" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+16" size="4" name="AES_KEYWORD4" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+20" size="4" name="AES_KEYWORD5" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+24" size="4" name="AES_KEYWORD6" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+28" size="4" name="AES_KEYWORD7" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x38" size="4" name="AES_INDATA" access="Read/Write" description="Indata" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+0" size="4" name="AES_INTVECTV0" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+4" size="4" name="AES_INTVECTV1" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+8" size="4" name="AES_INTVECTV2" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+12" size="4" name="AES_INTVECTV3" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+0" size="4" name="AES_HASHKEY0" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+4" size="4" name="AES_HASHKEY1" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+8" size="4" name="AES_HASHKEY2" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+12" size="4" name="AES_HASHKEY3" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+0" size="4" name="AES_GHASH0" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+4" size="4" name="AES_GHASH1" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+8" size="4" name="AES_GHASH2" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+12" size="4" name="AES_GHASH3" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x80" size="4" name="AES_CIPLEN" access="Read/Write" description="Cipher Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x84" size="4" name="AES_RANDSEED" access="Read/Write" description="Random Seed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="CCL" start="0x42003800" description="Configurable Custom Logic">
-    <Register start="+0x0" size="1" name="CCL_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x4+0" size="1" name="CCL_SEQCTRL0" access="Read/Write" description="SEQ Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SEQSEL" description="Sequential Selection">
-        <Enum name="DISABLE" start="0x0" description="Sequential logic is disabled" />
-        <Enum name="DFF" start="0x1" description="D flip flop" />
-        <Enum name="JK" start="0x2" description="JK flip flop" />
-        <Enum name="LATCH" start="0x3" description="D latch" />
-        <Enum name="RS" start="0x4" description="RS latch" />
-      </BitField>
-    </Register>
-    <Register start="+0x4+1" size="1" name="CCL_SEQCTRL1" access="Read/Write" description="SEQ Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SEQSEL" description="Sequential Selection">
-        <Enum name="DISABLE" start="0x0" description="Sequential logic is disabled" />
-        <Enum name="DFF" start="0x1" description="D flip flop" />
-        <Enum name="JK" start="0x2" description="JK flip flop" />
-        <Enum name="LATCH" start="0x3" description="D latch" />
-        <Enum name="RS" start="0x4" description="RS latch" />
-      </BitField>
-    </Register>
-    <Register start="+0x8+0" size="4" name="CCL_LUTCTRL0" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-    <Register start="+0x8+4" size="4" name="CCL_LUTCTRL1" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-    <Register start="+0x8+8" size="4" name="CCL_LUTCTRL2" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-    <Register start="+0x8+12" size="4" name="CCL_LUTCTRL3" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CMCC" start="0x41006000" description="Cortex M Cache Controller">
-    <Register start="+0x00" size="4" name="CMCC_TYPE" access="ReadOnly" description="Cache Type Register" reset_value="0x000012D2" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="GCLK" description="dynamic Clock Gating supported" />
-      <BitField start="4" size="1" name="RRP" description="Round Robin Policy supported" />
-      <BitField start="5" size="2" name="WAYNUM" description="Number of Way">
-        <Enum name="DMAPPED" start="0x0" description="Direct Mapped Cache" />
-        <Enum name="ARCH2WAY" start="0x1" description="2-WAY set associative" />
-        <Enum name="ARCH4WAY" start="0x2" description="4-WAY set associative" />
-      </BitField>
-      <BitField start="7" size="1" name="LCKDOWN" description="Lock Down supported" />
-      <BitField start="8" size="3" name="CSIZE" description="Cache Size">
-        <Enum name="CSIZE_1KB" start="0x0" description="Cache Size is 1 KB" />
-        <Enum name="CSIZE_2KB" start="0x1" description="Cache Size is 2 KB" />
-        <Enum name="CSIZE_4KB" start="0x2" description="Cache Size is 4 KB" />
-        <Enum name="CSIZE_8KB" start="0x3" description="Cache Size is 8 KB" />
-        <Enum name="CSIZE_16KB" start="0x4" description="Cache Size is 16 KB" />
-        <Enum name="CSIZE_32KB" start="0x5" description="Cache Size is 32 KB" />
-        <Enum name="CSIZE_64KB" start="0x6" description="Cache Size is 64 KB" />
-      </BitField>
-      <BitField start="11" size="3" name="CLSIZE" description="Cache Line Size">
-        <Enum name="CLSIZE_4B" start="0x0" description="Cache Line Size is 4 bytes" />
-        <Enum name="CLSIZE_8B" start="0x1" description="Cache Line Size is 8 bytes" />
-        <Enum name="CLSIZE_16B" start="0x2" description="Cache Line Size is 16 bytes" />
-        <Enum name="CLSIZE_32B" start="0x3" description="Cache Line Size is 32 bytes" />
-        <Enum name="CLSIZE_64B" start="0x4" description="Cache Line Size is 64 bytes" />
-        <Enum name="CLSIZE_128B" start="0x5" description="Cache Line Size is 128 bytes" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="CMCC_CFG" access="Read/Write" description="Cache Configuration Register" reset_value="0x00000020" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ICDIS" description="Instruction Cache Disable" />
-      <BitField start="2" size="1" name="DCDIS" description="Data Cache Disable" />
-      <BitField start="4" size="3" name="CSIZESW" description="Cache size configured by software">
-        <Enum name="CONF_CSIZE_1KB" start="0x0" description="the Cache Size is configured to 1KB" />
-        <Enum name="CONF_CSIZE_2KB" start="0x1" description="the Cache Size is configured to 2KB" />
-        <Enum name="CONF_CSIZE_4KB" start="0x2" description="the Cache Size is configured to 4KB" />
-        <Enum name="CONF_CSIZE_8KB" start="0x3" description="the Cache Size is configured to 8KB" />
-        <Enum name="CONF_CSIZE_16KB" start="0x4" description="the Cache Size is configured to 16KB" />
-        <Enum name="CONF_CSIZE_32KB" start="0x5" description="the Cache Size is configured to 32KB" />
-        <Enum name="CONF_CSIZE_64KB" start="0x6" description="the Cache Size is configured to 64KB" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="CMCC_CTRL" access="WriteOnly" description="Cache Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Cache Controller Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="CMCC_SR" access="ReadOnly" description="Cache Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTS" description="Cache Controller Status" />
-    </Register>
-    <Register start="+0x10" size="4" name="CMCC_LCKWAY" access="Read/Write" description="Cache Lock per Way Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="LCKWAY" description="Lockdown way Register" />
-    </Register>
-    <Register start="+0x20" size="4" name="CMCC_MAINT0" access="WriteOnly" description="Cache Maintenance Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVALL" description="Cache Controller invalidate All" />
-    </Register>
-    <Register start="+0x24" size="4" name="CMCC_MAINT1" access="WriteOnly" description="Cache Maintenance Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="8" name="INDEX" description="Invalidate Index" />
-      <BitField start="28" size="4" name="WAY" description="Invalidate Way">
-        <Enum name="WAY0" start="0x0" description="Way 0 is selection for index invalidation" />
-        <Enum name="WAY1" start="0x1" description="Way 1 is selection for index invalidation" />
-        <Enum name="WAY2" start="0x2" description="Way 2 is selection for index invalidation" />
-        <Enum name="WAY3" start="0x3" description="Way 3 is selection for index invalidation" />
-      </BitField>
-    </Register>
-    <Register start="+0x28" size="4" name="CMCC_MCFG" access="Read/Write" description="Cache Monitor Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Cache Controller Monitor Counter Mode">
-        <Enum name="CYCLE_COUNT" start="0x0" description="cycle counter" />
-        <Enum name="IHIT_COUNT" start="0x1" description="instruction hit counter" />
-        <Enum name="DHIT_COUNT" start="0x2" description="data hit counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x2C" size="4" name="CMCC_MEN" access="Read/Write" description="Cache Monitor Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MENABLE" description="Cache Controller Monitor Enable" />
-    </Register>
-    <Register start="+0x30" size="4" name="CMCC_MCTRL" access="WriteOnly" description="Cache Monitor Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Cache Controller Software Reset" />
-    </Register>
-    <Register start="+0x34" size="4" name="CMCC_MSR" access="ReadOnly" description="Cache Monitor Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EVENT_CNT" description="Monitor Event Counter" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x43002400" description="Digital-to-Analog Converter">
-    <Register start="+0x00" size="1" name="DAC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable DAC Controller" />
-    </Register>
-    <Register start="+0x01" size="1" name="DAC_CTRLB" access="Read/Write" description="Control B" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIFF" description="Differential mode enable" />
-      <BitField start="1" size="2" name="REFSEL" description="Reference Selection for DAC0/1">
-        <Enum name="VREFPU" start="0x0" description="External reference unbuffered" />
-        <Enum name="VDDANA" start="0x1" description="Analog supply" />
-        <Enum name="VREFPB" start="0x2" description="External reference buffered" />
-        <Enum name="INTREF" start="0x3" description="Internal bandgap reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x02" size="1" name="DAC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTEI0" description="Start Conversion Event Input DAC 0" />
-      <BitField start="1" size="1" name="STARTEI1" description="Start Conversion Event Input DAC 1" />
-      <BitField start="2" size="1" name="EMPTYEO0" description="Data Buffer Empty Event Output DAC 0" />
-      <BitField start="3" size="1" name="EMPTYEO1" description="Data Buffer Empty Event Output DAC 1" />
-      <BitField start="4" size="1" name="INVEI0" description="Enable Invertion of DAC 0 input event" />
-      <BitField start="5" size="1" name="INVEI1" description="Enable Invertion of DAC 1 input event" />
-      <BitField start="6" size="1" name="RESRDYEO0" description="Result Ready Event Output 0" />
-      <BitField start="7" size="1" name="RESRDYEO1" description="Result Ready Event Output 1" />
-    </Register>
-    <Register start="+0x04" size="1" name="DAC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN0" description="Underrun 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="UNDERRUN1" description="Underrun 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="EMPTY0" description="Data Buffer 0 Empty Interrupt Enable" />
-      <BitField start="3" size="1" name="EMPTY1" description="Data Buffer 1 Empty Interrupt Enable" />
-      <BitField start="4" size="1" name="RESRDY0" description="Result 0 Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="RESRDY1" description="Result 1 Ready Interrupt Enable" />
-      <BitField start="6" size="1" name="OVERRUN0" description="Overrun 0 Interrupt Enable" />
-      <BitField start="7" size="1" name="OVERRUN1" description="Overrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="DAC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN0" description="Underrun 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="UNDERRUN1" description="Underrun 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="EMPTY0" description="Data Buffer 0 Empty Interrupt Enable" />
-      <BitField start="3" size="1" name="EMPTY1" description="Data Buffer 1 Empty Interrupt Enable" />
-      <BitField start="4" size="1" name="RESRDY0" description="Result 0 Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="RESRDY1" description="Result 1 Ready Interrupt Enable" />
-      <BitField start="6" size="1" name="OVERRUN0" description="Overrun 0 Interrupt Enable" />
-      <BitField start="7" size="1" name="OVERRUN1" description="Overrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="DAC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN0" description="Result 0 Underrun" />
-      <BitField start="1" size="1" name="UNDERRUN1" description="Result 1 Underrun" />
-      <BitField start="2" size="1" name="EMPTY0" description="Data Buffer 0 Empty" />
-      <BitField start="3" size="1" name="EMPTY1" description="Data Buffer 1 Empty" />
-      <BitField start="4" size="1" name="RESRDY0" description="Result 0 Ready" />
-      <BitField start="5" size="1" name="RESRDY1" description="Result 1 Ready" />
-      <BitField start="6" size="1" name="OVERRUN0" description="Result 0 Overrun" />
-      <BitField start="7" size="1" name="OVERRUN1" description="Result 1 Overrun" />
-    </Register>
-    <Register start="+0x07" size="1" name="DAC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY0" description="DAC 0 Startup Ready" />
-      <BitField start="1" size="1" name="READY1" description="DAC 1 Startup Ready" />
-      <BitField start="2" size="1" name="EOC0" description="DAC 0 End of Conversion" />
-      <BitField start="3" size="1" name="EOC1" description="DAC 1 End of Conversion" />
-    </Register>
-    <Register start="+0x08" size="4" name="DAC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="DAC Enable Status" />
-      <BitField start="2" size="1" name="DATA0" description="Data DAC 0" />
-      <BitField start="3" size="1" name="DATA1" description="Data DAC 1" />
-      <BitField start="4" size="1" name="DATABUF0" description="Data Buffer DAC 0" />
-      <BitField start="5" size="1" name="DATABUF1" description="Data Buffer DAC 1" />
-    </Register>
-    <Register start="+0x0C+0" size="2" name="DAC_DACCTRL0" access="Read/Write" description="DAC n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left Adjusted Data" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable DAC0" />
-      <BitField start="2" size="2" name="CCTRL" description="Current Control">
-        <Enum name="CC100K" start="0x0" description="GCLK_DAC &lt;= 1.2MHz (100kSPS)" />
-        <Enum name="CC1M" start="0x1" description="1.2MHz &lt; GCLK_DAC  &lt;= 6MHz (500kSPS)" />
-        <Enum name="CC12M" start="0x2" description="6MHz &lt; GCLK_DAC &lt;= 12MHz (1MSPS)" />
-      </BitField>
-      <BitField start="5" size="1" name="FEXT" description="Standalone Filter" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="DITHER" description="Dithering Mode" />
-      <BitField start="8" size="4" name="REFRESH" description="Refresh period" />
-      <BitField start="13" size="3" name="OSR" description="Sampling Rate" />
-    </Register>
-    <Register start="+0x0C+2" size="2" name="DAC_DACCTRL1" access="Read/Write" description="DAC n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left Adjusted Data" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable DAC0" />
-      <BitField start="2" size="2" name="CCTRL" description="Current Control">
-        <Enum name="CC100K" start="0x0" description="GCLK_DAC &lt;= 1.2MHz (100kSPS)" />
-        <Enum name="CC1M" start="0x1" description="1.2MHz &lt; GCLK_DAC  &lt;= 6MHz (500kSPS)" />
-        <Enum name="CC12M" start="0x2" description="6MHz &lt; GCLK_DAC &lt;= 12MHz (1MSPS)" />
-      </BitField>
-      <BitField start="5" size="1" name="FEXT" description="Standalone Filter" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="DITHER" description="Dithering Mode" />
-      <BitField start="8" size="4" name="REFRESH" description="Refresh period" />
-      <BitField start="13" size="3" name="OSR" description="Sampling Rate" />
-    </Register>
-    <Register start="+0x10+0" size="2" name="DAC_DATA0" access="WriteOnly" description="DAC n Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="DAC0 Data" />
-    </Register>
-    <Register start="+0x10+2" size="2" name="DAC_DATA1" access="WriteOnly" description="DAC n Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="DAC0 Data" />
-    </Register>
-    <Register start="+0x14+0" size="2" name="DAC_DATABUF0" access="WriteOnly" description="DAC n Data Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATABUF" description="DAC0 Data Buffer" />
-    </Register>
-    <Register start="+0x14+2" size="2" name="DAC_DATABUF1" access="WriteOnly" description="DAC n Data Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATABUF" description="DAC0 Data Buffer" />
-    </Register>
-    <Register start="+0x18" size="1" name="DAC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="DAC_RESULT0" access="ReadOnly" description="Filter Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Filter Result" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="DAC_RESULT1" access="ReadOnly" description="Filter Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Filter Result" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMAC" start="0x4100A000" description="Direct Memory Access Controller">
-    <Register start="+0x00" size="2" name="DMAC_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="DMAENABLE" description="DMA Enable" />
-      <BitField start="8" size="1" name="LVLEN0" description="Priority Level 0 Enable" />
-      <BitField start="9" size="1" name="LVLEN1" description="Priority Level 1 Enable" />
-      <BitField start="10" size="1" name="LVLEN2" description="Priority Level 2 Enable" />
-      <BitField start="11" size="1" name="LVLEN3" description="Priority Level 3 Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="DMAC_CRCCTRL" access="Read/Write" description="CRC Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRCBEATSIZE" description="CRC Beat Size">
-        <Enum name="BYTE" start="0x0" description="8-bit bus transfer" />
-        <Enum name="HWORD" start="0x1" description="16-bit bus transfer" />
-        <Enum name="WORD" start="0x2" description="32-bit bus transfer" />
-      </BitField>
-      <BitField start="2" size="2" name="CRCPOLY" description="CRC Polynomial Type">
-        <Enum name="CRC16" start="0x0" description="CRC-16 (CRC-CCITT)" />
-        <Enum name="CRC32" start="0x1" description="CRC32 (IEEE 802.3)" />
-      </BitField>
-      <BitField start="8" size="6" name="CRCSRC" description="CRC Input Source">
-        <Enum name="DISABLE" start="0x0" description="CRC Disabled" />
-        <Enum name="IO" start="0x1" description="I/O interface" />
-      </BitField>
-      <BitField start="14" size="2" name="CRCMODE" description="CRC Operating Mode">
-        <Enum name="DEFAULT" start="0x0" description="Default operating mode" />
-        <Enum name="CRCMON" start="0x2" description="Memory CRC monitor operating mode" />
-        <Enum name="CRCGEN" start="0x3" description="Memory CRC generation operating mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="DMAC_CRCDATAIN" access="Read/Write" description="CRC Data Input" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCDATAIN" description="CRC Data Input" />
-    </Register>
-    <Register start="+0x08" size="4" name="DMAC_CRCCHKSUM" access="Read/Write" description="CRC Checksum" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCCHKSUM" description="CRC Checksum" />
-    </Register>
-    <Register start="+0x0C" size="1" name="DMAC_CRCSTATUS" access="Read/Write" description="CRC Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCBUSY" description="CRC Module Busy" />
-      <BitField start="1" size="1" name="CRCZERO" description="CRC Zero" />
-      <BitField start="2" size="1" name="CRCERR" description="CRC Error" />
-    </Register>
-    <Register start="+0x0D" size="1" name="DMAC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x10" size="4" name="DMAC_SWTRIGCTRL" access="Read/Write" description="Software Trigger Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWTRIG0" description="Channel 0 Software Trigger" />
-      <BitField start="1" size="1" name="SWTRIG1" description="Channel 1 Software Trigger" />
-      <BitField start="2" size="1" name="SWTRIG2" description="Channel 2 Software Trigger" />
-      <BitField start="3" size="1" name="SWTRIG3" description="Channel 3 Software Trigger" />
-      <BitField start="4" size="1" name="SWTRIG4" description="Channel 4 Software Trigger" />
-      <BitField start="5" size="1" name="SWTRIG5" description="Channel 5 Software Trigger" />
-      <BitField start="6" size="1" name="SWTRIG6" description="Channel 6 Software Trigger" />
-      <BitField start="7" size="1" name="SWTRIG7" description="Channel 7 Software Trigger" />
-      <BitField start="8" size="1" name="SWTRIG8" description="Channel 8 Software Trigger" />
-      <BitField start="9" size="1" name="SWTRIG9" description="Channel 9 Software Trigger" />
-      <BitField start="10" size="1" name="SWTRIG10" description="Channel 10 Software Trigger" />
-      <BitField start="11" size="1" name="SWTRIG11" description="Channel 11 Software Trigger" />
-      <BitField start="12" size="1" name="SWTRIG12" description="Channel 12 Software Trigger" />
-      <BitField start="13" size="1" name="SWTRIG13" description="Channel 13 Software Trigger" />
-      <BitField start="14" size="1" name="SWTRIG14" description="Channel 14 Software Trigger" />
-      <BitField start="15" size="1" name="SWTRIG15" description="Channel 15 Software Trigger" />
-      <BitField start="16" size="1" name="SWTRIG16" description="Channel 16 Software Trigger" />
-      <BitField start="17" size="1" name="SWTRIG17" description="Channel 17 Software Trigger" />
-      <BitField start="18" size="1" name="SWTRIG18" description="Channel 18 Software Trigger" />
-      <BitField start="19" size="1" name="SWTRIG19" description="Channel 19 Software Trigger" />
-      <BitField start="20" size="1" name="SWTRIG20" description="Channel 20 Software Trigger" />
-      <BitField start="21" size="1" name="SWTRIG21" description="Channel 21 Software Trigger" />
-      <BitField start="22" size="1" name="SWTRIG22" description="Channel 22 Software Trigger" />
-      <BitField start="23" size="1" name="SWTRIG23" description="Channel 23 Software Trigger" />
-      <BitField start="24" size="1" name="SWTRIG24" description="Channel 24 Software Trigger" />
-      <BitField start="25" size="1" name="SWTRIG25" description="Channel 25 Software Trigger" />
-      <BitField start="26" size="1" name="SWTRIG26" description="Channel 26 Software Trigger" />
-      <BitField start="27" size="1" name="SWTRIG27" description="Channel 27 Software Trigger" />
-      <BitField start="28" size="1" name="SWTRIG28" description="Channel 28 Software Trigger" />
-      <BitField start="29" size="1" name="SWTRIG29" description="Channel 29 Software Trigger" />
-      <BitField start="30" size="1" name="SWTRIG30" description="Channel 30 Software Trigger" />
-      <BitField start="31" size="1" name="SWTRIG31" description="Channel 31 Software Trigger" />
-    </Register>
-    <Register start="+0x14" size="4" name="DMAC_PRICTRL0" access="Read/Write" description="Priority Control 0" reset_value="0x40404040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="LVLPRI0" description="Level 0 Channel Priority Number" />
-      <BitField start="5" size="2" name="QOS0" description="Level 0 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="7" size="1" name="RRLVLEN0" description="Level 0 Round-Robin Scheduling Enable" />
-      <BitField start="8" size="5" name="LVLPRI1" description="Level 1 Channel Priority Number" />
-      <BitField start="13" size="2" name="QOS1" description="Level 1 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="15" size="1" name="RRLVLEN1" description="Level 1 Round-Robin Scheduling Enable" />
-      <BitField start="16" size="5" name="LVLPRI2" description="Level 2 Channel Priority Number" />
-      <BitField start="21" size="2" name="QOS2" description="Level 2 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="23" size="1" name="RRLVLEN2" description="Level 2 Round-Robin Scheduling Enable" />
-      <BitField start="24" size="5" name="LVLPRI3" description="Level 3 Channel Priority Number" />
-      <BitField start="29" size="2" name="QOS3" description="Level 3 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="31" size="1" name="RRLVLEN3" description="Level 3 Round-Robin Scheduling Enable" />
-    </Register>
-    <Register start="+0x20" size="2" name="DMAC_INTPEND" access="Read/Write" description="Interrupt Pending" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ID" description="Channel ID" />
-      <BitField start="8" size="1" name="TERR" description="Transfer Error" />
-      <BitField start="9" size="1" name="TCMPL" description="Transfer Complete" />
-      <BitField start="10" size="1" name="SUSP" description="Channel Suspend" />
-      <BitField start="12" size="1" name="CRCERR" description="CRC Error" />
-      <BitField start="13" size="1" name="FERR" description="Fetch Error" />
-      <BitField start="14" size="1" name="BUSY" description="Busy" />
-      <BitField start="15" size="1" name="PEND" description="Pending" />
-    </Register>
-    <Register start="+0x24" size="4" name="DMAC_INTSTATUS" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHINT0" description="Channel 0 Pending Interrupt" />
-      <BitField start="1" size="1" name="CHINT1" description="Channel 1 Pending Interrupt" />
-      <BitField start="2" size="1" name="CHINT2" description="Channel 2 Pending Interrupt" />
-      <BitField start="3" size="1" name="CHINT3" description="Channel 3 Pending Interrupt" />
-      <BitField start="4" size="1" name="CHINT4" description="Channel 4 Pending Interrupt" />
-      <BitField start="5" size="1" name="CHINT5" description="Channel 5 Pending Interrupt" />
-      <BitField start="6" size="1" name="CHINT6" description="Channel 6 Pending Interrupt" />
-      <BitField start="7" size="1" name="CHINT7" description="Channel 7 Pending Interrupt" />
-      <BitField start="8" size="1" name="CHINT8" description="Channel 8 Pending Interrupt" />
-      <BitField start="9" size="1" name="CHINT9" description="Channel 9 Pending Interrupt" />
-      <BitField start="10" size="1" name="CHINT10" description="Channel 10 Pending Interrupt" />
-      <BitField start="11" size="1" name="CHINT11" description="Channel 11 Pending Interrupt" />
-      <BitField start="12" size="1" name="CHINT12" description="Channel 12 Pending Interrupt" />
-      <BitField start="13" size="1" name="CHINT13" description="Channel 13 Pending Interrupt" />
-      <BitField start="14" size="1" name="CHINT14" description="Channel 14 Pending Interrupt" />
-      <BitField start="15" size="1" name="CHINT15" description="Channel 15 Pending Interrupt" />
-      <BitField start="16" size="1" name="CHINT16" description="Channel 16 Pending Interrupt" />
-      <BitField start="17" size="1" name="CHINT17" description="Channel 17 Pending Interrupt" />
-      <BitField start="18" size="1" name="CHINT18" description="Channel 18 Pending Interrupt" />
-      <BitField start="19" size="1" name="CHINT19" description="Channel 19 Pending Interrupt" />
-      <BitField start="20" size="1" name="CHINT20" description="Channel 20 Pending Interrupt" />
-      <BitField start="21" size="1" name="CHINT21" description="Channel 21 Pending Interrupt" />
-      <BitField start="22" size="1" name="CHINT22" description="Channel 22 Pending Interrupt" />
-      <BitField start="23" size="1" name="CHINT23" description="Channel 23 Pending Interrupt" />
-      <BitField start="24" size="1" name="CHINT24" description="Channel 24 Pending Interrupt" />
-      <BitField start="25" size="1" name="CHINT25" description="Channel 25 Pending Interrupt" />
-      <BitField start="26" size="1" name="CHINT26" description="Channel 26 Pending Interrupt" />
-      <BitField start="27" size="1" name="CHINT27" description="Channel 27 Pending Interrupt" />
-      <BitField start="28" size="1" name="CHINT28" description="Channel 28 Pending Interrupt" />
-      <BitField start="29" size="1" name="CHINT29" description="Channel 29 Pending Interrupt" />
-      <BitField start="30" size="1" name="CHINT30" description="Channel 30 Pending Interrupt" />
-      <BitField start="31" size="1" name="CHINT31" description="Channel 31 Pending Interrupt" />
-    </Register>
-    <Register start="+0x28" size="4" name="DMAC_BUSYCH" access="ReadOnly" description="Busy Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSYCH0" description="Busy Channel 0" />
-      <BitField start="1" size="1" name="BUSYCH1" description="Busy Channel 1" />
-      <BitField start="2" size="1" name="BUSYCH2" description="Busy Channel 2" />
-      <BitField start="3" size="1" name="BUSYCH3" description="Busy Channel 3" />
-      <BitField start="4" size="1" name="BUSYCH4" description="Busy Channel 4" />
-      <BitField start="5" size="1" name="BUSYCH5" description="Busy Channel 5" />
-      <BitField start="6" size="1" name="BUSYCH6" description="Busy Channel 6" />
-      <BitField start="7" size="1" name="BUSYCH7" description="Busy Channel 7" />
-      <BitField start="8" size="1" name="BUSYCH8" description="Busy Channel 8" />
-      <BitField start="9" size="1" name="BUSYCH9" description="Busy Channel 9" />
-      <BitField start="10" size="1" name="BUSYCH10" description="Busy Channel 10" />
-      <BitField start="11" size="1" name="BUSYCH11" description="Busy Channel 11" />
-      <BitField start="12" size="1" name="BUSYCH12" description="Busy Channel 12" />
-      <BitField start="13" size="1" name="BUSYCH13" description="Busy Channel 13" />
-      <BitField start="14" size="1" name="BUSYCH14" description="Busy Channel 14" />
-      <BitField start="15" size="1" name="BUSYCH15" description="Busy Channel 15" />
-      <BitField start="16" size="1" name="BUSYCH16" description="Busy Channel 16" />
-      <BitField start="17" size="1" name="BUSYCH17" description="Busy Channel 17" />
-      <BitField start="18" size="1" name="BUSYCH18" description="Busy Channel 18" />
-      <BitField start="19" size="1" name="BUSYCH19" description="Busy Channel 19" />
-      <BitField start="20" size="1" name="BUSYCH20" description="Busy Channel 20" />
-      <BitField start="21" size="1" name="BUSYCH21" description="Busy Channel 21" />
-      <BitField start="22" size="1" name="BUSYCH22" description="Busy Channel 22" />
-      <BitField start="23" size="1" name="BUSYCH23" description="Busy Channel 23" />
-      <BitField start="24" size="1" name="BUSYCH24" description="Busy Channel 24" />
-      <BitField start="25" size="1" name="BUSYCH25" description="Busy Channel 25" />
-      <BitField start="26" size="1" name="BUSYCH26" description="Busy Channel 26" />
-      <BitField start="27" size="1" name="BUSYCH27" description="Busy Channel 27" />
-      <BitField start="28" size="1" name="BUSYCH28" description="Busy Channel 28" />
-      <BitField start="29" size="1" name="BUSYCH29" description="Busy Channel 29" />
-      <BitField start="30" size="1" name="BUSYCH30" description="Busy Channel 30" />
-      <BitField start="31" size="1" name="BUSYCH31" description="Busy Channel 31" />
-    </Register>
-    <Register start="+0x2C" size="4" name="DMAC_PENDCH" access="ReadOnly" description="Pending Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PENDCH0" description="Pending Channel 0" />
-      <BitField start="1" size="1" name="PENDCH1" description="Pending Channel 1" />
-      <BitField start="2" size="1" name="PENDCH2" description="Pending Channel 2" />
-      <BitField start="3" size="1" name="PENDCH3" description="Pending Channel 3" />
-      <BitField start="4" size="1" name="PENDCH4" description="Pending Channel 4" />
-      <BitField start="5" size="1" name="PENDCH5" description="Pending Channel 5" />
-      <BitField start="6" size="1" name="PENDCH6" description="Pending Channel 6" />
-      <BitField start="7" size="1" name="PENDCH7" description="Pending Channel 7" />
-      <BitField start="8" size="1" name="PENDCH8" description="Pending Channel 8" />
-      <BitField start="9" size="1" name="PENDCH9" description="Pending Channel 9" />
-      <BitField start="10" size="1" name="PENDCH10" description="Pending Channel 10" />
-      <BitField start="11" size="1" name="PENDCH11" description="Pending Channel 11" />
-      <BitField start="12" size="1" name="PENDCH12" description="Pending Channel 12" />
-      <BitField start="13" size="1" name="PENDCH13" description="Pending Channel 13" />
-      <BitField start="14" size="1" name="PENDCH14" description="Pending Channel 14" />
-      <BitField start="15" size="1" name="PENDCH15" description="Pending Channel 15" />
-      <BitField start="16" size="1" name="PENDCH16" description="Pending Channel 16" />
-      <BitField start="17" size="1" name="PENDCH17" description="Pending Channel 17" />
-      <BitField start="18" size="1" name="PENDCH18" description="Pending Channel 18" />
-      <BitField start="19" size="1" name="PENDCH19" description="Pending Channel 19" />
-      <BitField start="20" size="1" name="PENDCH20" description="Pending Channel 20" />
-      <BitField start="21" size="1" name="PENDCH21" description="Pending Channel 21" />
-      <BitField start="22" size="1" name="PENDCH22" description="Pending Channel 22" />
-      <BitField start="23" size="1" name="PENDCH23" description="Pending Channel 23" />
-      <BitField start="24" size="1" name="PENDCH24" description="Pending Channel 24" />
-      <BitField start="25" size="1" name="PENDCH25" description="Pending Channel 25" />
-      <BitField start="26" size="1" name="PENDCH26" description="Pending Channel 26" />
-      <BitField start="27" size="1" name="PENDCH27" description="Pending Channel 27" />
-      <BitField start="28" size="1" name="PENDCH28" description="Pending Channel 28" />
-      <BitField start="29" size="1" name="PENDCH29" description="Pending Channel 29" />
-      <BitField start="30" size="1" name="PENDCH30" description="Pending Channel 30" />
-      <BitField start="31" size="1" name="PENDCH31" description="Pending Channel 31" />
-    </Register>
-    <Register start="+0x30" size="4" name="DMAC_ACTIVE" access="ReadOnly" description="Active Channel and Levels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LVLEX0" description="Level 0 Channel Trigger Request Executing" />
-      <BitField start="1" size="1" name="LVLEX1" description="Level 1 Channel Trigger Request Executing" />
-      <BitField start="2" size="1" name="LVLEX2" description="Level 2 Channel Trigger Request Executing" />
-      <BitField start="3" size="1" name="LVLEX3" description="Level 3 Channel Trigger Request Executing" />
-      <BitField start="8" size="5" name="ID" description="Active Channel ID" />
-      <BitField start="15" size="1" name="ABUSY" description="Active Channel Busy" />
-      <BitField start="16" size="16" name="BTCNT" description="Active Channel Block Transfer Count" />
-    </Register>
-    <Register start="+0x34" size="4" name="DMAC_BASEADDR" access="Read/Write" description="Descriptor Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASEADDR" description="Descriptor Memory Base Address" />
-    </Register>
-    <Register start="+0x38" size="4" name="DMAC_WRBADDR" access="Read/Write" description="Write-Back Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WRBADDR" description="Write-Back Memory Base Address" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="DMAC_CHCTRLA0" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+16" size="4" name="DMAC_CHCTRLA1" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+32" size="4" name="DMAC_CHCTRLA2" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+48" size="4" name="DMAC_CHCTRLA3" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+64" size="4" name="DMAC_CHCTRLA4" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+80" size="4" name="DMAC_CHCTRLA5" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+96" size="4" name="DMAC_CHCTRLA6" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+112" size="4" name="DMAC_CHCTRLA7" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+128" size="4" name="DMAC_CHCTRLA8" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+144" size="4" name="DMAC_CHCTRLA9" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+160" size="4" name="DMAC_CHCTRLA10" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+176" size="4" name="DMAC_CHCTRLA11" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+192" size="4" name="DMAC_CHCTRLA12" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+208" size="4" name="DMAC_CHCTRLA13" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+224" size="4" name="DMAC_CHCTRLA14" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+240" size="4" name="DMAC_CHCTRLA15" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+256" size="4" name="DMAC_CHCTRLA16" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+272" size="4" name="DMAC_CHCTRLA17" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+288" size="4" name="DMAC_CHCTRLA18" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+304" size="4" name="DMAC_CHCTRLA19" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+320" size="4" name="DMAC_CHCTRLA20" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+336" size="4" name="DMAC_CHCTRLA21" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+352" size="4" name="DMAC_CHCTRLA22" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+368" size="4" name="DMAC_CHCTRLA23" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+384" size="4" name="DMAC_CHCTRLA24" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+400" size="4" name="DMAC_CHCTRLA25" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+416" size="4" name="DMAC_CHCTRLA26" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+432" size="4" name="DMAC_CHCTRLA27" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+448" size="4" name="DMAC_CHCTRLA28" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+464" size="4" name="DMAC_CHCTRLA29" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+480" size="4" name="DMAC_CHCTRLA30" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+496" size="4" name="DMAC_CHCTRLA31" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+0" size="1" name="DMAC_CHCTRLB0" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+16" size="1" name="DMAC_CHCTRLB1" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+32" size="1" name="DMAC_CHCTRLB2" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+48" size="1" name="DMAC_CHCTRLB3" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+64" size="1" name="DMAC_CHCTRLB4" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+80" size="1" name="DMAC_CHCTRLB5" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+96" size="1" name="DMAC_CHCTRLB6" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+112" size="1" name="DMAC_CHCTRLB7" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+128" size="1" name="DMAC_CHCTRLB8" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+144" size="1" name="DMAC_CHCTRLB9" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+160" size="1" name="DMAC_CHCTRLB10" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+176" size="1" name="DMAC_CHCTRLB11" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+192" size="1" name="DMAC_CHCTRLB12" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+208" size="1" name="DMAC_CHCTRLB13" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+224" size="1" name="DMAC_CHCTRLB14" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+240" size="1" name="DMAC_CHCTRLB15" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+256" size="1" name="DMAC_CHCTRLB16" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+272" size="1" name="DMAC_CHCTRLB17" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+288" size="1" name="DMAC_CHCTRLB18" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+304" size="1" name="DMAC_CHCTRLB19" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+320" size="1" name="DMAC_CHCTRLB20" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+336" size="1" name="DMAC_CHCTRLB21" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+352" size="1" name="DMAC_CHCTRLB22" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+368" size="1" name="DMAC_CHCTRLB23" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+384" size="1" name="DMAC_CHCTRLB24" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+400" size="1" name="DMAC_CHCTRLB25" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+416" size="1" name="DMAC_CHCTRLB26" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+432" size="1" name="DMAC_CHCTRLB27" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+448" size="1" name="DMAC_CHCTRLB28" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+464" size="1" name="DMAC_CHCTRLB29" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+480" size="1" name="DMAC_CHCTRLB30" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+496" size="1" name="DMAC_CHCTRLB31" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+0" size="1" name="DMAC_CHPRILVL0" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+16" size="1" name="DMAC_CHPRILVL1" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+32" size="1" name="DMAC_CHPRILVL2" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+48" size="1" name="DMAC_CHPRILVL3" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+64" size="1" name="DMAC_CHPRILVL4" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+80" size="1" name="DMAC_CHPRILVL5" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+96" size="1" name="DMAC_CHPRILVL6" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+112" size="1" name="DMAC_CHPRILVL7" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+128" size="1" name="DMAC_CHPRILVL8" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+144" size="1" name="DMAC_CHPRILVL9" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+160" size="1" name="DMAC_CHPRILVL10" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+176" size="1" name="DMAC_CHPRILVL11" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+192" size="1" name="DMAC_CHPRILVL12" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+208" size="1" name="DMAC_CHPRILVL13" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+224" size="1" name="DMAC_CHPRILVL14" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+240" size="1" name="DMAC_CHPRILVL15" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+256" size="1" name="DMAC_CHPRILVL16" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+272" size="1" name="DMAC_CHPRILVL17" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+288" size="1" name="DMAC_CHPRILVL18" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+304" size="1" name="DMAC_CHPRILVL19" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+320" size="1" name="DMAC_CHPRILVL20" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+336" size="1" name="DMAC_CHPRILVL21" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+352" size="1" name="DMAC_CHPRILVL22" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+368" size="1" name="DMAC_CHPRILVL23" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+384" size="1" name="DMAC_CHPRILVL24" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+400" size="1" name="DMAC_CHPRILVL25" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+416" size="1" name="DMAC_CHPRILVL26" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+432" size="1" name="DMAC_CHPRILVL27" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+448" size="1" name="DMAC_CHPRILVL28" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+464" size="1" name="DMAC_CHPRILVL29" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+480" size="1" name="DMAC_CHPRILVL30" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+496" size="1" name="DMAC_CHPRILVL31" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x46+0" size="1" name="DMAC_CHEVCTRL0" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+16" size="1" name="DMAC_CHEVCTRL1" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+32" size="1" name="DMAC_CHEVCTRL2" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+48" size="1" name="DMAC_CHEVCTRL3" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+64" size="1" name="DMAC_CHEVCTRL4" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+80" size="1" name="DMAC_CHEVCTRL5" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+96" size="1" name="DMAC_CHEVCTRL6" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+112" size="1" name="DMAC_CHEVCTRL7" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+128" size="1" name="DMAC_CHEVCTRL8" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+144" size="1" name="DMAC_CHEVCTRL9" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+160" size="1" name="DMAC_CHEVCTRL10" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+176" size="1" name="DMAC_CHEVCTRL11" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+192" size="1" name="DMAC_CHEVCTRL12" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+208" size="1" name="DMAC_CHEVCTRL13" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+224" size="1" name="DMAC_CHEVCTRL14" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+240" size="1" name="DMAC_CHEVCTRL15" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+256" size="1" name="DMAC_CHEVCTRL16" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+272" size="1" name="DMAC_CHEVCTRL17" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+288" size="1" name="DMAC_CHEVCTRL18" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+304" size="1" name="DMAC_CHEVCTRL19" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+320" size="1" name="DMAC_CHEVCTRL20" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+336" size="1" name="DMAC_CHEVCTRL21" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+352" size="1" name="DMAC_CHEVCTRL22" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+368" size="1" name="DMAC_CHEVCTRL23" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+384" size="1" name="DMAC_CHEVCTRL24" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+400" size="1" name="DMAC_CHEVCTRL25" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+416" size="1" name="DMAC_CHEVCTRL26" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+432" size="1" name="DMAC_CHEVCTRL27" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+448" size="1" name="DMAC_CHEVCTRL28" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+464" size="1" name="DMAC_CHEVCTRL29" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+480" size="1" name="DMAC_CHEVCTRL30" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+496" size="1" name="DMAC_CHEVCTRL31" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x4C+0" size="1" name="DMAC_CHINTENCLR0" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+16" size="1" name="DMAC_CHINTENCLR1" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+32" size="1" name="DMAC_CHINTENCLR2" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+48" size="1" name="DMAC_CHINTENCLR3" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+64" size="1" name="DMAC_CHINTENCLR4" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+80" size="1" name="DMAC_CHINTENCLR5" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+96" size="1" name="DMAC_CHINTENCLR6" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+112" size="1" name="DMAC_CHINTENCLR7" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+128" size="1" name="DMAC_CHINTENCLR8" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+144" size="1" name="DMAC_CHINTENCLR9" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+160" size="1" name="DMAC_CHINTENCLR10" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+176" size="1" name="DMAC_CHINTENCLR11" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+192" size="1" name="DMAC_CHINTENCLR12" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+208" size="1" name="DMAC_CHINTENCLR13" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+224" size="1" name="DMAC_CHINTENCLR14" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+240" size="1" name="DMAC_CHINTENCLR15" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+256" size="1" name="DMAC_CHINTENCLR16" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+272" size="1" name="DMAC_CHINTENCLR17" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+288" size="1" name="DMAC_CHINTENCLR18" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+304" size="1" name="DMAC_CHINTENCLR19" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+320" size="1" name="DMAC_CHINTENCLR20" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+336" size="1" name="DMAC_CHINTENCLR21" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+352" size="1" name="DMAC_CHINTENCLR22" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+368" size="1" name="DMAC_CHINTENCLR23" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+384" size="1" name="DMAC_CHINTENCLR24" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+400" size="1" name="DMAC_CHINTENCLR25" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+416" size="1" name="DMAC_CHINTENCLR26" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+432" size="1" name="DMAC_CHINTENCLR27" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+448" size="1" name="DMAC_CHINTENCLR28" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+464" size="1" name="DMAC_CHINTENCLR29" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+480" size="1" name="DMAC_CHINTENCLR30" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+496" size="1" name="DMAC_CHINTENCLR31" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+0" size="1" name="DMAC_CHINTENSET0" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+16" size="1" name="DMAC_CHINTENSET1" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+32" size="1" name="DMAC_CHINTENSET2" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+48" size="1" name="DMAC_CHINTENSET3" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+64" size="1" name="DMAC_CHINTENSET4" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+80" size="1" name="DMAC_CHINTENSET5" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+96" size="1" name="DMAC_CHINTENSET6" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+112" size="1" name="DMAC_CHINTENSET7" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+128" size="1" name="DMAC_CHINTENSET8" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+144" size="1" name="DMAC_CHINTENSET9" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+160" size="1" name="DMAC_CHINTENSET10" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+176" size="1" name="DMAC_CHINTENSET11" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+192" size="1" name="DMAC_CHINTENSET12" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+208" size="1" name="DMAC_CHINTENSET13" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+224" size="1" name="DMAC_CHINTENSET14" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+240" size="1" name="DMAC_CHINTENSET15" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+256" size="1" name="DMAC_CHINTENSET16" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+272" size="1" name="DMAC_CHINTENSET17" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+288" size="1" name="DMAC_CHINTENSET18" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+304" size="1" name="DMAC_CHINTENSET19" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+320" size="1" name="DMAC_CHINTENSET20" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+336" size="1" name="DMAC_CHINTENSET21" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+352" size="1" name="DMAC_CHINTENSET22" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+368" size="1" name="DMAC_CHINTENSET23" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+384" size="1" name="DMAC_CHINTENSET24" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+400" size="1" name="DMAC_CHINTENSET25" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+416" size="1" name="DMAC_CHINTENSET26" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+432" size="1" name="DMAC_CHINTENSET27" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+448" size="1" name="DMAC_CHINTENSET28" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+464" size="1" name="DMAC_CHINTENSET29" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+480" size="1" name="DMAC_CHINTENSET30" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+496" size="1" name="DMAC_CHINTENSET31" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4E+0" size="1" name="DMAC_CHINTFLAG0" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+16" size="1" name="DMAC_CHINTFLAG1" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+32" size="1" name="DMAC_CHINTFLAG2" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+48" size="1" name="DMAC_CHINTFLAG3" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+64" size="1" name="DMAC_CHINTFLAG4" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+80" size="1" name="DMAC_CHINTFLAG5" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+96" size="1" name="DMAC_CHINTFLAG6" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+112" size="1" name="DMAC_CHINTFLAG7" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+128" size="1" name="DMAC_CHINTFLAG8" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+144" size="1" name="DMAC_CHINTFLAG9" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+160" size="1" name="DMAC_CHINTFLAG10" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+176" size="1" name="DMAC_CHINTFLAG11" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+192" size="1" name="DMAC_CHINTFLAG12" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+208" size="1" name="DMAC_CHINTFLAG13" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+224" size="1" name="DMAC_CHINTFLAG14" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+240" size="1" name="DMAC_CHINTFLAG15" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+256" size="1" name="DMAC_CHINTFLAG16" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+272" size="1" name="DMAC_CHINTFLAG17" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+288" size="1" name="DMAC_CHINTFLAG18" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+304" size="1" name="DMAC_CHINTFLAG19" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+320" size="1" name="DMAC_CHINTFLAG20" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+336" size="1" name="DMAC_CHINTFLAG21" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+352" size="1" name="DMAC_CHINTFLAG22" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+368" size="1" name="DMAC_CHINTFLAG23" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+384" size="1" name="DMAC_CHINTFLAG24" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+400" size="1" name="DMAC_CHINTFLAG25" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+416" size="1" name="DMAC_CHINTFLAG26" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+432" size="1" name="DMAC_CHINTFLAG27" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+448" size="1" name="DMAC_CHINTFLAG28" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+464" size="1" name="DMAC_CHINTFLAG29" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+480" size="1" name="DMAC_CHINTFLAG30" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+496" size="1" name="DMAC_CHINTFLAG31" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4F+0" size="1" name="DMAC_CHSTATUS0" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+16" size="1" name="DMAC_CHSTATUS1" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+32" size="1" name="DMAC_CHSTATUS2" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+48" size="1" name="DMAC_CHSTATUS3" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+64" size="1" name="DMAC_CHSTATUS4" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+80" size="1" name="DMAC_CHSTATUS5" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+96" size="1" name="DMAC_CHSTATUS6" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+112" size="1" name="DMAC_CHSTATUS7" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+128" size="1" name="DMAC_CHSTATUS8" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+144" size="1" name="DMAC_CHSTATUS9" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+160" size="1" name="DMAC_CHSTATUS10" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+176" size="1" name="DMAC_CHSTATUS11" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+192" size="1" name="DMAC_CHSTATUS12" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+208" size="1" name="DMAC_CHSTATUS13" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+224" size="1" name="DMAC_CHSTATUS14" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+240" size="1" name="DMAC_CHSTATUS15" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+256" size="1" name="DMAC_CHSTATUS16" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+272" size="1" name="DMAC_CHSTATUS17" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+288" size="1" name="DMAC_CHSTATUS18" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+304" size="1" name="DMAC_CHSTATUS19" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+320" size="1" name="DMAC_CHSTATUS20" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+336" size="1" name="DMAC_CHSTATUS21" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+352" size="1" name="DMAC_CHSTATUS22" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+368" size="1" name="DMAC_CHSTATUS23" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+384" size="1" name="DMAC_CHSTATUS24" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+400" size="1" name="DMAC_CHSTATUS25" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+416" size="1" name="DMAC_CHSTATUS26" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+432" size="1" name="DMAC_CHSTATUS27" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+448" size="1" name="DMAC_CHSTATUS28" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+464" size="1" name="DMAC_CHSTATUS29" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+480" size="1" name="DMAC_CHSTATUS30" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+496" size="1" name="DMAC_CHSTATUS31" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DSU" start="0x41002000" description="Device Service Unit">
-    <Register start="+0x0000" size="1" name="DSU_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="2" size="1" name="CRC" description="32-bit Cyclic Redundancy Code" />
-      <BitField start="3" size="1" name="MBIST" description="Memory built-in self-test" />
-      <BitField start="4" size="1" name="CE" description="Chip-Erase" />
-      <BitField start="6" size="1" name="ARR" description="Auxiliary Row Read" />
-      <BitField start="7" size="1" name="SMSA" description="Start Memory Stream Access" />
-    </Register>
-    <Register start="+0x0001" size="1" name="DSU_STATUSA" access="Read/Write" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Done" />
-      <BitField start="1" size="1" name="CRSTEXT" description="CPU Reset Phase Extension" />
-      <BitField start="2" size="1" name="BERR" description="Bus Error" />
-      <BitField start="3" size="1" name="FAIL" description="Failure" />
-      <BitField start="4" size="1" name="PERR" description="Protection Error" />
-    </Register>
-    <Register start="+0x0002" size="1" name="DSU_STATUSB" access="ReadOnly" description="Status B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PROT" description="Protected" />
-      <BitField start="1" size="1" name="DBGPRES" description="Debugger Present" />
-      <BitField start="2" size="1" name="DCCD0" description="Debug Communication Channel 0 Dirty" />
-      <BitField start="3" size="1" name="DCCD1" description="Debug Communication Channel 1 Dirty" />
-      <BitField start="4" size="1" name="HPE" description="Hot-Plugging Enable" />
-      <BitField start="5" size="1" name="CELCK" description="Chip Erase Locked" />
-      <BitField start="6" size="1" name="TDCCD0" description="Test Debug Communication Channel 0 Dirty" />
-      <BitField start="7" size="1" name="TDCCD1" description="Test Debug Communication Channel 1 Dirty" />
-    </Register>
-    <Register start="+0x0004" size="4" name="DSU_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AMOD" description="Access Mode" />
-      <BitField start="2" size="30" name="ADDR" description="Address" />
-    </Register>
-    <Register start="+0x0008" size="4" name="DSU_LENGTH" access="Read/Write" description="Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="30" name="LENGTH" description="Length" />
-    </Register>
-    <Register start="+0x000C" size="4" name="DSU_DATA" access="Read/Write" description="Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+0" size="4" name="DSU_DCC0" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+4" size="4" name="DSU_DCC1" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0018" size="4" name="DSU_DID" access="ReadOnly" description="Device Identification" reset_value="0x60060005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEVSEL" description="Device Select" />
-      <BitField start="8" size="4" name="REVISION" description="Revision Number" />
-      <BitField start="12" size="4" name="DIE" description="Die Number" />
-      <BitField start="16" size="6" name="SERIES" description="Series">
-        <Enum name="0" start="0x0" description="Cortex-M0+ processor, basic feature set" />
-        <Enum name="1" start="0x1" description="Cortex-M0+ processor, USB" />
-      </BitField>
-      <BitField start="23" size="5" name="FAMILY" description="Family">
-        <Enum name="0" start="0x0" description="General purpose microcontroller" />
-        <Enum name="1" start="0x1" description="PicoPower" />
-      </BitField>
-      <BitField start="28" size="4" name="PROCESSOR" description="Processor">
-        <Enum name="CM0P" start="0x1" description="Cortex-M0+" />
-        <Enum name="CM23" start="0x2" description="Cortex-M23" />
-        <Enum name="CM3" start="0x3" description="Cortex-M3" />
-        <Enum name="CM4" start="0x5" description="Cortex-M4" />
-        <Enum name="CM4F" start="0x6" description="Cortex-M4 with FPU" />
-        <Enum name="CM33" start="0x7" description="Cortex-M33" />
-      </BitField>
-    </Register>
-    <Register start="+0x001C" size="4" name="DSU_CFG" access="Read/Write" description="Configuration" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LQOS" description="Latency Quality Of Service" />
-      <BitField start="2" size="2" name="DCCDMALEVEL" description="DMA Trigger Level">
-        <Enum name="EMPTY" start="0x0" description="Trigger rises when DCC is empty" />
-        <Enum name="FULL" start="0x1" description="Trigger rises when DCC is full" />
-      </BitField>
-      <BitField start="4" size="1" name="ETBRAMEN" description="Trace Control" />
-    </Register>
-    <Register start="+0x0040" size="4" name="DSU_MBCTRL" access="Read/Write" description="MBIST Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="MBIST Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="MBIST Enable" />
-    </Register>
-    <Register start="+0x0044" size="4" name="DSU_MBCONFIG" access="Read/Write" description="MBIST Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ALGO" description="MBIST Algorithm">
-        <Enum name="MEMCLEAR" start="0x0" description="Memory Clear (1n)" />
-        <Enum name="VERIFY" start="0x1" description="Memory Verify (1n)" />
-        <Enum name="CLEARVER" start="0x2" description="Memory Clear and Verify (2n)" />
-        <Enum name="ADDR_DEC" start="0x3" description="Address Decoder (2n)" />
-        <Enum name="MARCH_LR" start="0x4" description="March LR (14n)" />
-        <Enum name="MARCH_SR" start="0x5" description="March SR (14n)" />
-        <Enum name="MARCH_SS" start="0x6" description="March SS (22n)" />
-        <Enum name="CRC_UP" start="0x8" description="CRC increasing address (1n)" />
-        <Enum name="CRC_DOWN" start="0x9" description="CRC decreasing address (1n)" />
-      </BitField>
-      <BitField start="6" size="1" name="DEFRDMARGIN" description="Force Default Read Margin" />
-      <BitField start="7" size="1" name="DBG" description="Enable Debug Mode" />
-    </Register>
-    <Register start="+0x0048" size="4" name="DSU_MBWORD" access="Read/Write" description="MBIST Background Word" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="MBIST Background Word" />
-    </Register>
-    <Register start="+0x004C" size="4" name="DSU_MBGSTAT" access="Read/Write" description="MBIST Global Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALLDONE" description="MBIST Completed" />
-      <BitField start="1" size="1" name="FAILED" description="MBIST Failed" />
-      <BitField start="2" size="1" name="ERRINFO" description="MBIST Error Info Present" />
-      <BitField start="3" size="1" name="CONFIGURED" description="MBIST Configuration Sent" />
-    </Register>
-    <Register start="+0x0050" size="4" name="DSU_MBDFAIL" access="ReadOnly" description="MBIST Fail Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Error Data Read" />
-    </Register>
-    <Register start="+0x0054" size="4" name="DSU_MBDEXP" access="ReadOnly" description="MBIST Expected Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Expected Data" />
-    </Register>
-    <Register start="+0x0058" size="4" name="DSU_MBAFAIL" access="ReadOnly" description="MBIST Fail Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="ADDR" description="Error Address" />
-    </Register>
-    <Register start="+0x005C" size="4" name="DSU_MBCONTEXT" access="ReadOnly" description="MBIST Fail Context" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="SUBSTEP" description="Algorithm Sub-step">
-        <Enum name="R0_1" start="0x1" />
-        <Enum name="R1_1" start="0x3" />
-        <Enum name="R0_2" start="0x5" />
-        <Enum name="R1_2" start="0x7" />
-        <Enum name="R0_3" start="0x9" />
-        <Enum name="R1_3" start="0xb" />
-      </BitField>
-      <BitField start="5" size="5" name="STEP" description="Algorithm Step">
-        <Enum name="DOWN_R0W1" start="0x2" />
-        <Enum name="UP_R1W0R0W1" start="0x3" />
-        <Enum name="UP_R1W0" start="0x4" />
-        <Enum name="UP_R0W1R1W0" start="0x5" />
-        <Enum name="UP_R0" start="0x6" />
-        <Enum name="UP_R0R0W0R0W1" start="0x7" />
-        <Enum name="UP_R1R1W1R1W0" start="0x8" />
-        <Enum name="DOWN_R0R0W0R0W1" start="0x9" />
-        <Enum name="DOWN_R1R1W1R1W0" start="0xa" />
-        <Enum name="UP_R0R0" start="0xc" />
-        <Enum name="DOWN_R1W0R0W1" start="0xe" />
-        <Enum name="DOWN_R1R1" start="0xf" />
-      </BitField>
-      <BitField start="10" size="1" name="PORT" description="DPRAM Port Index" />
-    </Register>
-    <Register start="+0x0060" size="4" name="DSU_MBENABLE0" access="Read/Write" description="MBIST Memory Enable 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE0" description="Memory 0 MBIST Enable" />
-      <BitField start="1" size="1" name="ENABLE1" description="Memory 1 MBIST Enable" />
-      <BitField start="2" size="1" name="ENABLE2" description="Memory 2 MBIST Enable" />
-      <BitField start="3" size="1" name="ENABLE3" description="Memory 3 MBIST Enable" />
-      <BitField start="4" size="1" name="ENABLE4" description="Memory 4 MBIST Enable" />
-      <BitField start="5" size="1" name="ENABLE5" description="Memory 5 MBIST Enable" />
-      <BitField start="6" size="1" name="ENABLE6" description="Memory 6 MBIST Enable" />
-      <BitField start="7" size="1" name="ENABLE7" description="Memory 7 MBIST Enable" />
-      <BitField start="8" size="1" name="ENABLE8" description="Memory 8 MBIST Enable" />
-      <BitField start="9" size="1" name="ENABLE9" description="Memory 9 MBIST Enable" />
-      <BitField start="10" size="1" name="ENABLE10" description="Memory 10 MBIST Enable" />
-      <BitField start="11" size="1" name="ENABLE11" description="Memory 11 MBIST Enable" />
-      <BitField start="12" size="1" name="ENABLE12" description="Memory 12 MBIST Enable" />
-      <BitField start="13" size="1" name="ENABLE13" description="Memory 13 MBIST Enable" />
-      <BitField start="14" size="1" name="ENABLE14" description="Memory 14 MBIST Enable" />
-      <BitField start="15" size="1" name="ENABLE15" description="Memory 15 MBIST Enable" />
-      <BitField start="16" size="1" name="ENABLE16" description="Memory 16 MBIST Enable" />
-      <BitField start="17" size="1" name="ENABLE17" description="Memory 17 MBIST Enable" />
-      <BitField start="18" size="1" name="ENABLE18" description="Memory 18 MBIST Enable" />
-      <BitField start="19" size="1" name="ENABLE19" description="Memory 19 MBIST Enable" />
-      <BitField start="20" size="1" name="ENABLE20" description="Memory 20 MBIST Enable" />
-      <BitField start="21" size="1" name="ENABLE21" description="Memory 21 MBIST Enable" />
-      <BitField start="22" size="1" name="ENABLE22" description="Memory 22 MBIST Enable" />
-      <BitField start="23" size="1" name="ENABLE23" description="Memory 23 MBIST Enable" />
-      <BitField start="24" size="1" name="ENABLE24" description="Memory 24 MBIST Enable" />
-      <BitField start="25" size="1" name="ENABLE25" description="Memory 25 MBIST Enable" />
-      <BitField start="26" size="1" name="ENABLE26" description="Memory 26 MBIST Enable" />
-      <BitField start="27" size="1" name="ENABLE27" description="Memory 27 MBIST Enable" />
-      <BitField start="28" size="1" name="ENABLE28" description="Memory 28 MBIST Enable" />
-    </Register>
-    <Register start="+0x0068" size="4" name="DSU_MBBUSY0" access="ReadOnly" description="MBIST Memory Busy 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY0" description="Memory 0 BIST Busy" />
-      <BitField start="1" size="1" name="BUSY1" description="Memory 1 BIST Busy" />
-      <BitField start="2" size="1" name="BUSY2" description="Memory 2 BIST Busy" />
-      <BitField start="3" size="1" name="BUSY3" description="Memory 3 BIST Busy" />
-      <BitField start="4" size="1" name="BUSY4" description="Memory 4 BIST Busy" />
-      <BitField start="5" size="1" name="BUSY5" description="Memory 5 BIST Busy" />
-      <BitField start="6" size="1" name="BUSY6" description="Memory 6 BIST Busy" />
-      <BitField start="7" size="1" name="BUSY7" description="Memory 7 BIST Busy" />
-      <BitField start="8" size="1" name="BUSY8" description="Memory 8 BIST Busy" />
-      <BitField start="9" size="1" name="BUSY9" description="Memory 9 BIST Busy" />
-      <BitField start="10" size="1" name="BUSY10" description="Memory 10 BIST Busy" />
-      <BitField start="11" size="1" name="BUSY11" description="Memory 11 BIST Busy" />
-      <BitField start="12" size="1" name="BUSY12" description="Memory 12 BIST Busy" />
-      <BitField start="13" size="1" name="BUSY13" description="Memory 13 BIST Busy" />
-      <BitField start="14" size="1" name="BUSY14" description="Memory 14 BIST Busy" />
-      <BitField start="15" size="1" name="BUSY15" description="Memory 15 BIST Busy" />
-      <BitField start="16" size="1" name="BUSY16" description="Memory 16 BIST Busy" />
-      <BitField start="17" size="1" name="BUSY17" description="Memory 17 BIST Busy" />
-      <BitField start="18" size="1" name="BUSY18" description="Memory 18 BIST Busy" />
-      <BitField start="19" size="1" name="BUSY19" description="Memory 19 BIST Busy" />
-      <BitField start="20" size="1" name="BUSY20" description="Memory 20 BIST Busy" />
-      <BitField start="21" size="1" name="BUSY21" description="Memory 21 BIST Busy" />
-      <BitField start="22" size="1" name="BUSY22" description="Memory 22 BIST Busy" />
-      <BitField start="23" size="1" name="BUSY23" description="Memory 23 BIST Busy" />
-      <BitField start="24" size="1" name="BUSY24" description="Memory 24 BIST Busy" />
-      <BitField start="25" size="1" name="BUSY25" description="Memory 25 BIST Busy" />
-      <BitField start="26" size="1" name="BUSY26" description="Memory 26 BIST Busy" />
-      <BitField start="27" size="1" name="BUSY27" description="Memory 27 BIST Busy" />
-      <BitField start="28" size="1" name="BUSY28" description="Memory 28 BIST Busy" />
-    </Register>
-    <Register start="+0x0070" size="4" name="DSU_MBSTATUS0" access="Read/Write" description="MBIST Memory Status 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS0" description="Memory 0 MBIST Status" />
-      <BitField start="1" size="1" name="STATUS1" description="Memory 1 MBIST Status" />
-      <BitField start="2" size="1" name="STATUS2" description="Memory 2 MBIST Status" />
-      <BitField start="3" size="1" name="STATUS3" description="Memory 3 MBIST Status" />
-      <BitField start="4" size="1" name="STATUS4" description="Memory 4 MBIST Status" />
-      <BitField start="5" size="1" name="STATUS5" description="Memory 5 MBIST Status" />
-      <BitField start="6" size="1" name="STATUS6" description="Memory 6 MBIST Status" />
-      <BitField start="7" size="1" name="STATUS7" description="Memory 7 MBIST Status" />
-      <BitField start="8" size="1" name="STATUS8" description="Memory 8 MBIST Status" />
-      <BitField start="9" size="1" name="STATUS9" description="Memory 9 MBIST Status" />
-      <BitField start="10" size="1" name="STATUS10" description="Memory 10 MBIST Status" />
-      <BitField start="11" size="1" name="STATUS11" description="Memory 11 MBIST Status" />
-      <BitField start="12" size="1" name="STATUS12" description="Memory 12 MBIST Status" />
-      <BitField start="13" size="1" name="STATUS13" description="Memory 13 MBIST Status" />
-      <BitField start="14" size="1" name="STATUS14" description="Memory 14 MBIST Status" />
-      <BitField start="15" size="1" name="STATUS15" description="Memory 15 MBIST Status" />
-      <BitField start="16" size="1" name="STATUS16" description="Memory 16 MBIST Status" />
-      <BitField start="17" size="1" name="STATUS17" description="Memory 17 MBIST Status" />
-      <BitField start="18" size="1" name="STATUS18" description="Memory 18 MBIST Status" />
-      <BitField start="19" size="1" name="STATUS19" description="Memory 19 MBIST Status" />
-      <BitField start="20" size="1" name="STATUS20" description="Memory 20 MBIST Status" />
-      <BitField start="21" size="1" name="STATUS21" description="Memory 21 MBIST Status" />
-      <BitField start="22" size="1" name="STATUS22" description="Memory 22 MBIST Status" />
-      <BitField start="23" size="1" name="STATUS23" description="Memory 23 MBIST Status" />
-      <BitField start="24" size="1" name="STATUS24" description="Memory 24 MBIST Status" />
-      <BitField start="25" size="1" name="STATUS25" description="Memory 25 MBIST Status" />
-      <BitField start="26" size="1" name="STATUS26" description="Memory 26 MBIST Status" />
-      <BitField start="27" size="1" name="STATUS27" description="Memory 27 MBIST Status" />
-      <BitField start="28" size="1" name="STATUS28" description="Memory 28 MBIST Status" />
-    </Register>
-    <Register start="+0x00F0+0" size="4" name="DSU_DCFG0" access="Read/Write" description="Device Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DCFG" description="Device Configuration" />
-    </Register>
-    <Register start="+0x00F0+4" size="4" name="DSU_DCFG1" access="Read/Write" description="Device Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DCFG" description="Device Configuration" />
-    </Register>
-    <Register start="+0x1000" size="4" name="DSU_ENTRY0" access="ReadOnly" description="CoreSight ROM Table Entry 0" reset_value="0x9F0FC002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRES" description="Entry Present" />
-      <BitField start="1" size="1" name="FMT" description="Format" />
-      <BitField start="12" size="20" name="ADDOFF" description="Address Offset" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DSU_ENTRY1" access="ReadOnly" description="CoreSight ROM Table Entry 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1008" size="4" name="DSU_END" access="ReadOnly" description="CoreSight ROM Table End" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End Marker" />
-    </Register>
-    <Register start="+0x1FCC" size="4" name="DSU_MEMTYPE" access="ReadOnly" description="CoreSight ROM Table Memory Type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SMEMP" description="System Memory Present" />
-    </Register>
-    <Register start="+0x1FD0" size="4" name="DSU_PID4" access="ReadOnly" description="Peripheral Identification 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="JEPCC" description="JEP-106 Continuation Code" />
-      <BitField start="4" size="4" name="FKBC" description="4KB count" />
-    </Register>
-    <Register start="+0x1FD4" size="4" name="DSU_PID5" access="ReadOnly" description="Peripheral Identification 5" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1FD8" size="4" name="DSU_PID6" access="ReadOnly" description="Peripheral Identification 6" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1FDC" size="4" name="DSU_PID7" access="ReadOnly" description="Peripheral Identification 7" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1FE0" size="4" name="DSU_PID0" access="ReadOnly" description="Peripheral Identification 0" reset_value="0x000000D0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PARTNBL" description="Part Number Low" />
-    </Register>
-    <Register start="+0x1FE4" size="4" name="DSU_PID1" access="ReadOnly" description="Peripheral Identification 1" reset_value="0x000000FC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PARTNBH" description="Part Number High" />
-      <BitField start="4" size="4" name="JEPIDCL" description="Low part of the JEP-106 Identity Code" />
-    </Register>
-    <Register start="+0x1FE8" size="4" name="DSU_PID2" access="ReadOnly" description="Peripheral Identification 2" reset_value="0x00000009" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="JEPIDCH" description="JEP-106 Identity Code High" />
-      <BitField start="3" size="1" name="JEPU" description="JEP-106 Identity Code is used" />
-      <BitField start="4" size="4" name="REVISION" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FEC" size="4" name="DSU_PID3" access="ReadOnly" description="Peripheral Identification 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CUSMOD" description="ARM CUSMOD" />
-      <BitField start="4" size="4" name="REVAND" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FF0" size="4" name="DSU_CID0" access="ReadOnly" description="Component Identification 0" reset_value="0x0000000D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB0" description="Preamble Byte 0" />
-    </Register>
-    <Register start="+0x1FF4" size="4" name="DSU_CID1" access="ReadOnly" description="Component Identification 1" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PREAMBLE" description="Preamble" />
-      <BitField start="4" size="4" name="CCLASS" description="Component Class" />
-    </Register>
-    <Register start="+0x1FF8" size="4" name="DSU_CID2" access="ReadOnly" description="Component Identification 2" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB2" description="Preamble Byte 2" />
-    </Register>
-    <Register start="+0x1FFC" size="4" name="DSU_CID3" access="ReadOnly" description="Component Identification 3" reset_value="0x000000B1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB3" description="Preamble Byte 3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EIC" start="0x40002800" description="External Interrupt Controller">
-    <Register start="+0x00" size="1" name="EIC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="4" size="1" name="CKSEL" description="Clock Selection" />
-    </Register>
-    <Register start="+0x01" size="1" name="EIC_NMICTRL" access="Read/Write" description="Non-Maskable Interrupt Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="NMISENSE" description="Non-Maskable Interrupt Sense Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="NMIFILTEN" description="Non-Maskable Interrupt Filter Enable" />
-      <BitField start="4" size="1" name="NMIASYNCH" description="Asynchronous Edge Detection Mode" />
-    </Register>
-    <Register start="+0x02" size="2" name="EIC_NMIFLAG" access="Read/Write" description="Non-Maskable Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMI" description="Non-Maskable Interrupt" />
-    </Register>
-    <Register start="+0x04" size="4" name="EIC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy Status" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy Status" />
-    </Register>
-    <Register start="+0x08" size="4" name="EIC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINTEO" description="External Interrupt Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="EIC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINT" description="External Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="EIC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINT" description="External Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="4" name="EIC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINT" description="External Interrupt" />
-    </Register>
-    <Register start="+0x18" size="4" name="EIC_ASYNCH" access="Read/Write" description="External Interrupt Asynchronous Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ASYNCH" description="Asynchronous Edge Detection Mode" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="EIC_CONFIG0" access="Read/Write" description="External Interrupt Sense Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense Configuration 0">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter Enable 0" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense Configuration 1">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter Enable 1" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense Configuration 2">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter Enable 2" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense Configuration 3">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter Enable 3" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense Configuration 4">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter Enable 4" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense Configuration 5">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter Enable 5" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense Configuration 6">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter Enable 6" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense Configuration 7">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter Enable 7" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="EIC_CONFIG1" access="Read/Write" description="External Interrupt Sense Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense Configuration 0">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter Enable 0" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense Configuration 1">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter Enable 1" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense Configuration 2">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter Enable 2" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense Configuration 3">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter Enable 3" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense Configuration 4">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter Enable 4" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense Configuration 5">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter Enable 5" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense Configuration 6">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter Enable 6" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense Configuration 7">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter Enable 7" />
-    </Register>
-    <Register start="+0x30" size="4" name="EIC_DEBOUNCEN" access="Read/Write" description="Debouncer Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DEBOUNCEN" description="Debouncer Enable" />
-    </Register>
-    <Register start="+0x34" size="4" name="EIC_DPRESCALER" access="Read/Write" description="Debouncer Prescaler" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER0" description="Debouncer Prescaler" />
-      <BitField start="4" size="3" name="PRESCALER1" description="Debouncer Prescaler" />
-      <BitField start="3" size="1" name="STATES0" description="Debouncer number of states" />
-      <BitField start="7" size="1" name="STATES1" description="Debouncer number of states" />
-      <BitField start="16" size="1" name="TICKON" description="Pin Sampler frequency selection" />
-    </Register>
-    <Register start="+0x38" size="4" name="EIC_PINSTATE" access="ReadOnly" description="Pin State" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINSTATE" description="Pin State" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVSYS" start="0x4100E000" description="Event System Interface">
-    <Register start="+0x000" size="1" name="EVSYS_CTRLA" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-    </Register>
-    <Register start="+0x004" size="4" name="EVSYS_SWEVT" access="WriteOnly" description="Software Event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHANNEL0" description="Channel 0 Software Selection" />
-      <BitField start="1" size="1" name="CHANNEL1" description="Channel 1 Software Selection" />
-      <BitField start="2" size="1" name="CHANNEL2" description="Channel 2 Software Selection" />
-      <BitField start="3" size="1" name="CHANNEL3" description="Channel 3 Software Selection" />
-      <BitField start="4" size="1" name="CHANNEL4" description="Channel 4 Software Selection" />
-      <BitField start="5" size="1" name="CHANNEL5" description="Channel 5 Software Selection" />
-      <BitField start="6" size="1" name="CHANNEL6" description="Channel 6 Software Selection" />
-      <BitField start="7" size="1" name="CHANNEL7" description="Channel 7 Software Selection" />
-      <BitField start="8" size="1" name="CHANNEL8" description="Channel 8 Software Selection" />
-      <BitField start="9" size="1" name="CHANNEL9" description="Channel 9 Software Selection" />
-      <BitField start="10" size="1" name="CHANNEL10" description="Channel 10 Software Selection" />
-      <BitField start="11" size="1" name="CHANNEL11" description="Channel 11 Software Selection" />
-      <BitField start="12" size="1" name="CHANNEL12" description="Channel 12 Software Selection" />
-      <BitField start="13" size="1" name="CHANNEL13" description="Channel 13 Software Selection" />
-      <BitField start="14" size="1" name="CHANNEL14" description="Channel 14 Software Selection" />
-      <BitField start="15" size="1" name="CHANNEL15" description="Channel 15 Software Selection" />
-      <BitField start="16" size="1" name="CHANNEL16" description="Channel 16 Software Selection" />
-      <BitField start="17" size="1" name="CHANNEL17" description="Channel 17 Software Selection" />
-      <BitField start="18" size="1" name="CHANNEL18" description="Channel 18 Software Selection" />
-      <BitField start="19" size="1" name="CHANNEL19" description="Channel 19 Software Selection" />
-      <BitField start="20" size="1" name="CHANNEL20" description="Channel 20 Software Selection" />
-      <BitField start="21" size="1" name="CHANNEL21" description="Channel 21 Software Selection" />
-      <BitField start="22" size="1" name="CHANNEL22" description="Channel 22 Software Selection" />
-      <BitField start="23" size="1" name="CHANNEL23" description="Channel 23 Software Selection" />
-      <BitField start="24" size="1" name="CHANNEL24" description="Channel 24 Software Selection" />
-      <BitField start="25" size="1" name="CHANNEL25" description="Channel 25 Software Selection" />
-      <BitField start="26" size="1" name="CHANNEL26" description="Channel 26 Software Selection" />
-      <BitField start="27" size="1" name="CHANNEL27" description="Channel 27 Software Selection" />
-      <BitField start="28" size="1" name="CHANNEL28" description="Channel 28 Software Selection" />
-      <BitField start="29" size="1" name="CHANNEL29" description="Channel 29 Software Selection" />
-      <BitField start="30" size="1" name="CHANNEL30" description="Channel 30 Software Selection" />
-      <BitField start="31" size="1" name="CHANNEL31" description="Channel 31 Software Selection" />
-    </Register>
-    <Register start="+0x008" size="1" name="EVSYS_PRICTRL" access="Read/Write" description="Priority Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRI" description="Channel Priority Number" />
-      <BitField start="7" size="1" name="RREN" description="Round-Robin Scheduling Enable" />
-    </Register>
-    <Register start="+0x010" size="2" name="EVSYS_INTPEND" access="Read/Write" description="Channel Pending Interrupt" reset_value="0x4000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Channel ID" />
-      <BitField start="8" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="9" size="1" name="EVD" description="Channel Event Detected" />
-      <BitField start="14" size="1" name="READY" description="Ready" />
-      <BitField start="15" size="1" name="BUSY" description="Busy" />
-    </Register>
-    <Register start="+0x014" size="4" name="EVSYS_INTSTATUS" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHINT0" description="Channel 0 Pending Interrupt" />
-      <BitField start="1" size="1" name="CHINT1" description="Channel 1 Pending Interrupt" />
-      <BitField start="2" size="1" name="CHINT2" description="Channel 2 Pending Interrupt" />
-      <BitField start="3" size="1" name="CHINT3" description="Channel 3 Pending Interrupt" />
-      <BitField start="4" size="1" name="CHINT4" description="Channel 4 Pending Interrupt" />
-      <BitField start="5" size="1" name="CHINT5" description="Channel 5 Pending Interrupt" />
-      <BitField start="6" size="1" name="CHINT6" description="Channel 6 Pending Interrupt" />
-      <BitField start="7" size="1" name="CHINT7" description="Channel 7 Pending Interrupt" />
-      <BitField start="8" size="1" name="CHINT8" description="Channel 8 Pending Interrupt" />
-      <BitField start="9" size="1" name="CHINT9" description="Channel 9 Pending Interrupt" />
-      <BitField start="10" size="1" name="CHINT10" description="Channel 10 Pending Interrupt" />
-      <BitField start="11" size="1" name="CHINT11" description="Channel 11 Pending Interrupt" />
-    </Register>
-    <Register start="+0x018" size="4" name="EVSYS_BUSYCH" access="ReadOnly" description="Busy Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSYCH0" description="Busy Channel 0" />
-      <BitField start="1" size="1" name="BUSYCH1" description="Busy Channel 1" />
-      <BitField start="2" size="1" name="BUSYCH2" description="Busy Channel 2" />
-      <BitField start="3" size="1" name="BUSYCH3" description="Busy Channel 3" />
-      <BitField start="4" size="1" name="BUSYCH4" description="Busy Channel 4" />
-      <BitField start="5" size="1" name="BUSYCH5" description="Busy Channel 5" />
-      <BitField start="6" size="1" name="BUSYCH6" description="Busy Channel 6" />
-      <BitField start="7" size="1" name="BUSYCH7" description="Busy Channel 7" />
-      <BitField start="8" size="1" name="BUSYCH8" description="Busy Channel 8" />
-      <BitField start="9" size="1" name="BUSYCH9" description="Busy Channel 9" />
-      <BitField start="10" size="1" name="BUSYCH10" description="Busy Channel 10" />
-      <BitField start="11" size="1" name="BUSYCH11" description="Busy Channel 11" />
-    </Register>
-    <Register start="+0x01C" size="4" name="EVSYS_READYUSR" access="ReadOnly" description="Ready Users" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READYUSR0" description="Ready User for Channel 0" />
-      <BitField start="1" size="1" name="READYUSR1" description="Ready User for Channel 1" />
-      <BitField start="2" size="1" name="READYUSR2" description="Ready User for Channel 2" />
-      <BitField start="3" size="1" name="READYUSR3" description="Ready User for Channel 3" />
-      <BitField start="4" size="1" name="READYUSR4" description="Ready User for Channel 4" />
-      <BitField start="5" size="1" name="READYUSR5" description="Ready User for Channel 5" />
-      <BitField start="6" size="1" name="READYUSR6" description="Ready User for Channel 6" />
-      <BitField start="7" size="1" name="READYUSR7" description="Ready User for Channel 7" />
-      <BitField start="8" size="1" name="READYUSR8" description="Ready User for Channel 8" />
-      <BitField start="9" size="1" name="READYUSR9" description="Ready User for Channel 9" />
-      <BitField start="10" size="1" name="READYUSR10" description="Ready User for Channel 10" />
-      <BitField start="11" size="1" name="READYUSR11" description="Ready User for Channel 11" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="EVSYS_CHANNEL0" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+8" size="4" name="EVSYS_CHANNEL1" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+16" size="4" name="EVSYS_CHANNEL2" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+24" size="4" name="EVSYS_CHANNEL3" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+32" size="4" name="EVSYS_CHANNEL4" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+40" size="4" name="EVSYS_CHANNEL5" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+48" size="4" name="EVSYS_CHANNEL6" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+56" size="4" name="EVSYS_CHANNEL7" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+64" size="4" name="EVSYS_CHANNEL8" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+72" size="4" name="EVSYS_CHANNEL9" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+80" size="4" name="EVSYS_CHANNEL10" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+88" size="4" name="EVSYS_CHANNEL11" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="EVSYS_CHANNEL12" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+104" size="4" name="EVSYS_CHANNEL13" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+112" size="4" name="EVSYS_CHANNEL14" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+120" size="4" name="EVSYS_CHANNEL15" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+128" size="4" name="EVSYS_CHANNEL16" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+136" size="4" name="EVSYS_CHANNEL17" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+144" size="4" name="EVSYS_CHANNEL18" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+152" size="4" name="EVSYS_CHANNEL19" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+160" size="4" name="EVSYS_CHANNEL20" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+168" size="4" name="EVSYS_CHANNEL21" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+176" size="4" name="EVSYS_CHANNEL22" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+184" size="4" name="EVSYS_CHANNEL23" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+192" size="4" name="EVSYS_CHANNEL24" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+200" size="4" name="EVSYS_CHANNEL25" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+208" size="4" name="EVSYS_CHANNEL26" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+216" size="4" name="EVSYS_CHANNEL27" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+224" size="4" name="EVSYS_CHANNEL28" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+232" size="4" name="EVSYS_CHANNEL29" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+240" size="4" name="EVSYS_CHANNEL30" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+248" size="4" name="EVSYS_CHANNEL31" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x024+0" size="1" name="EVSYS_CHINTENCLR0" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+8" size="1" name="EVSYS_CHINTENCLR1" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+16" size="1" name="EVSYS_CHINTENCLR2" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+24" size="1" name="EVSYS_CHINTENCLR3" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+32" size="1" name="EVSYS_CHINTENCLR4" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+40" size="1" name="EVSYS_CHINTENCLR5" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+48" size="1" name="EVSYS_CHINTENCLR6" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+56" size="1" name="EVSYS_CHINTENCLR7" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+64" size="1" name="EVSYS_CHINTENCLR8" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+72" size="1" name="EVSYS_CHINTENCLR9" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+80" size="1" name="EVSYS_CHINTENCLR10" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+88" size="1" name="EVSYS_CHINTENCLR11" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+96" size="1" name="EVSYS_CHINTENCLR12" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+104" size="1" name="EVSYS_CHINTENCLR13" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+112" size="1" name="EVSYS_CHINTENCLR14" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+120" size="1" name="EVSYS_CHINTENCLR15" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+128" size="1" name="EVSYS_CHINTENCLR16" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+136" size="1" name="EVSYS_CHINTENCLR17" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+144" size="1" name="EVSYS_CHINTENCLR18" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+152" size="1" name="EVSYS_CHINTENCLR19" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+160" size="1" name="EVSYS_CHINTENCLR20" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+168" size="1" name="EVSYS_CHINTENCLR21" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+176" size="1" name="EVSYS_CHINTENCLR22" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+184" size="1" name="EVSYS_CHINTENCLR23" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+192" size="1" name="EVSYS_CHINTENCLR24" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+200" size="1" name="EVSYS_CHINTENCLR25" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+208" size="1" name="EVSYS_CHINTENCLR26" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+216" size="1" name="EVSYS_CHINTENCLR27" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+224" size="1" name="EVSYS_CHINTENCLR28" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+232" size="1" name="EVSYS_CHINTENCLR29" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+240" size="1" name="EVSYS_CHINTENCLR30" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+248" size="1" name="EVSYS_CHINTENCLR31" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x025+0" size="1" name="EVSYS_CHINTENSET0" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+8" size="1" name="EVSYS_CHINTENSET1" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+16" size="1" name="EVSYS_CHINTENSET2" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+24" size="1" name="EVSYS_CHINTENSET3" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+32" size="1" name="EVSYS_CHINTENSET4" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+40" size="1" name="EVSYS_CHINTENSET5" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+48" size="1" name="EVSYS_CHINTENSET6" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+56" size="1" name="EVSYS_CHINTENSET7" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+64" size="1" name="EVSYS_CHINTENSET8" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+72" size="1" name="EVSYS_CHINTENSET9" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+80" size="1" name="EVSYS_CHINTENSET10" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+88" size="1" name="EVSYS_CHINTENSET11" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+96" size="1" name="EVSYS_CHINTENSET12" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+104" size="1" name="EVSYS_CHINTENSET13" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+112" size="1" name="EVSYS_CHINTENSET14" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+120" size="1" name="EVSYS_CHINTENSET15" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+128" size="1" name="EVSYS_CHINTENSET16" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+136" size="1" name="EVSYS_CHINTENSET17" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+144" size="1" name="EVSYS_CHINTENSET18" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+152" size="1" name="EVSYS_CHINTENSET19" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+160" size="1" name="EVSYS_CHINTENSET20" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+168" size="1" name="EVSYS_CHINTENSET21" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+176" size="1" name="EVSYS_CHINTENSET22" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+184" size="1" name="EVSYS_CHINTENSET23" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+192" size="1" name="EVSYS_CHINTENSET24" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+200" size="1" name="EVSYS_CHINTENSET25" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+208" size="1" name="EVSYS_CHINTENSET26" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+216" size="1" name="EVSYS_CHINTENSET27" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+224" size="1" name="EVSYS_CHINTENSET28" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+232" size="1" name="EVSYS_CHINTENSET29" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+240" size="1" name="EVSYS_CHINTENSET30" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+248" size="1" name="EVSYS_CHINTENSET31" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x026+0" size="1" name="EVSYS_CHINTFLAG0" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+8" size="1" name="EVSYS_CHINTFLAG1" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+16" size="1" name="EVSYS_CHINTFLAG2" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+24" size="1" name="EVSYS_CHINTFLAG3" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+32" size="1" name="EVSYS_CHINTFLAG4" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+40" size="1" name="EVSYS_CHINTFLAG5" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+48" size="1" name="EVSYS_CHINTFLAG6" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+56" size="1" name="EVSYS_CHINTFLAG7" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+64" size="1" name="EVSYS_CHINTFLAG8" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+72" size="1" name="EVSYS_CHINTFLAG9" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+80" size="1" name="EVSYS_CHINTFLAG10" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+88" size="1" name="EVSYS_CHINTFLAG11" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+96" size="1" name="EVSYS_CHINTFLAG12" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+104" size="1" name="EVSYS_CHINTFLAG13" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+112" size="1" name="EVSYS_CHINTFLAG14" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+120" size="1" name="EVSYS_CHINTFLAG15" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+128" size="1" name="EVSYS_CHINTFLAG16" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+136" size="1" name="EVSYS_CHINTFLAG17" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+144" size="1" name="EVSYS_CHINTFLAG18" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+152" size="1" name="EVSYS_CHINTFLAG19" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+160" size="1" name="EVSYS_CHINTFLAG20" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+168" size="1" name="EVSYS_CHINTFLAG21" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+176" size="1" name="EVSYS_CHINTFLAG22" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+184" size="1" name="EVSYS_CHINTFLAG23" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+192" size="1" name="EVSYS_CHINTFLAG24" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+200" size="1" name="EVSYS_CHINTFLAG25" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+208" size="1" name="EVSYS_CHINTFLAG26" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+216" size="1" name="EVSYS_CHINTFLAG27" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+224" size="1" name="EVSYS_CHINTFLAG28" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+232" size="1" name="EVSYS_CHINTFLAG29" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+240" size="1" name="EVSYS_CHINTFLAG30" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+248" size="1" name="EVSYS_CHINTFLAG31" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x027+0" size="1" name="EVSYS_CHSTATUS0" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+8" size="1" name="EVSYS_CHSTATUS1" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+16" size="1" name="EVSYS_CHSTATUS2" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+24" size="1" name="EVSYS_CHSTATUS3" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+32" size="1" name="EVSYS_CHSTATUS4" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+40" size="1" name="EVSYS_CHSTATUS5" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+48" size="1" name="EVSYS_CHSTATUS6" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+56" size="1" name="EVSYS_CHSTATUS7" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+64" size="1" name="EVSYS_CHSTATUS8" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+72" size="1" name="EVSYS_CHSTATUS9" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+80" size="1" name="EVSYS_CHSTATUS10" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+88" size="1" name="EVSYS_CHSTATUS11" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+96" size="1" name="EVSYS_CHSTATUS12" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+104" size="1" name="EVSYS_CHSTATUS13" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+112" size="1" name="EVSYS_CHSTATUS14" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+120" size="1" name="EVSYS_CHSTATUS15" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+128" size="1" name="EVSYS_CHSTATUS16" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+136" size="1" name="EVSYS_CHSTATUS17" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+144" size="1" name="EVSYS_CHSTATUS18" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+152" size="1" name="EVSYS_CHSTATUS19" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+160" size="1" name="EVSYS_CHSTATUS20" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+168" size="1" name="EVSYS_CHSTATUS21" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+176" size="1" name="EVSYS_CHSTATUS22" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+184" size="1" name="EVSYS_CHSTATUS23" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+192" size="1" name="EVSYS_CHSTATUS24" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+200" size="1" name="EVSYS_CHSTATUS25" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+208" size="1" name="EVSYS_CHSTATUS26" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+216" size="1" name="EVSYS_CHSTATUS27" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+224" size="1" name="EVSYS_CHSTATUS28" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+232" size="1" name="EVSYS_CHSTATUS29" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+240" size="1" name="EVSYS_CHSTATUS30" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+248" size="1" name="EVSYS_CHSTATUS31" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x120+0" size="4" name="EVSYS_USER0" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+4" size="4" name="EVSYS_USER1" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+8" size="4" name="EVSYS_USER2" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+12" size="4" name="EVSYS_USER3" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+16" size="4" name="EVSYS_USER4" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+20" size="4" name="EVSYS_USER5" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+24" size="4" name="EVSYS_USER6" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+28" size="4" name="EVSYS_USER7" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+32" size="4" name="EVSYS_USER8" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+36" size="4" name="EVSYS_USER9" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+40" size="4" name="EVSYS_USER10" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+44" size="4" name="EVSYS_USER11" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+48" size="4" name="EVSYS_USER12" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+52" size="4" name="EVSYS_USER13" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+56" size="4" name="EVSYS_USER14" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+60" size="4" name="EVSYS_USER15" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+64" size="4" name="EVSYS_USER16" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+68" size="4" name="EVSYS_USER17" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+72" size="4" name="EVSYS_USER18" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+76" size="4" name="EVSYS_USER19" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+80" size="4" name="EVSYS_USER20" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+84" size="4" name="EVSYS_USER21" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+88" size="4" name="EVSYS_USER22" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+92" size="4" name="EVSYS_USER23" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+96" size="4" name="EVSYS_USER24" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+100" size="4" name="EVSYS_USER25" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+104" size="4" name="EVSYS_USER26" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+108" size="4" name="EVSYS_USER27" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+112" size="4" name="EVSYS_USER28" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+116" size="4" name="EVSYS_USER29" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+120" size="4" name="EVSYS_USER30" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+124" size="4" name="EVSYS_USER31" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+128" size="4" name="EVSYS_USER32" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+132" size="4" name="EVSYS_USER33" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+136" size="4" name="EVSYS_USER34" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+140" size="4" name="EVSYS_USER35" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+144" size="4" name="EVSYS_USER36" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+148" size="4" name="EVSYS_USER37" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+152" size="4" name="EVSYS_USER38" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+156" size="4" name="EVSYS_USER39" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+160" size="4" name="EVSYS_USER40" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+164" size="4" name="EVSYS_USER41" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+168" size="4" name="EVSYS_USER42" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+172" size="4" name="EVSYS_USER43" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+176" size="4" name="EVSYS_USER44" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+180" size="4" name="EVSYS_USER45" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+184" size="4" name="EVSYS_USER46" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+188" size="4" name="EVSYS_USER47" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+192" size="4" name="EVSYS_USER48" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+196" size="4" name="EVSYS_USER49" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+200" size="4" name="EVSYS_USER50" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+204" size="4" name="EVSYS_USER51" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+208" size="4" name="EVSYS_USER52" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+212" size="4" name="EVSYS_USER53" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+216" size="4" name="EVSYS_USER54" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+220" size="4" name="EVSYS_USER55" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+224" size="4" name="EVSYS_USER56" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+228" size="4" name="EVSYS_USER57" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+232" size="4" name="EVSYS_USER58" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+236" size="4" name="EVSYS_USER59" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+240" size="4" name="EVSYS_USER60" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+244" size="4" name="EVSYS_USER61" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+248" size="4" name="EVSYS_USER62" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+252" size="4" name="EVSYS_USER63" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+256" size="4" name="EVSYS_USER64" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+260" size="4" name="EVSYS_USER65" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+264" size="4" name="EVSYS_USER66" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FREQM" start="0x40002C00" description="Frequency Meter">
-    <Register start="+0x00" size="1" name="FREQM_CTRLA" access="Read/Write" description="Control A Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x01" size="1" name="FREQM_CTRLB" access="WriteOnly" description="Control B Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start Measurement" />
-    </Register>
-    <Register start="+0x02" size="2" name="FREQM_CFGA" access="Read/Write" description="Config A register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="REFNUM" description="Number of Reference Clock Cycles" />
-    </Register>
-    <Register start="+0x08" size="1" name="FREQM_INTENCLR" access="Read/Write" description="Interrupt Enable Clear Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Measurement Done Interrupt Enable" />
-    </Register>
-    <Register start="+0x09" size="1" name="FREQM_INTENSET" access="Read/Write" description="Interrupt Enable Set Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Measurement Done Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="FREQM_INTFLAG" access="Read/Write" description="Interrupt Flag Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Measurement Done" />
-    </Register>
-    <Register start="+0x0B" size="1" name="FREQM_STATUS" access="Read/Write" description="Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="FREQM Status" />
-      <BitField start="1" size="1" name="OVF" description="Sticky Count Value Overflow" />
-    </Register>
-    <Register start="+0x0C" size="4" name="FREQM_SYNCBUSY" access="ReadOnly" description="Synchronization Busy Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="FREQM_VALUE" access="ReadOnly" description="Count Value Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="VALUE" description="Measurement Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GCLK" start="0x40001C00" description="Generic Clock Generator">
-    <Register start="+0x00" size="1" name="GCLK_CTRLA" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-    </Register>
-    <Register start="+0x04" size="4" name="GCLK_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchroniation Busy bit" />
-      <BitField start="2" size="1" name="GENCTRL0" description="Generic Clock Generator Control 0 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="3" size="1" name="GENCTRL1" description="Generic Clock Generator Control 1 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="4" size="1" name="GENCTRL2" description="Generic Clock Generator Control 2 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="5" size="1" name="GENCTRL3" description="Generic Clock Generator Control 3 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="GENCTRL4" description="Generic Clock Generator Control 4 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="7" size="1" name="GENCTRL5" description="Generic Clock Generator Control 5 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="8" size="1" name="GENCTRL6" description="Generic Clock Generator Control 6 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="9" size="1" name="GENCTRL7" description="Generic Clock Generator Control 7 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="10" size="1" name="GENCTRL8" description="Generic Clock Generator Control 8 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="11" size="1" name="GENCTRL9" description="Generic Clock Generator Control 9 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="12" size="1" name="GENCTRL10" description="Generic Clock Generator Control 10 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="13" size="1" name="GENCTRL11" description="Generic Clock Generator Control 11 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-    </Register>
-    <Register start="+0x20+0" size="4" name="GCLK_GENCTRL0" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="GCLK_GENCTRL1" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+8" size="4" name="GCLK_GENCTRL2" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+12" size="4" name="GCLK_GENCTRL3" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+16" size="4" name="GCLK_GENCTRL4" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+20" size="4" name="GCLK_GENCTRL5" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+24" size="4" name="GCLK_GENCTRL6" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+28" size="4" name="GCLK_GENCTRL7" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+32" size="4" name="GCLK_GENCTRL8" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+36" size="4" name="GCLK_GENCTRL9" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+40" size="4" name="GCLK_GENCTRL10" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+44" size="4" name="GCLK_GENCTRL11" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="GCLK_PCHCTRL0" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="GCLK_PCHCTRL1" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="GCLK_PCHCTRL2" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="GCLK_PCHCTRL3" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="GCLK_PCHCTRL4" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="GCLK_PCHCTRL5" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="GCLK_PCHCTRL6" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="GCLK_PCHCTRL7" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+32" size="4" name="GCLK_PCHCTRL8" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+36" size="4" name="GCLK_PCHCTRL9" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+40" size="4" name="GCLK_PCHCTRL10" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+44" size="4" name="GCLK_PCHCTRL11" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+48" size="4" name="GCLK_PCHCTRL12" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+52" size="4" name="GCLK_PCHCTRL13" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+56" size="4" name="GCLK_PCHCTRL14" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+60" size="4" name="GCLK_PCHCTRL15" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+64" size="4" name="GCLK_PCHCTRL16" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+68" size="4" name="GCLK_PCHCTRL17" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+72" size="4" name="GCLK_PCHCTRL18" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+76" size="4" name="GCLK_PCHCTRL19" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+80" size="4" name="GCLK_PCHCTRL20" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+84" size="4" name="GCLK_PCHCTRL21" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+88" size="4" name="GCLK_PCHCTRL22" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+92" size="4" name="GCLK_PCHCTRL23" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+96" size="4" name="GCLK_PCHCTRL24" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+100" size="4" name="GCLK_PCHCTRL25" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+104" size="4" name="GCLK_PCHCTRL26" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+108" size="4" name="GCLK_PCHCTRL27" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+112" size="4" name="GCLK_PCHCTRL28" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+116" size="4" name="GCLK_PCHCTRL29" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+120" size="4" name="GCLK_PCHCTRL30" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+124" size="4" name="GCLK_PCHCTRL31" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+128" size="4" name="GCLK_PCHCTRL32" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+132" size="4" name="GCLK_PCHCTRL33" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+136" size="4" name="GCLK_PCHCTRL34" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+140" size="4" name="GCLK_PCHCTRL35" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+144" size="4" name="GCLK_PCHCTRL36" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+148" size="4" name="GCLK_PCHCTRL37" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+152" size="4" name="GCLK_PCHCTRL38" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+156" size="4" name="GCLK_PCHCTRL39" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+160" size="4" name="GCLK_PCHCTRL40" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+164" size="4" name="GCLK_PCHCTRL41" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+168" size="4" name="GCLK_PCHCTRL42" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+172" size="4" name="GCLK_PCHCTRL43" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+176" size="4" name="GCLK_PCHCTRL44" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+180" size="4" name="GCLK_PCHCTRL45" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+184" size="4" name="GCLK_PCHCTRL46" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+188" size="4" name="GCLK_PCHCTRL47" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="HMATRIX" start="0x4100C000" description="HSB Matrix">
-    <Register start="+0x080+0" size="4" name="HMATRIXB_PRAS0" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+8" size="4" name="HMATRIXB_PRAS1" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+16" size="4" name="HMATRIXB_PRAS2" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+24" size="4" name="HMATRIXB_PRAS3" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+32" size="4" name="HMATRIXB_PRAS4" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+40" size="4" name="HMATRIXB_PRAS5" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+48" size="4" name="HMATRIXB_PRAS6" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+56" size="4" name="HMATRIXB_PRAS7" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+64" size="4" name="HMATRIXB_PRAS8" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+72" size="4" name="HMATRIXB_PRAS9" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+80" size="4" name="HMATRIXB_PRAS10" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+88" size="4" name="HMATRIXB_PRAS11" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+96" size="4" name="HMATRIXB_PRAS12" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+104" size="4" name="HMATRIXB_PRAS13" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+112" size="4" name="HMATRIXB_PRAS14" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+120" size="4" name="HMATRIXB_PRAS15" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+0" size="4" name="HMATRIXB_PRBS0" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+8" size="4" name="HMATRIXB_PRBS1" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+16" size="4" name="HMATRIXB_PRBS2" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+24" size="4" name="HMATRIXB_PRBS3" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+32" size="4" name="HMATRIXB_PRBS4" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+40" size="4" name="HMATRIXB_PRBS5" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+48" size="4" name="HMATRIXB_PRBS6" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+56" size="4" name="HMATRIXB_PRBS7" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+64" size="4" name="HMATRIXB_PRBS8" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+72" size="4" name="HMATRIXB_PRBS9" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+80" size="4" name="HMATRIXB_PRBS10" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+88" size="4" name="HMATRIXB_PRBS11" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+96" size="4" name="HMATRIXB_PRBS12" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+104" size="4" name="HMATRIXB_PRBS13" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+112" size="4" name="HMATRIXB_PRBS14" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+120" size="4" name="HMATRIXB_PRBS15" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="ICM" start="0x42002C00" description="Integrity Check Monitor">
-    <Register start="+0x00" size="4" name="ICM_CFG" access="Read/Write" description="Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WBDIS" description="Write Back Disable" />
-      <BitField start="1" size="1" name="EOMDIS" description="End of Monitoring Disable" />
-      <BitField start="2" size="1" name="SLBDIS" description="Secondary List Branching Disable" />
-      <BitField start="4" size="4" name="BBC" description="Bus Burden Control" />
-      <BitField start="8" size="1" name="ASCD" description="Automatic Switch To Compare Digest" />
-      <BitField start="9" size="1" name="DUALBUFF" description="Dual Input Buffer" />
-      <BitField start="12" size="1" name="UIHASH" description="User Initial Hash Value" />
-      <BitField start="13" size="3" name="UALGO" description="User SHA Algorithm">
-        <Enum name="SHA1" start="0x0" description="SHA1 Algorithm" />
-        <Enum name="SHA256" start="0x1" description="SHA256 Algorithm" />
-        <Enum name="SHA224" start="0x4" description="SHA224 Algorithm" />
-      </BitField>
-      <BitField start="16" size="6" name="HAPROT" description="Region Hash Area Protection" />
-      <BitField start="24" size="6" name="DAPROT" description="Region Descriptor Area Protection" />
-    </Register>
-    <Register start="+0x04" size="4" name="ICM_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="ICM Enable" />
-      <BitField start="1" size="1" name="DISABLE" description="ICM Disable Register" />
-      <BitField start="2" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="4" size="4" name="REHASH" description="Recompute Internal Hash" />
-      <BitField start="8" size="4" name="RMDIS" description="Region Monitoring Disable" />
-      <BitField start="12" size="4" name="RMEN" description="Region Monitoring Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="ICM_SR" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="ICM Controller Enable Register" />
-      <BitField start="8" size="4" name="RAWRMDIS" description="RAW Region Monitoring Disabled Status" />
-      <BitField start="12" size="4" name="RMDIS" description="Region Monitoring Disabled Status" />
-    </Register>
-    <Register start="+0x10" size="4" name="ICM_IER" access="WriteOnly" description="Interrupt Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed Interrupt Enable" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch Interrupt Enable" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error Interrupt Enable" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition detected Interrupt Enable" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition Detected Interrupt Enable" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Interrupt Disable" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="4" name="ICM_IDR" access="WriteOnly" description="Interrupt Disable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed Interrupt Disable" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch Interrupt Disable" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error Interrupt Disable" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition Detected Interrupt Disable" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition detected Interrupt Disable" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Interrupt Disable" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Interrupt Disable" />
-    </Register>
-    <Register start="+0x18" size="4" name="ICM_IMR" access="ReadOnly" description="Interrupt Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed Interrupt Mask" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch Interrupt Mask" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error Interrupt Mask" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition Detected Interrupt Mask" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition Detected Interrupt Mask" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Interrupt Mask" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Interrupt Mask" />
-    </Register>
-    <Register start="+0x1C" size="4" name="ICM_ISR" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition Detected" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition Detected" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Detected" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Status" />
-    </Register>
-    <Register start="+0x20" size="4" name="ICM_UASR" access="ReadOnly" description="Undefined Access Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="URAT" description="Undefined Register Access Trace">
-        <Enum name="UNSPEC_STRUCT_MEMBER" start="0x0" description="Unspecified structure member set to one detected when the descriptor is loaded" />
-        <Enum name="CFG_MODIFIED" start="0x1" description="CFG modified during active monitoring" />
-        <Enum name="DSCR_MODIFIED" start="0x2" description="DSCR modified during active monitoring" />
-        <Enum name="HASH_MODIFIED" start="0x3" description="HASH modified during active monitoring" />
-        <Enum name="READ_ACCESS" start="0x4" description="Write-only register read access" />
-      </BitField>
-    </Register>
-    <Register start="+0x30" size="4" name="ICM_DSCR" access="Read/Write" description="Region Descriptor Area Start Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="26" name="DASA" description="Descriptor Area Start Address" />
-    </Register>
-    <Register start="+0x34" size="4" name="ICM_HASH" access="Read/Write" description="Region Hash Area Start Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="25" name="HASA" description="Hash Area Start Address" />
-    </Register>
-    <Register start="+0x38+0" size="4" name="ICM_UIHVAL0" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+4" size="4" name="ICM_UIHVAL1" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+8" size="4" name="ICM_UIHVAL2" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+12" size="4" name="ICM_UIHVAL3" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+16" size="4" name="ICM_UIHVAL4" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+20" size="4" name="ICM_UIHVAL5" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+24" size="4" name="ICM_UIHVAL6" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+28" size="4" name="ICM_UIHVAL7" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x43002800" description="Inter-IC Sound Interface">
-    <Register start="+0x00" size="1" name="I2S_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable" />
-      <BitField start="4" size="1" name="TXEN" description="Tx Serializer Enable" />
-      <BitField start="5" size="1" name="RXEN" description="Rx Serializer Enable" />
-    </Register>
-    <Register start="+0x04+0" size="4" name="I2S_CLKCTRL0" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="9" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="10" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="11" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="12" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="13" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="14" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="15" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-      <BitField start="16" size="6" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="6" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-    </Register>
-    <Register start="+0x04+4" size="4" name="I2S_CLKCTRL1" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="9" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="10" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="11" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="12" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="13" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="14" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="15" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-      <BitField start="16" size="6" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="6" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-    </Register>
-    <Register start="+0x0C" size="2" name="I2S_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="2" name="I2S_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="2" name="I2S_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1" />
-    </Register>
-    <Register start="+0x18" size="2" name="I2S_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Status" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Status" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable Synchronization Status" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable Synchronization Status" />
-      <BitField start="4" size="1" name="TXEN" description="Tx Serializer Enable Synchronization Status" />
-      <BitField start="5" size="1" name="RXEN" description="Rx Serializer Enable Synchronization Status" />
-      <BitField start="8" size="1" name="TXDATA" description="Tx Data Synchronization Status" />
-      <BitField start="9" size="1" name="RXDATA" description="Rx Data Synchronization Status" />
-    </Register>
-    <Register start="+0x20" size="4" name="I2S_TXCTRL" access="Read/Write" description="Tx Serializer Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="TXDEFAULT" description="Line Default Line when Slot Disabled">
-        <Enum name="ZERO" start="0x0" description="Output Default Value is 0" />
-        <Enum name="ONE" start="0x1" description="Output Default Value is 1" />
-        <Enum name="HIZ" start="0x3" description="Output Default Value is high impedance" />
-      </BitField>
-      <BitField start="4" size="1" name="TXSAME" description="Transmit Data when Underrun">
-        <Enum name="ZERO" start="0x0" description="Zero data transmitted in case of underrun" />
-        <Enum name="SAME" start="0x1" description="Last data transmitted in case of underrun" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-    </Register>
-    <Register start="+0x24" size="4" name="I2S_RXCTRL" access="Read/Write" description="Rx Serializer Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SERMODE" description="Serializer Mode">
-        <Enum name="RX" start="0x0" description="Receive" />
-        <Enum name="PDM2" start="0x2" description="Receive one PDM data on each serial clock edge" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Unit Selection">
-        <Enum name="CLK0" start="0x0" description="Use Clock Unit 0" />
-        <Enum name="CLK1" start="0x1" description="Use Clock Unit 1" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-      <BitField start="26" size="1" name="RXLOOP" description="Loop-back Test Mode" />
-    </Register>
-    <Register start="+0x30" size="4" name="I2S_TXDATA" access="WriteOnly" description="Tx Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-    <Register start="+0x34" size="4" name="I2S_RXDATA" access="ReadOnly" description="Rx Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCLK" start="0x40000800" description="Main Clock">
-    <Register start="+0x01" size="1" name="MCLK_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x02" size="1" name="MCLK_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x03" size="1" name="MCLK_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready" />
-    </Register>
-    <Register start="+0x04" size="1" name="MCLK_HSDIV" access="ReadOnly" description="HS Clock Division" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="CPU Clock Division Factor">
-        <Enum name="DIV1" start="0x1" description="Divide by 1" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="MCLK_CPUDIV" access="Read/Write" description="CPU Clock Division" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="Low-Power Clock Division Factor">
-        <Enum name="DIV1" start="0x1" description="Divide by 1" />
-        <Enum name="DIV2" start="0x2" description="Divide by 2" />
-        <Enum name="DIV4" start="0x4" description="Divide by 4" />
-        <Enum name="DIV8" start="0x8" description="Divide by 8" />
-        <Enum name="DIV16" start="0x10" description="Divide by 16" />
-        <Enum name="DIV32" start="0x20" description="Divide by 32" />
-        <Enum name="DIV64" start="0x40" description="Divide by 64" />
-        <Enum name="DIV128" start="0x80" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x10" size="4" name="MCLK_AHBMASK" access="Read/Write" description="AHB Mask" reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HPB0_" description="HPB0 AHB Clock Mask" />
-      <BitField start="1" size="1" name="HPB1_" description="HPB1 AHB Clock Mask" />
-      <BitField start="2" size="1" name="HPB2_" description="HPB2 AHB Clock Mask" />
-      <BitField start="3" size="1" name="HPB3_" description="HPB3 AHB Clock Mask" />
-      <BitField start="4" size="1" name="DSU_" description="DSU AHB Clock Mask" />
-      <BitField start="5" size="1" name="HMATRIX_" description="HMATRIX AHB Clock Mask" />
-      <BitField start="6" size="1" name="NVMCTRL_" description="NVMCTRL AHB Clock Mask" />
-      <BitField start="7" size="1" name="HSRAM_" description="HSRAM AHB Clock Mask" />
-      <BitField start="8" size="1" name="CMCC_" description="CMCC AHB Clock Mask" />
-      <BitField start="9" size="1" name="DMAC_" description="DMAC AHB Clock Mask" />
-      <BitField start="10" size="1" name="USB_" description="USB AHB Clock Mask" />
-      <BitField start="11" size="1" name="BKUPRAM_" description="BKUPRAM AHB Clock Mask" />
-      <BitField start="12" size="1" name="PAC_" description="PAC AHB Clock Mask" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI AHB Clock Mask" />
-      <BitField start="15" size="1" name="SDHC0_" description="SDHC0 AHB Clock Mask" />
-      <BitField start="19" size="1" name="ICM_" description="ICM AHB Clock Mask" />
-      <BitField start="20" size="1" name="PUKCC_" description="PUKCC AHB Clock Mask" />
-      <BitField start="21" size="1" name="QSPI_2X_" description="QSPI_2X AHB Clock Mask" />
-      <BitField start="22" size="1" name="NVMCTRL_SMEEPROM_" description="NVMCTRL_SMEEPROM AHB Clock Mask" />
-      <BitField start="23" size="1" name="NVMCTRL_CACHE_" description="NVMCTRL_CACHE AHB Clock Mask" />
-    </Register>
-    <Register start="+0x14" size="4" name="MCLK_APBAMASK" access="Read/Write" description="APBA Mask" reset_value="0x000007FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC_" description="PAC APB Clock Enable" />
-      <BitField start="1" size="1" name="PM_" description="PM APB Clock Enable" />
-      <BitField start="2" size="1" name="MCLK_" description="MCLK APB Clock Enable" />
-      <BitField start="3" size="1" name="RSTC_" description="RSTC APB Clock Enable" />
-      <BitField start="4" size="1" name="OSCCTRL_" description="OSCCTRL APB Clock Enable" />
-      <BitField start="5" size="1" name="OSC32KCTRL_" description="OSC32KCTRL APB Clock Enable" />
-      <BitField start="6" size="1" name="SUPC_" description="SUPC APB Clock Enable" />
-      <BitField start="7" size="1" name="GCLK_" description="GCLK APB Clock Enable" />
-      <BitField start="8" size="1" name="WDT_" description="WDT APB Clock Enable" />
-      <BitField start="9" size="1" name="RTC_" description="RTC APB Clock Enable" />
-      <BitField start="10" size="1" name="EIC_" description="EIC APB Clock Enable" />
-      <BitField start="11" size="1" name="FREQM_" description="FREQM APB Clock Enable" />
-      <BitField start="12" size="1" name="SERCOM0_" description="SERCOM0 APB Clock Enable" />
-      <BitField start="13" size="1" name="SERCOM1_" description="SERCOM1 APB Clock Enable" />
-      <BitField start="14" size="1" name="TC0_" description="TC0 APB Clock Enable" />
-      <BitField start="15" size="1" name="TC1_" description="TC1 APB Clock Enable" />
-    </Register>
-    <Register start="+0x18" size="4" name="MCLK_APBBMASK" access="Read/Write" description="APBB Mask" reset_value="0x00018056" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_" description="USB APB Clock Enable" />
-      <BitField start="1" size="1" name="DSU_" description="DSU APB Clock Enable" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL APB Clock Enable" />
-      <BitField start="4" size="1" name="PORT_" description="PORT APB Clock Enable" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX APB Clock Enable" />
-      <BitField start="7" size="1" name="EVSYS_" description="EVSYS APB Clock Enable" />
-      <BitField start="9" size="1" name="SERCOM2_" description="SERCOM2 APB Clock Enable" />
-      <BitField start="10" size="1" name="SERCOM3_" description="SERCOM3 APB Clock Enable" />
-      <BitField start="11" size="1" name="TCC0_" description="TCC0 APB Clock Enable" />
-      <BitField start="12" size="1" name="TCC1_" description="TCC1 APB Clock Enable" />
-      <BitField start="13" size="1" name="TC2_" description="TC2 APB Clock Enable" />
-      <BitField start="14" size="1" name="TC3_" description="TC3 APB Clock Enable" />
-      <BitField start="15" size="1" name="TAL_" description="TAL APB Clock Enable" />
-      <BitField start="16" size="1" name="RAMECC_" description="RAMECC APB Clock Enable" />
-    </Register>
-    <Register start="+0x1C" size="4" name="MCLK_APBCMASK" access="Read/Write" description="APBC Mask" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="TCC2_" description="TCC2 APB Clock Enable" />
-      <BitField start="4" size="1" name="TCC3_" description="TCC3 APB Clock Enable" />
-      <BitField start="5" size="1" name="TC4_" description="TC4 APB Clock Enable" />
-      <BitField start="6" size="1" name="TC5_" description="TC5 APB Clock Enable" />
-      <BitField start="7" size="1" name="PDEC_" description="PDEC APB Clock Enable" />
-      <BitField start="8" size="1" name="AC_" description="AC APB Clock Enable" />
-      <BitField start="9" size="1" name="AES_" description="AES APB Clock Enable" />
-      <BitField start="10" size="1" name="TRNG_" description="TRNG APB Clock Enable" />
-      <BitField start="11" size="1" name="ICM_" description="ICM APB Clock Enable" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI APB Clock Enable" />
-      <BitField start="14" size="1" name="CCL_" description="CCL APB Clock Enable" />
-    </Register>
-    <Register start="+0x20" size="4" name="MCLK_APBDMASK" access="Read/Write" description="APBD Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4_" description="SERCOM4 APB Clock Enable" />
-      <BitField start="1" size="1" name="SERCOM5_" description="SERCOM5 APB Clock Enable" />
-      <BitField start="4" size="1" name="TCC4_" description="TCC4 APB Clock Enable" />
-      <BitField start="7" size="1" name="ADC0_" description="ADC0 APB Clock Enable" />
-      <BitField start="8" size="1" name="ADC1_" description="ADC1 APB Clock Enable" />
-      <BitField start="9" size="1" name="DAC_" description="DAC APB Clock Enable" />
-      <BitField start="10" size="1" name="I2S_" description="I2S APB Clock Enable" />
-      <BitField start="11" size="1" name="PCC_" description="PCC APB Clock Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVMCTRL" start="0x41004000" description="Non-Volatile Memory Controller">
-    <Register start="+0x00" size="2" name="NVMCTRL_CTRLA" access="Read/Write" description="Control A" reset_value="0x0004" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="AUTOWS" description="Auto Wait State Enable" />
-      <BitField start="3" size="1" name="SUSPEN" description="Suspend Enable" />
-      <BitField start="4" size="2" name="WMODE" description="Write Mode">
-        <Enum name="MAN" start="0x0" description="Manual Write" />
-        <Enum name="ADW" start="0x1" description="Automatic Double Word Write" />
-        <Enum name="AQW" start="0x2" description="Automatic Quad Word" />
-        <Enum name="AP" start="0x3" description="Automatic Page Write" />
-      </BitField>
-      <BitField start="6" size="2" name="PRM" description="Power Reduction Mode during Sleep">
-        <Enum name="SEMIAUTO" start="0x0" description="NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access." />
-        <Enum name="FULLAUTO" start="0x1" description="NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode." />
-        <Enum name="MANUAL" start="0x3" description="NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access." />
-      </BitField>
-      <BitField start="8" size="4" name="RWS" description="NVM Read Wait States" />
-      <BitField start="12" size="1" name="AHBNS0" description="Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated" />
-      <BitField start="13" size="1" name="AHBNS1" description="Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated" />
-      <BitField start="14" size="1" name="CACHEDIS0" description="AHB0 Cache Disable" />
-      <BitField start="15" size="1" name="CACHEDIS1" description="AHB1 Cache Disable" />
-    </Register>
-    <Register start="+0x04" size="2" name="NVMCTRL_CTRLB" access="WriteOnly" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CMD" description="Command">
-        <Enum name="EP" start="0x0" description="Erase Page - Only supported in the USER and AUX pages." />
-        <Enum name="EB" start="0x1" description="Erase Block - Erases the block addressed by the ADDR register, not supported in the user page" />
-        <Enum name="WP" start="0x3" description="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page" />
-        <Enum name="WQW" start="0x4" description="Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register." />
-        <Enum name="SWRST" start="0x10" description="Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers" />
-        <Enum name="LR" start="0x11" description="Lock Region - Locks the region containing the address location in the ADDR register." />
-        <Enum name="UR" start="0x12" description="Unlock Region - Unlocks the region containing the address location in the ADDR register." />
-        <Enum name="SPRM" start="0x13" description="Sets the power reduction mode." />
-        <Enum name="CPRM" start="0x14" description="Clears the power reduction mode." />
-        <Enum name="PBC" start="0x15" description="Page Buffer Clear - Clears the page buffer." />
-        <Enum name="SSB" start="0x16" description="Set Security Bit" />
-        <Enum name="BKSWRST" start="0x17" description="Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK" />
-        <Enum name="CELCK" start="0x18" description="Chip Erase Lock - DSU.CE command is not available" />
-        <Enum name="CEULCK" start="0x19" description="Chip Erase Unlock - DSU.CE command is available" />
-        <Enum name="SBPDIS" start="0x1a" description="Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence" />
-        <Enum name="CBPDIS" start="0x1b" description="Clears STATUS.BPDIS, Boot loader protection is not discarded" />
-        <Enum name="ASEES0" start="0x30" description="Activate SmartEEPROM Sector 0, deactivate Sector 1" />
-        <Enum name="ASEES1" start="0x31" description="Activate SmartEEPROM Sector 1, deactivate Sector 0" />
-        <Enum name="SEERALOC" start="0x32" description="Starts SmartEEPROM sector reallocation algorithm" />
-        <Enum name="SEEFLUSH" start="0x33" description="Flush SMEE data when in buffered mode" />
-        <Enum name="LSEE" start="0x34" description="Lock access to SmartEEPROM data from any mean" />
-        <Enum name="USEE" start="0x35" description="Unlock access to SmartEEPROM data" />
-        <Enum name="LSEER" start="0x36" description="Lock access to the SmartEEPROM Register Address Space (above 64KB)" />
-        <Enum name="USEER" start="0x37" description="Unlock access to the SmartEEPROM Register Address Space (above 64KB)" />
-      </BitField>
-      <BitField start="8" size="8" name="CMDEX" description="Command Execution">
-        <Enum name="KEY" start="0xa5" description="Execution Key" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="NVMCTRL_PARAM" access="ReadOnly" description="NVM Parameter" reset_value="0x00060000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NVMP" description="NVM Pages" />
-      <BitField start="16" size="3" name="PSZ" description="Page Size">
-        <Enum name="8" start="0x0" description="8 bytes" />
-        <Enum name="16" start="0x1" description="16 bytes" />
-        <Enum name="32" start="0x2" description="32 bytes" />
-        <Enum name="64" start="0x3" description="64 bytes" />
-        <Enum name="128" start="0x4" description="128 bytes" />
-        <Enum name="256" start="0x5" description="256 bytes" />
-        <Enum name="512" start="0x6" description="512 bytes" />
-        <Enum name="1024" start="0x7" description="1024 bytes" />
-      </BitField>
-      <BitField start="31" size="1" name="SEE" description="SmartEEPROM Supported" />
-    </Register>
-    <Register start="+0x0C" size="2" name="NVMCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Command Done Interrupt Clear" />
-      <BitField start="1" size="1" name="ADDRE" description="Address Error" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error Interrupt Clear" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error Interrupt Clear" />
-      <BitField start="4" size="1" name="ECCSE" description="ECC Single Error Interrupt Clear" />
-      <BitField start="5" size="1" name="ECCDE" description="ECC Dual Error Interrupt Clear" />
-      <BitField start="6" size="1" name="NVME" description="NVM Error Interrupt Clear" />
-      <BitField start="7" size="1" name="SUSP" description="Suspended Write Or Erase Interrupt Clear" />
-      <BitField start="8" size="1" name="SEESFULL" description="Active SEES Full Interrupt Clear" />
-      <BitField start="9" size="1" name="SEESOVF" description="Active SEES Overflow Interrupt Clear" />
-      <BitField start="10" size="1" name="SEEWRC" description="SEE Write Completed Interrupt Clear" />
-    </Register>
-    <Register start="+0x0E" size="2" name="NVMCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Command Done Interrupt Enable" />
-      <BitField start="1" size="1" name="ADDRE" description="Address Error Interrupt Enable" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error Interrupt Enable" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error Interrupt Enable" />
-      <BitField start="4" size="1" name="ECCSE" description="ECC Single Error Interrupt Enable" />
-      <BitField start="5" size="1" name="ECCDE" description="ECC Dual Error Interrupt Enable" />
-      <BitField start="6" size="1" name="NVME" description="NVM Error Interrupt Enable" />
-      <BitField start="7" size="1" name="SUSP" description="Suspended Write Or Erase  Interrupt Enable" />
-      <BitField start="8" size="1" name="SEESFULL" description="Active SEES Full Interrupt Enable" />
-      <BitField start="9" size="1" name="SEESOVF" description="Active SEES Overflow Interrupt Enable" />
-      <BitField start="10" size="1" name="SEEWRC" description="SEE Write Completed Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="2" name="NVMCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Command Done" />
-      <BitField start="1" size="1" name="ADDRE" description="Address Error" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error" />
-      <BitField start="4" size="1" name="ECCSE" description="ECC Single Error" />
-      <BitField start="5" size="1" name="ECCDE" description="ECC Dual Error" />
-      <BitField start="6" size="1" name="NVME" description="NVM Error" />
-      <BitField start="7" size="1" name="SUSP" description="Suspended Write Or Erase Operation" />
-      <BitField start="8" size="1" name="SEESFULL" description="Active SEES Full" />
-      <BitField start="9" size="1" name="SEESOVF" description="Active SEES Overflow" />
-      <BitField start="10" size="1" name="SEEWRC" description="SEE Write Completed" />
-    </Register>
-    <Register start="+0x12" size="2" name="NVMCTRL_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Ready to accept a command" />
-      <BitField start="1" size="1" name="PRM" description="Power Reduction Mode" />
-      <BitField start="2" size="1" name="LOAD" description="NVM Page Buffer Active Loading" />
-      <BitField start="3" size="1" name="SUSP" description="NVM Write Or Erase Operation Is Suspended" />
-      <BitField start="4" size="1" name="AFIRST" description="BANKA First" />
-      <BitField start="5" size="1" name="BPDIS" description="Boot Loader Protection Disable" />
-      <BitField start="8" size="4" name="BOOTPROT" description="Boot Loader Protection Size" />
-    </Register>
-    <Register start="+0x14" size="4" name="NVMCTRL_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="ADDR" description="NVM Address" />
-    </Register>
-    <Register start="+0x18" size="4" name="NVMCTRL_RUNLOCK" access="ReadOnly" description="Lock Section" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RUNLOCK" description="Region Un-Lock Bits" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="NVMCTRL_PBLDATA0" access="ReadOnly" description="Page Buffer Load Data x" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Page Buffer Data" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="NVMCTRL_PBLDATA1" access="ReadOnly" description="Page Buffer Load Data x" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Page Buffer Data" />
-    </Register>
-    <Register start="+0x24" size="4" name="NVMCTRL_ECCERR" access="ReadOnly" description="ECC Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="ADDR" description="Error Address" />
-      <BitField start="28" size="2" name="TYPEL" description="Low Double-Word Error Type">
-        <Enum name="None" start="0x0" description="No Error Detected Since Last Read" />
-        <Enum name="Single" start="0x1" description="At Least One Single Error Detected Since last Read" />
-        <Enum name="Dual" start="0x2" description="At Least One Dual Error Detected Since Last Read" />
-      </BitField>
-      <BitField start="30" size="2" name="TYPEH" description="High Double-Word Error Type">
-        <Enum name="None" start="0x0" description="No Error Detected Since Last Read" />
-        <Enum name="Single" start="0x1" description="At Least One Single Error Detected Since last Read" />
-        <Enum name="Dual" start="0x2" description="At Least One Dual Error Detected Since Last Read" />
-      </BitField>
-    </Register>
-    <Register start="+0x28" size="1" name="NVMCTRL_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ECCDIS" description="Debugger ECC Read Disable" />
-      <BitField start="1" size="1" name="ECCELOG" description="Debugger ECC Error Tracking Mode" />
-    </Register>
-    <Register start="+0x2A" size="1" name="NVMCTRL_SEECFG" access="Read/Write" description="SmartEEPROM Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WMODE" description="Write Mode">
-        <Enum name="UNBUFFERED" start="0x0" description="A NVM write command is issued after each write in the pagebuffer" />
-        <Enum name="BUFFERED" start="0x1" description="A NVM write command is issued when a write to a new page is requested" />
-      </BitField>
-      <BitField start="1" size="1" name="APRDIS" description="Automatic Page Reallocation Disable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="NVMCTRL_SEESTAT" access="ReadOnly" description="SmartEEPROM Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ASEES" description="Active SmartEEPROM Sector" />
-      <BitField start="1" size="1" name="LOAD" description="Page Buffer Loaded" />
-      <BitField start="2" size="1" name="BUSY" description="Busy" />
-      <BitField start="3" size="1" name="LOCK" description="SmartEEPROM Write Access Is Locked" />
-      <BitField start="4" size="1" name="RLOCK" description="SmartEEPROM Write Access To Register Address Space Is Locked" />
-      <BitField start="8" size="4" name="SBLK" description="Blocks Number In a Sector" />
-      <BitField start="16" size="3" name="PSZ" description="SmartEEPROM Page Size" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OSCCTRL" start="0x40001000" description="Oscillators Control">
-    <Register start="+0x00" size="1" name="OSCCTRL_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CFDEO0" description="Clock 0 Failure Detector Event Output Enable" />
-      <BitField start="1" size="1" name="CFDEO1" description="Clock 1 Failure Detector Event Output Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="OSCCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector Interrupt Enable" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall Interrupt Enable" />
-      <BitField start="18" size="1" name="DPLL0LTO" description="DPLL0 Lock Timeout Interrupt Enable" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete Interrupt Enable" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise Interrupt Enable" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall Interrupt Enable" />
-      <BitField start="26" size="1" name="DPLL1LTO" description="DPLL1 Lock Timeout Interrupt Enable" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="OSCCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector Interrupt Enable" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall Interrupt Enable" />
-      <BitField start="18" size="1" name="DPLL0LTO" description="DPLL0 Lock Timeout Interrupt Enable" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete Interrupt Enable" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise Interrupt Enable" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall Interrupt Enable" />
-      <BitField start="26" size="1" name="DPLL1LTO" description="DPLL1 Lock Timeout Interrupt Enable" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="OSCCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall" />
-      <BitField start="18" size="1" name="DPLL0LTO" description="DPLL0 Lock Timeout" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall" />
-      <BitField start="26" size="1" name="DPLL1LTO" description="DPLL1 Lock Timeout" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete" />
-    </Register>
-    <Register start="+0x10" size="4" name="OSCCTRL_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector" />
-      <BitField start="4" size="1" name="XOSCCKSW0" description="XOSC 0 Clock Switch" />
-      <BitField start="5" size="1" name="XOSCCKSW1" description="XOSC 1 Clock Switch" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall" />
-      <BitField start="18" size="1" name="DPLL0TO" description="DPLL0 Timeout" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall" />
-      <BitField start="26" size="1" name="DPLL1TO" description="DPLL1 Timeout" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete" />
-    </Register>
-    <Register start="+0x14+0" size="4" name="OSCCTRL_XOSCCTRL0" access="Read/Write" description="External Multipurpose Crystal Oscillator Control" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="1" name="LOWBUFGAIN" description="Low Buffer Gain Enable" />
-      <BitField start="9" size="2" name="IPTAT" description="Oscillator Current Reference" />
-      <BitField start="11" size="4" name="IMULT" description="Oscillator Current Multiplier" />
-      <BitField start="15" size="1" name="ENALC" description="Automatic Loop Control Enable" />
-      <BitField start="16" size="1" name="CFDEN" description="Clock Failure Detector Enable" />
-      <BitField start="17" size="1" name="SWBEN" description="Xosc Clock Switch Enable" />
-      <BitField start="20" size="4" name="STARTUP" description="Start-Up Time" />
-      <BitField start="24" size="4" name="CFDPRESC" description="Clock Failure Detector Prescaler" />
-    </Register>
-    <Register start="+0x14+4" size="4" name="OSCCTRL_XOSCCTRL1" access="Read/Write" description="External Multipurpose Crystal Oscillator Control" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="1" name="LOWBUFGAIN" description="Low Buffer Gain Enable" />
-      <BitField start="9" size="2" name="IPTAT" description="Oscillator Current Reference" />
-      <BitField start="11" size="4" name="IMULT" description="Oscillator Current Multiplier" />
-      <BitField start="15" size="1" name="ENALC" description="Automatic Loop Control Enable" />
-      <BitField start="16" size="1" name="CFDEN" description="Clock Failure Detector Enable" />
-      <BitField start="17" size="1" name="SWBEN" description="Xosc Clock Switch Enable" />
-      <BitField start="20" size="4" name="STARTUP" description="Start-Up Time" />
-      <BitField start="24" size="4" name="CFDPRESC" description="Clock Failure Detector Prescaler" />
-    </Register>
-    <Register start="+0x1C" size="1" name="OSCCTRL_DFLLCTRLA" access="Read/Write" description="DFLL48M Control A" reset_value="0x82" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DFLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-    </Register>
-    <Register start="+0x20" size="1" name="OSCCTRL_DFLLCTRLB" access="Read/Write" description="DFLL48M Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Operating Mode Selection" />
-      <BitField start="1" size="1" name="STABLE" description="Stable DFLL Frequency" />
-      <BitField start="2" size="1" name="LLAW" description="Lose Lock After Wake" />
-      <BitField start="3" size="1" name="USBCRM" description="USB Clock Recovery Mode" />
-      <BitField start="4" size="1" name="CCDIS" description="Chill Cycle Disable" />
-      <BitField start="5" size="1" name="QLDIS" description="Quick Lock Disable" />
-      <BitField start="6" size="1" name="BPLCKC" description="Bypass Coarse Lock" />
-      <BitField start="7" size="1" name="WAITLOCK" description="Wait Lock" />
-    </Register>
-    <Register start="+0x24" size="4" name="OSCCTRL_DFLLVAL" access="Read/Write" description="DFLL48M Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FINE" description="Fine Value" />
-      <BitField start="10" size="6" name="COARSE" description="Coarse Value" />
-      <BitField start="16" size="16" name="DIFF" description="Multiplication Ratio Difference" />
-    </Register>
-    <Register start="+0x28" size="4" name="OSCCTRL_DFLLMUL" access="Read/Write" description="DFLL48M Multiplier" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MUL" description="DFLL Multiply Factor" />
-      <BitField start="16" size="8" name="FSTEP" description="Fine Maximum Step" />
-      <BitField start="26" size="6" name="CSTEP" description="Coarse Maximum Step" />
-    </Register>
-    <Register start="+0x2C" size="1" name="OSCCTRL_DFLLSYNC" access="Read/Write" description="DFLL48M Synchronization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="ENABLE Synchronization Busy" />
-      <BitField start="2" size="1" name="DFLLCTRLB" description="DFLLCTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="DFLLVAL" description="DFLLVAL Synchronization Busy" />
-      <BitField start="4" size="1" name="DFLLMUL" description="DFLLMUL Synchronization Busy" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="OSCCTRL_DPLLCTRLA0" access="Read/Write" description="DPLL Control A" reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-    </Register>
-    <Register start="+0x30+20" size="1" name="OSCCTRL_DPLLCTRLA1" access="Read/Write" description="DPLL Control A" reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-    </Register>
-    <Register start="+0x34+0" size="4" name="OSCCTRL_DPLLRATIO0" access="Read/Write" description="DPLL Ratio Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="LDR" description="Loop Divider Ratio" />
-      <BitField start="16" size="5" name="LDRFRAC" description="Loop Divider Ratio Fractional Part" />
-    </Register>
-    <Register start="+0x34+20" size="4" name="OSCCTRL_DPLLRATIO1" access="Read/Write" description="DPLL Ratio Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="LDR" description="Loop Divider Ratio" />
-      <BitField start="16" size="5" name="LDRFRAC" description="Loop Divider Ratio Fractional Part" />
-    </Register>
-    <Register start="+0x38+0" size="4" name="OSCCTRL_DPLLCTRLB0" access="Read/Write" description="DPLL Control B" reset_value="0x00000020" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FILTER" description="Proportional Integral Filter Selection" />
-      <BitField start="4" size="1" name="WUF" description="Wake Up Fast" />
-      <BitField start="5" size="3" name="REFCLK" description="Reference Clock Selection">
-        <Enum name="GCLK" start="0x0" description="Dedicated GCLK clock reference" />
-        <Enum name="XOSC32" start="0x1" description="XOSC32K clock reference" />
-        <Enum name="XOSC0" start="0x2" description="XOSC0 clock reference" />
-        <Enum name="XOSC1" start="0x3" description="XOSC1 clock reference" />
-      </BitField>
-      <BitField start="8" size="3" name="LTIME" description="Lock Time">
-        <Enum name="DEFAULT" start="0x0" description="No time-out. Automatic lock" />
-        <Enum name="800US" start="0x4" description="Time-out if no lock within 800us" />
-        <Enum name="900US" start="0x5" description="Time-out if no lock within 900us" />
-        <Enum name="1MS" start="0x6" description="Time-out if no lock within 1ms" />
-        <Enum name="1P1MS" start="0x7" description="Time-out if no lock within 1.1ms" />
-      </BitField>
-      <BitField start="11" size="1" name="LBYPASS" description="Lock Bypass" />
-      <BitField start="12" size="3" name="DCOFILTER" description="Sigma-Delta DCO Filter Selection" />
-      <BitField start="15" size="1" name="DCOEN" description="DCO Filter Enable" />
-      <BitField start="16" size="11" name="DIV" description="Clock Divider" />
-    </Register>
-    <Register start="+0x38+20" size="4" name="OSCCTRL_DPLLCTRLB1" access="Read/Write" description="DPLL Control B" reset_value="0x00000020" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FILTER" description="Proportional Integral Filter Selection" />
-      <BitField start="4" size="1" name="WUF" description="Wake Up Fast" />
-      <BitField start="5" size="3" name="REFCLK" description="Reference Clock Selection">
-        <Enum name="GCLK" start="0x0" description="Dedicated GCLK clock reference" />
-        <Enum name="XOSC32" start="0x1" description="XOSC32K clock reference" />
-        <Enum name="XOSC0" start="0x2" description="XOSC0 clock reference" />
-        <Enum name="XOSC1" start="0x3" description="XOSC1 clock reference" />
-      </BitField>
-      <BitField start="8" size="3" name="LTIME" description="Lock Time">
-        <Enum name="DEFAULT" start="0x0" description="No time-out. Automatic lock" />
-        <Enum name="800US" start="0x4" description="Time-out if no lock within 800us" />
-        <Enum name="900US" start="0x5" description="Time-out if no lock within 900us" />
-        <Enum name="1MS" start="0x6" description="Time-out if no lock within 1ms" />
-        <Enum name="1P1MS" start="0x7" description="Time-out if no lock within 1.1ms" />
-      </BitField>
-      <BitField start="11" size="1" name="LBYPASS" description="Lock Bypass" />
-      <BitField start="12" size="3" name="DCOFILTER" description="Sigma-Delta DCO Filter Selection" />
-      <BitField start="15" size="1" name="DCOEN" description="DCO Filter Enable" />
-      <BitField start="16" size="11" name="DIV" description="Clock Divider" />
-    </Register>
-    <Register start="+0x3C+0" size="4" name="OSCCTRL_DPLLSYNCBUSY0" access="ReadOnly" description="DPLL Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable Synchronization Status" />
-      <BitField start="2" size="1" name="DPLLRATIO" description="DPLL Loop Divider Ratio Synchronization Status" />
-    </Register>
-    <Register start="+0x3C+20" size="4" name="OSCCTRL_DPLLSYNCBUSY1" access="ReadOnly" description="DPLL Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable Synchronization Status" />
-      <BitField start="2" size="1" name="DPLLRATIO" description="DPLL Loop Divider Ratio Synchronization Status" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="OSCCTRL_DPLLSTATUS0" access="ReadOnly" description="DPLL Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="DPLL Lock Status" />
-      <BitField start="1" size="1" name="CLKRDY" description="DPLL Clock Ready" />
-    </Register>
-    <Register start="+0x40+20" size="4" name="OSCCTRL_DPLLSTATUS1" access="ReadOnly" description="DPLL Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="DPLL Lock Status" />
-      <BitField start="1" size="1" name="CLKRDY" description="DPLL Clock Ready" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OSC32KCTRL" start="0x40001400" description="32kHz Oscillators Control">
-    <Register start="+0x00" size="4" name="OSC32KCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector Interrupt Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="OSC32KCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="OSC32KCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector" />
-    </Register>
-    <Register start="+0x0C" size="4" name="OSC32KCTRL_STATUS" access="ReadOnly" description="Power and Clocks Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector" />
-      <BitField start="3" size="1" name="XOSC32KSW" description="XOSC32K Clock switch" />
-    </Register>
-    <Register start="+0x10" size="1" name="OSC32KCTRL_RTCCTRL" access="Read/Write" description="RTC Clock Selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RTCSEL" description="RTC Clock Selection">
-        <Enum name="ULP1K" start="0x0" description="1.024kHz from 32kHz internal ULP oscillator" />
-        <Enum name="ULP32K" start="0x1" description="32.768kHz from 32kHz internal ULP oscillator" />
-        <Enum name="XOSC1K" start="0x4" description="1.024kHz from 32.768kHz internal oscillator" />
-        <Enum name="XOSC32K" start="0x5" description="32.768kHz from 32.768kHz external crystal oscillator" />
-      </BitField>
-    </Register>
-    <Register start="+0x14" size="2" name="OSC32KCTRL_XOSC32K" access="Read/Write" description="32kHz External Crystal Oscillator (XOSC32K) Control" reset_value="0x2080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="3" size="1" name="EN32K" description="32kHz Output Enable" />
-      <BitField start="4" size="1" name="EN1K" description="1kHz Output Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="STARTUP" description="Oscillator Start-Up Time" />
-      <BitField start="12" size="1" name="WRTLOCK" description="Write Lock" />
-      <BitField start="13" size="2" name="CGM" description="Control Gain Mode">
-        <Enum name="XT" start="0x1" description="Standard mode" />
-        <Enum name="HS" start="0x2" description="High Speed mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x16" size="1" name="OSC32KCTRL_CFDCTRL" access="Read/Write" description="Clock Failure Detector Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CFDEN" description="Clock Failure Detector Enable" />
-      <BitField start="1" size="1" name="SWBACK" description="Clock Switch Back" />
-      <BitField start="2" size="1" name="CFDPRESC" description="Clock Failure Detector Prescaler" />
-    </Register>
-    <Register start="+0x17" size="1" name="OSC32KCTRL_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CFDEO" description="Clock Failure Detector Event Output Enable" />
-    </Register>
-    <Register start="+0x1C" size="4" name="OSC32KCTRL_OSCULP32K" access="Read/Write" description="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="EN32K" description="Enable Out 32k" />
-      <BitField start="2" size="1" name="EN1K" description="Enable Out 1k" />
-      <BitField start="8" size="6" name="CALIB" description="Oscillator Calibration" />
-      <BitField start="15" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC" start="0x40000000" description="Peripheral Access Controller">
-    <Register start="+0x00" size="4" name="PAC_WRCTRL" access="Read/Write" description="Write control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PERID" description="Peripheral identifier" />
-      <BitField start="16" size="8" name="KEY" description="Peripheral access control key">
-        <Enum name="OFF" start="0x0" description="No action" />
-        <Enum name="CLR" start="0x1" description="Clear protection" />
-        <Enum name="SET" start="0x2" description="Set protection" />
-        <Enum name="SETLCK" start="0x3" description="Set and lock protection" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="PAC_EVCTRL" access="Read/Write" description="Event control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERREO" description="Peripheral acess error event output" />
-    </Register>
-    <Register start="+0x08" size="1" name="PAC_INTENCLR" access="Read/Write" description="Interrupt enable clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERR" description="Peripheral access error interrupt disable" />
-    </Register>
-    <Register start="+0x09" size="1" name="PAC_INTENSET" access="Read/Write" description="Interrupt enable set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERR" description="Peripheral access error interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="PAC_INTFLAGAHB" access="Read/Write" description="Bridge interrupt flag status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLASH_" description="FLASH" />
-      <BitField start="1" size="1" name="FLASH_ALT_" description="FLASH_ALT" />
-      <BitField start="2" size="1" name="SEEPROM_" description="SEEPROM" />
-      <BitField start="3" size="1" name="RAMCM4S_" description="RAMCM4S" />
-      <BitField start="4" size="1" name="RAMPPPDSU_" description="RAMPPPDSU" />
-      <BitField start="5" size="1" name="RAMDMAWR_" description="RAMDMAWR" />
-      <BitField start="6" size="1" name="RAMDMACICM_" description="RAMDMACICM" />
-      <BitField start="7" size="1" name="HPB0_" description="HPB0" />
-      <BitField start="8" size="1" name="HPB1_" description="HPB1" />
-      <BitField start="9" size="1" name="HPB2_" description="HPB2" />
-      <BitField start="10" size="1" name="HPB3_" description="HPB3" />
-      <BitField start="11" size="1" name="PUKCC_" description="PUKCC" />
-      <BitField start="12" size="1" name="SDHC0_" description="SDHC0" />
-      <BitField start="14" size="1" name="QSPI_" description="QSPI" />
-      <BitField start="15" size="1" name="BKUPRAM_" description="BKUPRAM" />
-    </Register>
-    <Register start="+0x14" size="4" name="PAC_INTFLAGA" access="Read/Write" description="Peripheral interrupt flag status - Bridge A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC_" description="PAC" />
-      <BitField start="1" size="1" name="PM_" description="PM" />
-      <BitField start="2" size="1" name="MCLK_" description="MCLK" />
-      <BitField start="3" size="1" name="RSTC_" description="RSTC" />
-      <BitField start="4" size="1" name="OSCCTRL_" description="OSCCTRL" />
-      <BitField start="5" size="1" name="OSC32KCTRL_" description="OSC32KCTRL" />
-      <BitField start="6" size="1" name="SUPC_" description="SUPC" />
-      <BitField start="7" size="1" name="GCLK_" description="GCLK" />
-      <BitField start="8" size="1" name="WDT_" description="WDT" />
-      <BitField start="9" size="1" name="RTC_" description="RTC" />
-      <BitField start="10" size="1" name="EIC_" description="EIC" />
-      <BitField start="11" size="1" name="FREQM_" description="FREQM" />
-      <BitField start="12" size="1" name="SERCOM0_" description="SERCOM0" />
-      <BitField start="13" size="1" name="SERCOM1_" description="SERCOM1" />
-      <BitField start="14" size="1" name="TC0_" description="TC0" />
-      <BitField start="15" size="1" name="TC1_" description="TC1" />
-    </Register>
-    <Register start="+0x18" size="4" name="PAC_INTFLAGB" access="Read/Write" description="Peripheral interrupt flag status - Bridge B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_" description="USB" />
-      <BitField start="1" size="1" name="DSU_" description="DSU" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL" />
-      <BitField start="3" size="1" name="CMCC_" description="CMCC" />
-      <BitField start="4" size="1" name="PORT_" description="PORT" />
-      <BitField start="5" size="1" name="DMAC_" description="DMAC" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX" />
-      <BitField start="7" size="1" name="EVSYS_" description="EVSYS" />
-      <BitField start="9" size="1" name="SERCOM2_" description="SERCOM2" />
-      <BitField start="10" size="1" name="SERCOM3_" description="SERCOM3" />
-      <BitField start="11" size="1" name="TCC0_" description="TCC0" />
-      <BitField start="12" size="1" name="TCC1_" description="TCC1" />
-      <BitField start="13" size="1" name="TC2_" description="TC2" />
-      <BitField start="14" size="1" name="TC3_" description="TC3" />
-      <BitField start="15" size="1" name="TAL_" description="TAL" />
-      <BitField start="16" size="1" name="RAMECC_" description="RAMECC" />
-    </Register>
-    <Register start="+0x1C" size="4" name="PAC_INTFLAGC" access="Read/Write" description="Peripheral interrupt flag status - Bridge C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="TCC2_" description="TCC2" />
-      <BitField start="4" size="1" name="TCC3_" description="TCC3" />
-      <BitField start="5" size="1" name="TC4_" description="TC4" />
-      <BitField start="6" size="1" name="TC5_" description="TC5" />
-      <BitField start="7" size="1" name="PDEC_" description="PDEC" />
-      <BitField start="8" size="1" name="AC_" description="AC" />
-      <BitField start="9" size="1" name="AES_" description="AES" />
-      <BitField start="10" size="1" name="TRNG_" description="TRNG" />
-      <BitField start="11" size="1" name="ICM_" description="ICM" />
-      <BitField start="12" size="1" name="PUKCC_" description="PUKCC" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI" />
-      <BitField start="14" size="1" name="CCL_" description="CCL" />
-    </Register>
-    <Register start="+0x20" size="4" name="PAC_INTFLAGD" access="Read/Write" description="Peripheral interrupt flag status - Bridge D" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4_" description="SERCOM4" />
-      <BitField start="1" size="1" name="SERCOM5_" description="SERCOM5" />
-      <BitField start="4" size="1" name="TCC4_" description="TCC4" />
-      <BitField start="7" size="1" name="ADC0_" description="ADC0" />
-      <BitField start="8" size="1" name="ADC1_" description="ADC1" />
-      <BitField start="9" size="1" name="DAC_" description="DAC" />
-      <BitField start="10" size="1" name="I2S_" description="I2S" />
-      <BitField start="11" size="1" name="PCC_" description="PCC" />
-    </Register>
-    <Register start="+0x34" size="4" name="PAC_STATUSA" access="ReadOnly" description="Peripheral write protection status - Bridge A" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC_" description="PAC APB Protect Enable" />
-      <BitField start="1" size="1" name="PM_" description="PM APB Protect Enable" />
-      <BitField start="2" size="1" name="MCLK_" description="MCLK APB Protect Enable" />
-      <BitField start="3" size="1" name="RSTC_" description="RSTC APB Protect Enable" />
-      <BitField start="4" size="1" name="OSCCTRL_" description="OSCCTRL APB Protect Enable" />
-      <BitField start="5" size="1" name="OSC32KCTRL_" description="OSC32KCTRL APB Protect Enable" />
-      <BitField start="6" size="1" name="SUPC_" description="SUPC APB Protect Enable" />
-      <BitField start="7" size="1" name="GCLK_" description="GCLK APB Protect Enable" />
-      <BitField start="8" size="1" name="WDT_" description="WDT APB Protect Enable" />
-      <BitField start="9" size="1" name="RTC_" description="RTC APB Protect Enable" />
-      <BitField start="10" size="1" name="EIC_" description="EIC APB Protect Enable" />
-      <BitField start="11" size="1" name="FREQM_" description="FREQM APB Protect Enable" />
-      <BitField start="12" size="1" name="SERCOM0_" description="SERCOM0 APB Protect Enable" />
-      <BitField start="13" size="1" name="SERCOM1_" description="SERCOM1 APB Protect Enable" />
-      <BitField start="14" size="1" name="TC0_" description="TC0 APB Protect Enable" />
-      <BitField start="15" size="1" name="TC1_" description="TC1 APB Protect Enable" />
-    </Register>
-    <Register start="+0x38" size="4" name="PAC_STATUSB" access="ReadOnly" description="Peripheral write protection status - Bridge B" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_" description="USB APB Protect Enable" />
-      <BitField start="1" size="1" name="DSU_" description="DSU APB Protect Enable" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL APB Protect Enable" />
-      <BitField start="3" size="1" name="CMCC_" description="CMCC APB Protect Enable" />
-      <BitField start="4" size="1" name="PORT_" description="PORT APB Protect Enable" />
-      <BitField start="5" size="1" name="DMAC_" description="DMAC APB Protect Enable" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX APB Protect Enable" />
-      <BitField start="7" size="1" name="EVSYS_" description="EVSYS APB Protect Enable" />
-      <BitField start="9" size="1" name="SERCOM2_" description="SERCOM2 APB Protect Enable" />
-      <BitField start="10" size="1" name="SERCOM3_" description="SERCOM3 APB Protect Enable" />
-      <BitField start="11" size="1" name="TCC0_" description="TCC0 APB Protect Enable" />
-      <BitField start="12" size="1" name="TCC1_" description="TCC1 APB Protect Enable" />
-      <BitField start="13" size="1" name="TC2_" description="TC2 APB Protect Enable" />
-      <BitField start="14" size="1" name="TC3_" description="TC3 APB Protect Enable" />
-      <BitField start="15" size="1" name="TAL_" description="TAL APB Protect Enable" />
-      <BitField start="16" size="1" name="RAMECC_" description="RAMECC APB Protect Enable" />
-    </Register>
-    <Register start="+0x3C" size="4" name="PAC_STATUSC" access="ReadOnly" description="Peripheral write protection status - Bridge C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="TCC2_" description="TCC2 APB Protect Enable" />
-      <BitField start="4" size="1" name="TCC3_" description="TCC3 APB Protect Enable" />
-      <BitField start="5" size="1" name="TC4_" description="TC4 APB Protect Enable" />
-      <BitField start="6" size="1" name="TC5_" description="TC5 APB Protect Enable" />
-      <BitField start="7" size="1" name="PDEC_" description="PDEC APB Protect Enable" />
-      <BitField start="8" size="1" name="AC_" description="AC APB Protect Enable" />
-      <BitField start="9" size="1" name="AES_" description="AES APB Protect Enable" />
-      <BitField start="10" size="1" name="TRNG_" description="TRNG APB Protect Enable" />
-      <BitField start="11" size="1" name="ICM_" description="ICM APB Protect Enable" />
-      <BitField start="12" size="1" name="PUKCC_" description="PUKCC APB Protect Enable" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI APB Protect Enable" />
-      <BitField start="14" size="1" name="CCL_" description="CCL APB Protect Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="PAC_STATUSD" access="ReadOnly" description="Peripheral write protection status - Bridge D" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4_" description="SERCOM4 APB Protect Enable" />
-      <BitField start="1" size="1" name="SERCOM5_" description="SERCOM5 APB Protect Enable" />
-      <BitField start="4" size="1" name="TCC4_" description="TCC4 APB Protect Enable" />
-      <BitField start="7" size="1" name="ADC0_" description="ADC0 APB Protect Enable" />
-      <BitField start="8" size="1" name="ADC1_" description="ADC1 APB Protect Enable" />
-      <BitField start="9" size="1" name="DAC_" description="DAC APB Protect Enable" />
-      <BitField start="10" size="1" name="I2S_" description="I2S APB Protect Enable" />
-      <BitField start="11" size="1" name="PCC_" description="PCC APB Protect Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PCC" start="0x43002C00" description="Parallel Capture Controller">
-    <Register start="+0x00" size="4" name="PCC_MR" access="Read/Write" description="Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCEN" description="Parallel Capture Enable" />
-      <BitField start="4" size="2" name="DSIZE" description="Data size" />
-      <BitField start="8" size="1" name="SCALE" description="Scale data" />
-      <BitField start="9" size="1" name="ALWYS" description="Always Sampling" />
-      <BitField start="10" size="1" name="HALFS" description="Half Sampling" />
-      <BitField start="11" size="1" name="FRSTS" description="First sample" />
-      <BitField start="16" size="3" name="ISIZE" description="Input Data Size" />
-      <BitField start="30" size="2" name="CID" description="Clear If Disabled" />
-    </Register>
-    <Register start="+0x04" size="4" name="PCC_IER" access="WriteOnly" description="Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="PCC_IDR" access="WriteOnly" description="Interrupt Disable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Disable" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="PCC_IMR" access="ReadOnly" description="Interrupt Mask Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Mask" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Mask" />
-    </Register>
-    <Register start="+0x10" size="4" name="PCC_ISR" access="ReadOnly" description="Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Status" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Status" />
-    </Register>
-    <Register start="+0x14" size="4" name="PCC_RHR" access="ReadOnly" description="Reception Holding Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RDATA" description="Reception Data" />
-    </Register>
-    <Register start="+0xE0" size="4" name="PCC_WPMR" access="Read/Write" description="Write Protection Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WPEN" description="Write Protection Enable" />
-      <BitField start="8" size="24" name="WPKEY" description="Write Protection Key" />
-    </Register>
-    <Register start="+0xE4" size="4" name="PCC_WPSR" access="ReadOnly" description="Write Protection Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WPVS" description="Write Protection Violation Source" />
-      <BitField start="8" size="16" name="WPVSRC" description="Write Protection Violation Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PDEC" start="0x42001C00" description="Quadrature Decodeur">
-    <Register start="+0x00" size="4" name="PDEC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operation Mode">
-        <Enum name="QDEC" start="0x0" description="QDEC operating mode" />
-        <Enum name="HALL" start="0x1" description="HALL operating mode" />
-        <Enum name="COUNTER" start="0x2" description="COUNTER operating mode" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="3" name="CONF" description="PDEC Configuration">
-        <Enum name="X4" start="0x0" description="Quadrature decoder direction" />
-        <Enum name="X4S" start="0x1" description="Secure Quadrature decoder direction" />
-        <Enum name="X2" start="0x2" description="Decoder direction" />
-        <Enum name="X2S" start="0x3" description="Secure decoder direction" />
-        <Enum name="AUTOC" start="0x4" description="Auto correction mode" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="14" size="1" name="SWAP" description="PDEC Phase A and B Swap" />
-      <BitField start="15" size="1" name="PEREN" description="Period Enable" />
-      <BitField start="16" size="1" name="PINEN0" description="PDEC Input From Pin 0 Enable" />
-      <BitField start="17" size="1" name="PINEN1" description="PDEC Input From Pin 1 Enable" />
-      <BitField start="18" size="1" name="PINEN2" description="PDEC Input From Pin 2 Enable" />
-      <BitField start="20" size="1" name="PINVEN0" description="IO Pin 0 Invert Enable" />
-      <BitField start="21" size="1" name="PINVEN1" description="IO Pin 1 Invert Enable" />
-      <BitField start="22" size="1" name="PINVEN2" description="IO Pin 2 Invert Enable" />
-      <BitField start="24" size="3" name="ANGULAR" description="Angular Counter Length" />
-      <BitField start="28" size="4" name="MAXCMP" description="Maximum Consecutive Missing Pulses" />
-    </Register>
-    <Register start="+0x04" size="1" name="PDEC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a counter restart or retrigger" />
-        <Enum name="UPDATE" start="0x2" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x3" description="Force a read synchronization of COUNT" />
-        <Enum name="START" start="0x4" description="Start QDEC/HALL" />
-        <Enum name="STOP" start="0x5" description="Stop QDEC/HALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="PDEC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a counter restart or retrigger" />
-        <Enum name="UPDATE" start="0x2" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x3" description="Force a read synchronization of COUNT" />
-        <Enum name="Start" start="0x4" description="Start QDEC/HALL" />
-        <Enum name="Stop" start="0x5" description="Stop QDEC/HALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="PDEC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-      </BitField>
-      <BitField start="2" size="3" name="EVINV" description="Inverted Event Input Enable" />
-      <BitField start="5" size="3" name="EVEI" description="Event Input Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="ERREO" description="Error  Output Event Enable" />
-      <BitField start="10" size="1" name="DIREO" description="Direction Output Event Enable" />
-      <BitField start="11" size="1" name="VLCEO" description="Velocity Output Event Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="PDEC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow/Underflow Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Disable" />
-      <BitField start="2" size="1" name="DIR" description="Direction Interrupt Disable" />
-      <BitField start="3" size="1" name="VLC" description="Velocity Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="Channel 0 Compare Match Disable" />
-      <BitField start="5" size="1" name="MC1" description="Channel 1 Compare Match Disable" />
-    </Register>
-    <Register start="+0x09" size="1" name="PDEC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow/Underflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="2" size="1" name="DIR" description="Direction Interrupt Enable" />
-      <BitField start="3" size="1" name="VLC" description="Velocity Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Channel 0 Compare Match Enable" />
-      <BitField start="5" size="1" name="MC1" description="Channel 1 Compare Match Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="PDEC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow/Underflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="2" size="1" name="DIR" description="Direction Change" />
-      <BitField start="3" size="1" name="VLC" description="Velocity" />
-      <BitField start="4" size="1" name="MC0" description="Channel 0 Compare Match" />
-      <BitField start="5" size="1" name="MC1" description="Channel 1 Compare Match" />
-    </Register>
-    <Register start="+0x0C" size="2" name="PDEC_STATUS" access="Read/Write" description="Status" reset_value="0x0040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="QERR" description="Quadrature Error Flag" />
-      <BitField start="1" size="1" name="IDXERR" description="Index Error Flag" />
-      <BitField start="2" size="1" name="MPERR" description="Missing Pulse Error flag" />
-      <BitField start="4" size="1" name="WINERR" description="Window Error Flag" />
-      <BitField start="5" size="1" name="HERR" description="Hall Error Flag" />
-      <BitField start="6" size="1" name="STOP" description="Stop" />
-      <BitField start="7" size="1" name="DIR" description="Direction Status Flag" />
-      <BitField start="8" size="1" name="PRESCBUFV" description="Prescaler Buffer Valid" />
-      <BitField start="9" size="1" name="FILTERBUFV" description="Filter Buffer Valid" />
-      <BitField start="12" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="13" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-    </Register>
-    <Register start="+0x0F" size="1" name="PDEC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x10" size="4" name="PDEC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Control B Synchronization Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Synchronization Busy" />
-      <BitField start="4" size="1" name="PRESC" description="Prescaler Synchronization Busy" />
-      <BitField start="5" size="1" name="FILTER" description="Filter Synchronization Busy" />
-      <BitField start="6" size="1" name="COUNT" description="Count Synchronization Busy" />
-      <BitField start="7" size="1" name="CC0" description="Compare Channel 0 Synchronization Busy" />
-      <BitField start="8" size="1" name="CC1" description="Compare Channel 1 Synchronization Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="PDEC_PRESC" access="Read/Write" description="Prescaler Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESC" description="Prescaler Value">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-        <Enum name="DIV256" start="0x8" description="Divide by 256" />
-        <Enum name="DIV512" start="0x9" description="Divide by 512" />
-        <Enum name="DIV1024" start="0xa" description="Divide by 1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x15" size="1" name="PDEC_FILTER" access="Read/Write" description="Filter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FILTER" description="Filter Value" />
-    </Register>
-    <Register start="+0x18" size="1" name="PDEC_PRESCBUF" access="Read/Write" description="Prescaler Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCBUF" description="Prescaler Buffer Value">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-        <Enum name="DIV256" start="0x8" description="Divide by 256" />
-        <Enum name="DIV512" start="0x9" description="Divide by 512" />
-        <Enum name="DIV1024" start="0xa" description="Divide by 1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x19" size="1" name="PDEC_FILTERBUF" access="Read/Write" description="Filter Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FILTERBUF" description="Filter Buffer Value" />
-    </Register>
-    <Register start="+0x1C" size="4" name="PDEC_COUNT" access="Read/Write" description="Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="PDEC_CC0" access="Read/Write" description="Channel n Compare Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Channel Compare Value" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="PDEC_CC1" access="Read/Write" description="Channel n Compare Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Channel Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="PDEC_CCBUF0" access="Read/Write" description="Channel Compare Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Channel Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="PDEC_CCBUF1" access="Read/Write" description="Channel Compare Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Channel Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PM" start="0x40000400" description="Power Manager">
-    <Register start="+0x00" size="1" name="PM_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="IORET" description="I/O Retention" />
-    </Register>
-    <Register start="+0x01" size="1" name="PM_SLEEPCFG" access="Read/Write" description="Sleep Configuration" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SLEEPMODE" description="Sleep Mode">
-        <Enum name="IDLE0" start="0x0" description="CPU clock is OFF" />
-        <Enum name="IDLE1" start="0x1" description="AHB clock is OFF" />
-        <Enum name="IDLE2" start="0x2" description="APB clock are OFF" />
-        <Enum name="STANDBY" start="0x4" description="All Clocks are OFF" />
-        <Enum name="HIBERNATE" start="0x5" description="Backup domain is ON as well as some PDRAMs" />
-        <Enum name="BACKUP" start="0x6" description="Only Backup domain is powered ON" />
-        <Enum name="OFF" start="0x7" description="All power domains are powered OFF" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="PM_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEPRDY" description="Sleep Mode Entry Ready Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="PM_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEPRDY" description="Sleep Mode Entry Ready Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="PM_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEPRDY" description="Sleep Mode Entry Ready" />
-    </Register>
-    <Register start="+0x08" size="1" name="PM_STDBYCFG" access="Read/Write" description="Standby Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAMCFG" description="Ram Configuration">
-        <Enum name="RET" start="0x0" description="All the RAMs are retained" />
-        <Enum name="PARTIAL" start="0x1" description="Only the first 32K bytes are retained" />
-        <Enum name="OFF" start="0x2" description="All the RAMs are OFF" />
-      </BitField>
-      <BitField start="4" size="2" name="FASTWKUP" description="Fast Wakeup" />
-    </Register>
-    <Register start="+0x09" size="1" name="PM_HIBCFG" access="Read/Write" description="Hibernate Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAMCFG" description="Ram Configuration" />
-      <BitField start="2" size="2" name="BRAMCFG" description="Backup Ram Configuration" />
-    </Register>
-    <Register start="+0x0A" size="1" name="PM_BKUPCFG" access="Read/Write" description="Backup Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRAMCFG" description="Ram Configuration" />
-    </Register>
-    <Register start="+0x12" size="1" name="PM_PWSAKDLY" access="Read/Write" description="Power Switch Acknowledge Delay" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DLYVAL" description="Delay Value" />
-      <BitField start="7" size="1" name="IGNACK" description="Ignore Acknowledge" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PORT" start="0x41008000" description="Port Module">
-    <Register start="+0x00+0" size="4" name="PORT_DIR0" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x00+128" size="4" name="PORT_DIR1" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x04+0" size="4" name="PORT_DIRCLR0" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x04+128" size="4" name="PORT_DIRCLR1" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x08+0" size="4" name="PORT_DIRSET0" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x08+128" size="4" name="PORT_DIRSET1" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x0C+0" size="4" name="PORT_DIRTGL0" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x0C+128" size="4" name="PORT_DIRTGL1" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x10+0" size="4" name="PORT_OUT0" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="PORT Data Output Value" />
-    </Register>
-    <Register start="+0x10+128" size="4" name="PORT_OUT1" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="PORT Data Output Value" />
-    </Register>
-    <Register start="+0x14+0" size="4" name="PORT_OUTCLR0" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="PORT Data Output Value Clear" />
-    </Register>
-    <Register start="+0x14+128" size="4" name="PORT_OUTCLR1" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="PORT Data Output Value Clear" />
-    </Register>
-    <Register start="+0x18+0" size="4" name="PORT_OUTSET0" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="PORT Data Output Value Set" />
-    </Register>
-    <Register start="+0x18+128" size="4" name="PORT_OUTSET1" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="PORT Data Output Value Set" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="PORT_OUTTGL0" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="PORT Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x1C+128" size="4" name="PORT_OUTTGL1" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="PORT Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="PORT_IN0" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="PORT Data Input Value" />
-    </Register>
-    <Register start="+0x20+128" size="4" name="PORT_IN1" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="PORT Data Input Value" />
-    </Register>
-    <Register start="+0x24+0" size="4" name="PORT_CTRL0" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x24+128" size="4" name="PORT_CTRL1" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x28+0" size="4" name="PORT_WRCONFIG0" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-    <Register start="+0x28+128" size="4" name="PORT_WRCONFIG1" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-    <Register start="+0x2C+0" size="4" name="PORT_EVCTRL0" access="Read/Write" description="Event Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PID0" description="PORT Event Pin Identifier 0" />
-      <BitField start="5" size="2" name="EVACT0" description="PORT Event Action 0">
-        <Enum name="OUT" start="0x0" description="Event output to pin" />
-        <Enum name="SET" start="0x1" description="Set output register of pin on event" />
-        <Enum name="CLR" start="0x2" description="Clear output register of pin on event" />
-        <Enum name="TGL" start="0x3" description="Toggle output register of pin on event" />
-      </BitField>
-      <BitField start="7" size="1" name="PORTEI0" description="PORT Event Input Enable 0" />
-      <BitField start="8" size="5" name="PID1" description="PORT Event Pin Identifier 1" />
-      <BitField start="13" size="2" name="EVACT1" description="PORT Event Action 1" />
-      <BitField start="15" size="1" name="PORTEI1" description="PORT Event Input Enable 1" />
-      <BitField start="16" size="5" name="PID2" description="PORT Event Pin Identifier 2" />
-      <BitField start="21" size="2" name="EVACT2" description="PORT Event Action 2" />
-      <BitField start="23" size="1" name="PORTEI2" description="PORT Event Input Enable 2" />
-      <BitField start="24" size="5" name="PID3" description="PORT Event Pin Identifier 3" />
-      <BitField start="29" size="2" name="EVACT3" description="PORT Event Action 3" />
-      <BitField start="31" size="1" name="PORTEI3" description="PORT Event Input Enable 3" />
-    </Register>
-    <Register start="+0x2C+128" size="4" name="PORT_EVCTRL1" access="Read/Write" description="Event Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PID0" description="PORT Event Pin Identifier 0" />
-      <BitField start="5" size="2" name="EVACT0" description="PORT Event Action 0">
-        <Enum name="OUT" start="0x0" description="Event output to pin" />
-        <Enum name="SET" start="0x1" description="Set output register of pin on event" />
-        <Enum name="CLR" start="0x2" description="Clear output register of pin on event" />
-        <Enum name="TGL" start="0x3" description="Toggle output register of pin on event" />
-      </BitField>
-      <BitField start="7" size="1" name="PORTEI0" description="PORT Event Input Enable 0" />
-      <BitField start="8" size="5" name="PID1" description="PORT Event Pin Identifier 1" />
-      <BitField start="13" size="2" name="EVACT1" description="PORT Event Action 1" />
-      <BitField start="15" size="1" name="PORTEI1" description="PORT Event Input Enable 1" />
-      <BitField start="16" size="5" name="PID2" description="PORT Event Pin Identifier 2" />
-      <BitField start="21" size="2" name="EVACT2" description="PORT Event Action 2" />
-      <BitField start="23" size="1" name="PORTEI2" description="PORT Event Input Enable 2" />
-      <BitField start="24" size="5" name="PID3" description="PORT Event Pin Identifier 3" />
-      <BitField start="29" size="2" name="EVACT3" description="PORT Event Action 3" />
-      <BitField start="31" size="1" name="PORTEI3" description="PORT Event Input Enable 3" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="PORT_PMUX0_0" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="PORT_PMUX0_1" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+2" size="1" name="PORT_PMUX0_2" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+3" size="1" name="PORT_PMUX0_3" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+4" size="1" name="PORT_PMUX0_4" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+5" size="1" name="PORT_PMUX0_5" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+6" size="1" name="PORT_PMUX0_6" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+7" size="1" name="PORT_PMUX0_7" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+8" size="1" name="PORT_PMUX0_8" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+9" size="1" name="PORT_PMUX0_9" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+10" size="1" name="PORT_PMUX0_10" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+11" size="1" name="PORT_PMUX0_11" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+12" size="1" name="PORT_PMUX0_12" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+13" size="1" name="PORT_PMUX0_13" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+14" size="1" name="PORT_PMUX0_14" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+15" size="1" name="PORT_PMUX0_15" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+0" size="1" name="PORT_PMUX1_0" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+1" size="1" name="PORT_PMUX1_1" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+2" size="1" name="PORT_PMUX1_2" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+3" size="1" name="PORT_PMUX1_3" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+4" size="1" name="PORT_PMUX1_4" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+5" size="1" name="PORT_PMUX1_5" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+6" size="1" name="PORT_PMUX1_6" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+7" size="1" name="PORT_PMUX1_7" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+8" size="1" name="PORT_PMUX1_8" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+9" size="1" name="PORT_PMUX1_9" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+10" size="1" name="PORT_PMUX1_10" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+11" size="1" name="PORT_PMUX1_11" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+12" size="1" name="PORT_PMUX1_12" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+13" size="1" name="PORT_PMUX1_13" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+14" size="1" name="PORT_PMUX1_14" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+15" size="1" name="PORT_PMUX1_15" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x40+0" size="1" name="PORT_PINCFG0_0" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+1" size="1" name="PORT_PINCFG0_1" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+2" size="1" name="PORT_PINCFG0_2" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+3" size="1" name="PORT_PINCFG0_3" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+4" size="1" name="PORT_PINCFG0_4" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+5" size="1" name="PORT_PINCFG0_5" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+6" size="1" name="PORT_PINCFG0_6" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+7" size="1" name="PORT_PINCFG0_7" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+8" size="1" name="PORT_PINCFG0_8" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+9" size="1" name="PORT_PINCFG0_9" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+10" size="1" name="PORT_PINCFG0_10" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+11" size="1" name="PORT_PINCFG0_11" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+12" size="1" name="PORT_PINCFG0_12" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+13" size="1" name="PORT_PINCFG0_13" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+14" size="1" name="PORT_PINCFG0_14" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+15" size="1" name="PORT_PINCFG0_15" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+16" size="1" name="PORT_PINCFG0_16" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+17" size="1" name="PORT_PINCFG0_17" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+18" size="1" name="PORT_PINCFG0_18" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+19" size="1" name="PORT_PINCFG0_19" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+20" size="1" name="PORT_PINCFG0_20" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+21" size="1" name="PORT_PINCFG0_21" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+22" size="1" name="PORT_PINCFG0_22" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+23" size="1" name="PORT_PINCFG0_23" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+24" size="1" name="PORT_PINCFG0_24" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+25" size="1" name="PORT_PINCFG0_25" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+26" size="1" name="PORT_PINCFG0_26" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+27" size="1" name="PORT_PINCFG0_27" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+28" size="1" name="PORT_PINCFG0_28" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+29" size="1" name="PORT_PINCFG0_29" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+30" size="1" name="PORT_PINCFG0_30" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+31" size="1" name="PORT_PINCFG0_31" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+0" size="1" name="PORT_PINCFG1_0" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+1" size="1" name="PORT_PINCFG1_1" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+2" size="1" name="PORT_PINCFG1_2" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+3" size="1" name="PORT_PINCFG1_3" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+4" size="1" name="PORT_PINCFG1_4" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+5" size="1" name="PORT_PINCFG1_5" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+6" size="1" name="PORT_PINCFG1_6" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+7" size="1" name="PORT_PINCFG1_7" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+8" size="1" name="PORT_PINCFG1_8" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+9" size="1" name="PORT_PINCFG1_9" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+10" size="1" name="PORT_PINCFG1_10" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+11" size="1" name="PORT_PINCFG1_11" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+12" size="1" name="PORT_PINCFG1_12" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+13" size="1" name="PORT_PINCFG1_13" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+14" size="1" name="PORT_PINCFG1_14" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+15" size="1" name="PORT_PINCFG1_15" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+16" size="1" name="PORT_PINCFG1_16" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+17" size="1" name="PORT_PINCFG1_17" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+18" size="1" name="PORT_PINCFG1_18" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+19" size="1" name="PORT_PINCFG1_19" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+20" size="1" name="PORT_PINCFG1_20" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+21" size="1" name="PORT_PINCFG1_21" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+22" size="1" name="PORT_PINCFG1_22" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+23" size="1" name="PORT_PINCFG1_23" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+24" size="1" name="PORT_PINCFG1_24" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+25" size="1" name="PORT_PINCFG1_25" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+26" size="1" name="PORT_PINCFG1_26" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+27" size="1" name="PORT_PINCFG1_27" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+28" size="1" name="PORT_PINCFG1_28" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+29" size="1" name="PORT_PINCFG1_29" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+30" size="1" name="PORT_PINCFG1_30" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+31" size="1" name="PORT_PINCFG1_31" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QSPI" start="0x42003400" description="Quad SPI interface">
-    <Register start="+0x00" size="4" name="QSPI_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="24" size="1" name="LASTXFER" description="Last Transfer" />
-    </Register>
-    <Register start="+0x04" size="4" name="QSPI_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Serial Memory Mode">
-        <Enum name="SPI" start="0x0" description="SPI operating mode" />
-        <Enum name="MEMORY" start="0x1" description="Serial Memory operating mode" />
-      </BitField>
-      <BitField start="1" size="1" name="LOOPEN" description="Local Loopback Enable" />
-      <BitField start="2" size="1" name="WDRBT" description="Wait Data Read Before Transfer" />
-      <BitField start="3" size="1" name="SMEMREG" description="Serial Memory reg" />
-      <BitField start="4" size="2" name="CSMODE" description="Chip Select Mode">
-        <Enum name="NORELOAD" start="0x0" description="The chip select is deasserted if TD has not been reloaded before the end of the current transfer." />
-        <Enum name="LASTXFER" start="0x1" description="The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred." />
-        <Enum name="SYSTEMATICALLY" start="0x2" description="The chip select is deasserted systematically after each transfer." />
-      </BitField>
-      <BitField start="8" size="4" name="DATALEN" description="Data Length">
-        <Enum name="8BITS" start="0x0" description="8-bits transfer" />
-        <Enum name="9BITS" start="0x1" description="9 bits transfer" />
-        <Enum name="10BITS" start="0x2" description="10-bits transfer" />
-        <Enum name="11BITS" start="0x3" description="11-bits transfer" />
-        <Enum name="12BITS" start="0x4" description="12-bits transfer" />
-        <Enum name="13BITS" start="0x5" description="13-bits transfer" />
-        <Enum name="14BITS" start="0x6" description="14-bits transfer" />
-        <Enum name="15BITS" start="0x7" description="15-bits transfer" />
-        <Enum name="16BITS" start="0x8" description="16-bits transfer" />
-      </BitField>
-      <BitField start="16" size="8" name="DLYBCT" description="Delay Between Consecutive Transfers" />
-      <BitField start="24" size="8" name="DLYCS" description="Minimum Inactive CS Delay" />
-    </Register>
-    <Register start="+0x08" size="4" name="QSPI_BAUD" access="Read/Write" description="Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="1" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="8" size="8" name="BAUD" description="Serial Clock Baud Rate" />
-      <BitField start="16" size="8" name="DLYBS" description="Delay Before SCK" />
-    </Register>
-    <Register start="+0x0C" size="4" name="QSPI_RXDATA" access="ReadOnly" description="Receive Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Receive Data" />
-    </Register>
-    <Register start="+0x10" size="4" name="QSPI_TXDATA" access="WriteOnly" description="Transmit Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Transmit Data" />
-    </Register>
-    <Register start="+0x14" size="4" name="QSPI_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXC" description="Receive Data Register Full Interrupt Disable" />
-      <BitField start="1" size="1" name="DRE" description="Transmit Data Register Empty Interrupt Disable" />
-      <BitField start="2" size="1" name="TXC" description="Transmission Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="ERROR" description="Overrun Error Interrupt Disable" />
-      <BitField start="8" size="1" name="CSRISE" description="Chip Select Rise Interrupt Disable" />
-      <BitField start="10" size="1" name="INSTREND" description="Instruction End Interrupt Disable" />
-    </Register>
-    <Register start="+0x18" size="4" name="QSPI_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXC" description="Receive Data Register Full Interrupt Enable" />
-      <BitField start="1" size="1" name="DRE" description="Transmit Data Register Empty Interrupt Enable" />
-      <BitField start="2" size="1" name="TXC" description="Transmission Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="ERROR" description="Overrun Error Interrupt Enable" />
-      <BitField start="8" size="1" name="CSRISE" description="Chip Select Rise Interrupt Enable" />
-      <BitField start="10" size="1" name="INSTREND" description="Instruction End Interrupt Enable" />
-    </Register>
-    <Register start="+0x1C" size="4" name="QSPI_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXC" description="Receive Data Register Full" />
-      <BitField start="1" size="1" name="DRE" description="Transmit Data Register Empty" />
-      <BitField start="2" size="1" name="TXC" description="Transmission Complete" />
-      <BitField start="3" size="1" name="ERROR" description="Overrun Error" />
-      <BitField start="8" size="1" name="CSRISE" description="Chip Select Rise" />
-      <BitField start="10" size="1" name="INSTREND" description="Instruction End" />
-    </Register>
-    <Register start="+0x20" size="4" name="QSPI_STATUS" access="ReadOnly" description="Status Register" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="9" size="1" name="CSSTATUS" description="Chip Select" />
-    </Register>
-    <Register start="+0x30" size="4" name="QSPI_INSTRADDR" access="Read/Write" description="Instruction Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="Instruction Address" />
-    </Register>
-    <Register start="+0x34" size="4" name="QSPI_INSTRCTRL" access="Read/Write" description="Instruction Code" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="INSTR" description="Instruction Code" />
-      <BitField start="16" size="8" name="OPTCODE" description="Option Code" />
-    </Register>
-    <Register start="+0x38" size="4" name="QSPI_INSTRFRAME" access="Read/Write" description="Instruction Frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WIDTH" description="Instruction Code, Address, Option Code and Data Width">
-        <Enum name="SINGLE_BIT_SPI" start="0x0" description="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI" />
-        <Enum name="DUAL_OUTPUT" start="0x1" description="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI" />
-        <Enum name="QUAD_OUTPUT" start="0x2" description="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI" />
-        <Enum name="DUAL_IO" start="0x3" description="Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI" />
-        <Enum name="QUAD_IO" start="0x4" description="Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI" />
-        <Enum name="DUAL_CMD" start="0x5" description="Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI" />
-        <Enum name="QUAD_CMD" start="0x6" description="Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI" />
-      </BitField>
-      <BitField start="4" size="1" name="INSTREN" description="Instruction Enable" />
-      <BitField start="5" size="1" name="ADDREN" description="Address Enable" />
-      <BitField start="6" size="1" name="OPTCODEEN" description="Option Enable" />
-      <BitField start="7" size="1" name="DATAEN" description="Data Enable" />
-      <BitField start="8" size="2" name="OPTCODELEN" description="Option Code Length">
-        <Enum name="1BIT" start="0x0" description="1-bit length option code" />
-        <Enum name="2BITS" start="0x1" description="2-bits length option code" />
-        <Enum name="4BITS" start="0x2" description="4-bits length option code" />
-        <Enum name="8BITS" start="0x3" description="8-bits length option code" />
-      </BitField>
-      <BitField start="10" size="1" name="ADDRLEN" description="Address Length">
-        <Enum name="24BITS" start="0x0" description="24-bits address length" />
-        <Enum name="32BITS" start="0x1" description="32-bits address length" />
-      </BitField>
-      <BitField start="12" size="2" name="TFRTYPE" description="Data Transfer Type">
-        <Enum name="READ" start="0x0" description="Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible." />
-        <Enum name="READMEMORY" start="0x1" description="Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible." />
-        <Enum name="WRITE" start="0x2" description="Write transfer into the serial memory.Scrambling is not performed." />
-        <Enum name="WRITEMEMORY" start="0x3" description="Write data transfer into the serial memory.If enabled, scrambling is performed." />
-      </BitField>
-      <BitField start="14" size="1" name="CRMODE" description="Continuous Read Mode" />
-      <BitField start="15" size="1" name="DDREN" description="Double Data Rate Enable" />
-      <BitField start="16" size="5" name="DUMMYLEN" description="Dummy Cycles Length" />
-    </Register>
-    <Register start="+0x40" size="4" name="QSPI_SCRAMBCTRL" access="Read/Write" description="Scrambling Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Scrambling/Unscrambling Enable" />
-      <BitField start="1" size="1" name="RANDOMDIS" description="Scrambling/Unscrambling Random Value Disable" />
-    </Register>
-    <Register start="+0x44" size="4" name="QSPI_SCRAMBKEY" access="WriteOnly" description="Scrambling Key" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="KEY" description="Scrambling User Key" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RAMECC" start="0x41020000" description="RAM ECC">
-    <Register start="+0x0" size="1" name="RAMECC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SINGLEE" description="Single Bit ECC Error Interrupt Enable Clear" />
-      <BitField start="1" size="1" name="DUALE" description="Dual Bit ECC Error Interrupt Enable Clear" />
-    </Register>
-    <Register start="+0x1" size="1" name="RAMECC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SINGLEE" description="Single Bit ECC Error Interrupt Enable Set" />
-      <BitField start="1" size="1" name="DUALE" description="Dual Bit ECC Error Interrupt Enable Set" />
-    </Register>
-    <Register start="+0x2" size="1" name="RAMECC_INTFLAG" access="Read/Write" description="Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SINGLEE" description="Single Bit ECC Error Interrupt" />
-      <BitField start="1" size="1" name="DUALE" description="Dual Bit ECC Error Interrupt" />
-    </Register>
-    <Register start="+0x3" size="1" name="RAMECC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ECCDIS" description="ECC Disable" />
-    </Register>
-    <Register start="+0x4" size="4" name="RAMECC_ERRADDR" access="ReadOnly" description="Error Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="ERRADDR" description="Error Address" />
-    </Register>
-    <Register start="+0xF" size="1" name="RAMECC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ECCDIS" description="ECC Disable" />
-      <BitField start="1" size="1" name="ECCELOG" description="ECC Error Log" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RSTC" start="0x40000C00" description="Reset Controller">
-    <Register start="+0x00" size="1" name="RSTC_RCAUSE" access="ReadOnly" description="Reset Cause" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POR" description="Power On Reset" />
-      <BitField start="1" size="1" name="BODCORE" description="Brown Out CORE Detector Reset" />
-      <BitField start="2" size="1" name="BODVDD" description="Brown Out VDD Detector Reset" />
-      <BitField start="3" size="1" name="NVM" description="NVM Reset" />
-      <BitField start="4" size="1" name="EXT" description="External Reset" />
-      <BitField start="5" size="1" name="WDT" description="Watchdog Reset" />
-      <BitField start="6" size="1" name="SYST" description="System Reset Request" />
-      <BitField start="7" size="1" name="BACKUP" description="Backup Reset" />
-    </Register>
-    <Register start="+0x02" size="1" name="RSTC_BKUPEXIT" access="ReadOnly" description="Backup Exit Source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RTC" description="Real Timer Counter Interrupt" />
-      <BitField start="2" size="1" name="BBPS" description="Battery Backup Power Switch" />
-      <BitField start="7" size="1" name="HIB" description="Hibernate" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE0)" start="0x40002400" description="Real-Time Counter">
-    <Register start="+0x00" size="2" name="RTC_CTRLA" access="Read/Write" description="MODE0 Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="OFF" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV1" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xb" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-      <BitField start="13" size="1" name="BKTRST" description="BKUP Registers Reset On Tamper Enable" />
-      <BitField start="14" size="1" name="GPTRST" description="GP Registers Reset On Tamper Enable" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Read Synchronization Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_CTRLB" access="Read/Write" description="MODE0 Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GP0EN" description="General Purpose 0 Enable" />
-      <BitField start="1" size="1" name="GP2EN" description="General Purpose 2 Enable" />
-      <BitField start="4" size="1" name="DEBMAJ" description="Debouncer Majority Enable" />
-      <BitField start="5" size="1" name="DEBASYNC" description="Debouncer Asynchronous Enable" />
-      <BitField start="6" size="1" name="RTCOUT" description="RTC Output Enable" />
-      <BitField start="7" size="1" name="DMAEN" description="DMA Enable" />
-      <BitField start="8" size="3" name="DEBF" description="Debounce Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_DEB = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_DEB = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_DEB = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_DEB = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_DEB = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_DEB = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_DEB = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_DEB = CLK_RTC/256" />
-      </BitField>
-      <BitField start="12" size="3" name="ACTF" description="Active Layer Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_OUT = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_OUT = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_OUT = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_OUT = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_OUT = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_OUT = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_OUT = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_OUT = CLK_RTC/256" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="RTC_EVCTRL" access="Read/Write" description="MODE0 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="9" size="1" name="CMPEO1" description="Compare 1 Event Output Enable" />
-      <BitField start="14" size="1" name="TAMPEREO" description="Tamper Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-      <BitField start="16" size="1" name="TAMPEVEI" description="Tamper Event Input Enable" />
-    </Register>
-    <Register start="+0x08" size="2" name="RTC_INTENCLR" access="Read/Write" description="MODE0 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="2" name="RTC_INTENSET" access="Read/Write" description="MODE0 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="RTC_INTFLAG" access="Read/Write" description="MODE0 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper" />
-      <BitField start="15" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x0E" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_SYNCBUSY" access="ReadOnly" description="MODE0 Synchronization Busy Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Bit Busy" />
-      <BitField start="2" size="1" name="FREQCORR" description="FREQCORR Register Busy" />
-      <BitField start="3" size="1" name="COUNT" description="COUNT Register Busy" />
-      <BitField start="5" size="1" name="COMP0" description="COMP 0 Register Busy" />
-      <BitField start="6" size="1" name="COMP1" description="COMP 1 Register Busy" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Synchronization Enable Bit Busy" />
-      <BitField start="16" size="1" name="GP0" description="General Purpose 0 Register Busy" />
-      <BitField start="17" size="1" name="GP1" description="General Purpose 1 Register Busy" />
-      <BitField start="18" size="1" name="GP2" description="General Purpose 2 Register Busy" />
-      <BitField start="19" size="1" name="GP3" description="General Purpose 3 Register Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x18" size="4" name="RTC_COUNT" access="Read/Write" description="MODE0 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="RTC_COMP0" access="Read/Write" description="MODE0 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="RTC_COMP1" access="Read/Write" description="MODE0 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="RTC_GP0" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+4" size="4" name="RTC_GP1" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+8" size="4" name="RTC_GP2" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+12" size="4" name="RTC_GP3" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x60" size="4" name="RTC_TAMPCTRL" access="Read/Write" description="Tamper Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IN0ACT" description="Tamper Input 0 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN0 to OUT" />
-      </BitField>
-      <BitField start="2" size="2" name="IN1ACT" description="Tamper Input 1 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN1 to OUT" />
-      </BitField>
-      <BitField start="4" size="2" name="IN2ACT" description="Tamper Input 2 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN2 to OUT" />
-      </BitField>
-      <BitField start="6" size="2" name="IN3ACT" description="Tamper Input 3 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN3 to OUT" />
-      </BitField>
-      <BitField start="8" size="2" name="IN4ACT" description="Tamper Input 4 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN4 to OUT" />
-      </BitField>
-      <BitField start="16" size="1" name="TAMLVL0" description="Tamper Level Select 0" />
-      <BitField start="17" size="1" name="TAMLVL1" description="Tamper Level Select 1" />
-      <BitField start="18" size="1" name="TAMLVL2" description="Tamper Level Select 2" />
-      <BitField start="19" size="1" name="TAMLVL3" description="Tamper Level Select 3" />
-      <BitField start="20" size="1" name="TAMLVL4" description="Tamper Level Select 4" />
-      <BitField start="24" size="1" name="DEBNC0" description="Debouncer Enable 0" />
-      <BitField start="25" size="1" name="DEBNC1" description="Debouncer Enable 1" />
-      <BitField start="26" size="1" name="DEBNC2" description="Debouncer Enable 2" />
-      <BitField start="27" size="1" name="DEBNC3" description="Debouncer Enable 3" />
-      <BitField start="28" size="1" name="DEBNC4" description="Debouncer Enable 4" />
-    </Register>
-    <Register start="+0x64" size="4" name="RTC_TIMESTAMP" access="ReadOnly" description="MODE0 Timestamp" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Timestamp Value" />
-    </Register>
-    <Register start="+0x68" size="4" name="RTC_TAMPID" access="Read/Write" description="Tamper ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TAMPID0" description="Tamper Input 0 Detected" />
-      <BitField start="1" size="1" name="TAMPID1" description="Tamper Input 1 Detected" />
-      <BitField start="2" size="1" name="TAMPID2" description="Tamper Input 2 Detected" />
-      <BitField start="3" size="1" name="TAMPID3" description="Tamper Input 3 Detected" />
-      <BitField start="4" size="1" name="TAMPID4" description="Tamper Input 4 Detected" />
-      <BitField start="31" size="1" name="TAMPEVT" description="Tamper Event Detected" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="RTC_BKUP0" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="RTC_BKUP1" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="RTC_BKUP2" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="RTC_BKUP3" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="RTC_BKUP4" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="RTC_BKUP5" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="RTC_BKUP6" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="RTC_BKUP7" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE1)" start="0x40002400" description="Real-Time Counter">
-    <Register start="+0x00" size="2" name="RTC_CTRLA" access="Read/Write" description="MODE1 Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="OFF" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV1" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xb" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-      <BitField start="13" size="1" name="BKTRST" description="BKUP Registers Reset On Tamper Enable" />
-      <BitField start="14" size="1" name="GPTRST" description="GP Registers Reset On Tamper Enable" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Read Synchronization Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_CTRLB" access="Read/Write" description="MODE1 Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GP0EN" description="General Purpose 0 Enable" />
-      <BitField start="1" size="1" name="GP2EN" description="General Purpose 2 Enable" />
-      <BitField start="4" size="1" name="DEBMAJ" description="Debouncer Majority Enable" />
-      <BitField start="5" size="1" name="DEBASYNC" description="Debouncer Asynchronous Enable" />
-      <BitField start="6" size="1" name="RTCOUT" description="RTC Output Enable" />
-      <BitField start="7" size="1" name="DMAEN" description="DMA Enable" />
-      <BitField start="8" size="3" name="DEBF" description="Debounce Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_DEB = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_DEB = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_DEB = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_DEB = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_DEB = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_DEB = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_DEB = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_DEB = CLK_RTC/256" />
-      </BitField>
-      <BitField start="12" size="3" name="ACTF" description="Active Layer Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_OUT = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_OUT = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_OUT = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_OUT = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_OUT = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_OUT = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_OUT = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_OUT = CLK_RTC/256" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="RTC_EVCTRL" access="Read/Write" description="MODE1 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="9" size="1" name="CMPEO1" description="Compare 1 Event Output Enable" />
-      <BitField start="10" size="1" name="CMPEO2" description="Compare 2 Event Output Enable" />
-      <BitField start="11" size="1" name="CMPEO3" description="Compare 3 Event Output Enable" />
-      <BitField start="14" size="1" name="TAMPEREO" description="Tamper Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-      <BitField start="16" size="1" name="TAMPEVEI" description="Tamper Event Input Enable" />
-    </Register>
-    <Register start="+0x08" size="2" name="RTC_INTENCLR" access="Read/Write" description="MODE1 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="10" size="1" name="CMP2" description="Compare 2 Interrupt Enable" />
-      <BitField start="11" size="1" name="CMP3" description="Compare 3 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="2" name="RTC_INTENSET" access="Read/Write" description="MODE1 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="10" size="1" name="CMP2" description="Compare 2 Interrupt Enable" />
-      <BitField start="11" size="1" name="CMP3" description="Compare 3 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="RTC_INTFLAG" access="Read/Write" description="MODE1 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1" />
-      <BitField start="10" size="1" name="CMP2" description="Compare 2" />
-      <BitField start="11" size="1" name="CMP3" description="Compare 3" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper" />
-      <BitField start="15" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x0E" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_SYNCBUSY" access="ReadOnly" description="MODE1 Synchronization Busy Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Bit Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Bit Busy" />
-      <BitField start="2" size="1" name="FREQCORR" description="FREQCORR Register Busy" />
-      <BitField start="3" size="1" name="COUNT" description="COUNT Register Busy" />
-      <BitField start="4" size="1" name="PER" description="PER Register Busy" />
-      <BitField start="5" size="1" name="COMP0" description="COMP 0 Register Busy" />
-      <BitField start="6" size="1" name="COMP1" description="COMP 1 Register Busy" />
-      <BitField start="7" size="1" name="COMP2" description="COMP 2 Register Busy" />
-      <BitField start="8" size="1" name="COMP3" description="COMP 3 Register Busy" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Synchronization Enable Bit Busy" />
-      <BitField start="16" size="1" name="GP0" description="General Purpose 0 Register Busy" />
-      <BitField start="17" size="1" name="GP1" description="General Purpose 1 Register Busy" />
-      <BitField start="18" size="1" name="GP2" description="General Purpose 2 Register Busy" />
-      <BitField start="19" size="1" name="GP3" description="General Purpose 3 Register Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x18" size="2" name="RTC_COUNT" access="Read/Write" description="MODE1 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C" size="2" name="RTC_PER" access="Read/Write" description="MODE1 Counter Period" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PER" description="Counter Period" />
-    </Register>
-    <Register start="+0x20+0" size="2" name="RTC_COMP0" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+2" size="2" name="RTC_COMP1" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+4" size="2" name="RTC_COMP2" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+6" size="2" name="RTC_COMP3" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="RTC_GP0" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+4" size="4" name="RTC_GP1" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+8" size="4" name="RTC_GP2" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+12" size="4" name="RTC_GP3" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x60" size="4" name="RTC_TAMPCTRL" access="Read/Write" description="Tamper Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IN0ACT" description="Tamper Input 0 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN0 to OUT" />
-      </BitField>
-      <BitField start="2" size="2" name="IN1ACT" description="Tamper Input 1 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN1 to OUT" />
-      </BitField>
-      <BitField start="4" size="2" name="IN2ACT" description="Tamper Input 2 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN2 to OUT" />
-      </BitField>
-      <BitField start="6" size="2" name="IN3ACT" description="Tamper Input 3 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN3 to OUT" />
-      </BitField>
-      <BitField start="8" size="2" name="IN4ACT" description="Tamper Input 4 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN4 to OUT" />
-      </BitField>
-      <BitField start="16" size="1" name="TAMLVL0" description="Tamper Level Select 0" />
-      <BitField start="17" size="1" name="TAMLVL1" description="Tamper Level Select 1" />
-      <BitField start="18" size="1" name="TAMLVL2" description="Tamper Level Select 2" />
-      <BitField start="19" size="1" name="TAMLVL3" description="Tamper Level Select 3" />
-      <BitField start="20" size="1" name="TAMLVL4" description="Tamper Level Select 4" />
-      <BitField start="24" size="1" name="DEBNC0" description="Debouncer Enable 0" />
-      <BitField start="25" size="1" name="DEBNC1" description="Debouncer Enable 1" />
-      <BitField start="26" size="1" name="DEBNC2" description="Debouncer Enable 2" />
-      <BitField start="27" size="1" name="DEBNC3" description="Debouncer Enable 3" />
-      <BitField start="28" size="1" name="DEBNC4" description="Debouncer Enable 4" />
-    </Register>
-    <Register start="+0x64" size="4" name="RTC_TIMESTAMP" access="ReadOnly" description="MODE1 Timestamp" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Timestamp Value" />
-    </Register>
-    <Register start="+0x68" size="4" name="RTC_TAMPID" access="Read/Write" description="Tamper ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TAMPID0" description="Tamper Input 0 Detected" />
-      <BitField start="1" size="1" name="TAMPID1" description="Tamper Input 1 Detected" />
-      <BitField start="2" size="1" name="TAMPID2" description="Tamper Input 2 Detected" />
-      <BitField start="3" size="1" name="TAMPID3" description="Tamper Input 3 Detected" />
-      <BitField start="4" size="1" name="TAMPID4" description="Tamper Input 4 Detected" />
-      <BitField start="31" size="1" name="TAMPEVT" description="Tamper Event Detected" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="RTC_BKUP0" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="RTC_BKUP1" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="RTC_BKUP2" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="RTC_BKUP3" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="RTC_BKUP4" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="RTC_BKUP5" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="RTC_BKUP6" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="RTC_BKUP7" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE2)" start="0x40002400" description="Real-Time Counter">
-    <Register start="+0x00" size="2" name="RTC_CTRLA" access="Read/Write" description="MODE2 Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="6" size="1" name="CLKREP" description="Clock Representation" />
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="OFF" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV1" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xb" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-      <BitField start="13" size="1" name="BKTRST" description="BKUP Registers Reset On Tamper Enable" />
-      <BitField start="14" size="1" name="GPTRST" description="GP Registers Reset On Tamper Enable" />
-      <BitField start="15" size="1" name="CLOCKSYNC" description="Clock Read Synchronization Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_CTRLB" access="Read/Write" description="MODE2 Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GP0EN" description="General Purpose 0 Enable" />
-      <BitField start="1" size="1" name="GP2EN" description="General Purpose 2 Enable" />
-      <BitField start="4" size="1" name="DEBMAJ" description="Debouncer Majority Enable" />
-      <BitField start="5" size="1" name="DEBASYNC" description="Debouncer Asynchronous Enable" />
-      <BitField start="6" size="1" name="RTCOUT" description="RTC Output Enable" />
-      <BitField start="7" size="1" name="DMAEN" description="DMA Enable" />
-      <BitField start="8" size="3" name="DEBF" description="Debounce Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_DEB = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_DEB = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_DEB = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_DEB = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_DEB = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_DEB = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_DEB = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_DEB = CLK_RTC/256" />
-      </BitField>
-      <BitField start="12" size="3" name="ACTF" description="Active Layer Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_OUT = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_OUT = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_OUT = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_OUT = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_OUT = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_OUT = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_OUT = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_OUT = CLK_RTC/256" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="RTC_EVCTRL" access="Read/Write" description="MODE2 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="ALARMEO0" description="Alarm 0 Event Output Enable" />
-      <BitField start="9" size="1" name="ALARMEO1" description="Alarm 1 Event Output Enable" />
-      <BitField start="14" size="1" name="TAMPEREO" description="Tamper Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-      <BitField start="16" size="1" name="TAMPEVEI" description="Tamper Event Input Enable" />
-    </Register>
-    <Register start="+0x08" size="2" name="RTC_INTENCLR" access="Read/Write" description="MODE2 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="ALARM1" description="Alarm 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="2" name="RTC_INTENSET" access="Read/Write" description="MODE2 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Enable" />
-      <BitField start="8" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="ALARM1" description="Alarm 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="RTC_INTFLAG" access="Read/Write" description="MODE2 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7" />
-      <BitField start="8" size="1" name="ALARM0" description="Alarm 0" />
-      <BitField start="9" size="1" name="ALARM1" description="Alarm 1" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper" />
-      <BitField start="15" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x0E" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_SYNCBUSY" access="ReadOnly" description="MODE2 Synchronization Busy Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Bit Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Bit Busy" />
-      <BitField start="2" size="1" name="FREQCORR" description="FREQCORR Register Busy" />
-      <BitField start="3" size="1" name="CLOCK" description="CLOCK Register Busy" />
-      <BitField start="5" size="1" name="ALARM0" description="ALARM 0 Register Busy" />
-      <BitField start="6" size="1" name="ALARM1" description="ALARM 1 Register Busy" />
-      <BitField start="11" size="1" name="MASK0" description="MASK 0 Register Busy" />
-      <BitField start="12" size="1" name="MASK1" description="MASK 1 Register Busy" />
-      <BitField start="15" size="1" name="CLOCKSYNC" description="Clock Synchronization Enable Bit Busy" />
-      <BitField start="16" size="1" name="GP0" description="General Purpose 0 Register Busy" />
-      <BitField start="17" size="1" name="GP1" description="General Purpose 1 Register Busy" />
-      <BitField start="18" size="1" name="GP2" description="General Purpose 2 Register Busy" />
-      <BitField start="19" size="1" name="GP3" description="General Purpose 3 Register Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x18" size="4" name="RTC_CLOCK" access="Read/Write" description="MODE2 Clock Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="AM" start="0x0" description="AM when CLKREP in 12-hour" />
-        <Enum name="PM" start="0x10" description="PM when CLKREP in 12-hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="RTC_ALARM0" access="Read/Write" description="MODE2 Alarm n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="AM" start="0x0" description="Morning hour" />
-        <Enum name="PM" start="0x10" description="Afternoon hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x20+8" size="4" name="RTC_ALARM1" access="Read/Write" description="MODE2 Alarm n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="AM" start="0x0" description="Morning hour" />
-        <Enum name="PM" start="0x10" description="Afternoon hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x24+0" size="1" name="RTC_MASK0" access="Read/Write" description="MODE2 Alarm n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SEL" description="Alarm Mask Selection">
-        <Enum name="OFF" start="0x0" description="Alarm Disabled" />
-        <Enum name="SS" start="0x1" description="Match seconds only" />
-        <Enum name="MMSS" start="0x2" description="Match seconds and minutes only" />
-        <Enum name="HHMMSS" start="0x3" description="Match seconds, minutes, and hours only" />
-        <Enum name="DDHHMMSS" start="0x4" description="Match seconds, minutes, hours, and days only" />
-        <Enum name="MMDDHHMMSS" start="0x5" description="Match seconds, minutes, hours, days, and months only" />
-        <Enum name="YYMMDDHHMMSS" start="0x6" description="Match seconds, minutes, hours, days, months, and years" />
-      </BitField>
-    </Register>
-    <Register start="+0x24+8" size="1" name="RTC_MASK1" access="Read/Write" description="MODE2 Alarm n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SEL" description="Alarm Mask Selection">
-        <Enum name="OFF" start="0x0" description="Alarm Disabled" />
-        <Enum name="SS" start="0x1" description="Match seconds only" />
-        <Enum name="MMSS" start="0x2" description="Match seconds and minutes only" />
-        <Enum name="HHMMSS" start="0x3" description="Match seconds, minutes, and hours only" />
-        <Enum name="DDHHMMSS" start="0x4" description="Match seconds, minutes, hours, and days only" />
-        <Enum name="MMDDHHMMSS" start="0x5" description="Match seconds, minutes, hours, days, and months only" />
-        <Enum name="YYMMDDHHMMSS" start="0x6" description="Match seconds, minutes, hours, days, months, and years" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+0" size="4" name="RTC_GP0" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+4" size="4" name="RTC_GP1" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+8" size="4" name="RTC_GP2" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+12" size="4" name="RTC_GP3" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x60" size="4" name="RTC_TAMPCTRL" access="Read/Write" description="Tamper Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IN0ACT" description="Tamper Input 0 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN0 to OUT" />
-      </BitField>
-      <BitField start="2" size="2" name="IN1ACT" description="Tamper Input 1 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN1 to OUT" />
-      </BitField>
-      <BitField start="4" size="2" name="IN2ACT" description="Tamper Input 2 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN2 to OUT" />
-      </BitField>
-      <BitField start="6" size="2" name="IN3ACT" description="Tamper Input 3 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN3 to OUT" />
-      </BitField>
-      <BitField start="8" size="2" name="IN4ACT" description="Tamper Input 4 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN4 to OUT" />
-      </BitField>
-      <BitField start="16" size="1" name="TAMLVL0" description="Tamper Level Select 0" />
-      <BitField start="17" size="1" name="TAMLVL1" description="Tamper Level Select 1" />
-      <BitField start="18" size="1" name="TAMLVL2" description="Tamper Level Select 2" />
-      <BitField start="19" size="1" name="TAMLVL3" description="Tamper Level Select 3" />
-      <BitField start="20" size="1" name="TAMLVL4" description="Tamper Level Select 4" />
-      <BitField start="24" size="1" name="DEBNC0" description="Debouncer Enable 0" />
-      <BitField start="25" size="1" name="DEBNC1" description="Debouncer Enable 1" />
-      <BitField start="26" size="1" name="DEBNC2" description="Debouncer Enable 2" />
-      <BitField start="27" size="1" name="DEBNC3" description="Debouncer Enable 3" />
-      <BitField start="28" size="1" name="DEBNC4" description="Debouncer Enable 4" />
-    </Register>
-    <Register start="+0x64" size="4" name="RTC_TIMESTAMP" access="ReadOnly" description="MODE2 Timestamp" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second Timestamp Value" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute Timestamp Value" />
-      <BitField start="12" size="5" name="HOUR" description="Hour Timestamp Value">
-        <Enum name="AM" start="0x0" description="AM when CLKREP in 12-hour" />
-        <Enum name="PM" start="0x10" description="PM when CLKREP in 12-hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day Timestamp Value" />
-      <BitField start="22" size="4" name="MONTH" description="Month Timestamp Value" />
-      <BitField start="26" size="6" name="YEAR" description="Year Timestamp Value" />
-    </Register>
-    <Register start="+0x68" size="4" name="RTC_TAMPID" access="Read/Write" description="Tamper ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TAMPID0" description="Tamper Input 0 Detected" />
-      <BitField start="1" size="1" name="TAMPID1" description="Tamper Input 1 Detected" />
-      <BitField start="2" size="1" name="TAMPID2" description="Tamper Input 2 Detected" />
-      <BitField start="3" size="1" name="TAMPID3" description="Tamper Input 3 Detected" />
-      <BitField start="4" size="1" name="TAMPID4" description="Tamper Input 4 Detected" />
-      <BitField start="31" size="1" name="TAMPEVT" description="Tamper Event Detected" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="RTC_BKUP0" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="RTC_BKUP1" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="RTC_BKUP2" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="RTC_BKUP3" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="RTC_BKUP4" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="RTC_BKUP5" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="RTC_BKUP6" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="RTC_BKUP7" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDHC0" start="0x45000000" description="SD/MMC Host Controller">
-    <Register start="+0x000" size="4" name="SDHC_SSAR" access="Read/Write" description="SDMA System Address / Argument 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="SDMA System Address" />
-    </Register>
-    <Register start="+0x000" size="4" name="SDHC_SSAR_CMD23" access="Read/Write" description="SDMA System Address / Argument 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ARG2" description="Argument 2" />
-    </Register>
-    <Register start="+0x004" size="2" name="SDHC_BSR" access="Read/Write" description="Block Size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BLOCKSIZE" description="Transfer Block Size" />
-      <BitField start="12" size="3" name="BOUNDARY" description="SDMA Buffer Boundary">
-        <Enum name="4K" start="0x0" description="4k bytes" />
-        <Enum name="8K" start="0x1" description="8k bytes" />
-        <Enum name="16K" start="0x2" description="16k bytes" />
-        <Enum name="32K" start="0x3" description="32k bytes" />
-        <Enum name="64K" start="0x4" description="64k bytes" />
-        <Enum name="128K" start="0x5" description="128k bytes" />
-        <Enum name="256K" start="0x6" description="256k bytes" />
-        <Enum name="512K" start="0x7" description="512k bytes" />
-      </BitField>
-    </Register>
-    <Register start="+0x006" size="2" name="SDHC_BCR" access="Read/Write" description="Block Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BCNT" description="Blocks Count for Current Transfer" />
-    </Register>
-    <Register start="+0x008" size="4" name="SDHC_ARG1R" access="Read/Write" description="Argument 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ARG" description="Argument 1" />
-    </Register>
-    <Register start="+0x00C" size="2" name="SDHC_TMR" access="Read/Write" description="Transfer Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMAEN" description="DMA Enable">
-        <Enum name="DISABLE" start="0x0" description="No data transfer or Non DMA data transfer" />
-        <Enum name="ENABLE" start="0x1" description="DMA data transfer" />
-      </BitField>
-      <BitField start="1" size="1" name="BCEN" description="Block Count Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="2" name="ACMDEN" description="Auto Command Enable">
-        <Enum name="DISABLED" start="0x0" description="Auto Command Disabled" />
-        <Enum name="CMD12" start="0x1" description="Auto CMD12 Enable" />
-        <Enum name="CMD23" start="0x2" description="Auto CMD23 Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="DTDSEL" description="Data Transfer Direction Selection">
-        <Enum name="WRITE" start="0x0" description="Write (Host to Card)" />
-        <Enum name="READ" start="0x1" description="Read (Card to Host)" />
-      </BitField>
-      <BitField start="5" size="1" name="MSBSEL" description="Multi/Single Block Selection">
-        <Enum name="SINGLE" start="0x0" description="Single Block" />
-        <Enum name="MULTIPLE" start="0x1" description="Multiple Block" />
-      </BitField>
-    </Register>
-    <Register start="+0x00E" size="2" name="SDHC_CR" access="Read/Write" description="Command" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESPTYP" description="Response Type">
-        <Enum name="NONE" start="0x0" description="No response" />
-        <Enum name="136_BIT" start="0x1" description="136-bit response" />
-        <Enum name="48_BIT" start="0x2" description="48-bit response" />
-        <Enum name="48_BIT_BUSY" start="0x3" description="48-bit response check busy after response" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDCCEN" description="Command CRC Check Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="CMDICEN" description="Command Index Check Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="DPSEL" description="Data Present Select">
-        <Enum name="NO_DATA" start="0x0" description="No Data Present" />
-        <Enum name="DATA" start="0x1" description="Data Present" />
-      </BitField>
-      <BitField start="6" size="2" name="CMDTYP" description="Command Type">
-        <Enum name="NORMAL" start="0x0" description="Other commands" />
-        <Enum name="SUSPEND" start="0x1" description="CMD52 for writing Bus Suspend in CCCR" />
-        <Enum name="RESUME" start="0x2" description="CMD52 for writing Function Select in CCCR" />
-        <Enum name="ABORT" start="0x3" description="CMD12, CMD52 for writing I/O Abort in CCCR" />
-      </BitField>
-      <BitField start="8" size="6" name="CMDIDX" description="Command Index" />
-    </Register>
-    <Register start="+0x010+0" size="4" name="SDHC_RR0" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x010+4" size="4" name="SDHC_RR1" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x010+8" size="4" name="SDHC_RR2" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x010+12" size="4" name="SDHC_RR3" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x020" size="4" name="SDHC_BDPR" access="Read/Write" description="Buffer Data Port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BUFDATA" description="Buffer Data" />
-    </Register>
-    <Register start="+0x024" size="4" name="SDHC_PSR" access="ReadOnly" description="Present State" reset_value="0x00F80000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDINHC" description="Command Inhibit (CMD)">
-        <Enum name="CAN" start="0x0" description="Can issue command using only CMD line" />
-        <Enum name="CANNOT" start="0x1" description="Cannot issue command" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDINHD" description="Command Inhibit (DAT)">
-        <Enum name="CAN" start="0x0" description="Can issue command which uses the DAT line" />
-        <Enum name="CANNOT" start="0x1" description="Cannot issue command which uses the DAT line" />
-      </BitField>
-      <BitField start="2" size="1" name="DLACT" description="DAT Line Active">
-        <Enum name="INACTIVE" start="0x0" description="DAT Line Inactive" />
-        <Enum name="ACTIVE" start="0x1" description="DAT Line Active" />
-      </BitField>
-      <BitField start="3" size="1" name="RTREQ" description="Re-Tuning Request">
-        <Enum name="OK" start="0x0" description="Fixed or well-tuned sampling clock" />
-        <Enum name="REQUIRED" start="0x1" description="Sampling clock needs re-tuning" />
-      </BitField>
-      <BitField start="8" size="1" name="WTACT" description="Write Transfer Active">
-        <Enum name="NO" start="0x0" description="No valid data" />
-        <Enum name="YES" start="0x1" description="Transferring data" />
-      </BitField>
-      <BitField start="9" size="1" name="RTACT" description="Read Transfer Active">
-        <Enum name="NO" start="0x0" description="No valid data" />
-        <Enum name="YES" start="0x1" description="Transferring data" />
-      </BitField>
-      <BitField start="10" size="1" name="BUFWREN" description="Buffer Write Enable">
-        <Enum name="DISABLE" start="0x0" description="Write disable" />
-        <Enum name="ENABLE" start="0x1" description="Write enable" />
-      </BitField>
-      <BitField start="11" size="1" name="BUFRDEN" description="Buffer Read Enable">
-        <Enum name="DISABLE" start="0x0" description="Read disable" />
-        <Enum name="ENABLE" start="0x1" description="Read enable" />
-      </BitField>
-      <BitField start="16" size="1" name="CARDINS" description="Card Inserted">
-        <Enum name="NO" start="0x0" description="Reset or Debouncing or No Card" />
-        <Enum name="YES" start="0x1" description="Card inserted" />
-      </BitField>
-      <BitField start="17" size="1" name="CARDSS" description="Card State Stable">
-        <Enum name="NO" start="0x0" description="Reset or Debouncing" />
-        <Enum name="YES" start="0x1" description="No Card or Insered" />
-      </BitField>
-      <BitField start="18" size="1" name="CARDDPL" description="Card Detect Pin Level">
-        <Enum name="NO" start="0x0" description="No card present (SDCD#=1)" />
-        <Enum name="YES" start="0x1" description="Card present (SDCD#=0)" />
-      </BitField>
-      <BitField start="19" size="1" name="WRPPL" description="Write Protect Pin Level">
-        <Enum name="PROTECTED" start="0x0" description="Write protected (SDWP#=0)" />
-        <Enum name="ENABLED" start="0x1" description="Write enabled (SDWP#=1)" />
-      </BitField>
-      <BitField start="20" size="4" name="DATLL" description="DAT[3:0] Line Level" />
-      <BitField start="24" size="1" name="CMDLL" description="CMD Line Level" />
-    </Register>
-    <Register start="+0x028" size="1" name="SDHC_HC1R" access="Read/Write" description="Host Control 1" reset_value="0xE00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEDCTRL" description="LED Control">
-        <Enum name="OFF" start="0x0" description="LED off" />
-        <Enum name="ON" start="0x1" description="LED on" />
-      </BitField>
-      <BitField start="1" size="1" name="DW" description="Data Width">
-        <Enum name="1BIT" start="0x0" description="1-bit mode" />
-        <Enum name="4BIT" start="0x1" description="4-bit mode" />
-      </BitField>
-      <BitField start="2" size="1" name="HSEN" description="High Speed Enable">
-        <Enum name="NORMAL" start="0x0" description="Normal Speed mode" />
-        <Enum name="HIGH" start="0x1" description="High Speed mode" />
-      </BitField>
-      <BitField start="3" size="2" name="DMASEL" description="DMA Select">
-        <Enum name="SDMA" start="0x0" description="SDMA is selected" />
-        <Enum name="32BIT" start="0x2" description="32-bit Address ADMA2 is selected" />
-      </BitField>
-      <BitField start="6" size="1" name="CARDDTL" description="Card Detect Test Level">
-        <Enum name="NO" start="0x0" description="No Card" />
-        <Enum name="YES" start="0x1" description="Card Inserted" />
-      </BitField>
-      <BitField start="7" size="1" name="CARDDSEL" description="Card Detect Signal Selection">
-        <Enum name="NORMAL" start="0x0" description="SDCD# is selected (for normal use)" />
-        <Enum name="TEST" start="0x1" description="The Card Select Test Level is selected (for test purpose)" />
-      </BitField>
-    </Register>
-    <Register start="+0x028" size="1" name="SDHC_HC1R_EMMC" access="Read/Write" description="Host Control 1" reset_value="0xE00" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="DW" description="Data Width">
-        <Enum name="1BIT" start="0x0" description="1-bit mode" />
-        <Enum name="4BIT" start="0x1" description="4-bit mode" />
-      </BitField>
-      <BitField start="2" size="1" name="HSEN" description="High Speed Enable">
-        <Enum name="NORMAL" start="0x0" description="Normal Speed mode" />
-        <Enum name="HIGH" start="0x1" description="High Speed mode" />
-      </BitField>
-      <BitField start="3" size="2" name="DMASEL" description="DMA Select">
-        <Enum name="SDMA" start="0x0" description="SDMA is selected" />
-        <Enum name="32BIT" start="0x2" description="32-bit Address ADMA2 is selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x029" size="1" name="SDHC_PCR" access="Read/Write" description="Power Control" reset_value="0x0E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDBPWR" description="SD Bus Power">
-        <Enum name="OFF" start="0x0" description="Power off" />
-        <Enum name="ON" start="0x1" description="Power on" />
-      </BitField>
-      <BitField start="1" size="3" name="SDBVSEL" description="SD Bus Voltage Select">
-        <Enum name="1V8" start="0x5" description="1.8V (Typ.)" />
-        <Enum name="3V0" start="0x6" description="3.0V (Typ.)" />
-        <Enum name="3V3" start="0x7" description="3.3V (Typ.)" />
-      </BitField>
-    </Register>
-    <Register start="+0x02A" size="1" name="SDHC_BGCR" access="Read/Write" description="Block Gap Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STPBGR" description="Stop at Block Gap Request">
-        <Enum name="TRANSFER" start="0x0" description="Transfer" />
-        <Enum name="STOP" start="0x1" description="Stop" />
-      </BitField>
-      <BitField start="1" size="1" name="CONTR" description="Continue Request">
-        <Enum name="GO_ON" start="0x0" description="Not affected" />
-        <Enum name="RESTART" start="0x1" description="Restart" />
-      </BitField>
-      <BitField start="2" size="1" name="RWCTRL" description="Read Wait Control">
-        <Enum name="DISABLE" start="0x0" description="Disable Read Wait Control" />
-        <Enum name="ENABLE" start="0x1" description="Enable Read Wait Control" />
-      </BitField>
-      <BitField start="3" size="1" name="INTBG" description="Interrupt at Block Gap">
-        <Enum name="DISABLED" start="0x0" description="Disabled" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x02A" size="1" name="SDHC_BGCR_EMMC" access="Read/Write" description="Block Gap Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STPBGR" description="Stop at Block Gap Request">
-        <Enum name="TRANSFER" start="0x0" description="Transfer" />
-        <Enum name="STOP" start="0x1" description="Stop" />
-      </BitField>
-      <BitField start="1" size="1" name="CONTR" description="Continue Request">
-        <Enum name="GO_ON" start="0x0" description="Not affected" />
-        <Enum name="RESTART" start="0x1" description="Restart" />
-      </BitField>
-    </Register>
-    <Register start="+0x02B" size="1" name="SDHC_WCR" access="Read/Write" description="Wakeup Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WKENCINT" description="Wakeup Event Enable on Card Interrupt">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="WKENCINS" description="Wakeup Event Enable on Card Insertion">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="WKENCREM" description="Wakeup Event Enable on Card Removal">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x02C" size="2" name="SDHC_CCR" access="Read/Write" description="Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTCLKEN" description="Internal Clock Enable">
-        <Enum name="OFF" start="0x0" description="Stop" />
-        <Enum name="ON" start="0x1" description="Oscillate" />
-      </BitField>
-      <BitField start="1" size="1" name="INTCLKS" description="Internal Clock Stable">
-        <Enum name="NOT_READY" start="0x0" description="Not Ready" />
-        <Enum name="READY" start="0x1" description="Ready" />
-      </BitField>
-      <BitField start="2" size="1" name="SDCLKEN" description="SD Clock Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKGSEL" description="Clock Generator Select">
-        <Enum name="DIV" start="0x0" description="Divided Clock Mode" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Mode" />
-      </BitField>
-      <BitField start="6" size="2" name="USDCLKFSEL" description="Upper Bits of SDCLK Frequency Select" />
-      <BitField start="8" size="8" name="SDCLKFSEL" description="SDCLK Frequency Select" />
-    </Register>
-    <Register start="+0x02E" size="1" name="SDHC_TCR" access="Read/Write" description="Timeout Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DTCVAL" description="Data Timeout Counter Value" />
-    </Register>
-    <Register start="+0x02F" size="1" name="SDHC_SRR" access="Read/Write" description="Software Reset" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRSTALL" description="Software Reset For All">
-        <Enum name="WORK" start="0x0" description="Work" />
-        <Enum name="RESET" start="0x1" description="Reset" />
-      </BitField>
-      <BitField start="1" size="1" name="SWRSTCMD" description="Software Reset For CMD Line">
-        <Enum name="WORK" start="0x0" description="Work" />
-        <Enum name="RESET" start="0x1" description="Reset" />
-      </BitField>
-      <BitField start="2" size="1" name="SWRSTDAT" description="Software Reset For DAT Line">
-        <Enum name="WORK" start="0x0" description="Work" />
-        <Enum name="RESET" start="0x1" description="Reset" />
-      </BitField>
-    </Register>
-    <Register start="+0x030" size="2" name="SDHC_NISTR" access="Read/Write" description="Normal Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete">
-        <Enum name="NO" start="0x0" description="No command complete" />
-        <Enum name="YES" start="0x1" description="Command complete" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete">
-        <Enum name="NO" start="0x0" description="Not complete" />
-        <Enum name="YES" start="0x1" description="Command execution is completed" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event">
-        <Enum name="NO" start="0x0" description="No Block Gap Event" />
-        <Enum name="STOP" start="0x1" description="Transaction stopped at block gap" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt">
-        <Enum name="NO" start="0x0" description="No DMA Interrupt" />
-        <Enum name="YES" start="0x1" description="DMA Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready">
-        <Enum name="NO" start="0x0" description="Not ready to write buffer" />
-        <Enum name="YES" start="0x1" description="Ready to write buffer" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready">
-        <Enum name="NO" start="0x0" description="Not ready to read buffer" />
-        <Enum name="YES" start="0x1" description="Ready to read buffer" />
-      </BitField>
-      <BitField start="6" size="1" name="CINS" description="Card Insertion">
-        <Enum name="NO" start="0x0" description="Card state stable or Debouncing" />
-        <Enum name="YES" start="0x1" description="Card inserted" />
-      </BitField>
-      <BitField start="7" size="1" name="CREM" description="Card Removal">
-        <Enum name="NO" start="0x0" description="Card state stable or Debouncing" />
-        <Enum name="YES" start="0x1" description="Card Removed" />
-      </BitField>
-      <BitField start="8" size="1" name="CINT" description="Card Interrupt">
-        <Enum name="NO" start="0x0" description="No Card Interrupt" />
-        <Enum name="YES" start="0x1" description="Generate Card Interrupt" />
-      </BitField>
-      <BitField start="15" size="1" name="ERRINT" description="Error Interrupt">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x030" size="2" name="SDHC_NISTR_EMMC" access="Read/Write" description="Normal Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete">
-        <Enum name="NO" start="0x0" description="No command complete" />
-        <Enum name="YES" start="0x1" description="Command complete" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete">
-        <Enum name="NO" start="0x0" description="Not complete" />
-        <Enum name="YES" start="0x1" description="Command execution is completed" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event">
-        <Enum name="NO" start="0x0" description="No Block Gap Event" />
-        <Enum name="STOP" start="0x1" description="Transaction stopped at block gap" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt">
-        <Enum name="NO" start="0x0" description="No DMA Interrupt" />
-        <Enum name="YES" start="0x1" description="DMA Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready">
-        <Enum name="NO" start="0x0" description="Not ready to write buffer" />
-        <Enum name="YES" start="0x1" description="Ready to write buffer" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready">
-        <Enum name="NO" start="0x0" description="Not ready to read buffer" />
-        <Enum name="YES" start="0x1" description="Ready to read buffer" />
-      </BitField>
-      <BitField start="14" size="1" name="BOOTAR" description="Boot Acknowledge Received" />
-      <BitField start="15" size="1" name="ERRINT" description="Error Interrupt">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x032" size="2" name="SDHC_EISTR" access="Read/Write" description="Error Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="CRC Error Generated" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="End Bit Error Generated" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Power Fail" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x032" size="2" name="SDHC_EISTR_EMMC" access="Read/Write" description="Error Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="CRC Error Generated" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="End Bit Error Generated" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Power Fail" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Boot Acknowledge Error">
-        <Enum name="0" start="0x0" description="FIFO contains at least one byte" />
-        <Enum name="1" start="0x1" description="FIFO is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x034" size="2" name="SDHC_NISTER" access="Read/Write" description="Normal Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CINS" description="Card Insertion Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CREM" description="Card Removal Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CINT" description="Card Interrupt Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x034" size="2" name="SDHC_NISTER_EMMC" access="Read/Write" description="Normal Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BOOTAR" description="Boot Acknowledge Received Status Enable" />
-    </Register>
-    <Register start="+0x036" size="2" name="SDHC_EISTER" access="Read/Write" description="Error Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x036" size="2" name="SDHC_EISTER_EMMC" access="Read/Write" description="Error Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Boot Acknowledge Error Status Enable" />
-    </Register>
-    <Register start="+0x038" size="2" name="SDHC_NISIER" access="Read/Write" description="Normal Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CINS" description="Card Insertion Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CREM" description="Card Removal Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CINT" description="Card Interrupt Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x038" size="2" name="SDHC_NISIER_EMMC" access="Read/Write" description="Normal Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BOOTAR" description="Boot Acknowledge Received Signal Enable" />
-    </Register>
-    <Register start="+0x03A" size="2" name="SDHC_EISIER" access="Read/Write" description="Error Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x03A" size="2" name="SDHC_EISIER_EMMC" access="Read/Write" description="Error Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Boot Acknowledge Error Signal Enable" />
-    </Register>
-    <Register start="+0x03C" size="2" name="SDHC_ACESR" access="ReadOnly" description="Auto CMD Error Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACMD12NE" description="Auto CMD12 Not Executed">
-        <Enum name="EXEC" start="0x0" description="Executed" />
-        <Enum name="NOT_EXEC" start="0x1" description="Not executed" />
-      </BitField>
-      <BitField start="1" size="1" name="ACMDTEO" description="Auto CMD Timeout Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="2" size="1" name="ACMDCRC" description="Auto CMD CRC Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="CRC Error Generated" />
-      </BitField>
-      <BitField start="3" size="1" name="ACMDEND" description="Auto CMD End Bit Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="End Bit Error Generated" />
-      </BitField>
-      <BitField start="4" size="1" name="ACMDIDX" description="Auto CMD Index Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="7" size="1" name="CMDNI" description="Command not Issued By Auto CMD12 Error">
-        <Enum name="OK" start="0x0" description="No error" />
-        <Enum name="NOT_ISSUED" start="0x1" description="Not Issued" />
-      </BitField>
-    </Register>
-    <Register start="+0x03E" size="2" name="SDHC_HC2R" access="Read/Write" description="Host Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="UHSMS" description="UHS Mode Select">
-        <Enum name="SDR12" start="0x0" description="SDR12" />
-        <Enum name="SDR25" start="0x1" description="SDR25" />
-        <Enum name="SDR50" start="0x2" description="SDR50" />
-        <Enum name="SDR104" start="0x3" description="SDR104" />
-        <Enum name="DDR50" start="0x4" description="DDR50" />
-      </BitField>
-      <BitField start="3" size="1" name="VS18EN" description="1.8V Signaling Enable">
-        <Enum name="S33V" start="0x0" description="3.3V Signaling" />
-        <Enum name="S18V" start="0x1" description="1.8V Signaling" />
-      </BitField>
-      <BitField start="4" size="2" name="DRVSEL" description="Driver Strength Select">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected (Default)" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-      <BitField start="6" size="1" name="EXTUN" description="Execute Tuning">
-        <Enum name="NO" start="0x0" description="Not Tuned or Tuning Completed" />
-        <Enum name="REQUESTED" start="0x1" description="Execute Tuning" />
-      </BitField>
-      <BitField start="7" size="1" name="SLCKSEL" description="Sampling Clock Select">
-        <Enum name="FIXED" start="0x0" description="Fixed clock is used to sample data" />
-        <Enum name="TUNED" start="0x1" description="Tuned clock is used to sample data" />
-      </BitField>
-      <BitField start="14" size="1" name="ASINTEN" description="Asynchronous Interrupt Enable">
-        <Enum name="DISABLED" start="0x0" description="Disabled" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="PVALEN" description="Preset Value Enable">
-        <Enum name="HOST" start="0x0" description="SDCLK and Driver Strength are controlled by Host Controller" />
-        <Enum name="AUTO" start="0x1" description="Automatic Selection by Preset Value is Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x03E" size="2" name="SDHC_HC2R_EMMC" access="Read/Write" description="Host Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="HS200EN" description="HS200 Mode Enable">
-        <Enum name="SDR12" start="0x0" description="SDR12" />
-        <Enum name="SDR25" start="0x1" description="SDR25" />
-        <Enum name="SDR50" start="0x2" description="SDR50" />
-        <Enum name="SDR104" start="0x3" description="SDR104" />
-        <Enum name="DDR50" start="0x4" description="DDR50" />
-      </BitField>
-      <BitField start="4" size="2" name="DRVSEL" description="Driver Strength Select">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected (Default)" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-      <BitField start="6" size="1" name="EXTUN" description="Execute Tuning">
-        <Enum name="NO" start="0x0" description="Not Tuned or Tuning Completed" />
-        <Enum name="REQUESTED" start="0x1" description="Execute Tuning" />
-      </BitField>
-      <BitField start="7" size="1" name="SLCKSEL" description="Sampling Clock Select">
-        <Enum name="FIXED" start="0x0" description="Fixed clock is used to sample data" />
-        <Enum name="TUNED" start="0x1" description="Tuned clock is used to sample data" />
-      </BitField>
-      <BitField start="15" size="1" name="PVALEN" description="Preset Value Enable">
-        <Enum name="HOST" start="0x0" description="SDCLK and Driver Strength are controlled by Host Controller" />
-        <Enum name="AUTO" start="0x1" description="Automatic Selection by Preset Value is Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x040" size="4" name="SDHC_CA0R" access="ReadOnly" description="Capabilities 0" reset_value="0x27E80080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TEOCLKF" description="Timeout Clock Frequency">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-      </BitField>
-      <BitField start="7" size="1" name="TEOCLKU" description="Timeout Clock Unit">
-        <Enum name="KHZ" start="0x0" description="kHz" />
-        <Enum name="MHZ" start="0x1" description="MHz" />
-      </BitField>
-      <BitField start="8" size="8" name="BASECLKF" description="Base Clock Frequency">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-      </BitField>
-      <BitField start="16" size="2" name="MAXBLKL" description="Max Block Length">
-        <Enum name="512" start="0x0" description="512 bytes" />
-        <Enum name="1024" start="0x1" description="1024 bytes" />
-        <Enum name="2048" start="0x2" description="2048 bytes" />
-      </BitField>
-      <BitField start="18" size="1" name="ED8SUP" description="8-bit Support for Embedded Device">
-        <Enum name="NO" start="0x0" description="8-bit Bus Width not Supported" />
-        <Enum name="YES" start="0x1" description="8-bit Bus Width Supported" />
-      </BitField>
-      <BitField start="19" size="1" name="ADMA2SUP" description="ADMA2 Support">
-        <Enum name="NO" start="0x0" description="ADMA2 not Supported" />
-        <Enum name="YES" start="0x1" description="ADMA2 Supported" />
-      </BitField>
-      <BitField start="21" size="1" name="HSSUP" description="High Speed Support">
-        <Enum name="NO" start="0x0" description="High Speed not Supported" />
-        <Enum name="YES" start="0x1" description="High Speed Supported" />
-      </BitField>
-      <BitField start="22" size="1" name="SDMASUP" description="SDMA Support">
-        <Enum name="NO" start="0x0" description="SDMA not Supported" />
-        <Enum name="YES" start="0x1" description="SDMA Supported" />
-      </BitField>
-      <BitField start="23" size="1" name="SRSUP" description="Suspend/Resume Support">
-        <Enum name="NO" start="0x0" description="Suspend/Resume not Supported" />
-        <Enum name="YES" start="0x1" description="Suspend/Resume Supported" />
-      </BitField>
-      <BitField start="24" size="1" name="V33VSUP" description="Voltage Support 3.3V">
-        <Enum name="NO" start="0x0" description="3.3V Not Supported" />
-        <Enum name="YES" start="0x1" description="3.3V Supported" />
-      </BitField>
-      <BitField start="25" size="1" name="V30VSUP" description="Voltage Support 3.0V">
-        <Enum name="NO" start="0x0" description="3.0V Not Supported" />
-        <Enum name="YES" start="0x1" description="3.0V Supported" />
-      </BitField>
-      <BitField start="26" size="1" name="V18VSUP" description="Voltage Support 1.8V">
-        <Enum name="NO" start="0x0" description="1.8V Not Supported" />
-        <Enum name="YES" start="0x1" description="1.8V Supported" />
-      </BitField>
-      <BitField start="28" size="1" name="SB64SUP" description="64-Bit System Bus Support">
-        <Enum name="NO" start="0x0" description="32-bit Address Descriptors and System Bus" />
-        <Enum name="YES" start="0x1" description="64-bit Address Descriptors and System Bus" />
-      </BitField>
-      <BitField start="29" size="1" name="ASINTSUP" description="Asynchronous Interrupt Support">
-        <Enum name="NO" start="0x0" description="Asynchronous Interrupt not Supported" />
-        <Enum name="YES" start="0x1" description="Asynchronous Interrupt supported" />
-      </BitField>
-      <BitField start="30" size="2" name="SLTYPE" description="Slot Type">
-        <Enum name="REMOVABLE" start="0x0" description="Removable Card Slot" />
-        <Enum name="EMBEDDED" start="0x1" description="Embedded Slot for One Device" />
-      </BitField>
-    </Register>
-    <Register start="+0x044" size="4" name="SDHC_CA1R" access="ReadOnly" description="Capabilities 1" reset_value="0x00000070" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDR50SUP" description="SDR50 Support">
-        <Enum name="NO" start="0x0" description="SDR50 is Not Supported" />
-        <Enum name="YES" start="0x1" description="SDR50 is Supported" />
-      </BitField>
-      <BitField start="1" size="1" name="SDR104SUP" description="SDR104 Support">
-        <Enum name="NO" start="0x0" description="SDR104 is Not Supported" />
-        <Enum name="YES" start="0x1" description="SDR104 is Supported" />
-      </BitField>
-      <BitField start="2" size="1" name="DDR50SUP" description="DDR50 Support">
-        <Enum name="NO" start="0x0" description="DDR50 is Not Supported" />
-        <Enum name="YES" start="0x1" description="DDR50 is Supported" />
-      </BitField>
-      <BitField start="4" size="1" name="DRVASUP" description="Driver Type A Support">
-        <Enum name="NO" start="0x0" description="Driver Type A is Not Supported" />
-        <Enum name="YES" start="0x1" description="Driver Type A is Supported" />
-      </BitField>
-      <BitField start="5" size="1" name="DRVCSUP" description="Driver Type C Support">
-        <Enum name="NO" start="0x0" description="Driver Type C is Not Supported" />
-        <Enum name="YES" start="0x1" description="Driver Type C is Supported" />
-      </BitField>
-      <BitField start="6" size="1" name="DRVDSUP" description="Driver Type D Support">
-        <Enum name="NO" start="0x0" description="Driver Type D is Not Supported" />
-        <Enum name="YES" start="0x1" description="Driver Type D is Supported" />
-      </BitField>
-      <BitField start="8" size="4" name="TCNTRT" description="Timer Count for Re-Tuning">
-        <Enum name="DISABLED" start="0x0" description="Re-Tuning Timer disabled" />
-        <Enum name="1S" start="0x1" description="1 second" />
-        <Enum name="2S" start="0x2" description="2 seconds" />
-        <Enum name="4S" start="0x3" description="4 seconds" />
-        <Enum name="8S" start="0x4" description="8 seconds" />
-        <Enum name="16S" start="0x5" description="16 seconds" />
-        <Enum name="32S" start="0x6" description="32 seconds" />
-        <Enum name="64S" start="0x7" description="64 seconds" />
-        <Enum name="128S" start="0x8" description="128 seconds" />
-        <Enum name="256S" start="0x9" description="256 seconds" />
-        <Enum name="512S" start="0xa" description="512 seconds" />
-        <Enum name="1024S" start="0xb" description="1024 seconds" />
-        <Enum name="OTHER" start="0xf" description="Get information from other source" />
-      </BitField>
-      <BitField start="13" size="1" name="TSDR50" description="Use Tuning for SDR50">
-        <Enum name="NO" start="0x0" description="SDR50 does not require tuning" />
-        <Enum name="YES" start="0x1" description="SDR50 requires tuning" />
-      </BitField>
-      <BitField start="16" size="8" name="CLKMULT" description="Clock Multiplier">
-        <Enum name="NO" start="0x0" description="Clock Multiplier is Not Supported" />
-      </BitField>
-    </Register>
-    <Register start="+0x048" size="4" name="SDHC_MCCAR" access="ReadOnly" description="Maximum Current Capabilities" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCUR33V" description="Maximum Current for 3.3V">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-        <Enum name="4MA" start="0x1" description="4mA" />
-        <Enum name="8MA" start="0x2" description="8mA" />
-        <Enum name="12MA" start="0x3" description="12mA" />
-      </BitField>
-      <BitField start="8" size="8" name="MAXCUR30V" description="Maximum Current for 3.0V">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-        <Enum name="4MA" start="0x1" description="4mA" />
-        <Enum name="8MA" start="0x2" description="8mA" />
-        <Enum name="12MA" start="0x3" description="12mA" />
-      </BitField>
-      <BitField start="16" size="8" name="MAXCUR18V" description="Maximum Current for 1.8V">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-        <Enum name="4MA" start="0x1" description="4mA" />
-        <Enum name="8MA" start="0x2" description="8mA" />
-        <Enum name="12MA" start="0x3" description="12mA" />
-      </BitField>
-    </Register>
-    <Register start="+0x050" size="2" name="SDHC_FERACES" access="WriteOnly" description="Force Event for Auto CMD Error Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACMD12NE" description="Force Event for Auto CMD12 Not Executed">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="1" size="1" name="ACMDTEO" description="Force Event for Auto CMD Timeout Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="2" size="1" name="ACMDCRC" description="Force Event for Auto CMD CRC Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="3" size="1" name="ACMDEND" description="Force Event for Auto CMD End Bit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="ACMDIDX" description="Force Event for Auto CMD Index Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="7" size="1" name="CMDNI" description="Force Event for Command Not Issued By Auto CMD12 Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-    </Register>
-    <Register start="+0x052" size="2" name="SDHC_FEREIS" access="WriteOnly" description="Force Event for Error Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Force Event for Command Timeout Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Force Event for Command CRC Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Force Event for Command End Bit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Force Event for Command Index Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Force Event for Data Timeout Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Force Event for Data CRC Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Force Event for Data End Bit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Force Event for Current Limit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Force Event for Auto CMD Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="Force Event for ADMA Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Force Event for Boot Acknowledge Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-    </Register>
-    <Register start="+0x054" size="1" name="SDHC_AESR" access="ReadOnly" description="ADMA Error Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ERRST" description="ADMA Error State">
-        <Enum name="STOP" start="0x0" description="ST_STOP (Stop DMA)" />
-        <Enum name="FDS" start="0x1" description="ST_FDS (Fetch Descriptor)" />
-        <Enum name="TFR" start="0x3" description="ST_TFR (Transfer Data)" />
-      </BitField>
-      <BitField start="2" size="1" name="LMIS" description="ADMA Length Mismatch Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x058+0" size="4" name="SDHC_ASAR0" access="Read/Write" description="ADMA System Address n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADMASA" description="ADMA System Address" />
-    </Register>
-    <Register start="+0x060+0" size="2" name="SDHC_PVR0" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+2" size="2" name="SDHC_PVR1" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+4" size="2" name="SDHC_PVR2" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+6" size="2" name="SDHC_PVR3" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+8" size="2" name="SDHC_PVR4" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+10" size="2" name="SDHC_PVR5" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+12" size="2" name="SDHC_PVR6" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+14" size="2" name="SDHC_PVR7" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x0FC" size="2" name="SDHC_SISR" access="ReadOnly" description="Slot Interrupt Status" reset_value="0x20000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSSL" description="Interrupt Signal for Each Slot" />
-    </Register>
-    <Register start="+0x0FE" size="2" name="SDHC_HCVR" access="ReadOnly" description="Host Controller Version" reset_value="0x1802" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SVER" description="Spec Version" />
-      <BitField start="8" size="8" name="VVER" description="Vendor Version" />
-    </Register>
-    <Register start="+0x204" size="1" name="SDHC_MC1R" access="Read/Write" description="MMC Control 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMDTYP" description="e.MMC Command Type">
-        <Enum name="NORMAL" start="0x0" description="Not a MMC specific command" />
-        <Enum name="WAITIRQ" start="0x1" description="Wait IRQ Command" />
-        <Enum name="STREAM" start="0x2" description="Stream Command" />
-        <Enum name="BOOT" start="0x3" description="Boot Command" />
-      </BitField>
-      <BitField start="3" size="1" name="DDR" description="e.MMC HSDDR Mode" />
-      <BitField start="4" size="1" name="OPD" description="e.MMC Open Drain Mode" />
-      <BitField start="5" size="1" name="BOOTA" description="e.MMC Boot Acknowledge Enable" />
-      <BitField start="6" size="1" name="RSTN" description="e.MMC Reset Signal" />
-      <BitField start="7" size="1" name="FCD" description="e.MMC Force Card Detect" />
-    </Register>
-    <Register start="+0x205" size="1" name="SDHC_MC2R" access="WriteOnly" description="MMC Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SRESP" description="e.MMC Abort Wait IRQ" />
-      <BitField start="1" size="1" name="ABOOT" description="e.MMC Abort Boot" />
-    </Register>
-    <Register start="+0x208" size="4" name="SDHC_ACR" access="Read/Write" description="AHB Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BMAX" description="AHB Maximum Burst">
-        <Enum name="INCR16" start="0x0" />
-        <Enum name="INCR8" start="0x1" />
-        <Enum name="INCR4" start="0x2" />
-        <Enum name="SINGLE" start="0x3" />
-      </BitField>
-    </Register>
-    <Register start="+0x20C" size="4" name="SDHC_CC2R" access="Read/Write" description="Clock Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSDCLKD" description="Force SDCK Disabled">
-        <Enum name="NOEFFECT" start="0x0" description="No effect" />
-        <Enum name="DISABLE" start="0x1" description="SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x230" size="4" name="SDHC_CACR" access="Read/Write" description="Capabilities Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAPWREN" description="Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)" />
-      <BitField start="8" size="8" name="KEY" description="Key (0x46)" />
-    </Register>
-    <Register start="+0x234" size="1" name="SDHC_DBGR" access="Read/Write" description="Debug" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NIDBG" description="Non-intrusive debug enable">
-        <Enum name="IDBG" start="0x0" description="Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer)" />
-        <Enum name="NIDBG" start="0x1" description="Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CM)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CS)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (SPI)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (USART)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CM)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CS)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (SPI)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (USART)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CM)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CS)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (SPI)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (USART)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CM)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CS)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (SPI)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (USART)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CM)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CS)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (SPI)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (USART)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CM)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CS)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (SPI)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (USART)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SUPC" start="0x40001800" description="Supply Controller">
-    <Register start="+0x00" size="4" name="SUPC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x04" size="4" name="SUPC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x08" size="4" name="SUPC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SUPC_STATUS" access="ReadOnly" description="Power and Clocks Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x10" size="4" name="SUPC_BOD33" access="Read/Write" description="BOD33 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="ACTION" description="Action when Threshold Crossed">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RESET" start="0x1" description="The BOD33 generates a reset" />
-        <Enum name="INT" start="0x2" description="The BOD33 generates an interrupt" />
-        <Enum name="BKUP" start="0x3" description="The BOD33 puts the device in backup sleep mode" />
-      </BitField>
-      <BitField start="4" size="1" name="STDBYCFG" description="Configuration in Standby mode" />
-      <BitField start="5" size="1" name="RUNSTDBY" description="Run in Standby mode" />
-      <BitField start="6" size="1" name="RUNHIB" description="Run in Hibernate mode" />
-      <BitField start="7" size="1" name="RUNBKUP" description="Run in Backup mode" />
-      <BitField start="8" size="4" name="HYST" description="Hysteresis value" />
-      <BitField start="12" size="3" name="PSEL" description="Prescaler Select">
-        <Enum name="NODIV" start="0x0" description="Not divided" />
-        <Enum name="DIV4" start="0x1" description="Divide clock by 4" />
-        <Enum name="DIV8" start="0x2" description="Divide clock by 8" />
-        <Enum name="DIV16" start="0x3" description="Divide clock by 16" />
-        <Enum name="DIV32" start="0x4" description="Divide clock by 32" />
-        <Enum name="DIV64" start="0x5" description="Divide clock by 64" />
-        <Enum name="DIV128" start="0x6" description="Divide clock by 128" />
-        <Enum name="DIV256" start="0x7" description="Divide clock by 256" />
-      </BitField>
-      <BitField start="16" size="8" name="LEVEL" description="Threshold Level for VDD" />
-      <BitField start="24" size="8" name="VBATLEVEL" description="Threshold Level in battery backup sleep mode for VBAT" />
-    </Register>
-    <Register start="+0x14" size="4" name="SUPC_BOD12" access="Read/Write" description="BOD12 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="HYST" description="Hysteresis Enable" />
-      <BitField start="3" size="2" name="ACTION" description="Action when Threshold Crossed">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RESET" start="0x1" description="The BOD12 generates a reset" />
-        <Enum name="INT" start="0x2" description="The BOD12 generates an interrupt" />
-      </BitField>
-      <BitField start="5" size="1" name="STDBYCFG" description="Configuration in Standby mode" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="ACTCFG" description="Configuration in Active mode" />
-      <BitField start="12" size="4" name="PSEL" description="Prescaler Select">
-        <Enum name="DIV2" start="0x0" description="Divide clock by 2" />
-        <Enum name="DIV4" start="0x1" description="Divide clock by 4" />
-        <Enum name="DIV8" start="0x2" description="Divide clock by 8" />
-        <Enum name="DIV16" start="0x3" description="Divide clock by 16" />
-        <Enum name="DIV32" start="0x4" description="Divide clock by 32" />
-        <Enum name="DIV64" start="0x5" description="Divide clock by 64" />
-        <Enum name="DIV128" start="0x6" description="Divide clock by 128" />
-        <Enum name="DIV256" start="0x7" description="Divide clock by 256" />
-        <Enum name="DIV512" start="0x8" description="Divide clock by 512" />
-        <Enum name="DIV1024" start="0x9" description="Divide clock by 1024" />
-        <Enum name="DIV2048" start="0xa" description="Divide clock by 2048" />
-        <Enum name="DIV4096" start="0xb" description="Divide clock by 4096" />
-        <Enum name="DIV8192" start="0xc" description="Divide clock by 8192" />
-        <Enum name="DIV16384" start="0xd" description="Divide clock by 16384" />
-        <Enum name="DIV32768" start="0xe" description="Divide clock by 32768" />
-        <Enum name="DIV65536" start="0xf" description="Divide clock by 65536" />
-      </BitField>
-      <BitField start="16" size="6" name="LEVEL" description="Threshold Level" />
-    </Register>
-    <Register start="+0x18" size="4" name="SUPC_VREG" access="Read/Write" description="VREG Control" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="SEL" description="Voltage Regulator Selection">
-        <Enum name="LDO" start="0x0" description="LDO selection" />
-        <Enum name="BUCK" start="0x1" description="Buck selection" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNBKUP" description="Run in Backup mode" />
-      <BitField start="16" size="1" name="VSEN" description="Voltage Scaling Enable" />
-      <BitField start="24" size="3" name="VSPER" description="Voltage Scaling Period" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SUPC_VREF" access="Read/Write" description="VREF Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="TSEN" description="Temperature Sensor Output Enable" />
-      <BitField start="2" size="1" name="VREFOE" description="Voltage Reference Output Enable" />
-      <BitField start="3" size="1" name="TSSEL" description="Temperature Sensor Selection" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Contrl" />
-      <BitField start="16" size="4" name="SEL" description="Voltage Reference Selection">
-        <Enum name="1V0" start="0x0" description="1.0V voltage reference typical value" />
-        <Enum name="1V1" start="0x1" description="1.1V voltage reference typical value" />
-        <Enum name="1V2" start="0x2" description="1.2V voltage reference typical value" />
-        <Enum name="1V25" start="0x3" description="1.25V voltage reference typical value" />
-        <Enum name="2V0" start="0x4" description="2.0V voltage reference typical value" />
-        <Enum name="2V2" start="0x5" description="2.2V voltage reference typical value" />
-        <Enum name="2V4" start="0x6" description="2.4V voltage reference typical value" />
-        <Enum name="2V5" start="0x7" description="2.5V voltage reference typical value" />
-      </BitField>
-    </Register>
-    <Register start="+0x20" size="4" name="SUPC_BBPS" access="Read/Write" description="Battery Backup Power Switch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONF" description="Battery Backup Configuration">
-        <Enum name="BOD33" start="0x0" description="The power switch is handled by the BOD33" />
-        <Enum name="FORCED" start="0x1" description="In Backup Domain, the backup domain is always supplied by battery backup power" />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEEN" description="Wake Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SUPC_BKOUT" access="Read/Write" description="Backup Output Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="EN" description="Enable Output" />
-      <BitField start="8" size="2" name="CLR" description="Clear Output" />
-      <BitField start="16" size="2" name="SET" description="Set Output" />
-      <BitField start="24" size="2" name="RTCTGL" description="RTC Toggle Output" />
-    </Register>
-    <Register start="+0x28" size="4" name="SUPC_BKIN" access="ReadOnly" description="Backup Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BKIN" description="Backup Input Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TAL" start="0x4101E000" description="Trigger Allocator">
-    <Register start="+0x000" size="1" name="TAL_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x001" size="1" name="TAL_EXTCTRL" access="Read/Write" description="External Break Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable BRK Pin" />
-      <BitField start="1" size="1" name="INV" description="Invert BRK Pin" />
-    </Register>
-    <Register start="+0x004" size="2" name="TAL_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRKEI" description="Break Input Event Enable" />
-      <BitField start="1" size="1" name="BRKEO" description="Break Output Event Enable" />
-      <BitField start="2" size="1" name="IRQMONEO0" description="Interrupt Request Monitor 0 Output Event Enable" />
-    </Register>
-    <Register start="+0x008" size="1" name="TAL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRK" description="Break Interrupt Enable" />
-      <BitField start="1" size="1" name="IPS0" description="Inter-Processor Signal Interrupt Enable for CPU 0" />
-      <BitField start="2" size="1" name="IPS1" description="Inter-Processor Signal Interrupt Enable for CPU 1" />
-    </Register>
-    <Register start="+0x009" size="1" name="TAL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRK" description="Break Interrupt Enable" />
-      <BitField start="1" size="1" name="IPS0" description="Inter-Processor Signal Interrupt Enable for CPU 0" />
-      <BitField start="2" size="1" name="IPS1" description="Inter-Processor Signal Interrupt Enable for CPU 1" />
-    </Register>
-    <Register start="+0x00A" size="1" name="TAL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRK" description="Break" />
-      <BitField start="1" size="1" name="IPS0" description="Inter-Processor Signal for CPU 0" />
-      <BitField start="2" size="1" name="IPS1" description="Inter-Processor Signal for CPU 1" />
-    </Register>
-    <Register start="+0x00B" size="1" name="TAL_GLOBMASK" access="Read/Write" description="Global Break Requests Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x00C" size="1" name="TAL_HALT" access="WriteOnly" description="Debug Halt Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x00D" size="1" name="TAL_RESTART" access="WriteOnly" description="Debug Restart Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x00E" size="2" name="TAL_BRKSTATUS" access="ReadOnly" description="Break Request Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CPU0" description="CPU 0 Break Request" />
-      <BitField start="2" size="2" name="CPU1" description="CPU 1 Break Request" />
-      <BitField start="12" size="2" name="EVBRK" description="Event Break Request" />
-      <BitField start="14" size="2" name="EXTBRK" description="External Break Request" />
-    </Register>
-    <Register start="+0x010+0" size="1" name="TAL_CTICTRLA0" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x010+2" size="1" name="TAL_CTICTRLA1" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x010+4" size="1" name="TAL_CTICTRLA2" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x010+6" size="1" name="TAL_CTICTRLA3" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x011+0" size="1" name="TAL_CTIMASK0" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x011+2" size="1" name="TAL_CTIMASK1" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x011+4" size="1" name="TAL_CTIMASK2" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x011+6" size="1" name="TAL_CTIMASK3" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x020+0" size="1" name="TAL_INTSTATUS0" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+1" size="1" name="TAL_INTSTATUS1" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+2" size="1" name="TAL_INTSTATUS2" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+3" size="1" name="TAL_INTSTATUS3" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+4" size="1" name="TAL_INTSTATUS4" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+5" size="1" name="TAL_INTSTATUS5" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+6" size="1" name="TAL_INTSTATUS6" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+7" size="1" name="TAL_INTSTATUS7" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+8" size="1" name="TAL_INTSTATUS8" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+9" size="1" name="TAL_INTSTATUS9" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+10" size="1" name="TAL_INTSTATUS10" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+11" size="1" name="TAL_INTSTATUS11" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+12" size="1" name="TAL_INTSTATUS12" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+13" size="1" name="TAL_INTSTATUS13" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+14" size="1" name="TAL_INTSTATUS14" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+15" size="1" name="TAL_INTSTATUS15" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+16" size="1" name="TAL_INTSTATUS16" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+17" size="1" name="TAL_INTSTATUS17" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+18" size="1" name="TAL_INTSTATUS18" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+19" size="1" name="TAL_INTSTATUS19" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+20" size="1" name="TAL_INTSTATUS20" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+21" size="1" name="TAL_INTSTATUS21" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+22" size="1" name="TAL_INTSTATUS22" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+23" size="1" name="TAL_INTSTATUS23" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+24" size="1" name="TAL_INTSTATUS24" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+25" size="1" name="TAL_INTSTATUS25" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+26" size="1" name="TAL_INTSTATUS26" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+27" size="1" name="TAL_INTSTATUS27" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+28" size="1" name="TAL_INTSTATUS28" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+29" size="1" name="TAL_INTSTATUS29" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+30" size="1" name="TAL_INTSTATUS30" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+31" size="1" name="TAL_INTSTATUS31" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+32" size="1" name="TAL_INTSTATUS32" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+33" size="1" name="TAL_INTSTATUS33" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+34" size="1" name="TAL_INTSTATUS34" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+35" size="1" name="TAL_INTSTATUS35" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+36" size="1" name="TAL_INTSTATUS36" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+37" size="1" name="TAL_INTSTATUS37" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+38" size="1" name="TAL_INTSTATUS38" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+39" size="1" name="TAL_INTSTATUS39" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+40" size="1" name="TAL_INTSTATUS40" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+41" size="1" name="TAL_INTSTATUS41" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+42" size="1" name="TAL_INTSTATUS42" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+43" size="1" name="TAL_INTSTATUS43" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+44" size="1" name="TAL_INTSTATUS44" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+45" size="1" name="TAL_INTSTATUS45" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+46" size="1" name="TAL_INTSTATUS46" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+47" size="1" name="TAL_INTSTATUS47" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+48" size="1" name="TAL_INTSTATUS48" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+49" size="1" name="TAL_INTSTATUS49" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+50" size="1" name="TAL_INTSTATUS50" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+51" size="1" name="TAL_INTSTATUS51" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+52" size="1" name="TAL_INTSTATUS52" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+53" size="1" name="TAL_INTSTATUS53" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+54" size="1" name="TAL_INTSTATUS54" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+55" size="1" name="TAL_INTSTATUS55" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+56" size="1" name="TAL_INTSTATUS56" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+57" size="1" name="TAL_INTSTATUS57" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+58" size="1" name="TAL_INTSTATUS58" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+59" size="1" name="TAL_INTSTATUS59" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+60" size="1" name="TAL_INTSTATUS60" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+61" size="1" name="TAL_INTSTATUS61" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+62" size="1" name="TAL_INTSTATUS62" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+63" size="1" name="TAL_INTSTATUS63" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+64" size="1" name="TAL_INTSTATUS64" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+65" size="1" name="TAL_INTSTATUS65" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+66" size="1" name="TAL_INTSTATUS66" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+67" size="1" name="TAL_INTSTATUS67" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+68" size="1" name="TAL_INTSTATUS68" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+69" size="1" name="TAL_INTSTATUS69" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+70" size="1" name="TAL_INTSTATUS70" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+71" size="1" name="TAL_INTSTATUS71" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+72" size="1" name="TAL_INTSTATUS72" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+73" size="1" name="TAL_INTSTATUS73" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+74" size="1" name="TAL_INTSTATUS74" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+75" size="1" name="TAL_INTSTATUS75" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+76" size="1" name="TAL_INTSTATUS76" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+77" size="1" name="TAL_INTSTATUS77" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+78" size="1" name="TAL_INTSTATUS78" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+79" size="1" name="TAL_INTSTATUS79" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+80" size="1" name="TAL_INTSTATUS80" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+81" size="1" name="TAL_INTSTATUS81" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+82" size="1" name="TAL_INTSTATUS82" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+83" size="1" name="TAL_INTSTATUS83" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+84" size="1" name="TAL_INTSTATUS84" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+85" size="1" name="TAL_INTSTATUS85" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+86" size="1" name="TAL_INTSTATUS86" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+87" size="1" name="TAL_INTSTATUS87" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+88" size="1" name="TAL_INTSTATUS88" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+89" size="1" name="TAL_INTSTATUS89" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+90" size="1" name="TAL_INTSTATUS90" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+91" size="1" name="TAL_INTSTATUS91" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+92" size="1" name="TAL_INTSTATUS92" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+93" size="1" name="TAL_INTSTATUS93" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+94" size="1" name="TAL_INTSTATUS94" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+95" size="1" name="TAL_INTSTATUS95" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+96" size="1" name="TAL_INTSTATUS96" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+97" size="1" name="TAL_INTSTATUS97" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+98" size="1" name="TAL_INTSTATUS98" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+99" size="1" name="TAL_INTSTATUS99" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+100" size="1" name="TAL_INTSTATUS100" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+101" size="1" name="TAL_INTSTATUS101" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+102" size="1" name="TAL_INTSTATUS102" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+103" size="1" name="TAL_INTSTATUS103" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+104" size="1" name="TAL_INTSTATUS104" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+105" size="1" name="TAL_INTSTATUS105" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+106" size="1" name="TAL_INTSTATUS106" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+107" size="1" name="TAL_INTSTATUS107" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+108" size="1" name="TAL_INTSTATUS108" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+109" size="1" name="TAL_INTSTATUS109" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+110" size="1" name="TAL_INTSTATUS110" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+111" size="1" name="TAL_INTSTATUS111" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+112" size="1" name="TAL_INTSTATUS112" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+113" size="1" name="TAL_INTSTATUS113" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+114" size="1" name="TAL_INTSTATUS114" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+115" size="1" name="TAL_INTSTATUS115" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+116" size="1" name="TAL_INTSTATUS116" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+117" size="1" name="TAL_INTSTATUS117" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+118" size="1" name="TAL_INTSTATUS118" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+119" size="1" name="TAL_INTSTATUS119" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+120" size="1" name="TAL_INTSTATUS120" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+121" size="1" name="TAL_INTSTATUS121" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+122" size="1" name="TAL_INTSTATUS122" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+123" size="1" name="TAL_INTSTATUS123" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+124" size="1" name="TAL_INTSTATUS124" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+125" size="1" name="TAL_INTSTATUS125" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+126" size="1" name="TAL_INTSTATUS126" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+127" size="1" name="TAL_INTSTATUS127" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+128" size="1" name="TAL_INTSTATUS128" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+129" size="1" name="TAL_INTSTATUS129" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+130" size="1" name="TAL_INTSTATUS130" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+131" size="1" name="TAL_INTSTATUS131" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+132" size="1" name="TAL_INTSTATUS132" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+133" size="1" name="TAL_INTSTATUS133" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+134" size="1" name="TAL_INTSTATUS134" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+135" size="1" name="TAL_INTSTATUS135" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+136" size="1" name="TAL_INTSTATUS136" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x110" size="4" name="TAL_DMACPUSEL0" access="Read/Write" description="DMA Channel Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="DMA Channel 0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CH1" description="DMA Channel 1 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="CH2" description="DMA Channel 2 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="CH3" description="DMA Channel 3 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="CH4" description="DMA Channel 4 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="CH5" description="DMA Channel 5 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="CH6" description="DMA Channel 6 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="CH7" description="DMA Channel 7 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="CH8" description="DMA Channel 8 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="CH9" description="DMA Channel 9 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="CH10" description="DMA Channel 10 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="CH11" description="DMA Channel 11 Interrupt CPU Select" />
-      <BitField start="24" size="1" name="CH12" description="DMA Channel 12 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="CH13" description="DMA Channel 13 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="CH14" description="DMA Channel 14 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="CH15" description="DMA Channel 15 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x114" size="4" name="TAL_DMACPUSEL1" access="Read/Write" description="DMA Channel Interrupts CPU Select 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH16" description="DMA Channel 16 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CH17" description="DMA Channel 17 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="CH18" description="DMA Channel 18 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="CH19" description="DMA Channel 19 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="CH20" description="DMA Channel 20 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="CH21" description="DMA Channel 21 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="CH22" description="DMA Channel 22 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="CH23" description="DMA Channel 23 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="CH24" description="DMA Channel 24 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="CH25" description="DMA Channel 25 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="CH26" description="DMA Channel 26 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="CH27" description="DMA Channel 27 Interrupt CPU Select" />
-      <BitField start="24" size="1" name="CH28" description="DMA Channel 28 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="CH29" description="DMA Channel 29 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="CH30" description="DMA Channel 30 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="CH31" description="DMA Channel 31 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x118" size="4" name="TAL_EVCPUSEL0" access="Read/Write" description="EVSYS Channel Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Event Channel 0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CH1" description="Event Channel 1 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="CH2" description="Event Channel 2 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="CH3" description="Event Channel 3 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="CH4" description="Event Channel 4 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="CH5" description="Event Channel 5 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="CH6" description="Event Channel 6 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="CH7" description="Event Channel 7 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="CH8" description="Event Channel 8 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="CH9" description="Event Channel 9 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="CH10" description="Event Channel 10 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="CH11" description="Event Channel 11 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x120" size="4" name="TAL_EICCPUSEL0" access="Read/Write" description="EIC External Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0 CPU Select" />
-      <BitField start="2" size="1" name="EXTINT1" description="External Interrupt 1 CPU Select" />
-      <BitField start="4" size="1" name="EXTINT2" description="External Interrupt 2 CPU Select" />
-      <BitField start="6" size="1" name="EXTINT3" description="External Interrupt 3 CPU Select" />
-      <BitField start="8" size="1" name="EXTINT4" description="External Interrupt 4 CPU Select" />
-      <BitField start="10" size="1" name="EXTINT5" description="External Interrupt 5 CPU Select" />
-      <BitField start="12" size="1" name="EXTINT6" description="External Interrupt 6 CPU Select" />
-      <BitField start="14" size="1" name="EXTINT7" description="External Interrupt 7 CPU Select" />
-      <BitField start="16" size="1" name="EXTINT8" description="External Interrupt 8 CPU Select" />
-      <BitField start="18" size="1" name="EXTINT9" description="External Interrupt 9 CPU Select" />
-      <BitField start="20" size="1" name="EXTINT10" description="External Interrupt 10 CPU Select" />
-      <BitField start="22" size="1" name="EXTINT11" description="External Interrupt 11 CPU Select" />
-      <BitField start="24" size="1" name="EXTINT12" description="External Interrupt 12 CPU Select" />
-      <BitField start="26" size="1" name="EXTINT13" description="External Interrupt 13 CPU Select" />
-      <BitField start="28" size="1" name="EXTINT14" description="External Interrupt 14 CPU Select" />
-      <BitField start="30" size="1" name="EXTINT15" description="External Interrupt 15 CPU Select" />
-    </Register>
-    <Register start="+0x128" size="4" name="TAL_INTCPUSEL0" access="Read/Write" description="Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC" description="PAC Interrupt CPU Select" />
-      <BitField start="2" size="1" name="PM" description="PM Interrupt CPU Select" />
-      <BitField start="4" size="1" name="MCLK" description="MCLK Interrupt CPU Select" />
-      <BitField start="8" size="1" name="OSCCTRL" description="OSCCTRL Interrupt CPU Select" />
-      <BitField start="10" size="1" name="OSC32KCTRL" description="OSC32KCTRL Interrupt CPU Select" />
-      <BitField start="12" size="1" name="SUPC" description="SUPC Interrupt CPU Select" />
-      <BitField start="16" size="1" name="WDT" description="WDT Interrupt CPU Select" />
-      <BitField start="18" size="1" name="RTC" description="RTC Interrupt CPU Select" />
-      <BitField start="20" size="1" name="EIC" description="EIC Interrupt CPU Select" />
-      <BitField start="22" size="1" name="FREQM" description="FREQM Interrupt CPU Select" />
-      <BitField start="24" size="1" name="SERCOM0" description="SERCOM0 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="SERCOM1" description="SERCOM1 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="TC0" description="TC0 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="TC1" description="TC1 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TAL_INTCPUSEL1" access="Read/Write" description="Interrupts CPU Select 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130" size="4" name="TAL_INTCPUSEL2" access="Read/Write" description="Interrupts CPU Select 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB" description="USB Interrupt CPU Select" />
-      <BitField start="4" size="1" name="NVMCTRL" description="NVMCTRL Interrupt CPU Select" />
-      <BitField start="10" size="1" name="DMAC" description="DMAC Interrupt CPU Select" />
-      <BitField start="14" size="1" name="EVSYS" description="EVSYS Interrupt CPU Select" />
-      <BitField start="16" size="1" name="PICOP" description="PICOP Interrupt CPU Select" />
-      <BitField start="18" size="1" name="SERCOM2" description="SERCOM2 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="SERCOM3" description="SERCOM3 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="TCC0" description="TCC0 Interrupt CPU Select" />
-      <BitField start="24" size="1" name="TCC1" description="TCC1 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="TC2" description="TC2 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="TC3" description="TC3 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="TAL" description="TAL Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x134" size="4" name="TAL_INTCPUSEL3" access="Read/Write" description="Interrupts CPU Select 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAMECC" description="RAMECC Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x138" size="4" name="TAL_INTCPUSEL4" access="Read/Write" description="Interrupts CPU Select 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAN0" description="CAN0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CAN1" description="CAN1 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="GMAC" description="GMAC Interrupt CPU Select" />
-      <BitField start="6" size="1" name="TCC2" description="TCC2 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="TCC3" description="TCC3 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="TC4" description="TC4 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="TC5" description="TC5 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="PDEC" description="PDEC Interrupt CPU Select" />
-      <BitField start="16" size="1" name="AC" description="AC Interrupt CPU Select" />
-      <BitField start="18" size="1" name="AES" description="AES Interrupt CPU Select" />
-      <BitField start="20" size="1" name="TRNG" description="TRNG Interrupt CPU Select" />
-      <BitField start="22" size="1" name="ICM" description="ICM Interrupt CPU Select" />
-      <BitField start="24" size="1" name="PUKCC" description="PUKCC Interrupt CPU Select" />
-      <BitField start="26" size="1" name="QSPI" description="QSPI Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x13C" size="4" name="TAL_INTCPUSEL5" access="Read/Write" description="Interrupts CPU Select 5" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140" size="4" name="TAL_INTCPUSEL6" access="Read/Write" description="Interrupts CPU Select 6" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4" description="SERCOM4 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="SERCOM5" description="SERCOM5 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="SERCOM6" description="SERCOM6 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="SERCOM7" description="SERCOM7 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="TCC4" description="TCC4 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="TC6" description="TC6 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="TC7" description="TC7 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="ADC0" description="ADC0 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="ADC1" description="ADC1 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="DAC" description="DAC Interrupt CPU Select" />
-      <BitField start="20" size="1" name="I2S" description="I2S Interrupt CPU Select" />
-      <BitField start="22" size="1" name="PCC" description="PCC Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x144" size="4" name="TAL_INTCPUSEL7" access="Read/Write" description="Interrupts CPU Select 7" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="TAL_INTCPUSEL8" access="Read/Write" description="Interrupts CPU Select 8" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDHC0" description="SDHC0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="SDHC1" description="SDHC1 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x164" size="4" name="TAL_IRQTRIG" access="Read/Write" description="Interrupt Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Trigger Enable" />
-      <BitField start="8" size="8" name="IRQNUM" description="Interrupt Request Number" />
-      <BitField start="16" size="8" name="OVERRIDE" description="Interrupt Request Override Value" />
-    </Register>
-    <Register start="+0x168+0" size="2" name="TAL_IRQMON0" access="Read/Write" description="Interrupt Monitor Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTEND" description="Extended Interrupt Request">
-        <Enum name="NO" start="0x0" description="Event is Interrupt Request signal" />
-        <Enum name="YES" start="0x1" description="Event is Interrupt Request signal extended until end of Interrupt Handler" />
-      </BitField>
-      <BitField start="1" size="1" name="DROP" description="Drop Shortened Events" />
-      <BitField start="2" size="1" name="CPUID" description="ID of CPU currently servicing this IRQ" />
-      <BitField start="8" size="8" name="IRQNUM" description="Interrupt Request Number" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="TAL_CPUIRQS0_0" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="TAL_CPUIRQS0_1" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="TAL_CPUIRQS0_2" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+12" size="4" name="TAL_CPUIRQS0_3" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+16" size="4" name="TAL_CPUIRQS0_4" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+0" size="4" name="TAL_CPUIRQS1_0" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+4" size="4" name="TAL_CPUIRQS1_1" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+8" size="4" name="TAL_CPUIRQS1_2" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+12" size="4" name="TAL_CPUIRQS1_3" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+16" size="4" name="TAL_CPUIRQS1_4" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="TAL_SMASK0_0" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="TAL_SMASK0_1" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x208+0" size="4" name="TAL_SMASK1_0" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x208+4" size="4" name="TAL_SMASK1_1" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x220+0" size="4" name="TAL_SFLAGCLR0" access="WriteOnly" description="Inter-Process Signal Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x220+4" size="4" name="TAL_SFLAGCLR1" access="WriteOnly" description="Inter-Process Signal Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x228+0" size="4" name="TAL_SFLAGSET0" access="WriteOnly" description="Inter-Process Signal Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x228+4" size="4" name="TAL_SFLAGSET1" access="WriteOnly" description="Inter-Process Signal Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x230+0" size="4" name="TAL_SFLAG0" access="ReadOnly" description="Inter-Process Signal Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x230+4" size="4" name="TAL_SFLAG1" access="ReadOnly" description="Inter-Process Signal Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x300+0" size="1" name="TAL_SFLAGCLRR0" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+1" size="1" name="TAL_SFLAGCLRR1" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+2" size="1" name="TAL_SFLAGCLRR2" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+3" size="1" name="TAL_SFLAGCLRR3" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+4" size="1" name="TAL_SFLAGCLRR4" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+5" size="1" name="TAL_SFLAGCLRR5" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+6" size="1" name="TAL_SFLAGCLRR6" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+7" size="1" name="TAL_SFLAGCLRR7" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+8" size="1" name="TAL_SFLAGCLRR8" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+9" size="1" name="TAL_SFLAGCLRR9" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+10" size="1" name="TAL_SFLAGCLRR10" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+11" size="1" name="TAL_SFLAGCLRR11" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+12" size="1" name="TAL_SFLAGCLRR12" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+13" size="1" name="TAL_SFLAGCLRR13" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+14" size="1" name="TAL_SFLAGCLRR14" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+15" size="1" name="TAL_SFLAGCLRR15" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+16" size="1" name="TAL_SFLAGCLRR16" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+17" size="1" name="TAL_SFLAGCLRR17" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+18" size="1" name="TAL_SFLAGCLRR18" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+19" size="1" name="TAL_SFLAGCLRR19" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+20" size="1" name="TAL_SFLAGCLRR20" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+21" size="1" name="TAL_SFLAGCLRR21" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+22" size="1" name="TAL_SFLAGCLRR22" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+23" size="1" name="TAL_SFLAGCLRR23" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+24" size="1" name="TAL_SFLAGCLRR24" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+25" size="1" name="TAL_SFLAGCLRR25" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+26" size="1" name="TAL_SFLAGCLRR26" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+27" size="1" name="TAL_SFLAGCLRR27" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+28" size="1" name="TAL_SFLAGCLRR28" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+29" size="1" name="TAL_SFLAGCLRR29" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+30" size="1" name="TAL_SFLAGCLRR30" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+31" size="1" name="TAL_SFLAGCLRR31" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+32" size="1" name="TAL_SFLAGCLRR32" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+33" size="1" name="TAL_SFLAGCLRR33" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+34" size="1" name="TAL_SFLAGCLRR34" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+35" size="1" name="TAL_SFLAGCLRR35" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+36" size="1" name="TAL_SFLAGCLRR36" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+37" size="1" name="TAL_SFLAGCLRR37" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+38" size="1" name="TAL_SFLAGCLRR38" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+39" size="1" name="TAL_SFLAGCLRR39" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+40" size="1" name="TAL_SFLAGCLRR40" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+41" size="1" name="TAL_SFLAGCLRR41" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+42" size="1" name="TAL_SFLAGCLRR42" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+43" size="1" name="TAL_SFLAGCLRR43" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+44" size="1" name="TAL_SFLAGCLRR44" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+45" size="1" name="TAL_SFLAGCLRR45" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+46" size="1" name="TAL_SFLAGCLRR46" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+47" size="1" name="TAL_SFLAGCLRR47" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+48" size="1" name="TAL_SFLAGCLRR48" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+49" size="1" name="TAL_SFLAGCLRR49" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+50" size="1" name="TAL_SFLAGCLRR50" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+51" size="1" name="TAL_SFLAGCLRR51" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+52" size="1" name="TAL_SFLAGCLRR52" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+53" size="1" name="TAL_SFLAGCLRR53" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+54" size="1" name="TAL_SFLAGCLRR54" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+55" size="1" name="TAL_SFLAGCLRR55" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+56" size="1" name="TAL_SFLAGCLRR56" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+57" size="1" name="TAL_SFLAGCLRR57" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+58" size="1" name="TAL_SFLAGCLRR58" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+59" size="1" name="TAL_SFLAGCLRR59" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+60" size="1" name="TAL_SFLAGCLRR60" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+61" size="1" name="TAL_SFLAGCLRR61" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+62" size="1" name="TAL_SFLAGCLRR62" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+63" size="1" name="TAL_SFLAGCLRR63" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC0 (COUNT8)" start="0x40003800" description="Basic Timer Counter 0">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC0 (COUNT16)" start="0x40003800" description="Basic Timer Counter 0">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC0 (COUNT32)" start="0x40003800" description="Basic Timer Counter 0">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC1 (COUNT8)" start="0x40003C00" description="Basic Timer Counter 1">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC1 (COUNT16)" start="0x40003C00" description="Basic Timer Counter 1">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC1 (COUNT32)" start="0x40003C00" description="Basic Timer Counter 1">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC2 (COUNT8)" start="0x4101A000" description="Basic Timer Counter 2">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC2 (COUNT16)" start="0x4101A000" description="Basic Timer Counter 2">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC2 (COUNT32)" start="0x4101A000" description="Basic Timer Counter 2">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT8)" start="0x4101C000" description="Basic Timer Counter 3">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT16)" start="0x4101C000" description="Basic Timer Counter 3">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT32)" start="0x4101C000" description="Basic Timer Counter 3">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT8)" start="0x42001400" description="Basic Timer Counter 4">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT16)" start="0x42001400" description="Basic Timer Counter 4">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT32)" start="0x42001400" description="Basic Timer Counter 4">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT8)" start="0x42001800" description="Basic Timer Counter 5">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT16)" start="0x42001800" description="Basic Timer Counter 5">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT32)" start="0x42001800" description="Basic Timer Counter 5">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC0" start="0x41016000" description="Timer Counter Control 0">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC1" start="0x41018000" description="Timer Counter Control 1">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC2" start="0x42000C00" description="Timer Counter Control 2">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC3" start="0x42001000" description="Timer Counter Control 3">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC4" start="0x43001000" description="Timer Counter Control 4">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TRNG" start="0x42002800" description="True Random Generator">
-    <Register start="+0x00" size="1" name="TRNG_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x04" size="1" name="TRNG_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDYEO" description="Data Ready Event Output" />
-    </Register>
-    <Register start="+0x08" size="1" name="TRNG_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Data Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x09" size="1" name="TRNG_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Data Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TRNG_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Data Ready Interrupt Flag" />
-    </Register>
-    <Register start="+0x20" size="4" name="TRNG_DATA" access="ReadOnly" description="Output Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Output Data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (DEVICE)" start="0x41000000" description="Universal Serial Bus">
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x0F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service" />
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service" />
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="DEVICE Control B" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETACH" description="Detach" />
-      <BitField start="1" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration">
-        <Enum name="FS" start="0x0" description="FS : Full Speed" />
-        <Enum name="LS" start="0x1" description="LS : Low Speed" />
-        <Enum name="HS" start="0x2" description="HS : High Speed capable" />
-        <Enum name="HSTM" start="0x3" description="HSTM: High Speed Test Mode (force high-speed mode for test mode)" />
-      </BitField>
-      <BitField start="4" size="1" name="NREPLY" description="No Reply" />
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="7" size="1" name="TSTPCKT" description="Test packet mode" />
-      <BitField start="8" size="1" name="OPMODE2" description="Specific Operational Mode" />
-      <BitField start="9" size="1" name="GNAK" description="Global NAK" />
-      <BitField start="10" size="2" name="LPMHDSK" description="Link Power Management Handshake">
-        <Enum name="NO" start="0x0" description="No handshake. LPM is not supported" />
-        <Enum name="ACK" start="0x1" description="ACK" />
-        <Enum name="NYET" start="0x2" description="NYET" />
-        <Enum name="STALL" start="0x3" description="STALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_DADD" access="Read/Write" description="DEVICE Device Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DADD" description="Device Address" />
-      <BitField start="7" size="1" name="ADDEN" description="Device Address Enable" />
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="ReadOnly" description="DEVICE Status" reset_value="0x40" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status">
-        <Enum name="FS" start="0x0" description="Full-speed mode" />
-        <Enum name="LS" start="0x1" description="Low-speed mode" />
-        <Enum name="HS" start="0x2" description="High-speed mode" />
-      </BitField>
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status">
-        <Enum name="0" start="0x0" description="SE0/RESET" />
-        <Enum name="1" start="0x1" description="FS-J or LS-K State" />
-        <Enum name="2" start="0x2" description="FS-K or LS-J State" />
-      </BitField>
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="ReadOnly" description="DEVICE Device Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-      <BitField start="15" size="1" name="FNCERR" description="Frame Number CRC Error" />
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="DEVICE Device Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="DEVICE Device Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="DEVICE Device Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_EPINTSMRY" access="ReadOnly" description="DEVICE End Point Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="End Point 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="End Point 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="End Point 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="End Point 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="End Point 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="End Point 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="End Point 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="End Point 7 Interrupt" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_EPCFG0" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_EPCFG1" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_EPCFG2" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_EPCFG3" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_EPCFG4" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_EPCFG5" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_EPCFG6" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_EPCFG7" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_EPSTATUSCLR0" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_EPSTATUSCLR1" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_EPSTATUSCLR2" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_EPSTATUSCLR3" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_EPSTATUSCLR4" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_EPSTATUSCLR5" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_EPSTATUSCLR6" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_EPSTATUSCLR7" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_EPSTATUSSET0" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_EPSTATUSSET1" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_EPSTATUSSET2" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_EPSTATUSSET3" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_EPSTATUSSET4" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_EPSTATUSSET5" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_EPSTATUSSET6" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_EPSTATUSSET7" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_EPSTATUS0" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_EPSTATUS1" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_EPSTATUS2" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_EPSTATUS3" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_EPSTATUS4" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_EPSTATUS5" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_EPSTATUS6" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_EPSTATUS7" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_EPINTFLAG0" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_EPINTFLAG1" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_EPINTFLAG2" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_EPINTFLAG3" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_EPINTFLAG4" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_EPINTFLAG5" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_EPINTFLAG6" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_EPINTFLAG7" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_EPINTENCLR0" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_EPINTENCLR1" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_EPINTENCLR2" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_EPINTENCLR3" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_EPINTENCLR4" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_EPINTENCLR5" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_EPINTENCLR6" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_EPINTENCLR7" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_EPINTENSET0" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_EPINTENSET1" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_EPINTENSET2" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_EPINTENSET3" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_EPINTENSET4" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_EPINTENSET5" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_EPINTENSET6" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_EPINTENSET7" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (HOST)" start="0x41000000" description="Universal Serial Bus">
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x0F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service" />
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service" />
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="HOST Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RESUME" description="Send USB Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration for Host">
-        <Enum name="NORMAL" start="0x0" description="Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." />
-        <Enum name="FS" start="0x3" description="Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." />
-      </BitField>
-      <BitField start="4" size="1" name="AUTORESUME" description="Auto Resume Enable" />
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="8" size="1" name="SOFE" description="Start of Frame Generation Enable" />
-      <BitField start="9" size="1" name="BUSRESET" description="Send USB Reset" />
-      <BitField start="10" size="1" name="VBUSOK" description="VBUS is OK" />
-      <BitField start="11" size="1" name="L1RESUME" description="Send L1 Resume" />
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_HSOFC" access="Read/Write" description="HOST Host Start Of Frame Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FLENC" description="Frame Length Control" />
-      <BitField start="7" size="1" name="FLENCE" description="Frame Length Control Enable" />
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="Read/Write" description="HOST Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status" />
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status" />
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="Read/Write" description="HOST Host Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-    </Register>
-    <Register start="+0x012" size="1" name="USB_FLENHIGH" access="ReadOnly" description="HOST Host Frame Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FLENHIGH" description="Frame Length" />
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="HOST Host Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Disable" />
-      <BitField start="3" size="1" name="RST" description="BUS Reset Interrupt Disable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Disable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to Device Interrupt Disable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from Device Interrupt Disable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Disable" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection Interrupt Disable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Disable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="HOST Host Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to the Device Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume fromthe device Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="DCONN" description="Link Power Management Interrupt Enable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="HOST Host Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="DNRSM" description="Downstream" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from the Device" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_PINTSMRY" access="ReadOnly" description="HOST Pipe Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="Pipe 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="Pipe 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="Pipe 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="Pipe 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="Pipe 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="Pipe 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="Pipe 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="Pipe 7 Interrupt" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_PCFG0" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_PCFG1" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_PCFG2" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_PCFG3" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_PCFG4" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_PCFG5" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_PCFG6" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_PCFG7" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x103+0" size="1" name="USB_BINTERVAL0" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+32" size="1" name="USB_BINTERVAL1" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+64" size="1" name="USB_BINTERVAL2" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+96" size="1" name="USB_BINTERVAL3" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+128" size="1" name="USB_BINTERVAL4" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+160" size="1" name="USB_BINTERVAL5" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+192" size="1" name="USB_BINTERVAL6" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+224" size="1" name="USB_BINTERVAL7" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_PSTATUSCLR0" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_PSTATUSCLR1" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_PSTATUSCLR2" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_PSTATUSCLR3" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_PSTATUSCLR4" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_PSTATUSCLR5" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_PSTATUSCLR6" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_PSTATUSCLR7" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_PSTATUSSET0" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_PSTATUSSET1" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_PSTATUSSET2" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_PSTATUSSET3" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_PSTATUSSET4" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_PSTATUSSET5" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_PSTATUSSET6" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_PSTATUSSET7" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_PSTATUS0" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_PSTATUS1" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_PSTATUS2" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_PSTATUS3" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_PSTATUS4" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_PSTATUS5" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_PSTATUS6" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_PSTATUS7" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_PINTFLAG0" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_PINTFLAG1" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_PINTFLAG2" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_PINTFLAG3" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_PINTFLAG4" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_PINTFLAG5" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_PINTFLAG6" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_PINTFLAG7" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_PINTENCLR0" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_PINTENCLR1" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_PINTENCLR2" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_PINTENCLR3" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_PINTENCLR4" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_PINTENCLR5" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_PINTENCLR6" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_PINTENCLR7" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_PINTENSET0" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_PINTENSET1" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_PINTENSET2" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_PINTENSET3" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_PINTENSET4" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_PINTENSET5" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_PINTENSET6" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_PINTENSET7" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WDT" start="0x40002000" description="Watchdog Timer">
-    <Register start="+0x0" size="1" name="WDT_CTRLA" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="WEN" description="Watchdog Timer Window Mode Enable" />
-      <BitField start="7" size="1" name="ALWAYSON" description="Always-On" />
-    </Register>
-    <Register start="+0x1" size="1" name="WDT_CONFIG" access="Read/Write" description="Configuration" reset_value="0xBB" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PER" description="Time-Out Period">
-        <Enum name="CYC8" start="0x0" description="8 clock cycles" />
-        <Enum name="CYC16" start="0x1" description="16 clock cycles" />
-        <Enum name="CYC32" start="0x2" description="32 clock cycles" />
-        <Enum name="CYC64" start="0x3" description="64 clock cycles" />
-        <Enum name="CYC128" start="0x4" description="128 clock cycles" />
-        <Enum name="CYC256" start="0x5" description="256 clock cycles" />
-        <Enum name="CYC512" start="0x6" description="512 clock cycles" />
-        <Enum name="CYC1024" start="0x7" description="1024 clock cycles" />
-        <Enum name="CYC2048" start="0x8" description="2048 clock cycles" />
-        <Enum name="CYC4096" start="0x9" description="4096 clock cycles" />
-        <Enum name="CYC8192" start="0xa" description="8192 clock cycles" />
-        <Enum name="CYC16384" start="0xb" description="16384 clock cycles" />
-      </BitField>
-      <BitField start="4" size="4" name="WINDOW" description="Window Mode Time-Out Period">
-        <Enum name="CYC8" start="0x0" description="8 clock cycles" />
-        <Enum name="CYC16" start="0x1" description="16 clock cycles" />
-        <Enum name="CYC32" start="0x2" description="32 clock cycles" />
-        <Enum name="CYC64" start="0x3" description="64 clock cycles" />
-        <Enum name="CYC128" start="0x4" description="128 clock cycles" />
-        <Enum name="CYC256" start="0x5" description="256 clock cycles" />
-        <Enum name="CYC512" start="0x6" description="512 clock cycles" />
-        <Enum name="CYC1024" start="0x7" description="1024 clock cycles" />
-        <Enum name="CYC2048" start="0x8" description="2048 clock cycles" />
-        <Enum name="CYC4096" start="0x9" description="4096 clock cycles" />
-        <Enum name="CYC8192" start="0xa" description="8192 clock cycles" />
-        <Enum name="CYC16384" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x2" size="1" name="WDT_EWCTRL" access="Read/Write" description="Early Warning Interrupt Control" reset_value="0x0B" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EWOFFSET" description="Early Warning Interrupt Time Offset">
-        <Enum name="CYC8" start="0x0" description="8 clock cycles" />
-        <Enum name="CYC16" start="0x1" description="16 clock cycles" />
-        <Enum name="CYC32" start="0x2" description="32 clock cycles" />
-        <Enum name="CYC64" start="0x3" description="64 clock cycles" />
-        <Enum name="CYC128" start="0x4" description="128 clock cycles" />
-        <Enum name="CYC256" start="0x5" description="256 clock cycles" />
-        <Enum name="CYC512" start="0x6" description="512 clock cycles" />
-        <Enum name="CYC1024" start="0x7" description="1024 clock cycles" />
-        <Enum name="CYC2048" start="0x8" description="2048 clock cycles" />
-        <Enum name="CYC4096" start="0x9" description="4096 clock cycles" />
-        <Enum name="CYC8192" start="0xa" description="8192 clock cycles" />
-        <Enum name="CYC16384" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x4" size="1" name="WDT_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x5" size="1" name="WDT_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x6" size="1" name="WDT_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning" />
-    </Register>
-    <Register start="+0x8" size="4" name="WDT_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="WEN" description="Window Enable Synchronization Busy" />
-      <BitField start="3" size="1" name="ALWAYSON" description="Always-On Synchronization Busy" />
-      <BitField start="4" size="1" name="CLEAR" description="Clear Synchronization Busy" />
-    </Register>
-    <Register start="+0xC" size="1" name="WDT_CLEAR" access="WriteOnly" description="Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLEAR" description="Watchdog Clear">
-        <Enum name="KEY" start="0xa5" description="Clear Key" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000E000" name="SCB">
-    <Register start="0xE000E004" name="ICTR" aka="Interrupt_Control_Type" access="ReadOnly" description="Interrupt Controller Type Register">
-      <BitField size="5" start="0" name="INTLINESNUM" description="Total number of interrupt lines in groups">
-        <Enum name="0...32" start="0x0" />
-        <Enum name="33...64" start="0x1" />
-        <Enum name="65...96" start="0x2" />
-        <Enum name="97...128" start="0x3" />
-        <Enum name="129...160" start="0x4" />
-        <Enum name="161...192" start="0x5" />
-        <Enum name="193...224" start="0x6" />
-        <Enum name="225...256" start="0x7" />
-      </BitField>
-    </Register>
-    <Register start="0xE000E008" name="ACTLR" description="Auxiliary Control Register">
-      <BitField size="1" start="0" name="DISMCYCINT" description="Disable load/store multiple" />
-      <BitField size="1" start="1" name="DISDEFWBUF" description="Disable write buffer" />
-      <BitField size="1" start="2" name="DISFOLD" description="Disable IT folding" />
-      <BitField size="1" start="8" name="DISFPCA" description="Disable FPCA update" />
-      <BitField size="1" start="9" name="DISOOFP" description="Disable out of order FP execution" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000E010" name="SysTick" description="24Bit System Tick Timer for use in RTOS">
-    <Register start="0xE000E010" name="SYST_CSR" aka="SysTick_Control_And_Status" description="SysTick Control and Status Register">
-      <BitField size="1" name="COUNTFLAG" start="16" description="Counter Flag" />
-      <BitField size="1" name="CLKSOURCE" start="2" description="Timer Clock Source" />
-      <BitField size="1" name="TICKINT" start="1" description="Tick Interrupt Enable" />
-      <BitField size="1" name="ENABLE" start="0" description="Enable SysTick Timer" />
-    </Register>
-    <Register start="0xE000E014" name="SYST_RVR" aka="SysTick_Reload_Value" description="SysTick Reload Value Register">
-      <BitField size="24" name="RELOAD" start="0" description="Value to auto reload SysTick after reaching zero" />
-    </Register>
-    <Register start="0xE000E018" name="SYST_CVR" aka="SysTick_Current_Value" description="SysTick Current Value Register">
-      <BitField size="24" name="CURRENT" start="0" description="Current value" />
-    </Register>
-    <Register start="0xE000E01C" name="SYST_CALIB" aka="SysTick_Calibration_Value" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField size="1" name="NOREF" start="31" description="No Ref" />
-      <BitField size="1" name="SKEW" start="30" description="Clock Skew" />
-      <BitField size="24" name="TENMS" start="0" description="Reload value to use for 10ms timing" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000E100" name="NVIC" description="Nested Vectored Interrupt Controller">
-    <Register start="0xE000E100" name="NVIC_ISER0" aka="Irq_0_to_31_Set_Enable" description="Interrupt Set-Enable Register 0" />
-    <Register start="0xE000E104" name="NVIC_ISER1" aka="Irq_32_to_63_Set_Enable" description="Interrupt Set-Enable Register 1" />
-    <Register start="0xE000E108" name="NVIC_ISER2" aka="Irq_64_to_95_Set_Enable" description="Interrupt Set-Enable Register 2" />
-    <Register start="0xE000E10C" name="NVIC_ISER3" aka="Irq_96_to_127_Set_Enable" description="Interrupt Set-Enable Register 3" />
-    <Register start="0xE000E110" name="NVIC_ISER4" aka="Irq_128_to_159_Set_Enable" description="Interrupt Set-Enable Register 4" />
-    <Register start="0xE000E180" name="NVIC_ICER0" aka="Irq_0_to_31_Clear_Enable" description="Interrupt Clear-Enable Register 0" />
-    <Register start="0xE000E184" name="NVIC_ICER1" aka="Irq_32_to_63_Clear_Enable" description="Interrupt Clear-Enable Register 1" />
-    <Register start="0xE000E188" name="NVIC_ICER2" aka="Irq_64_to_95_Clear_Enable" description="Interrupt Clear-Enable Register 2" />
-    <Register start="0xE000E18C" name="NVIC_ICER3" aka="Irq_96_to_127_Clear_Enable" description="Interrupt Clear-Enable Register 3" />
-    <Register start="0xE000E190" name="NVIC_ICER4" aka="Irq_128_to_159_Clear_Enable" description="Interrupt Clear-Enable Register 4" />
-    <Register start="0xE000E200" name="NVIC_ISPR0" aka="Irq_0_to_31_Set_Pending" description="Interrupt Set-Pending Register 0" />
-    <Register start="0xE000E204" name="NVIC_ISPR1" aka="Irq_32_to_63_Set_Pending" description="Interrupt Set-Pending Register 1" />
-    <Register start="0xE000E208" name="NVIC_ISPR2" aka="Irq_64_to_95_Set_Pending" description="Interrupt Set-Pending Register 2" />
-    <Register start="0xE000E20C" name="NVIC_ISPR3" aka="Irq_96_to_127_Set_Pending" description="Interrupt Set-Pending Register 3" />
-    <Register start="0xE000E210" name="NVIC_ISPR4" aka="Irq_128_to_159_Set_Pending" description="Interrupt Set-Pending Register 4" />
-    <Register start="0xE000E280" name="NVIC_ICPR0" aka="Irq_0_to_31_Clear_Pending" description="Interrupt Clear-Pending Register 0" />
-    <Register start="0xE000E284" name="NVIC_ICPR1" aka="Irq_32_to_63_Clear_Pending" description="Interrupt Clear-Pending Register 1" />
-    <Register start="0xE000E288" name="NVIC_ICPR2" aka="Irq_64_to_95_Clear_Pending" description="Interrupt Clear-Pending Register 2" />
-    <Register start="0xE000E28C" name="NVIC_ICPR3" aka="Irq_96_to_127_Clear_Pending" description="Interrupt Clear-Pending Register 3" />
-    <Register start="0xE000E290" name="NVIC_ICPR4" aka="Irq_128_to_159_Clear_Pending" description="Interrupt Clear-Pending Register 4" />
-    <Register start="0xE000E300" name="NVIC_IABR0" aka="Irq_0_to_31_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 0" />
-    <Register start="0xE000E304" name="NVIC_IABR1" aka="Irq_32_to_63_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 1" />
-    <Register start="0xE000E308" name="NVIC_IABR2" aka="Irq_64_to_95_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 2" />
-    <Register start="0xE000E30C" name="NVIC_IABR3" aka="Irq_96_to_127_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 3" />
-    <Register start="0xE000E310" name="NVIC_IABR4" aka="Irq_128_to_159_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 4" />
-    <Register start="0xE000E400" name="NVIC_IPR0" aka="Irq_0_to_3_Priority" description="Interrupt Priority Register 0">
-      <BitField size="3" name="PRI_0" start="5" />
-      <BitField size="3" name="PRI_1" start="13" />
-      <BitField size="3" name="PRI_2" start="21" />
-      <BitField size="3" name="PRI_3" start="29" />
-    </Register>
-    <Register start="0xE000E404" name="NVIC_IPR1" aka="Irq_4_to_7_Priority" description="Interrupt Priority Register 1">
-      <BitField size="3" name="PRI_4" start="5" />
-      <BitField size="3" name="PRI_5" start="13" />
-      <BitField size="3" name="PRI_6" start="21" />
-      <BitField size="3" name="PRI_7" start="29" />
-    </Register>
-    <Register start="0xE000E408" name="NVIC_IPR2" aka="Irq_8_to_11_Priority" description="Interrupt Priority Register 2">
-      <BitField size="3" name="PRI_8" start="5" />
-      <BitField size="3" name="PRI_9" start="13" />
-      <BitField size="3" name="PRI_10" start="21" />
-      <BitField size="3" name="PRI_11" start="29" />
-    </Register>
-    <Register start="0xE000E40C" name="NVIC_IPR3" aka="Irq_12_to_15_Priority" description="Interrupt Priority Register 3">
-      <BitField size="3" name="PRI_12" start="5" />
-      <BitField size="3" name="PRI_13" start="13" />
-      <BitField size="3" name="PRI_14" start="21" />
-      <BitField size="3" name="PRI_15" start="29" />
-    </Register>
-    <Register start="0xE000E410" name="NVIC_IPR4" aka="Irq_16_to_19_Priority" description="Interrupt Priority Register 4">
-      <BitField size="3" name="PRI_16" start="5" />
-      <BitField size="3" name="PRI_17" start="13" />
-      <BitField size="3" name="PRI_18" start="21" />
-      <BitField size="3" name="PRI_19" start="29" />
-    </Register>
-    <Register start="0xE000E414" name="NVIC_IPR5" aka="Irq_20_to_23_Priority" description="Interrupt Priority Register 5">
-      <BitField size="3" name="PRI_20" start="5" />
-      <BitField size="3" name="PRI_21" start="13" />
-      <BitField size="3" name="PRI_22" start="21" />
-      <BitField size="3" name="PRI_23" start="29" />
-    </Register>
-    <Register start="0xE000E418" name="NVIC_IPR6" aka="Irq_24_to_27_Priority" description="Interrupt Priority Register 6">
-      <BitField size="3" name="PRI_24" start="5" />
-      <BitField size="3" name="PRI_25" start="13" />
-      <BitField size="3" name="PRI_26" start="21" />
-      <BitField size="3" name="PRI_27" start="29" />
-    </Register>
-    <Register start="0xE000E41C" name="NVIC_IPR7" aka="Irq_28_to_31_Priority" description="Interrupt Priority Register 7">
-      <BitField size="3" name="PRI_28" start="5" />
-      <BitField size="3" name="PRI_29" start="13" />
-      <BitField size="3" name="PRI_30" start="21" />
-      <BitField size="3" name="PRI_31" start="29" />
-    </Register>
-    <Register start="0xE000E420" name="NVIC_IPR8" aka="Irq_32_to_35_Priority" description="Interrupt Priority Register 8">
-      <BitField size="3" name="PRI_32" start="5" />
-      <BitField size="3" name="PRI_33" start="13" />
-      <BitField size="3" name="PRI_34" start="21" />
-      <BitField size="3" name="PRI_35" start="29" />
-    </Register>
-    <Register start="0xE000E424" name="NVIC_IPR9" aka="Irq_36_to_39_Priority" description="Interrupt Priority Register 9">
-      <BitField size="3" name="PRI_36" start="5" />
-      <BitField size="3" name="PRI_37" start="13" />
-      <BitField size="3" name="PRI_38" start="21" />
-      <BitField size="3" name="PRI_39" start="29" />
-    </Register>
-    <Register start="0xE000E428" name="NVIC_IPR10" aka="Irq_40_to_43_Priority" description="Interrupt Priority Register 10">
-      <BitField size="3" name="PRI_40" start="5" />
-      <BitField size="3" name="PRI_41" start="13" />
-      <BitField size="3" name="PRI_42" start="21" />
-      <BitField size="3" name="PRI_43" start="29" />
-    </Register>
-    <Register start="0xE000E42C" name="NVIC_IPR11" aka="Irq_44_to_47_Priority" description="Interrupt Priority Register 11">
-      <BitField size="3" name="PRI_44" start="5" />
-      <BitField size="3" name="PRI_45" start="13" />
-      <BitField size="3" name="PRI_46" start="21" />
-      <BitField size="3" name="PRI_47" start="29" />
-    </Register>
-    <Register start="0xE000E430" name="NVIC_IPR12" aka="Irq_48_to_51_Priority" description="Interrupt Priority Register 12">
-      <BitField size="3" name="PRI_48" start="5" />
-      <BitField size="3" name="PRI_49" start="13" />
-      <BitField size="3" name="PRI_50" start="21" />
-      <BitField size="3" name="PRI_51" start="29" />
-    </Register>
-    <Register start="0xE000E434" name="NVIC_IPR13" aka="Irq_52_to_55_Priority" description="Interrupt Priority Register 13">
-      <BitField size="3" name="PRI_52" start="5" />
-      <BitField size="3" name="PRI_53" start="13" />
-      <BitField size="3" name="PRI_54" start="21" />
-      <BitField size="3" name="PRI_55" start="29" />
-    </Register>
-    <Register start="0xE000E438" name="NVIC_IPR14" aka="Irq_56_to_59_Priority" description="Interrupt Priority Register 14">
-      <BitField size="3" name="PRI_56" start="5" />
-      <BitField size="3" name="PRI_57" start="13" />
-      <BitField size="3" name="PRI_58" start="21" />
-      <BitField size="3" name="PRI_59" start="29" />
-    </Register>
-    <Register start="0xE000E43C" name="NVIC_IPR15" aka="Irq_60_to_63_Priority" description="Interrupt Priority Register 15">
-      <BitField size="3" name="PRI_60" start="5" />
-      <BitField size="3" name="PRI_61" start="13" />
-      <BitField size="3" name="PRI_62" start="21" />
-      <BitField size="3" name="PRI_63" start="29" />
-    </Register>
-    <Register start="0xE000E440" name="NVIC_IPR16" aka="Irq_64_to_67_Priority" description="Interrupt Priority Register 16">
-      <BitField size="3" name="PRI_64" start="5" />
-      <BitField size="3" name="PRI_65" start="13" />
-      <BitField size="3" name="PRI_66" start="21" />
-      <BitField size="3" name="PRI_67" start="29" />
-    </Register>
-    <Register start="0xE000E444" name="NVIC_IPR17" aka="Irq_68_to_71_Priority" description="Interrupt Priority Register 17">
-      <BitField size="3" name="PRI_68" start="5" />
-      <BitField size="3" name="PRI_69" start="13" />
-      <BitField size="3" name="PRI_70" start="21" />
-      <BitField size="3" name="PRI_71" start="29" />
-    </Register>
-    <Register start="0xE000E448" name="NVIC_IPR18" aka="Irq_72_to_75_Priority" description="Interrupt Priority Register 18">
-      <BitField size="3" name="PRI_72" start="5" />
-      <BitField size="3" name="PRI_73" start="13" />
-      <BitField size="3" name="PRI_74" start="21" />
-      <BitField size="3" name="PRI_75" start="29" />
-    </Register>
-    <Register start="0xE000E44C" name="NVIC_IPR19" aka="Irq_76_to_79_Priority" description="Interrupt Priority Register 19">
-      <BitField size="3" name="PRI_76" start="5" />
-      <BitField size="3" name="PRI_77" start="13" />
-      <BitField size="3" name="PRI_78" start="21" />
-      <BitField size="3" name="PRI_79" start="29" />
-    </Register>
-    <Register start="0xE000E450" name="NVIC_IPR20" aka="Irq_80_to_83_Priority" description="Interrupt Priority Register 20">
-      <BitField size="3" name="PRI_80" start="5" />
-      <BitField size="3" name="PRI_81" start="13" />
-      <BitField size="3" name="PRI_82" start="21" />
-      <BitField size="3" name="PRI_83" start="29" />
-    </Register>
-    <Register start="0xE000E454" name="NVIC_IPR21" aka="Irq_84_to_87_Priority" description="Interrupt Priority Register 21">
-      <BitField size="3" name="PRI_84" start="5" />
-      <BitField size="3" name="PRI_85" start="13" />
-      <BitField size="3" name="PRI_86" start="21" />
-      <BitField size="3" name="PRI_87" start="29" />
-    </Register>
-    <Register start="0xE000E458" name="NVIC_IPR22" aka="Irq_88_to_91_Priority" description="Interrupt Priority Register 22">
-      <BitField size="3" name="PRI_88" start="5" />
-      <BitField size="3" name="PRI_89" start="13" />
-      <BitField size="3" name="PRI_90" start="21" />
-      <BitField size="3" name="PRI_91" start="29" />
-    </Register>
-    <Register start="0xE000E45C" name="NVIC_IPR23" aka="Irq_92_to_95_Priority" description="Interrupt Priority Register 23">
-      <BitField size="3" name="PRI_92" start="5" />
-      <BitField size="3" name="PRI_93" start="13" />
-      <BitField size="3" name="PRI_94" start="21" />
-      <BitField size="3" name="PRI_95" start="29" />
-    </Register>
-    <Register start="0xE000E460" name="NVIC_IPR24" aka="Irq_96_to_99_Priority" description="Interrupt Priority Register 24">
-      <BitField size="3" name="PRI_96" start="5" />
-      <BitField size="3" name="PRI_97" start="13" />
-      <BitField size="3" name="PRI_98" start="21" />
-      <BitField size="3" name="PRI_99" start="29" />
-    </Register>
-    <Register start="0xE000E464" name="NVIC_IPR25" aka="Irq_100_to_103_Priority" description="Interrupt Priority Register 25">
-      <BitField size="3" name="PRI_100" start="5" />
-      <BitField size="3" name="PRI_101" start="13" />
-      <BitField size="3" name="PRI_102" start="21" />
-      <BitField size="3" name="PRI_103" start="29" />
-    </Register>
-    <Register start="0xE000E468" name="NVIC_IPR26" aka="Irq_104_to_107_Priority" description="Interrupt Priority Register 26">
-      <BitField size="3" name="PRI_104" start="5" />
-      <BitField size="3" name="PRI_105" start="13" />
-      <BitField size="3" name="PRI_106" start="21" />
-      <BitField size="3" name="PRI_107" start="29" />
-    </Register>
-    <Register start="0xE000E46C" name="NVIC_IPR27" aka="Irq_108_to_111_Priority" description="Interrupt Priority Register 27">
-      <BitField size="3" name="PRI_108" start="5" />
-      <BitField size="3" name="PRI_109" start="13" />
-      <BitField size="3" name="PRI_110" start="21" />
-      <BitField size="3" name="PRI_111" start="29" />
-    </Register>
-    <Register start="0xE000E470" name="NVIC_IPR28" aka="Irq_112_to_115_Priority" description="Interrupt Priority Register 28">
-      <BitField size="3" name="PRI_112" start="5" />
-      <BitField size="3" name="PRI_113" start="13" />
-      <BitField size="3" name="PRI_114" start="21" />
-      <BitField size="3" name="PRI_115" start="29" />
-    </Register>
-    <Register start="0xE000E474" name="NVIC_IPR29" aka="Irq_116_to_119_Priority" description="Interrupt Priority Register 29">
-      <BitField size="3" name="PRI_116" start="5" />
-      <BitField size="3" name="PRI_117" start="13" />
-      <BitField size="3" name="PRI_118" start="21" />
-      <BitField size="3" name="PRI_119" start="29" />
-    </Register>
-    <Register start="0xE000E478" name="NVIC_IPR30" aka="Irq_120_to_123_Priority" description="Interrupt Priority Register 30">
-      <BitField size="3" name="PRI_120" start="5" />
-      <BitField size="3" name="PRI_121" start="13" />
-      <BitField size="3" name="PRI_122" start="21" />
-      <BitField size="3" name="PRI_123" start="29" />
-    </Register>
-    <Register start="0xE000E47C" name="NVIC_IPR31" aka="Irq_124_to_127_Priority" description="Interrupt Priority Register 31">
-      <BitField size="3" name="PRI_124" start="5" />
-      <BitField size="3" name="PRI_125" start="13" />
-      <BitField size="3" name="PRI_126" start="21" />
-      <BitField size="3" name="PRI_127" start="29" />
-    </Register>
-    <Register start="0xE000E480" name="NVIC_IPR32" aka="Irq_128_to_131_Priority" description="Interrupt Priority Register 32">
-      <BitField size="3" name="PRI_128" start="5" />
-      <BitField size="3" name="PRI_129" start="13" />
-      <BitField size="3" name="PRI_130" start="21" />
-      <BitField size="3" name="PRI_131" start="29" />
-    </Register>
-    <Register start="0xE000E484" name="NVIC_IPR33" aka="Irq_132_to_135_Priority" description="Interrupt Priority Register 33">
-      <BitField size="3" name="PRI_132" start="5" />
-      <BitField size="3" name="PRI_133" start="13" />
-      <BitField size="3" name="PRI_134" start="21" />
-      <BitField size="3" name="PRI_135" start="29" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000ED00" name="SCB">
-    <Register start="0xE000ED04" name="ICSR" aka="Interrupt_Control_State" description="Interrupt Control and State Register">
-      <BitField size="1" name="NMIPENDSET" start="31" description="NMI set-pending bit" />
-      <BitField size="1" name="PENDSVSET" start="28" description="PendSV Set-Pending Bit" />
-      <BitField size="1" name="PENDSVCLR" start="27" description="PendSV Clear-Pending Bit" />
-      <BitField size="1" name="PENDSTSET" start="26" description="SysTick Exception Set-Pending Bit" />
-      <BitField size="1" name="PENDSTCLR" start="25" description="SysTick Exception Clear-Pending Bit" />
-      <BitField size="1" name="ISRPREEMPT" start="23" />
-      <BitField size="1" name="ISRPENDING" start="22" description="Interrupt Pending Flag" />
-      <BitField size="9" name="VECTPENDING" start="12" description="Vector Pending" />
-      <BitField size="1" name="RETTOBASE" start="11" description="Return to Base" />
-      <BitField size="9" name="VECTACTIVE" start="0" description="Active Exception Number" />
-    </Register>
-    <Register start="0xE000ED08" name="VTOR" aka="Vector_Table_Offset" description="Vector Table Offset Register">
-      <BitField size="1" name="TBLBASE" start="29" />
-      <BitField size="25" name="TBLOFF" start="7" />
-    </Register>
-    <Register start="0xE000ED0C" name="AIRCR" aka="Application_Interrupt_and_Reset_Control" description="Application Interrupt and Reset Control Register">
-      <BitField size="16" name="VECTKEY" start="16" description="Register Key" />
-      <BitField size="1" name="ENDIANESS" start="15" description="Data Endianness Bit" />
-      <BitField size="3" name="PRIGROUP" start="8" description="Interrupt Priority Grouping Field" />
-      <BitField size="1" name="SYSRESETREQ" start="2" description="System Reset Request" />
-      <BitField size="1" name="VECTCLRACTIVE" start="1" />
-      <BitField size="1" name="VECTRESET" start="0" />
-    </Register>
-    <Register start="0xE000ED10" name="SCR" aka="System_Control" description="System Control Register">
-      <BitField size="1" name="SEVONPEND" start="4" description="Send Event on Pending" />
-      <BitField size="1" name="SLEEPDEEP" start="2" description="Sleep or Deep Sleep" />
-      <BitField size="1" name="SLEEPONEXIT" start="1" description="Sleep on Exit" />
-    </Register>
-    <Register start="0xE000ED14" name="CCR" aka="Configuration_Control" description="Configuration and Control Register">
-      <BitField size="1" name="STKALIGN" start="9" description="Stack Alignment" />
-      <BitField size="1" name="BFHFNMIGN" start="8" description="Bus Fault Hard Fault and NMI Ignore" />
-      <BitField size="1" name="DIV_0_TRP" start="4" description="Divide by Zero Trap Enable" />
-      <BitField size="1" name="UNALIGN_TRP" start="3" description="Unaligned Access Trap Enable" />
-      <BitField size="1" name="USERSETMPEND" start="1" description="User Set Pending Enable" />
-      <BitField size="1" name="NONBASETHRDENA" start="0" description="Non Base Thread Mode Enable" />
-    </Register>
-    <Register start="0xE000ED18" name="SHPR1" aka="System_Handlers_4_7_Priority" description="System Handler Priority Register 1">
-      <BitField size="3" name="PRI_4(MemManage)" start="8-3" description="Priority of system handler 4, MemManage" />
-      <BitField size="3" name="PRI_5(BusFault)" start="16-3" description="Priority of system handler 5, BusFault" />
-      <BitField size="3" name="PRI_6(UsageFault)" start="24-3" description="Priority of system handler 6, UsageFault" />
-      <BitField size="3" name="PRI_7" start="32-3" />
-    </Register>
-    <Register start="0xE000ED1C" name="SHPR2" aka="System_Handlers_8_11_Priority" description="System Handler Priority Register 2">
-      <BitField size="3" name="PRI_8" start="8-3" />
-      <BitField size="3" name="PRI_9" start="16-3" />
-      <BitField size="3" name="PRI_10" start="24-3" />
-      <BitField size="3" name="PRI_11(SVCall)" start="32-3" description="Priority of system handler 11, SVCall" />
-    </Register>
-    <Register start="0xE000ED20" name="SHPR3" aka="System_Handlers_12_15_Priority" description="System Handler Priority Register 3">
-      <BitField size="3" name="PRI_12(DebugMonitor)" start="8-3" />
-      <BitField size="3" name="PRI_13" start="16-3" />
-      <BitField size="3" name="PRI_14(PendSV)" start="24-3" />
-      <BitField size="3" name="PRI_15(SysTick)" start="32-3" />
-    </Register>
-    <Register start="0xE000ED24" name="SHCSR" aka="System_Handler_Control_and_State" description="System Handler Control and State Register">
-      <BitField size="1" name="USGFAULTENA" start="18" description="UsageFault Enable Bit" />
-      <BitField size="1" name="BUSFAULTENA" start="17" description="BusFault Enable Bit" />
-      <BitField size="1" name="MEMFAULTENA" start="16" description="MemManage Enable Bit" />
-      <BitField size="1" name="SVCALLPENDED" start="15" description="SVCall Pending Bit" />
-      <BitField size="1" name="BUSFAULTPENDED" start="14" description="BusFault Exception Pending Bit" />
-      <BitField size="1" name="MEMFAULTPENDED" start="13" description="MemManage Exception Pending Bit" />
-      <BitField size="1" name="USGFAULTPENDED" start="12" description="UsageFault Exception Pending Bit" />
-      <BitField size="1" name="SYSTICKACT" start="11" description="SysTick Exception Active Bit" />
-      <BitField size="1" name="PENDSVACT" start="10" description="PendSV Exception Active Bit" />
-      <BitField size="1" name="MONITORACT" start="8" description="Debug Monitor Active Bit" />
-      <BitField size="1" name="SVCALLACT" start="7" description="SVCall Active Bit" />
-      <BitField size="1" name="USGFAULTACT" start="3" description="UsageFault Exception Active Bit" />
-      <BitField size="1" name="BUSFAULTACT" start="1" description="BusFault Exception Active Bit" />
-      <BitField size="1" name="MEMFAULTACT" start="0" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register start="0xE000ED28" size="1" name="MMFSR" aka="Memory_Manage_Fault_Status">
-      <BitField size="1" name="MMARVALID" start="7" />
-      <BitField size="1" name="MLSPERR" start="5" />
-      <BitField size="1" name="MSTKERR" start="4" />
-      <BitField size="1" name="MUNSTKERR" start="3" />
-      <BitField size="1" name="DACCVIOL" start="1" />
-      <BitField size="1" name="IACCVIOL" start="0" />
-    </Register>
-    <Register start="0xE000ED29" size="1" name="BFSR" aka="Bus_Fault_Status">
-      <BitField size="1" name="BFARVALID" start="7" />
-      <BitField size="1" name="LSPERR" start="5" />
-      <BitField size="1" name="STKERR" start="4" />
-      <BitField size="1" name="UNSTKERR" start="3" />
-      <BitField size="1" name="IMPRECISERR" start="2" />
-      <BitField size="1" name="PRECISERR" start="1" />
-      <BitField size="1" name="IBUSERR" start="0" />
-    </Register>
-    <Register start="0xE000ED2A" size="2" name="UFSR" aka="Usage_Fault_Status">
-      <BitField size="1" name="DIVBYZERO" start="9" />
-      <BitField size="1" name="UNALIGNED" start="8" />
-      <BitField size="1" name="NOCP" start="3" />
-      <BitField size="1" name="INVPC" start="2" />
-      <BitField size="1" name="INVSTATE" start="1" />
-      <BitField size="1" name="UNDEFINSTR" start="0" />
-    </Register>
-    <Register start="0xE000ED2C" name="HFSR" aka="Hard_Fault_Status">
-      <BitField size="1" name="DEBUGEVT" start="31" />
-      <BitField size="1" name="FORCED" start="30" />
-      <BitField size="1" name="VECTTBL" start="1" />
-    </Register>
-    <Register start="0xE000ED30" name="DFSR" aka="Debug_Fault_Status">
-      <BitField size="1" name="EXTERNAL" start="4" />
-      <BitField size="1" name="VCATCH" start="3" />
-      <BitField size="1" name="DWTTRAP" start="2" />
-      <BitField size="1" name="BKPT" start="1" />
-      <BitField size="1" name="HALTED" start="0" />
-    </Register>
-    <Register start="0xE000ED34" name="MMFAR" aka="Memory_Manage_Fault_Address" />
-    <Register start="0xE000ED38" name="BFAR" aka="Bus_Fault_Address" />
-    <Register start="0xE000ED3C" name="AFSR" aka="Auxillary_Fault_Address" />
-    <Register start="0xE000ED88" name="CPACR" description="Coprocessor Access Control Register">
-      <BitField size="2" name="CP0" start="0" />
-      <BitField size="2" name="CP1" start="2" />
-      <BitField size="2" name="CP2" start="4" />
-      <BitField size="2" name="CP3" start="6" />
-      <BitField size="2" name="CP4" start="8" />
-      <BitField size="2" name="CP5" start="10" />
-      <BitField size="2" name="CP6" start="12" />
-      <BitField size="2" name="CP7" start="14" />
-      <BitField size="2" name="CP10" start="20" />
-      <BitField size="2" name="CP11" start="22" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000ED00" name="CPUID">
-    <Register start="0xE000ED00" name="CPUID" aka="CPUID_Base" access="ReadOnly" description="CPUID Base Register">
-      <BitField size="8" name="IMPLEMENTER" start="24" description="Implementer Code" />
-      <BitField size="4" name="VARIANT" start="20" description="Variant Number" />
-      <BitField size="12" name="PARTNO" start="4" description="Part Number" />
-      <BitField size="4" name="REVISION" start="0" description="Revision Number" />
-    </Register>
-    <Register start="0xE000ED40" name="ID_PFR0" aka="PFR0" access="ReadOnly" />
-    <Register start="0xE000ED44" name="ID_PFR1" aka="PFR1" access="ReadOnly" />
-    <Register start="0xE000ED48" name="ID_DFR0" aka="DFR0" access="ReadOnly" />
-    <Register start="0xE000ED4C" name="ID_AFR0" aka="AFR0" access="ReadOnly" />
-    <Register start="0xE000ED50" name="ID_MMFR0" aka="MMFR0" access="ReadOnly" />
-    <Register start="0xE000ED54" name="ID_MMFR1" aka="MMFR1" access="ReadOnly" />
-    <Register start="0xE000ED58" name="ID_MMFR2" aka="MMFR2" access="ReadOnly" />
-    <Register start="0xE000ED5C" name="ID_MMFR3" aka="MMFR3" access="ReadOnly" />
-    <Register start="0xE000ED60" name="ID_ISAR0" aka="ISAR0" access="ReadOnly" />
-    <Register start="0xE000ED64" name="ID_ISAR1" aka="ISAR1" access="ReadOnly" />
-    <Register start="0xE000ED68" name="ID_ISAR2" aka="ISAR2" access="ReadOnly" />
-    <Register start="0xE000ED6C" name="ID_ISAR3" aka="ISAR3" access="ReadOnly" />
-    <Register start="0xE000ED70" name="ID_ISAR4" aka="ISAR4" access="ReadOnly" />
-  </RegisterGroup>
-  <RegisterGroup start="0xE000ED90" name="MPU">
-    <Register start="0xE000ED90" name="MPU_TYPE" aka="MPU_Type" access="ReadOnly" description="MPU Type Register">
-      <BitField size="8" name="IREGION" start="16" description="Number of supported MPU instruction regions" />
-      <BitField size="8" name="DREGION" start="8" description="Number of supported MPU data regions" />
-      <BitField size="8" name="SEPARATE" start="0" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register start="0xE000ED94" name="MPU_CTRL" aka="MPU_Control" description="MPU Control Register">
-      <BitField size="1" name="PRIVDEFENA" start="2" description="Enables privileged software access to the default memory map" />
-      <BitField size="1" name="HFNMIENA" start="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField size="1" name="ENABLE" start="0" description="Enable MPU" />
-    </Register>
-    <Register start="0xE000ED98" name="MPU_RNR" aka="MPU_Region_Number" description="MPU Region Number Register">
-      <BitField size="8" name="REGION" start="0" />
-    </Register>
-    <Register start="0xE000ED9C" name="MPU_RBAR" aka="MPU_Region_Base_Address" description="MPU Region Base Address Register">
-      <BitField size="27" name="ADDR" start="5" description="Region base address field" />
-      <BitField size="1" name="VALID" start="4" description="MPU Region Number valid bit" />
-      <BitField size="4" name="REGION" start="0" description="MPU region field" />
-    </Register>
-    <Register start="0xE000EDA0" name="MPU_RASR" aka="MPU_Attribute_and_Size" description="MPU Region Attribute and Size Register">
-      <BitField size="1" name="XN" start="28" description="Instruction access disable bit" />
-      <BitField size="3" name="AP" start="24" description="Access permission field" />
-      <BitField size="3" name="TEX" start="19" description="Memory access attribute" />
-      <BitField size="1" name="S" start="18" description="Shareable bit" />
-      <BitField size="1" name="C" start="17" description="Memory access attribute" />
-      <BitField size="1" name="B" start="16" description="Memory access attribute" />
-      <BitField size="8" name="SRD" start="8" description="Subregion disable bits" />
-      <BitField size="5" name="SIZE" start="1" description="MPU protection region size" />
-      <BitField size="1" name="ENABLE" start="0" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EDF0" name="CoreDebug">
-    <Register start="0xE000EDF0" name="DHCSR" />
-    <Register start="0xE000EDF4" name="DCRSR" />
-    <Register start="0xE000EDF8" name="DCRDR" />
-    <Register start="0xE000EDFC" name="DEMCR" />
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EF00" name="SCB">
-    <Register start="0xE000EF00" name="STIR" aka="SCB_SW_TRIG" access="WriteOnly" description="Software Trigger Interrupt Register">
-      <BitField size="10" name="INTID" start="0" description="ID of the interrupt to trigger" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EF34" name="SCB_FP">
-    <Register start="0xE000EF34" name="FPCCR" description="Floating-point Context Control Register">
-      <BitField size="1" name="ASPEN" start="31" description="Automatic State Preservation" />
-      <BitField size="1" name="LSPEN" start="30" description="Lazy State Preservation Enabled" />
-      <BitField size="1" name="MONRDY" start="8" description="Monitor Ready" />
-      <BitField size="1" name="BFRDY" start="6" description="BusFault Ready" />
-      <BitField size="1" name="MMRDY" start="5" description="MemManage Ready" />
-      <BitField size="1" name="HFRDY" start="4" description="HardFault Ready" />
-      <BitField size="1" name="THREAD" start="3" description="Thread Mode Allocated Stack Frame" />
-      <BitField size="1" name="USER" start="1" description="User Allocated Stack Frame" />
-      <BitField size="1" name="LSPACT" start="0" description="Lazy State Preservation Active" />
-    </Register>
-    <Register start="0xE000EF38" name="FPCAR" description="Floating-point Context Address Register" />
-    <Register start="0xE000EF3C" name="FPDSCR" description="Floating-point Default Status Control Register">
-      <BitField size="1" name="AHP" start="26" description="Default value for FPSCR.AHP" />
-      <BitField size="1" name="DN" start="25" description="Default value for FPSCR.DN" />
-      <BitField size="1" name="FZ" start="24" description="Default value for FPSCR.FZ" />
-      <BitField size="2" name="RMode" start="22" description="Default value for FPSCR.RMode" />
-    </Register>
-    <Register start="0xE000EF40" name="MVFR0" />
-    <Register start="0xE000EF44" name="MVFR1" />
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EFD0" name="ID_space">
-    <Register start="0xE000EFD0" size="1" name="PID4" access="ReadOnly" />
-    <Register start="0xE000EFD4" size="1" name="PID5" access="ReadOnly" />
-    <Register start="0xE000EFD8" size="1" name="PID6" access="ReadOnly" />
-    <Register start="0xE000EFDC" size="1" name="PID7" access="ReadOnly" />
-    <Register start="0xE000EFE0" size="1" name="PID0" access="ReadOnly" />
-    <Register start="0xE000EFE4" size="1" name="PID1" access="ReadOnly" />
-    <Register start="0xE000EFE8" size="1" name="PID2" access="ReadOnly" />
-    <Register start="0xE000EFEC" size="1" name="PID3" access="ReadOnly" />
-    <Register start="0xE000EFF0" size="1" name="CID0" access="ReadOnly" />
-    <Register start="0xE000EFF4" size="1" name="CID1" access="ReadOnly" />
-    <Register start="0xE000EFF8" size="1" name="CID2" access="ReadOnly" />
-    <Register start="0xE000EFFC" size="1" name="CID3" access="ReadOnly" />
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_Vectors.s b/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_Vectors.s
deleted file mode 100644
index 6369de86..00000000
--- a/examples/device/cdc_msc/ses/samd51/ATSAMD51J19A_Vectors.s
+++ /dev/null
@@ -1,1227 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * STARTUP_FROM_RESET                                                        *
- *                                                                           *
- *   If defined, the program will startup from power-on/reset. If not        *
- *   defined the program will just loop endlessly from power-on/reset.       *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-#ifndef STARTUP_FROM_RESET
-
-  .thumb_func
-  .weak Reset_Wait
-Reset_Wait:
-  b .
-
-#endif
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak PM_Handler
-  .thumb_set PM_Handler,Dummy_Handler
-
-  .weak MCLK_Handler
-  .thumb_set MCLK_Handler,Dummy_Handler
-
-  .weak OSCCTRL_0_Handler
-  .thumb_set OSCCTRL_0_Handler,Dummy_Handler
-
-  .weak OSCCTRL_1_Handler
-  .thumb_set OSCCTRL_1_Handler,Dummy_Handler
-
-  .weak OSCCTRL_2_Handler
-  .thumb_set OSCCTRL_2_Handler,Dummy_Handler
-
-  .weak OSCCTRL_3_Handler
-  .thumb_set OSCCTRL_3_Handler,Dummy_Handler
-
-  .weak OSCCTRL_4_Handler
-  .thumb_set OSCCTRL_4_Handler,Dummy_Handler
-
-  .weak OSC32KCTRL_Handler
-  .thumb_set OSC32KCTRL_Handler,Dummy_Handler
-
-  .weak SUPC_0_Handler
-  .thumb_set SUPC_0_Handler,Dummy_Handler
-
-  .weak SUPC_1_Handler
-  .thumb_set SUPC_1_Handler,Dummy_Handler
-
-  .weak WDT_Handler
-  .thumb_set WDT_Handler,Dummy_Handler
-
-  .weak RTC_Handler
-  .thumb_set RTC_Handler,Dummy_Handler
-
-  .weak EIC_0_Handler
-  .thumb_set EIC_0_Handler,Dummy_Handler
-
-  .weak EIC_1_Handler
-  .thumb_set EIC_1_Handler,Dummy_Handler
-
-  .weak EIC_2_Handler
-  .thumb_set EIC_2_Handler,Dummy_Handler
-
-  .weak EIC_3_Handler
-  .thumb_set EIC_3_Handler,Dummy_Handler
-
-  .weak EIC_4_Handler
-  .thumb_set EIC_4_Handler,Dummy_Handler
-
-  .weak EIC_5_Handler
-  .thumb_set EIC_5_Handler,Dummy_Handler
-
-  .weak EIC_6_Handler
-  .thumb_set EIC_6_Handler,Dummy_Handler
-
-  .weak EIC_7_Handler
-  .thumb_set EIC_7_Handler,Dummy_Handler
-
-  .weak EIC_8_Handler
-  .thumb_set EIC_8_Handler,Dummy_Handler
-
-  .weak EIC_9_Handler
-  .thumb_set EIC_9_Handler,Dummy_Handler
-
-  .weak EIC_10_Handler
-  .thumb_set EIC_10_Handler,Dummy_Handler
-
-  .weak EIC_11_Handler
-  .thumb_set EIC_11_Handler,Dummy_Handler
-
-  .weak EIC_12_Handler
-  .thumb_set EIC_12_Handler,Dummy_Handler
-
-  .weak EIC_13_Handler
-  .thumb_set EIC_13_Handler,Dummy_Handler
-
-  .weak EIC_14_Handler
-  .thumb_set EIC_14_Handler,Dummy_Handler
-
-  .weak EIC_15_Handler
-  .thumb_set EIC_15_Handler,Dummy_Handler
-
-  .weak FREQM_Handler
-  .thumb_set FREQM_Handler,Dummy_Handler
-
-  .weak NVMCTRL_0_Handler
-  .thumb_set NVMCTRL_0_Handler,Dummy_Handler
-
-  .weak NVMCTRL_1_Handler
-  .thumb_set NVMCTRL_1_Handler,Dummy_Handler
-
-  .weak DMAC_0_Handler
-  .thumb_set DMAC_0_Handler,Dummy_Handler
-
-  .weak DMAC_1_Handler
-  .thumb_set DMAC_1_Handler,Dummy_Handler
-
-  .weak DMAC_2_Handler
-  .thumb_set DMAC_2_Handler,Dummy_Handler
-
-  .weak DMAC_3_Handler
-  .thumb_set DMAC_3_Handler,Dummy_Handler
-
-  .weak DMAC_4_Handler
-  .thumb_set DMAC_4_Handler,Dummy_Handler
-
-  .weak EVSYS_0_Handler
-  .thumb_set EVSYS_0_Handler,Dummy_Handler
-
-  .weak EVSYS_1_Handler
-  .thumb_set EVSYS_1_Handler,Dummy_Handler
-
-  .weak EVSYS_2_Handler
-  .thumb_set EVSYS_2_Handler,Dummy_Handler
-
-  .weak EVSYS_3_Handler
-  .thumb_set EVSYS_3_Handler,Dummy_Handler
-
-  .weak EVSYS_4_Handler
-  .thumb_set EVSYS_4_Handler,Dummy_Handler
-
-  .weak PAC_Handler
-  .thumb_set PAC_Handler,Dummy_Handler
-
-  .weak TAL_0_Handler
-  .thumb_set TAL_0_Handler,Dummy_Handler
-
-  .weak TAL_1_Handler
-  .thumb_set TAL_1_Handler,Dummy_Handler
-
-  .weak RAMECC_Handler
-  .thumb_set RAMECC_Handler,Dummy_Handler
-
-  .weak SERCOM0_0_Handler
-  .thumb_set SERCOM0_0_Handler,Dummy_Handler
-
-  .weak SERCOM0_1_Handler
-  .thumb_set SERCOM0_1_Handler,Dummy_Handler
-
-  .weak SERCOM0_2_Handler
-  .thumb_set SERCOM0_2_Handler,Dummy_Handler
-
-  .weak SERCOM0_3_Handler
-  .thumb_set SERCOM0_3_Handler,Dummy_Handler
-
-  .weak SERCOM1_0_Handler
-  .thumb_set SERCOM1_0_Handler,Dummy_Handler
-
-  .weak SERCOM1_1_Handler
-  .thumb_set SERCOM1_1_Handler,Dummy_Handler
-
-  .weak SERCOM1_2_Handler
-  .thumb_set SERCOM1_2_Handler,Dummy_Handler
-
-  .weak SERCOM1_3_Handler
-  .thumb_set SERCOM1_3_Handler,Dummy_Handler
-
-  .weak SERCOM2_0_Handler
-  .thumb_set SERCOM2_0_Handler,Dummy_Handler
-
-  .weak SERCOM2_1_Handler
-  .thumb_set SERCOM2_1_Handler,Dummy_Handler
-
-  .weak SERCOM2_2_Handler
-  .thumb_set SERCOM2_2_Handler,Dummy_Handler
-
-  .weak SERCOM2_3_Handler
-  .thumb_set SERCOM2_3_Handler,Dummy_Handler
-
-  .weak SERCOM3_0_Handler
-  .thumb_set SERCOM3_0_Handler,Dummy_Handler
-
-  .weak SERCOM3_1_Handler
-  .thumb_set SERCOM3_1_Handler,Dummy_Handler
-
-  .weak SERCOM3_2_Handler
-  .thumb_set SERCOM3_2_Handler,Dummy_Handler
-
-  .weak SERCOM3_3_Handler
-  .thumb_set SERCOM3_3_Handler,Dummy_Handler
-
-  .weak SERCOM4_0_Handler
-  .thumb_set SERCOM4_0_Handler,Dummy_Handler
-
-  .weak SERCOM4_1_Handler
-  .thumb_set SERCOM4_1_Handler,Dummy_Handler
-
-  .weak SERCOM4_2_Handler
-  .thumb_set SERCOM4_2_Handler,Dummy_Handler
-
-  .weak SERCOM4_3_Handler
-  .thumb_set SERCOM4_3_Handler,Dummy_Handler
-
-  .weak SERCOM5_0_Handler
-  .thumb_set SERCOM5_0_Handler,Dummy_Handler
-
-  .weak SERCOM5_1_Handler
-  .thumb_set SERCOM5_1_Handler,Dummy_Handler
-
-  .weak SERCOM5_2_Handler
-  .thumb_set SERCOM5_2_Handler,Dummy_Handler
-
-  .weak SERCOM5_3_Handler
-  .thumb_set SERCOM5_3_Handler,Dummy_Handler
-
-  .weak USB_0_Handler
-  .thumb_set USB_0_Handler,Dummy_Handler
-
-  .weak USB_1_Handler
-  .thumb_set USB_1_Handler,Dummy_Handler
-
-  .weak USB_2_Handler
-  .thumb_set USB_2_Handler,Dummy_Handler
-
-  .weak USB_3_Handler
-  .thumb_set USB_3_Handler,Dummy_Handler
-
-  .weak TCC0_0_Handler
-  .thumb_set TCC0_0_Handler,Dummy_Handler
-
-  .weak TCC0_1_Handler
-  .thumb_set TCC0_1_Handler,Dummy_Handler
-
-  .weak TCC0_2_Handler
-  .thumb_set TCC0_2_Handler,Dummy_Handler
-
-  .weak TCC0_3_Handler
-  .thumb_set TCC0_3_Handler,Dummy_Handler
-
-  .weak TCC0_4_Handler
-  .thumb_set TCC0_4_Handler,Dummy_Handler
-
-  .weak TCC0_5_Handler
-  .thumb_set TCC0_5_Handler,Dummy_Handler
-
-  .weak TCC0_6_Handler
-  .thumb_set TCC0_6_Handler,Dummy_Handler
-
-  .weak TCC1_0_Handler
-  .thumb_set TCC1_0_Handler,Dummy_Handler
-
-  .weak TCC1_1_Handler
-  .thumb_set TCC1_1_Handler,Dummy_Handler
-
-  .weak TCC1_2_Handler
-  .thumb_set TCC1_2_Handler,Dummy_Handler
-
-  .weak TCC1_3_Handler
-  .thumb_set TCC1_3_Handler,Dummy_Handler
-
-  .weak TCC1_4_Handler
-  .thumb_set TCC1_4_Handler,Dummy_Handler
-
-  .weak TCC2_0_Handler
-  .thumb_set TCC2_0_Handler,Dummy_Handler
-
-  .weak TCC2_1_Handler
-  .thumb_set TCC2_1_Handler,Dummy_Handler
-
-  .weak TCC2_2_Handler
-  .thumb_set TCC2_2_Handler,Dummy_Handler
-
-  .weak TCC2_3_Handler
-  .thumb_set TCC2_3_Handler,Dummy_Handler
-
-  .weak TCC3_0_Handler
-  .thumb_set TCC3_0_Handler,Dummy_Handler
-
-  .weak TCC3_1_Handler
-  .thumb_set TCC3_1_Handler,Dummy_Handler
-
-  .weak TCC3_2_Handler
-  .thumb_set TCC3_2_Handler,Dummy_Handler
-
-  .weak TCC4_0_Handler
-  .thumb_set TCC4_0_Handler,Dummy_Handler
-
-  .weak TCC4_1_Handler
-  .thumb_set TCC4_1_Handler,Dummy_Handler
-
-  .weak TCC4_2_Handler
-  .thumb_set TCC4_2_Handler,Dummy_Handler
-
-  .weak TC0_Handler
-  .thumb_set TC0_Handler,Dummy_Handler
-
-  .weak TC1_Handler
-  .thumb_set TC1_Handler,Dummy_Handler
-
-  .weak TC2_Handler
-  .thumb_set TC2_Handler,Dummy_Handler
-
-  .weak TC3_Handler
-  .thumb_set TC3_Handler,Dummy_Handler
-
-  .weak TC4_Handler
-  .thumb_set TC4_Handler,Dummy_Handler
-
-  .weak TC5_Handler
-  .thumb_set TC5_Handler,Dummy_Handler
-
-  .weak PDEC_0_Handler
-  .thumb_set PDEC_0_Handler,Dummy_Handler
-
-  .weak PDEC_1_Handler
-  .thumb_set PDEC_1_Handler,Dummy_Handler
-
-  .weak PDEC_2_Handler
-  .thumb_set PDEC_2_Handler,Dummy_Handler
-
-  .weak ADC0_0_Handler
-  .thumb_set ADC0_0_Handler,Dummy_Handler
-
-  .weak ADC0_1_Handler
-  .thumb_set ADC0_1_Handler,Dummy_Handler
-
-  .weak ADC1_0_Handler
-  .thumb_set ADC1_0_Handler,Dummy_Handler
-
-  .weak ADC1_1_Handler
-  .thumb_set ADC1_1_Handler,Dummy_Handler
-
-  .weak AC_Handler
-  .thumb_set AC_Handler,Dummy_Handler
-
-  .weak DAC_0_Handler
-  .thumb_set DAC_0_Handler,Dummy_Handler
-
-  .weak DAC_1_Handler
-  .thumb_set DAC_1_Handler,Dummy_Handler
-
-  .weak DAC_2_Handler
-  .thumb_set DAC_2_Handler,Dummy_Handler
-
-  .weak DAC_3_Handler
-  .thumb_set DAC_3_Handler,Dummy_Handler
-
-  .weak DAC_4_Handler
-  .thumb_set DAC_4_Handler,Dummy_Handler
-
-  .weak I2S_Handler
-  .thumb_set I2S_Handler,Dummy_Handler
-
-  .weak PCC_Handler
-  .thumb_set PCC_Handler,Dummy_Handler
-
-  .weak AES_Handler
-  .thumb_set AES_Handler,Dummy_Handler
-
-  .weak TRNG_Handler
-  .thumb_set TRNG_Handler,Dummy_Handler
-
-  .weak ICM_Handler
-  .thumb_set ICM_Handler,Dummy_Handler
-
-  .weak QSPI_Handler
-  .thumb_set QSPI_Handler,Dummy_Handler
-
-  .weak SDHC0_Handler
-  .thumb_set SDHC0_Handler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak PM_Handler
-PM_Handler:
-  b .
-
-  .thumb_func
-  .weak MCLK_Handler
-MCLK_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_0_Handler
-OSCCTRL_0_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_1_Handler
-OSCCTRL_1_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_2_Handler
-OSCCTRL_2_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_3_Handler
-OSCCTRL_3_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_4_Handler
-OSCCTRL_4_Handler:
-  b .
-
-  .thumb_func
-  .weak OSC32KCTRL_Handler
-OSC32KCTRL_Handler:
-  b .
-
-  .thumb_func
-  .weak SUPC_0_Handler
-SUPC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SUPC_1_Handler
-SUPC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak WDT_Handler
-WDT_Handler:
-  b .
-
-  .thumb_func
-  .weak RTC_Handler
-RTC_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_0_Handler
-EIC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_1_Handler
-EIC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_2_Handler
-EIC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_3_Handler
-EIC_3_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_4_Handler
-EIC_4_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_5_Handler
-EIC_5_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_6_Handler
-EIC_6_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_7_Handler
-EIC_7_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_8_Handler
-EIC_8_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_9_Handler
-EIC_9_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_10_Handler
-EIC_10_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_11_Handler
-EIC_11_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_12_Handler
-EIC_12_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_13_Handler
-EIC_13_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_14_Handler
-EIC_14_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_15_Handler
-EIC_15_Handler:
-  b .
-
-  .thumb_func
-  .weak FREQM_Handler
-FREQM_Handler:
-  b .
-
-  .thumb_func
-  .weak NVMCTRL_0_Handler
-NVMCTRL_0_Handler:
-  b .
-
-  .thumb_func
-  .weak NVMCTRL_1_Handler
-NVMCTRL_1_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_0_Handler
-DMAC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_1_Handler
-DMAC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_2_Handler
-DMAC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_3_Handler
-DMAC_3_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_4_Handler
-DMAC_4_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_0_Handler
-EVSYS_0_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_1_Handler
-EVSYS_1_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_2_Handler
-EVSYS_2_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_3_Handler
-EVSYS_3_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_4_Handler
-EVSYS_4_Handler:
-  b .
-
-  .thumb_func
-  .weak PAC_Handler
-PAC_Handler:
-  b .
-
-  .thumb_func
-  .weak TAL_0_Handler
-TAL_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TAL_1_Handler
-TAL_1_Handler:
-  b .
-
-  .thumb_func
-  .weak RAMECC_Handler
-RAMECC_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_0_Handler
-SERCOM0_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_1_Handler
-SERCOM0_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_2_Handler
-SERCOM0_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_3_Handler
-SERCOM0_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_0_Handler
-SERCOM1_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_1_Handler
-SERCOM1_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_2_Handler
-SERCOM1_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_3_Handler
-SERCOM1_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_0_Handler
-SERCOM2_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_1_Handler
-SERCOM2_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_2_Handler
-SERCOM2_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_3_Handler
-SERCOM2_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_0_Handler
-SERCOM3_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_1_Handler
-SERCOM3_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_2_Handler
-SERCOM3_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_3_Handler
-SERCOM3_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_0_Handler
-SERCOM4_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_1_Handler
-SERCOM4_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_2_Handler
-SERCOM4_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_3_Handler
-SERCOM4_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_0_Handler
-SERCOM5_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_1_Handler
-SERCOM5_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_2_Handler
-SERCOM5_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_3_Handler
-SERCOM5_3_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_0_Handler
-USB_0_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_1_Handler
-USB_1_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_2_Handler
-USB_2_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_3_Handler
-USB_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_0_Handler
-TCC0_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_1_Handler
-TCC0_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_2_Handler
-TCC0_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_3_Handler
-TCC0_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_4_Handler
-TCC0_4_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_5_Handler
-TCC0_5_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_6_Handler
-TCC0_6_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_0_Handler
-TCC1_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_1_Handler
-TCC1_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_2_Handler
-TCC1_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_3_Handler
-TCC1_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_4_Handler
-TCC1_4_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_0_Handler
-TCC2_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_1_Handler
-TCC2_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_2_Handler
-TCC2_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_3_Handler
-TCC2_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC3_0_Handler
-TCC3_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC3_1_Handler
-TCC3_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC3_2_Handler
-TCC3_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC4_0_Handler
-TCC4_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC4_1_Handler
-TCC4_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC4_2_Handler
-TCC4_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TC0_Handler
-TC0_Handler:
-  b .
-
-  .thumb_func
-  .weak TC1_Handler
-TC1_Handler:
-  b .
-
-  .thumb_func
-  .weak TC2_Handler
-TC2_Handler:
-  b .
-
-  .thumb_func
-  .weak TC3_Handler
-TC3_Handler:
-  b .
-
-  .thumb_func
-  .weak TC4_Handler
-TC4_Handler:
-  b .
-
-  .thumb_func
-  .weak TC5_Handler
-TC5_Handler:
-  b .
-
-  .thumb_func
-  .weak PDEC_0_Handler
-PDEC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak PDEC_1_Handler
-PDEC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak PDEC_2_Handler
-PDEC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC0_0_Handler
-ADC0_0_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC0_1_Handler
-ADC0_1_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC1_0_Handler
-ADC1_0_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC1_1_Handler
-ADC1_1_Handler:
-  b .
-
-  .thumb_func
-  .weak AC_Handler
-AC_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_0_Handler
-DAC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_1_Handler
-DAC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_2_Handler
-DAC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_3_Handler
-DAC_3_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_4_Handler
-DAC_4_Handler:
-  b .
-
-  .thumb_func
-  .weak I2S_Handler
-I2S_Handler:
-  b .
-
-  .thumb_func
-  .weak PCC_Handler
-PCC_Handler:
-  b .
-
-  .thumb_func
-  .weak AES_Handler
-AES_Handler:
-  b .
-
-  .thumb_func
-  .weak TRNG_Handler
-TRNG_Handler:
-  b .
-
-  .thumb_func
-  .weak ICM_Handler
-ICM_Handler:
-  b .
-
-  .thumb_func
-  .weak QSPI_Handler
-QSPI_Handler:
-  b .
-
-  .thumb_func
-  .weak SDHC0_Handler
-SDHC0_Handler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-#ifdef STARTUP_FROM_RESET
-  .extern Reset_Handler
-#endif
-
-_vectors:
-  .word __stack_end__
-#ifdef STARTUP_FROM_RESET
-  .word Reset_Handler
-#else
-  .word Reset_Wait
-#endif
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word PM_Handler
-  .word MCLK_Handler
-  .word OSCCTRL_0_Handler
-  .word OSCCTRL_1_Handler
-  .word OSCCTRL_2_Handler
-  .word OSCCTRL_3_Handler
-  .word OSCCTRL_4_Handler
-  .word OSC32KCTRL_Handler
-  .word SUPC_0_Handler
-  .word SUPC_1_Handler
-  .word WDT_Handler
-  .word RTC_Handler
-  .word EIC_0_Handler
-  .word EIC_1_Handler
-  .word EIC_2_Handler
-  .word EIC_3_Handler
-  .word EIC_4_Handler
-  .word EIC_5_Handler
-  .word EIC_6_Handler
-  .word EIC_7_Handler
-  .word EIC_8_Handler
-  .word EIC_9_Handler
-  .word EIC_10_Handler
-  .word EIC_11_Handler
-  .word EIC_12_Handler
-  .word EIC_13_Handler
-  .word EIC_14_Handler
-  .word EIC_15_Handler
-  .word FREQM_Handler
-  .word NVMCTRL_0_Handler
-  .word NVMCTRL_1_Handler
-  .word DMAC_0_Handler
-  .word DMAC_1_Handler
-  .word DMAC_2_Handler
-  .word DMAC_3_Handler
-  .word DMAC_4_Handler
-  .word EVSYS_0_Handler
-  .word EVSYS_1_Handler
-  .word EVSYS_2_Handler
-  .word EVSYS_3_Handler
-  .word EVSYS_4_Handler
-  .word PAC_Handler
-  .word TAL_0_Handler
-  .word TAL_1_Handler
-  .word Dummy_Handler /* Reserved */
-  .word RAMECC_Handler
-  .word SERCOM0_0_Handler
-  .word SERCOM0_1_Handler
-  .word SERCOM0_2_Handler
-  .word SERCOM0_3_Handler
-  .word SERCOM1_0_Handler
-  .word SERCOM1_1_Handler
-  .word SERCOM1_2_Handler
-  .word SERCOM1_3_Handler
-  .word SERCOM2_0_Handler
-  .word SERCOM2_1_Handler
-  .word SERCOM2_2_Handler
-  .word SERCOM2_3_Handler
-  .word SERCOM3_0_Handler
-  .word SERCOM3_1_Handler
-  .word SERCOM3_2_Handler
-  .word SERCOM3_3_Handler
-  .word SERCOM4_0_Handler
-  .word SERCOM4_1_Handler
-  .word SERCOM4_2_Handler
-  .word SERCOM4_3_Handler
-  .word SERCOM5_0_Handler
-  .word SERCOM5_1_Handler
-  .word SERCOM5_2_Handler
-  .word SERCOM5_3_Handler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word USB_0_Handler
-  .word USB_1_Handler
-  .word USB_2_Handler
-  .word USB_3_Handler
-  .word Dummy_Handler /* Reserved */
-  .word TCC0_0_Handler
-  .word TCC0_1_Handler
-  .word TCC0_2_Handler
-  .word TCC0_3_Handler
-  .word TCC0_4_Handler
-  .word TCC0_5_Handler
-  .word TCC0_6_Handler
-  .word TCC1_0_Handler
-  .word TCC1_1_Handler
-  .word TCC1_2_Handler
-  .word TCC1_3_Handler
-  .word TCC1_4_Handler
-  .word TCC2_0_Handler
-  .word TCC2_1_Handler
-  .word TCC2_2_Handler
-  .word TCC2_3_Handler
-  .word TCC3_0_Handler
-  .word TCC3_1_Handler
-  .word TCC3_2_Handler
-  .word TCC4_0_Handler
-  .word TCC4_1_Handler
-  .word TCC4_2_Handler
-  .word TC0_Handler
-  .word TC1_Handler
-  .word TC2_Handler
-  .word TC3_Handler
-  .word TC4_Handler
-  .word TC5_Handler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word PDEC_0_Handler
-  .word PDEC_1_Handler
-  .word PDEC_2_Handler
-  .word ADC0_0_Handler
-  .word ADC0_1_Handler
-  .word ADC1_0_Handler
-  .word ADC1_1_Handler
-  .word AC_Handler
-  .word DAC_0_Handler
-  .word DAC_1_Handler
-  .word DAC_2_Handler
-  .word DAC_3_Handler
-  .word DAC_4_Handler
-  .word I2S_Handler
-  .word PCC_Handler
-  .word AES_Handler
-  .word TRNG_Handler
-  .word ICM_Handler
-  .word Dummy_Handler /* Reserved */
-  .word QSPI_Handler
-  .word SDHC0_Handler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/samd51/SAMD51_Startup.s b/examples/device/cdc_msc/ses/samd51/SAMD51_Startup.s
deleted file mode 100644
index 03bf54de..00000000
--- a/examples/device/cdc_msc/ses/samd51/SAMD51_Startup.s
+++ /dev/null
@@ -1,128 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/samd51/SAMD51_Target.js b/examples/device/cdc_msc/ses/samd51/SAMD51_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/samd51/SAMD51_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/samd51/flash_placement.xml b/examples/device/cdc_msc/ses/samd51/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/samd51/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/samd51/samd51.emProject b/examples/device/cdc_msc/ses/samd51/samd51.emProject
deleted file mode 100644
index d4049e83..00000000
--- a/examples/device/cdc_msc/ses/samd51/samd51.emProject
+++ /dev/null
@@ -1,112 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="samd51" target="8" version="2">
-  <project Name="samd51">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="nRF52840_xxAA"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 20000000,00030000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="ATSAMD51J19"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="__SAMD51_FAMILY;__SAMD51J19A__;ARM_MATH_CM4;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;CFG_TUSB_MCU=OPT_MCU_SAMD51"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk"
-      debug_register_definition_file="ATSAMD51J19A_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
-      macros="DeviceFamily=SAMD51;Target=ATSAMD51J19A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd51"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/SAMD51_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="metro_m4_express">
-          <file file_name="../../../../../hw/bsp/metro_m4_express/metro_m4_express.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="microchip">
-          <folder Name="samd">
-            <folder Name="asf4">
-              <folder Name="samd51">
-                <folder Name="gcc">
-                  <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c" />
-                </folder>
-                <folder Name="hpl">
-                  <folder Name="osc32kctrl">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" />
-                  </folder>
-                  <folder Name="oscctrl">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c" />
-                  </folder>
-                  <folder Name="mclk">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c" />
-                  </folder>
-                  <folder Name="gclk">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c" />
-                  </folder>
-                </folder>
-                <folder Name="hal">
-                  <folder Name="src">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hal/src/hal_atomic.c" />
-                  </folder>
-                </folder>
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="ATSAMD51J19A_MemoryMap.xml" />
-      <file file_name="ATSAMD51J19A_Registers.xml" />
-      <file file_name="ATSAMD51J19A_Vectors.s" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="SAMD51_Startup.s" />
-      <file file_name="SAMD51_Target.js" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <configuration
-      Name="Metro M4 Express"
-      c_preprocessor_definitions="BOARD_METRO_M4_EXPRESS" />
-  </project>
-  <configuration Name="Metro M4 Express" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/samd51/thumb_crt0.s b/examples/device/cdc_msc/ses/samd51/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/samd51/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc/ses/stm32f4/STM32F407VG_MemoryMap.xml b/examples/device/cdc_msc/ses/stm32f4/STM32F407VG_MemoryMap.xml
deleted file mode 100644
index 54f86de7..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/STM32F407VG_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="STM32F407VG">
-  <MemorySegment name="FLASH" start="0x08000000" size="0x00100000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00010000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00020000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc/ses/stm32f4/STM32F40x_Registers.xml b/examples/device/cdc_msc/ses/stm32f4/STM32F40x_Registers.xml
deleted file mode 100644
index a11cf730..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/STM32F40x_Registers.xml
+++ /dev/null
@@ -1,13923 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="STM32F40x" description="STM32F40x">
-  <RegisterGroup name="RNG" start="0x50060800" description="Random number generator">
-    <Register start="+0x0" size="0" name="CR" access="Read/Write" description="control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="IE" description="Interrupt enable" />
-      <BitField start="2" size="1" name="RNGEN" description="Random number generator&#xa;              enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="SEIS" description="Seed error interrupt&#xa;              status" />
-      <BitField start="5" size="1" name="CEIS" description="Clock error interrupt&#xa;              status" />
-      <BitField start="2" size="1" name="SECS" description="Seed error current status" />
-      <BitField start="1" size="1" name="CECS" description="Clock error current status" />
-      <BitField start="0" size="1" name="DRDY" description="Data ready" />
-    </Register>
-    <Register start="+0x8" size="0" name="DR" access="ReadOnly" description="data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RNDATA" description="Random data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DCMI" start="0x50050000" description="Digital camera interface">
-    <Register start="+0x0" size="0" name="CR" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="ENABLE" description="DCMI enable" />
-      <BitField start="10" size="2" name="EDM" description="Extended data mode" />
-      <BitField start="8" size="2" name="FCRC" description="Frame capture rate control" />
-      <BitField start="7" size="1" name="VSPOL" description="Vertical synchronization&#xa;              polarity" />
-      <BitField start="6" size="1" name="HSPOL" description="Horizontal synchronization&#xa;              polarity" />
-      <BitField start="5" size="1" name="PCKPOL" description="Pixel clock polarity" />
-      <BitField start="4" size="1" name="ESS" description="Embedded synchronization&#xa;              select" />
-      <BitField start="3" size="1" name="JPEG" description="JPEG format" />
-      <BitField start="2" size="1" name="CROP" description="Crop feature" />
-      <BitField start="1" size="1" name="CM" description="Capture mode" />
-      <BitField start="0" size="1" name="CAPTURE" description="Capture enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="SR" access="ReadOnly" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="FNE" description="FIFO not empty" />
-      <BitField start="1" size="1" name="VSYNC" description="VSYNC" />
-      <BitField start="0" size="1" name="HSYNC" description="HSYNC" />
-    </Register>
-    <Register start="+0x8" size="0" name="RIS" access="ReadOnly" description="raw interrupt status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="1" name="LINE_RIS" description="Line raw interrupt status" />
-      <BitField start="3" size="1" name="VSYNC_RIS" description="VSYNC raw interrupt status" />
-      <BitField start="2" size="1" name="ERR_RIS" description="Synchronization error raw interrupt&#xa;              status" />
-      <BitField start="1" size="1" name="OVR_RIS" description="Overrun raw interrupt&#xa;              status" />
-      <BitField start="0" size="1" name="FRAME_RIS" description="Capture complete raw interrupt&#xa;              status" />
-    </Register>
-    <Register start="+0xC" size="0" name="IER" access="Read/Write" description="interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="1" name="LINE_IE" description="Line interrupt enable" />
-      <BitField start="3" size="1" name="VSYNC_IE" description="VSYNC interrupt enable" />
-      <BitField start="2" size="1" name="ERR_IE" description="Synchronization error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="OVR_IE" description="Overrun interrupt enable" />
-      <BitField start="0" size="1" name="FRAME_IE" description="Capture complete interrupt&#xa;              enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="MIS" access="ReadOnly" description="masked interrupt status&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="1" name="LINE_MIS" description="Line masked interrupt&#xa;              status" />
-      <BitField start="3" size="1" name="VSYNC_MIS" description="VSYNC masked interrupt&#xa;              status" />
-      <BitField start="2" size="1" name="ERR_MIS" description="Synchronization error masked interrupt&#xa;              status" />
-      <BitField start="1" size="1" name="OVR_MIS" description="Overrun masked interrupt&#xa;              status" />
-      <BitField start="0" size="1" name="FRAME_MIS" description="Capture complete masked interrupt&#xa;              status" />
-    </Register>
-    <Register start="+0x14" size="0" name="ICR" access="WriteOnly" description="interrupt clear register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="1" name="LINE_ISC" description="line interrupt status&#xa;              clear" />
-      <BitField start="3" size="1" name="VSYNC_ISC" description="Vertical synch interrupt status&#xa;              clear" />
-      <BitField start="2" size="1" name="ERR_ISC" description="Synchronization error interrupt status&#xa;              clear" />
-      <BitField start="1" size="1" name="OVR_ISC" description="Overrun interrupt status&#xa;              clear" />
-      <BitField start="0" size="1" name="FRAME_ISC" description="Capture complete interrupt status&#xa;              clear" />
-    </Register>
-    <Register start="+0x18" size="0" name="ESCR" access="Read/Write" description="embedded synchronization code&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="FEC" description="Frame end delimiter code" />
-      <BitField start="16" size="8" name="LEC" description="Line end delimiter code" />
-      <BitField start="8" size="8" name="LSC" description="Line start delimiter code" />
-      <BitField start="0" size="8" name="FSC" description="Frame start delimiter code" />
-    </Register>
-    <Register start="+0x1C" size="0" name="ESUR" access="Read/Write" description="embedded synchronization unmask&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="FEU" description="Frame end delimiter unmask" />
-      <BitField start="16" size="8" name="LEU" description="Line end delimiter unmask" />
-      <BitField start="8" size="8" name="LSU" description="Line start delimiter&#xa;              unmask" />
-      <BitField start="0" size="8" name="FSU" description="Frame start delimiter&#xa;              unmask" />
-    </Register>
-    <Register start="+0x20" size="0" name="CWSTRT" access="Read/Write" description="crop window start" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="13" name="VST" description="Vertical start line count" />
-      <BitField start="0" size="14" name="HOFFCNT" description="Horizontal offset count" />
-    </Register>
-    <Register start="+0x24" size="0" name="CWSIZE" access="Read/Write" description="crop window size" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="14" name="VLINE" description="Vertical line count" />
-      <BitField start="0" size="14" name="CAPCNT" description="Capture count" />
-    </Register>
-    <Register start="+0x28" size="0" name="DR" access="ReadOnly" description="data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="Byte3" description="Data byte 3" />
-      <BitField start="16" size="8" name="Byte2" description="Data byte 2" />
-      <BitField start="8" size="8" name="Byte1" description="Data byte 1" />
-      <BitField start="0" size="8" name="Byte0" description="Data byte 0" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FSMC" start="0xA0000000" description="Flexible static memory controller">
-    <Register start="+0x0" size="0" name="BCR1" access="Read/Write" description="SRAM/NOR-Flash chip-select control register&#xa;          1" reset_value="0x000030D0" reset_mask="0xFFFFFFFF">
-      <BitField start="19" size="1" name="CBURSTRW" description="CBURSTRW" />
-      <BitField start="15" size="1" name="ASYNCWAIT" description="ASYNCWAIT" />
-      <BitField start="14" size="1" name="EXTMOD" description="EXTMOD" />
-      <BitField start="13" size="1" name="WAITEN" description="WAITEN" />
-      <BitField start="12" size="1" name="WREN" description="WREN" />
-      <BitField start="11" size="1" name="WAITCFG" description="WAITCFG" />
-      <BitField start="9" size="1" name="WAITPOL" description="WAITPOL" />
-      <BitField start="8" size="1" name="BURSTEN" description="BURSTEN" />
-      <BitField start="6" size="1" name="FACCEN" description="FACCEN" />
-      <BitField start="4" size="2" name="MWID" description="MWID" />
-      <BitField start="2" size="2" name="MTYP" description="MTYP" />
-      <BitField start="1" size="1" name="MUXEN" description="MUXEN" />
-      <BitField start="0" size="1" name="MBKEN" description="MBKEN" />
-    </Register>
-    <Register start="+0x4" size="0" name="BTR1" access="Read/Write" description="SRAM/NOR-Flash chip-select timing register&#xa;          1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="16" size="4" name="BUSTURN" description="BUSTURN" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x8" size="0" name="BCR2" access="Read/Write" description="SRAM/NOR-Flash chip-select control register&#xa;          2" reset_value="0x000030D0" reset_mask="0xFFFFFFFF">
-      <BitField start="19" size="1" name="CBURSTRW" description="CBURSTRW" />
-      <BitField start="15" size="1" name="ASYNCWAIT" description="ASYNCWAIT" />
-      <BitField start="14" size="1" name="EXTMOD" description="EXTMOD" />
-      <BitField start="13" size="1" name="WAITEN" description="WAITEN" />
-      <BitField start="12" size="1" name="WREN" description="WREN" />
-      <BitField start="11" size="1" name="WAITCFG" description="WAITCFG" />
-      <BitField start="10" size="1" name="WRAPMOD" description="WRAPMOD" />
-      <BitField start="9" size="1" name="WAITPOL" description="WAITPOL" />
-      <BitField start="8" size="1" name="BURSTEN" description="BURSTEN" />
-      <BitField start="6" size="1" name="FACCEN" description="FACCEN" />
-      <BitField start="4" size="2" name="MWID" description="MWID" />
-      <BitField start="2" size="2" name="MTYP" description="MTYP" />
-      <BitField start="1" size="1" name="MUXEN" description="MUXEN" />
-      <BitField start="0" size="1" name="MBKEN" description="MBKEN" />
-    </Register>
-    <Register start="+0xC" size="0" name="BTR2" access="Read/Write" description="SRAM/NOR-Flash chip-select timing register&#xa;          2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="16" size="4" name="BUSTURN" description="BUSTURN" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x10" size="0" name="BCR3" access="Read/Write" description="SRAM/NOR-Flash chip-select control register&#xa;          3" reset_value="0x000030D0" reset_mask="0xFFFFFFFF">
-      <BitField start="19" size="1" name="CBURSTRW" description="CBURSTRW" />
-      <BitField start="15" size="1" name="ASYNCWAIT" description="ASYNCWAIT" />
-      <BitField start="14" size="1" name="EXTMOD" description="EXTMOD" />
-      <BitField start="13" size="1" name="WAITEN" description="WAITEN" />
-      <BitField start="12" size="1" name="WREN" description="WREN" />
-      <BitField start="11" size="1" name="WAITCFG" description="WAITCFG" />
-      <BitField start="10" size="1" name="WRAPMOD" description="WRAPMOD" />
-      <BitField start="9" size="1" name="WAITPOL" description="WAITPOL" />
-      <BitField start="8" size="1" name="BURSTEN" description="BURSTEN" />
-      <BitField start="6" size="1" name="FACCEN" description="FACCEN" />
-      <BitField start="4" size="2" name="MWID" description="MWID" />
-      <BitField start="2" size="2" name="MTYP" description="MTYP" />
-      <BitField start="1" size="1" name="MUXEN" description="MUXEN" />
-      <BitField start="0" size="1" name="MBKEN" description="MBKEN" />
-    </Register>
-    <Register start="+0x14" size="0" name="BTR3" access="Read/Write" description="SRAM/NOR-Flash chip-select timing register&#xa;          3" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="16" size="4" name="BUSTURN" description="BUSTURN" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x18" size="0" name="BCR4" access="Read/Write" description="SRAM/NOR-Flash chip-select control register&#xa;          4" reset_value="0x000030D0" reset_mask="0xFFFFFFFF">
-      <BitField start="19" size="1" name="CBURSTRW" description="CBURSTRW" />
-      <BitField start="15" size="1" name="ASYNCWAIT" description="ASYNCWAIT" />
-      <BitField start="14" size="1" name="EXTMOD" description="EXTMOD" />
-      <BitField start="13" size="1" name="WAITEN" description="WAITEN" />
-      <BitField start="12" size="1" name="WREN" description="WREN" />
-      <BitField start="11" size="1" name="WAITCFG" description="WAITCFG" />
-      <BitField start="10" size="1" name="WRAPMOD" description="WRAPMOD" />
-      <BitField start="9" size="1" name="WAITPOL" description="WAITPOL" />
-      <BitField start="8" size="1" name="BURSTEN" description="BURSTEN" />
-      <BitField start="6" size="1" name="FACCEN" description="FACCEN" />
-      <BitField start="4" size="2" name="MWID" description="MWID" />
-      <BitField start="2" size="2" name="MTYP" description="MTYP" />
-      <BitField start="1" size="1" name="MUXEN" description="MUXEN" />
-      <BitField start="0" size="1" name="MBKEN" description="MBKEN" />
-    </Register>
-    <Register start="+0x1C" size="0" name="BTR4" access="Read/Write" description="SRAM/NOR-Flash chip-select timing register&#xa;          4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="16" size="4" name="BUSTURN" description="BUSTURN" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x60" size="0" name="PCR2" access="Read/Write" description="PC Card/NAND Flash control register&#xa;          2" reset_value="0x00000018" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="3" name="ECCPS" description="ECCPS" />
-      <BitField start="13" size="4" name="TAR" description="TAR" />
-      <BitField start="9" size="4" name="TCLR" description="TCLR" />
-      <BitField start="6" size="1" name="ECCEN" description="ECCEN" />
-      <BitField start="4" size="2" name="PWID" description="PWID" />
-      <BitField start="3" size="1" name="PTYP" description="PTYP" />
-      <BitField start="2" size="1" name="PBKEN" description="PBKEN" />
-      <BitField start="1" size="1" name="PWAITEN" description="PWAITEN" />
-    </Register>
-    <Register start="+0x64" size="0" name="SR2" access="Read/Write" description="FIFO status and interrupt register&#xa;          2" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="FEMPT" description="FEMPT" />
-      <BitField start="5" size="1" name="IFEN" description="IFEN" />
-      <BitField start="4" size="1" name="ILEN" description="ILEN" />
-      <BitField start="3" size="1" name="IREN" description="IREN" />
-      <BitField start="2" size="1" name="IFS" description="IFS" />
-      <BitField start="1" size="1" name="ILS" description="ILS" />
-      <BitField start="0" size="1" name="IRS" description="IRS" />
-    </Register>
-    <Register start="+0x68" size="0" name="PMEM2" access="Read/Write" description="Common memory space timing register&#xa;          2" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="MEMHIZx" description="MEMHIZx" />
-      <BitField start="16" size="8" name="MEMHOLDx" description="MEMHOLDx" />
-      <BitField start="8" size="8" name="MEMWAITx" description="MEMWAITx" />
-      <BitField start="0" size="8" name="MEMSETx" description="MEMSETx" />
-    </Register>
-    <Register start="+0x6C" size="0" name="PATT2" access="Read/Write" description="Attribute memory space timing register&#xa;          2" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="ATTHIZx" description="ATTHIZx" />
-      <BitField start="16" size="8" name="ATTHOLDx" description="ATTHOLDx" />
-      <BitField start="8" size="8" name="ATTWAITx" description="ATTWAITx" />
-      <BitField start="0" size="8" name="ATTSETx" description="ATTSETx" />
-    </Register>
-    <Register start="+0x74" size="0" name="ECCR2" access="ReadOnly" description="ECC result register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ECCx" description="ECCx" />
-    </Register>
-    <Register start="+0x80" size="0" name="PCR3" access="Read/Write" description="PC Card/NAND Flash control register&#xa;          3" reset_value="0x00000018" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="3" name="ECCPS" description="ECCPS" />
-      <BitField start="13" size="4" name="TAR" description="TAR" />
-      <BitField start="9" size="4" name="TCLR" description="TCLR" />
-      <BitField start="6" size="1" name="ECCEN" description="ECCEN" />
-      <BitField start="4" size="2" name="PWID" description="PWID" />
-      <BitField start="3" size="1" name="PTYP" description="PTYP" />
-      <BitField start="2" size="1" name="PBKEN" description="PBKEN" />
-      <BitField start="1" size="1" name="PWAITEN" description="PWAITEN" />
-    </Register>
-    <Register start="+0x84" size="0" name="SR3" access="Read/Write" description="FIFO status and interrupt register&#xa;          3" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="FEMPT" description="FEMPT" />
-      <BitField start="5" size="1" name="IFEN" description="IFEN" />
-      <BitField start="4" size="1" name="ILEN" description="ILEN" />
-      <BitField start="3" size="1" name="IREN" description="IREN" />
-      <BitField start="2" size="1" name="IFS" description="IFS" />
-      <BitField start="1" size="1" name="ILS" description="ILS" />
-      <BitField start="0" size="1" name="IRS" description="IRS" />
-    </Register>
-    <Register start="+0x88" size="0" name="PMEM3" access="Read/Write" description="Common memory space timing register&#xa;          3" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="MEMHIZx" description="MEMHIZx" />
-      <BitField start="16" size="8" name="MEMHOLDx" description="MEMHOLDx" />
-      <BitField start="8" size="8" name="MEMWAITx" description="MEMWAITx" />
-      <BitField start="0" size="8" name="MEMSETx" description="MEMSETx" />
-    </Register>
-    <Register start="+0x8C" size="0" name="PATT3" access="Read/Write" description="Attribute memory space timing register&#xa;          3" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="ATTHIZx" description="ATTHIZx" />
-      <BitField start="16" size="8" name="ATTHOLDx" description="ATTHOLDx" />
-      <BitField start="8" size="8" name="ATTWAITx" description="ATTWAITx" />
-      <BitField start="0" size="8" name="ATTSETx" description="ATTSETx" />
-    </Register>
-    <Register start="+0x94" size="0" name="ECCR3" access="ReadOnly" description="ECC result register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ECCx" description="ECCx" />
-    </Register>
-    <Register start="+0xA0" size="0" name="PCR4" access="Read/Write" description="PC Card/NAND Flash control register&#xa;          4" reset_value="0x00000018" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="3" name="ECCPS" description="ECCPS" />
-      <BitField start="13" size="4" name="TAR" description="TAR" />
-      <BitField start="9" size="4" name="TCLR" description="TCLR" />
-      <BitField start="6" size="1" name="ECCEN" description="ECCEN" />
-      <BitField start="4" size="2" name="PWID" description="PWID" />
-      <BitField start="3" size="1" name="PTYP" description="PTYP" />
-      <BitField start="2" size="1" name="PBKEN" description="PBKEN" />
-      <BitField start="1" size="1" name="PWAITEN" description="PWAITEN" />
-    </Register>
-    <Register start="+0xA4" size="0" name="SR4" access="Read/Write" description="FIFO status and interrupt register&#xa;          4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="FEMPT" description="FEMPT" />
-      <BitField start="5" size="1" name="IFEN" description="IFEN" />
-      <BitField start="4" size="1" name="ILEN" description="ILEN" />
-      <BitField start="3" size="1" name="IREN" description="IREN" />
-      <BitField start="2" size="1" name="IFS" description="IFS" />
-      <BitField start="1" size="1" name="ILS" description="ILS" />
-      <BitField start="0" size="1" name="IRS" description="IRS" />
-    </Register>
-    <Register start="+0xA8" size="0" name="PMEM4" access="Read/Write" description="Common memory space timing register&#xa;          4" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="MEMHIZx" description="MEMHIZx" />
-      <BitField start="16" size="8" name="MEMHOLDx" description="MEMHOLDx" />
-      <BitField start="8" size="8" name="MEMWAITx" description="MEMWAITx" />
-      <BitField start="0" size="8" name="MEMSETx" description="MEMSETx" />
-    </Register>
-    <Register start="+0xAC" size="0" name="PATT4" access="Read/Write" description="Attribute memory space timing register&#xa;          4" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="ATTHIZx" description="ATTHIZx" />
-      <BitField start="16" size="8" name="ATTHOLDx" description="ATTHOLDx" />
-      <BitField start="8" size="8" name="ATTWAITx" description="ATTWAITx" />
-      <BitField start="0" size="8" name="ATTSETx" description="ATTSETx" />
-    </Register>
-    <Register start="+0xB0" size="0" name="PIO4" access="Read/Write" description="I/O space timing register 4" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="IOHIZx" description="IOHIZx" />
-      <BitField start="16" size="8" name="IOHOLDx" description="IOHOLDx" />
-      <BitField start="8" size="8" name="IOWAITx" description="IOWAITx" />
-      <BitField start="0" size="8" name="IOSETx" description="IOSETx" />
-    </Register>
-    <Register start="+0x104" size="0" name="BWTR1" access="Read/Write" description="SRAM/NOR-Flash write timing registers&#xa;          1" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x10C" size="0" name="BWTR2" access="Read/Write" description="SRAM/NOR-Flash write timing registers&#xa;          2" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x114" size="0" name="BWTR3" access="Read/Write" description="SRAM/NOR-Flash write timing registers&#xa;          3" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-    <Register start="+0x11C" size="0" name="BWTR4" access="Read/Write" description="SRAM/NOR-Flash write timing registers&#xa;          4" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="2" name="ACCMOD" description="ACCMOD" />
-      <BitField start="24" size="4" name="DATLAT" description="DATLAT" />
-      <BitField start="20" size="4" name="CLKDIV" description="CLKDIV" />
-      <BitField start="8" size="8" name="DATAST" description="DATAST" />
-      <BitField start="4" size="4" name="ADDHLD" description="ADDHLD" />
-      <BitField start="0" size="4" name="ADDSET" description="ADDSET" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DBG" start="0xE0042000" description="Debug support">
-    <Register start="+0x0" size="0" name="DBGMCU_IDCODE" access="ReadOnly" description="IDCODE" reset_value="0x10006411" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DEV_ID" description="DEV_ID" />
-      <BitField start="16" size="16" name="REV_ID" description="REV_ID" />
-    </Register>
-    <Register start="+0x4" size="0" name="DBGMCU_CR" access="Read/Write" description="Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBG_SLEEP" description="DBG_SLEEP" />
-      <BitField start="1" size="1" name="DBG_STOP" description="DBG_STOP" />
-      <BitField start="2" size="1" name="DBG_STANDBY" description="DBG_STANDBY" />
-      <BitField start="5" size="1" name="TRACE_IOEN" description="TRACE_IOEN" />
-      <BitField start="6" size="2" name="TRACE_MODE" description="TRACE_MODE" />
-      <BitField start="16" size="1" name="DBG_I2C2_SMBUS_TIMEOUT" description="DBG_I2C2_SMBUS_TIMEOUT" />
-      <BitField start="17" size="1" name="DBG_TIM8_STOP" description="DBG_TIM8_STOP" />
-      <BitField start="18" size="1" name="DBG_TIM5_STOP" description="DBG_TIM5_STOP" />
-      <BitField start="19" size="1" name="DBG_TIM6_STOP" description="DBG_TIM6_STOP" />
-      <BitField start="20" size="1" name="DBG_TIM7_STOP" description="DBG_TIM7_STOP" />
-    </Register>
-    <Register start="+0x8" size="0" name="DBGMCU_APB1_FZ" access="Read/Write" description="Debug MCU APB1 Freeze registe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBG_TIM2_STOP" description="DBG_TIM2_STOP" />
-      <BitField start="1" size="1" name="DBG_TIM3_STOP" description="DBG_TIM3 _STOP" />
-      <BitField start="2" size="1" name="DBG_TIM4_STOP" description="DBG_TIM4_STOP" />
-      <BitField start="3" size="1" name="DBG_TIM5_STOP" description="DBG_TIM5_STOP" />
-      <BitField start="4" size="1" name="DBG_TIM6_STOP" description="DBG_TIM6_STOP" />
-      <BitField start="5" size="1" name="DBG_TIM7_STOP" description="DBG_TIM7_STOP" />
-      <BitField start="6" size="1" name="DBG_TIM12_STOP" description="DBG_TIM12_STOP" />
-      <BitField start="7" size="1" name="DBG_TIM13_STOP" description="DBG_TIM13_STOP" />
-      <BitField start="8" size="1" name="DBG_TIM14_STOP" description="DBG_TIM14_STOP" />
-      <BitField start="11" size="1" name="DBG_WWDG_STOP" description="DBG_WWDG_STOP" />
-      <BitField start="12" size="1" name="DBG_IWDEG_STOP" description="DBG_IWDEG_STOP" />
-      <BitField start="21" size="1" name="DBG_J2C1_SMBUS_TIMEOUT" description="DBG_J2C1_SMBUS_TIMEOUT" />
-      <BitField start="22" size="1" name="DBG_J2C2_SMBUS_TIMEOUT" description="DBG_J2C2_SMBUS_TIMEOUT" />
-      <BitField start="23" size="1" name="DBG_J2C3SMBUS_TIMEOUT" description="DBG_J2C3SMBUS_TIMEOUT" />
-      <BitField start="25" size="1" name="DBG_CAN1_STOP" description="DBG_CAN1_STOP" />
-      <BitField start="26" size="1" name="DBG_CAN2_STOP" description="DBG_CAN2_STOP" />
-    </Register>
-    <Register start="+0xC" size="0" name="DBGMCU_APB2_FZ" access="Read/Write" description="Debug MCU APB2 Freeze registe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBG_TIM1_STOP" description="TIM1 counter stopped when core is&#xa;              halted" />
-      <BitField start="1" size="1" name="DBG_TIM8_STOP" description="TIM8 counter stopped when core is&#xa;              halted" />
-      <BitField start="16" size="1" name="DBG_TIM9_STOP" description="TIM9 counter stopped when core is&#xa;              halted" />
-      <BitField start="17" size="1" name="DBG_TIM10_STOP" description="TIM10 counter stopped when core is&#xa;              halted" />
-      <BitField start="18" size="1" name="DBG_TIM11_STOP" description="TIM11 counter stopped when core is&#xa;              halted" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMA2" start="0x40026400" description="DMA controller">
-    <Register start="+0x0" size="0" name="LISR" access="ReadOnly" description="low interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="TCIF3" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="26" size="1" name="HTIF3" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="25" size="1" name="TEIF3" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="24" size="1" name="DMEIF3" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="22" size="1" name="FEIF3" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="21" size="1" name="TCIF2" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="20" size="1" name="HTIF2" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="19" size="1" name="TEIF2" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="18" size="1" name="DMEIF2" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="16" size="1" name="FEIF2" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="11" size="1" name="TCIF1" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="10" size="1" name="HTIF1" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="9" size="1" name="TEIF1" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="8" size="1" name="DMEIF1" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="6" size="1" name="FEIF1" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="5" size="1" name="TCIF0" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="4" size="1" name="HTIF0" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="3" size="1" name="TEIF0" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="2" size="1" name="DMEIF0" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="0" size="1" name="FEIF0" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-    </Register>
-    <Register start="+0x4" size="0" name="HISR" access="ReadOnly" description="high interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="TCIF7" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="26" size="1" name="HTIF7" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="25" size="1" name="TEIF7" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="24" size="1" name="DMEIF7" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="22" size="1" name="FEIF7" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="21" size="1" name="TCIF6" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="20" size="1" name="HTIF6" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="19" size="1" name="TEIF6" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="18" size="1" name="DMEIF6" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="16" size="1" name="FEIF6" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="11" size="1" name="TCIF5" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="10" size="1" name="HTIF5" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="9" size="1" name="TEIF5" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="8" size="1" name="DMEIF5" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="6" size="1" name="FEIF5" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="5" size="1" name="TCIF4" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="4" size="1" name="HTIF4" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="3" size="1" name="TEIF4" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="2" size="1" name="DMEIF4" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="0" size="1" name="FEIF4" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-    </Register>
-    <Register start="+0x8" size="0" name="LIFCR" access="Read/Write" description="low interrupt flag clear&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="CTCIF3" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="26" size="1" name="CHTIF3" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="25" size="1" name="CTEIF3" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="24" size="1" name="CDMEIF3" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="22" size="1" name="CFEIF3" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-      <BitField start="21" size="1" name="CTCIF2" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="20" size="1" name="CHTIF2" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="19" size="1" name="CTEIF2" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="18" size="1" name="CDMEIF2" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="16" size="1" name="CFEIF2" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-      <BitField start="11" size="1" name="CTCIF1" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="10" size="1" name="CHTIF1" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="9" size="1" name="CTEIF1" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="8" size="1" name="CDMEIF1" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="6" size="1" name="CFEIF1" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-      <BitField start="5" size="1" name="CTCIF0" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="4" size="1" name="CHTIF0" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="3" size="1" name="CTEIF0" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="2" size="1" name="CDMEIF0" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="0" size="1" name="CFEIF0" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-    </Register>
-    <Register start="+0xC" size="0" name="HIFCR" access="Read/Write" description="high interrupt flag clear&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="CTCIF7" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="26" size="1" name="CHTIF7" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="25" size="1" name="CTEIF7" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="24" size="1" name="CDMEIF7" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="22" size="1" name="CFEIF7" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-      <BitField start="21" size="1" name="CTCIF6" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="20" size="1" name="CHTIF6" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="19" size="1" name="CTEIF6" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="18" size="1" name="CDMEIF6" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="16" size="1" name="CFEIF6" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-      <BitField start="11" size="1" name="CTCIF5" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="10" size="1" name="CHTIF5" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="9" size="1" name="CTEIF5" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="8" size="1" name="CDMEIF5" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="6" size="1" name="CFEIF5" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-      <BitField start="5" size="1" name="CTCIF4" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="4" size="1" name="CHTIF4" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="3" size="1" name="CTEIF4" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="2" size="1" name="CDMEIF4" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="0" size="1" name="CFEIF4" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-    </Register>
-    <Register start="+0x10" size="0" name="S0CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x14" size="0" name="S0NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x18" size="0" name="S0PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x1C" size="0" name="S0M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x20" size="0" name="S0M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x24" size="0" name="S0FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x28" size="0" name="S1CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x2C" size="0" name="S1NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x30" size="0" name="S1PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x34" size="0" name="S1M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x38" size="0" name="S1M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x3C" size="0" name="S1FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x40" size="0" name="S2CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x44" size="0" name="S2NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x48" size="0" name="S2PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="S2M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x50" size="0" name="S2M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x54" size="0" name="S2FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x58" size="0" name="S3CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x5C" size="0" name="S3NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x60" size="0" name="S3PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x64" size="0" name="S3M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x68" size="0" name="S3M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x6C" size="0" name="S3FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x70" size="0" name="S4CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x74" size="0" name="S4NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x78" size="0" name="S4PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x7C" size="0" name="S4M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x80" size="0" name="S4M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x84" size="0" name="S4FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x88" size="0" name="S5CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x8C" size="0" name="S5NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x90" size="0" name="S5PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x94" size="0" name="S5M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x98" size="0" name="S5M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x9C" size="0" name="S5FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0xA0" size="0" name="S6CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0xA4" size="0" name="S6NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0xA8" size="0" name="S6PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0xAC" size="0" name="S6M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0xB0" size="0" name="S6M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0xB4" size="0" name="S6FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0xB8" size="0" name="S7CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0xBC" size="0" name="S7NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0xC0" size="0" name="S7PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0xC4" size="0" name="S7M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0xC8" size="0" name="S7M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0xCC" size="0" name="S7FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMA1" start="0x40026000" description="DMA controller">
-    <Register start="+0x0" size="0" name="LISR" access="ReadOnly" description="low interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="TCIF3" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="26" size="1" name="HTIF3" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="25" size="1" name="TEIF3" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="24" size="1" name="DMEIF3" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="22" size="1" name="FEIF3" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="21" size="1" name="TCIF2" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="20" size="1" name="HTIF2" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="19" size="1" name="TEIF2" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="18" size="1" name="DMEIF2" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="16" size="1" name="FEIF2" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="11" size="1" name="TCIF1" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="10" size="1" name="HTIF1" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="9" size="1" name="TEIF1" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="8" size="1" name="DMEIF1" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="6" size="1" name="FEIF1" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="5" size="1" name="TCIF0" description="Stream x transfer complete interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="4" size="1" name="HTIF0" description="Stream x half transfer interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="3" size="1" name="TEIF0" description="Stream x transfer error interrupt flag&#xa;              (x=3..0)" />
-      <BitField start="2" size="1" name="DMEIF0" description="Stream x direct mode error interrupt&#xa;              flag (x=3..0)" />
-      <BitField start="0" size="1" name="FEIF0" description="Stream x FIFO error interrupt flag&#xa;              (x=3..0)" />
-    </Register>
-    <Register start="+0x4" size="0" name="HISR" access="ReadOnly" description="high interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="TCIF7" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="26" size="1" name="HTIF7" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="25" size="1" name="TEIF7" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="24" size="1" name="DMEIF7" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="22" size="1" name="FEIF7" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="21" size="1" name="TCIF6" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="20" size="1" name="HTIF6" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="19" size="1" name="TEIF6" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="18" size="1" name="DMEIF6" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="16" size="1" name="FEIF6" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="11" size="1" name="TCIF5" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="10" size="1" name="HTIF5" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="9" size="1" name="TEIF5" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="8" size="1" name="DMEIF5" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="6" size="1" name="FEIF5" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="5" size="1" name="TCIF4" description="Stream x transfer complete interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="4" size="1" name="HTIF4" description="Stream x half transfer interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="3" size="1" name="TEIF4" description="Stream x transfer error interrupt flag&#xa;              (x=7..4)" />
-      <BitField start="2" size="1" name="DMEIF4" description="Stream x direct mode error interrupt&#xa;              flag (x=7..4)" />
-      <BitField start="0" size="1" name="FEIF4" description="Stream x FIFO error interrupt flag&#xa;              (x=7..4)" />
-    </Register>
-    <Register start="+0x8" size="0" name="LIFCR" access="Read/Write" description="low interrupt flag clear&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="CTCIF3" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="26" size="1" name="CHTIF3" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="25" size="1" name="CTEIF3" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="24" size="1" name="CDMEIF3" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="22" size="1" name="CFEIF3" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-      <BitField start="21" size="1" name="CTCIF2" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="20" size="1" name="CHTIF2" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="19" size="1" name="CTEIF2" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="18" size="1" name="CDMEIF2" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="16" size="1" name="CFEIF2" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-      <BitField start="11" size="1" name="CTCIF1" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="10" size="1" name="CHTIF1" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="9" size="1" name="CTEIF1" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="8" size="1" name="CDMEIF1" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="6" size="1" name="CFEIF1" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-      <BitField start="5" size="1" name="CTCIF0" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="4" size="1" name="CHTIF0" description="Stream x clear half transfer interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="3" size="1" name="CTEIF0" description="Stream x clear transfer error interrupt&#xa;              flag (x = 3..0)" />
-      <BitField start="2" size="1" name="CDMEIF0" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 3..0)" />
-      <BitField start="0" size="1" name="CFEIF0" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 3..0)" />
-    </Register>
-    <Register start="+0xC" size="0" name="HIFCR" access="Read/Write" description="high interrupt flag clear&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="CTCIF7" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="26" size="1" name="CHTIF7" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="25" size="1" name="CTEIF7" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="24" size="1" name="CDMEIF7" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="22" size="1" name="CFEIF7" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-      <BitField start="21" size="1" name="CTCIF6" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="20" size="1" name="CHTIF6" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="19" size="1" name="CTEIF6" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="18" size="1" name="CDMEIF6" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="16" size="1" name="CFEIF6" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-      <BitField start="11" size="1" name="CTCIF5" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="10" size="1" name="CHTIF5" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="9" size="1" name="CTEIF5" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="8" size="1" name="CDMEIF5" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="6" size="1" name="CFEIF5" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-      <BitField start="5" size="1" name="CTCIF4" description="Stream x clear transfer complete&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="4" size="1" name="CHTIF4" description="Stream x clear half transfer interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="3" size="1" name="CTEIF4" description="Stream x clear transfer error interrupt&#xa;              flag (x = 7..4)" />
-      <BitField start="2" size="1" name="CDMEIF4" description="Stream x clear direct mode error&#xa;              interrupt flag (x = 7..4)" />
-      <BitField start="0" size="1" name="CFEIF4" description="Stream x clear FIFO error interrupt flag&#xa;              (x = 7..4)" />
-    </Register>
-    <Register start="+0x10" size="0" name="S0CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x14" size="0" name="S0NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x18" size="0" name="S0PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x1C" size="0" name="S0M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x20" size="0" name="S0M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x24" size="0" name="S0FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x28" size="0" name="S1CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x2C" size="0" name="S1NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x30" size="0" name="S1PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x34" size="0" name="S1M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x38" size="0" name="S1M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x3C" size="0" name="S1FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x40" size="0" name="S2CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x44" size="0" name="S2NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x48" size="0" name="S2PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="S2M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x50" size="0" name="S2M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x54" size="0" name="S2FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x58" size="0" name="S3CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x5C" size="0" name="S3NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x60" size="0" name="S3PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x64" size="0" name="S3M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x68" size="0" name="S3M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x6C" size="0" name="S3FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x70" size="0" name="S4CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x74" size="0" name="S4NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x78" size="0" name="S4PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x7C" size="0" name="S4M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x80" size="0" name="S4M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x84" size="0" name="S4FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0x88" size="0" name="S5CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0x8C" size="0" name="S5NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0x90" size="0" name="S5PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0x94" size="0" name="S5M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0x98" size="0" name="S5M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0x9C" size="0" name="S5FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0xA0" size="0" name="S6CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0xA4" size="0" name="S6NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0xA8" size="0" name="S6PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0xAC" size="0" name="S6M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0xB0" size="0" name="S6M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0xB4" size="0" name="S6FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-    <Register start="+0xB8" size="0" name="S7CR" access="Read/Write" description="stream x configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="3" name="CHSEL" description="Channel selection" />
-      <BitField start="23" size="2" name="MBURST" description="Memory burst transfer&#xa;              configuration" />
-      <BitField start="21" size="2" name="PBURST" description="Peripheral burst transfer&#xa;              configuration" />
-      <BitField start="20" size="1" name="ACK" description="ACK" />
-      <BitField start="19" size="1" name="CT" description="Current target (only in double buffer&#xa;              mode)" />
-      <BitField start="18" size="1" name="DBM" description="Double buffer mode" />
-      <BitField start="16" size="2" name="PL" description="Priority level" />
-      <BitField start="15" size="1" name="PINCOS" description="Peripheral increment offset&#xa;              size" />
-      <BitField start="13" size="2" name="MSIZE" description="Memory data size" />
-      <BitField start="11" size="2" name="PSIZE" description="Peripheral data size" />
-      <BitField start="10" size="1" name="MINC" description="Memory increment mode" />
-      <BitField start="9" size="1" name="PINC" description="Peripheral increment mode" />
-      <BitField start="8" size="1" name="CIRC" description="Circular mode" />
-      <BitField start="6" size="2" name="DIR" description="Data transfer direction" />
-      <BitField start="5" size="1" name="PFCTRL" description="Peripheral flow controller" />
-      <BitField start="4" size="1" name="TCIE" description="Transfer complete interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="HTIE" description="Half transfer interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="TEIE" description="Transfer error interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DMEIE" description="Direct mode error interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="EN" description="Stream enable / flag stream ready when&#xa;              read low" />
-    </Register>
-    <Register start="+0xBC" size="0" name="S7NDTR" access="Read/Write" description="stream x number of data&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NDT" description="Number of data items to&#xa;              transfer" />
-    </Register>
-    <Register start="+0xC0" size="0" name="S7PAR" access="Read/Write" description="stream x peripheral address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PA" description="Peripheral address" />
-    </Register>
-    <Register start="+0xC4" size="0" name="S7M0AR" access="Read/Write" description="stream x memory 0 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M0A" description="Memory 0 address" />
-    </Register>
-    <Register start="+0xC8" size="0" name="S7M1AR" access="Read/Write" description="stream x memory 1 address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="M1A" description="Memory 1 address (used in case of Double&#xa;              buffer mode)" />
-    </Register>
-    <Register start="+0xCC" size="0" name="S7FCR" access="Read/Write" description="stream x FIFO control register" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="FEIE" description="FIFO error interrupt&#xa;              enable" />
-      <BitField start="3" size="3" name="FS" description="FIFO status" />
-      <BitField start="2" size="1" name="DMDIS" description="Direct mode disable" />
-      <BitField start="0" size="2" name="FTH" description="FIFO threshold selection" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RCC" start="0x40023800" description="Reset and clock control">
-    <Register start="+0x0" size="0" name="CR" access="Read/Write" description="clock control register" reset_value="0x00000083" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="PLLI2SRDY" description="PLLI2S clock ready flag" />
-      <BitField start="26" size="1" name="PLLI2SON" description="PLLI2S enable" />
-      <BitField start="25" size="1" name="PLLRDY" description="Main PLL (PLL) clock ready&#xa;              flag" />
-      <BitField start="24" size="1" name="PLLON" description="Main PLL (PLL) enable" />
-      <BitField start="19" size="1" name="CSSON" description="Clock security system&#xa;              enable" />
-      <BitField start="18" size="1" name="HSEBYP" description="HSE clock bypass" />
-      <BitField start="17" size="1" name="HSERDY" description="HSE clock ready flag" />
-      <BitField start="16" size="1" name="HSEON" description="HSE clock enable" />
-      <BitField start="8" size="8" name="HSICAL" description="Internal high-speed clock&#xa;              calibration" />
-      <BitField start="3" size="5" name="HSITRIM" description="Internal high-speed clock&#xa;              trimming" />
-      <BitField start="1" size="1" name="HSIRDY" description="Internal high-speed clock ready&#xa;              flag" />
-      <BitField start="0" size="1" name="HSION" description="Internal high-speed clock&#xa;              enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="PLLCFGR" access="Read/Write" description="PLL configuration register" reset_value="0x24003010" reset_mask="0xFFFFFFFF">
-      <BitField start="27" size="1" name="PLLQ3" description="Main PLL (PLL) division factor for USB&#xa;              OTG FS, SDIO and random number generator&#xa;              clocks" />
-      <BitField start="26" size="1" name="PLLQ2" description="Main PLL (PLL) division factor for USB&#xa;              OTG FS, SDIO and random number generator&#xa;              clocks" />
-      <BitField start="25" size="1" name="PLLQ1" description="Main PLL (PLL) division factor for USB&#xa;              OTG FS, SDIO and random number generator&#xa;              clocks" />
-      <BitField start="24" size="1" name="PLLQ0" description="Main PLL (PLL) division factor for USB&#xa;              OTG FS, SDIO and random number generator&#xa;              clocks" />
-      <BitField start="22" size="1" name="PLLSRC" description="Main PLL(PLL) and audio PLL (PLLI2S)&#xa;              entry clock source" />
-      <BitField start="17" size="1" name="PLLP1" description="Main PLL (PLL) division factor for main&#xa;              system clock" />
-      <BitField start="16" size="1" name="PLLP0" description="Main PLL (PLL) division factor for main&#xa;              system clock" />
-      <BitField start="14" size="1" name="PLLN8" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="13" size="1" name="PLLN7" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="12" size="1" name="PLLN6" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="11" size="1" name="PLLN5" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="10" size="1" name="PLLN4" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="9" size="1" name="PLLN3" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="8" size="1" name="PLLN2" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="7" size="1" name="PLLN1" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="6" size="1" name="PLLN0" description="Main PLL (PLL) multiplication factor for&#xa;              VCO" />
-      <BitField start="5" size="1" name="PLLM5" description="Division factor for the main PLL (PLL)&#xa;              and audio PLL (PLLI2S) input clock" />
-      <BitField start="4" size="1" name="PLLM4" description="Division factor for the main PLL (PLL)&#xa;              and audio PLL (PLLI2S) input clock" />
-      <BitField start="3" size="1" name="PLLM3" description="Division factor for the main PLL (PLL)&#xa;              and audio PLL (PLLI2S) input clock" />
-      <BitField start="2" size="1" name="PLLM2" description="Division factor for the main PLL (PLL)&#xa;              and audio PLL (PLLI2S) input clock" />
-      <BitField start="1" size="1" name="PLLM1" description="Division factor for the main PLL (PLL)&#xa;              and audio PLL (PLLI2S) input clock" />
-      <BitField start="0" size="1" name="PLLM0" description="Division factor for the main PLL (PLL)&#xa;              and audio PLL (PLLI2S) input clock" />
-    </Register>
-    <Register start="+0x8" size="0" name="CFGR" access="Read/Write" description="clock configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MCO2" description="Microcontroller clock output&#xa;              2" />
-      <BitField start="27" size="3" name="MCO2PRE" description="MCO2 prescaler" />
-      <BitField start="24" size="3" name="MCO1PRE" description="MCO1 prescaler" />
-      <BitField start="23" size="1" name="I2SSRC" description="I2S clock selection" />
-      <BitField start="21" size="2" name="MCO1" description="Microcontroller clock output&#xa;              1" />
-      <BitField start="16" size="5" name="RTCPRE" description="HSE division factor for RTC&#xa;              clock" />
-      <BitField start="13" size="3" name="PPRE2" description="APB high-speed prescaler&#xa;              (APB2)" />
-      <BitField start="10" size="3" name="PPRE1" description="APB Low speed prescaler&#xa;              (APB1)" />
-      <BitField start="4" size="4" name="HPRE" description="AHB prescaler" />
-      <BitField start="3" size="1" name="SWS1" description="System clock switch status" />
-      <BitField start="2" size="1" name="SWS0" description="System clock switch status" />
-      <BitField start="1" size="1" name="SW1" description="System clock switch" />
-      <BitField start="0" size="1" name="SW0" description="System clock switch" />
-    </Register>
-    <Register start="+0xC" size="0" name="CIR" access="Read/Write" description="clock interrupt register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="CSSC" description="Clock security system interrupt&#xa;              clear" />
-      <BitField start="21" size="1" name="PLLI2SRDYC" description="PLLI2S ready interrupt&#xa;              clear" />
-      <BitField start="20" size="1" name="PLLRDYC" description="Main PLL(PLL) ready interrupt&#xa;              clear" />
-      <BitField start="19" size="1" name="HSERDYC" description="HSE ready interrupt clear" />
-      <BitField start="18" size="1" name="HSIRDYC" description="HSI ready interrupt clear" />
-      <BitField start="17" size="1" name="LSERDYC" description="LSE ready interrupt clear" />
-      <BitField start="16" size="1" name="LSIRDYC" description="LSI ready interrupt clear" />
-      <BitField start="13" size="1" name="PLLI2SRDYIE" description="PLLI2S ready interrupt&#xa;              enable" />
-      <BitField start="12" size="1" name="PLLRDYIE" description="Main PLL (PLL) ready interrupt&#xa;              enable" />
-      <BitField start="11" size="1" name="HSERDYIE" description="HSE ready interrupt enable" />
-      <BitField start="10" size="1" name="HSIRDYIE" description="HSI ready interrupt enable" />
-      <BitField start="9" size="1" name="LSERDYIE" description="LSE ready interrupt enable" />
-      <BitField start="8" size="1" name="LSIRDYIE" description="LSI ready interrupt enable" />
-      <BitField start="7" size="1" name="CSSF" description="Clock security system interrupt&#xa;              flag" />
-      <BitField start="5" size="1" name="PLLI2SRDYF" description="PLLI2S ready interrupt&#xa;              flag" />
-      <BitField start="4" size="1" name="PLLRDYF" description="Main PLL (PLL) ready interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="HSERDYF" description="HSE ready interrupt flag" />
-      <BitField start="2" size="1" name="HSIRDYF" description="HSI ready interrupt flag" />
-      <BitField start="1" size="1" name="LSERDYF" description="LSE ready interrupt flag" />
-      <BitField start="0" size="1" name="LSIRDYF" description="LSI ready interrupt flag" />
-    </Register>
-    <Register start="+0x10" size="0" name="AHB1RSTR" access="Read/Write" description="AHB1 peripheral reset register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="1" name="OTGHSRST" description="USB OTG HS module reset" />
-      <BitField start="25" size="1" name="ETHMACRST" description="Ethernet MAC reset" />
-      <BitField start="22" size="1" name="DMA2RST" description="DMA2 reset" />
-      <BitField start="21" size="1" name="DMA1RST" description="DMA2 reset" />
-      <BitField start="12" size="1" name="CRCRST" description="CRC reset" />
-      <BitField start="8" size="1" name="GPIOIRST" description="IO port I reset" />
-      <BitField start="7" size="1" name="GPIOHRST" description="IO port H reset" />
-      <BitField start="6" size="1" name="GPIOGRST" description="IO port G reset" />
-      <BitField start="5" size="1" name="GPIOFRST" description="IO port F reset" />
-      <BitField start="4" size="1" name="GPIOERST" description="IO port E reset" />
-      <BitField start="3" size="1" name="GPIODRST" description="IO port D reset" />
-      <BitField start="2" size="1" name="GPIOCRST" description="IO port C reset" />
-      <BitField start="1" size="1" name="GPIOBRST" description="IO port B reset" />
-      <BitField start="0" size="1" name="GPIOARST" description="IO port A reset" />
-    </Register>
-    <Register start="+0x14" size="0" name="AHB2RSTR" access="Read/Write" description="AHB2 peripheral reset register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="OTGFSRST" description="USB OTG FS module reset" />
-      <BitField start="6" size="1" name="RNGRST" description="Random number generator module&#xa;              reset" />
-      <BitField start="0" size="1" name="DCMIRST" description="Camera interface reset" />
-    </Register>
-    <Register start="+0x18" size="0" name="AHB3RSTR" access="Read/Write" description="AHB3 peripheral reset register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSMCRST" description="Flexible static memory controller module&#xa;              reset" />
-    </Register>
-    <Register start="+0x20" size="0" name="APB1RSTR" access="Read/Write" description="APB1 peripheral reset register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="1" name="DACRST" description="DAC reset" />
-      <BitField start="28" size="1" name="PWRRST" description="Power interface reset" />
-      <BitField start="26" size="1" name="CAN2RST" description="CAN2 reset" />
-      <BitField start="25" size="1" name="CAN1RST" description="CAN1 reset" />
-      <BitField start="23" size="1" name="I2C3RST" description="I2C3 reset" />
-      <BitField start="22" size="1" name="I2C2RST" description="I2C 2 reset" />
-      <BitField start="21" size="1" name="I2C1RST" description="I2C 1 reset" />
-      <BitField start="20" size="1" name="UART5RST" description="USART 5 reset" />
-      <BitField start="19" size="1" name="UART4RST" description="USART 4 reset" />
-      <BitField start="18" size="1" name="UART3RST" description="USART 3 reset" />
-      <BitField start="17" size="1" name="UART2RST" description="USART 2 reset" />
-      <BitField start="15" size="1" name="SPI3RST" description="SPI 3 reset" />
-      <BitField start="14" size="1" name="SPI2RST" description="SPI 2 reset" />
-      <BitField start="11" size="1" name="WWDGRST" description="Window watchdog reset" />
-      <BitField start="8" size="1" name="TIM14RST" description="TIM14 reset" />
-      <BitField start="7" size="1" name="TIM13RST" description="TIM13 reset" />
-      <BitField start="6" size="1" name="TIM12RST" description="TIM12 reset" />
-      <BitField start="5" size="1" name="TIM7RST" description="TIM7 reset" />
-      <BitField start="4" size="1" name="TIM6RST" description="TIM6 reset" />
-      <BitField start="3" size="1" name="TIM5RST" description="TIM5 reset" />
-      <BitField start="2" size="1" name="TIM4RST" description="TIM4 reset" />
-      <BitField start="1" size="1" name="TIM3RST" description="TIM3 reset" />
-      <BitField start="0" size="1" name="TIM2RST" description="TIM2 reset" />
-    </Register>
-    <Register start="+0x24" size="0" name="APB2RSTR" access="Read/Write" description="APB2 peripheral reset register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="18" size="1" name="TIM11RST" description="TIM11 reset" />
-      <BitField start="17" size="1" name="TIM10RST" description="TIM10 reset" />
-      <BitField start="16" size="1" name="TIM9RST" description="TIM9 reset" />
-      <BitField start="14" size="1" name="SYSCFGRST" description="System configuration controller&#xa;              reset" />
-      <BitField start="12" size="1" name="SPI1RST" description="SPI 1 reset" />
-      <BitField start="11" size="1" name="SDIORST" description="SDIO reset" />
-      <BitField start="8" size="1" name="ADCRST" description="ADC interface reset (common to all&#xa;              ADCs)" />
-      <BitField start="5" size="1" name="USART6RST" description="USART6 reset" />
-      <BitField start="4" size="1" name="USART1RST" description="USART1 reset" />
-      <BitField start="1" size="1" name="TIM8RST" description="TIM8 reset" />
-      <BitField start="0" size="1" name="TIM1RST" description="TIM1 reset" />
-    </Register>
-    <Register start="+0x30" size="0" name="AHB1ENR" access="Read/Write" description="AHB1 peripheral clock register" reset_value="0x00100000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="1" name="OTGHSULPIEN" description="USB OTG HSULPI clock&#xa;              enable" />
-      <BitField start="29" size="1" name="OTGHSEN" description="USB OTG HS clock enable" />
-      <BitField start="28" size="1" name="ETHMACPTPEN" description="Ethernet PTP clock enable" />
-      <BitField start="27" size="1" name="ETHMACRXEN" description="Ethernet Reception clock&#xa;              enable" />
-      <BitField start="26" size="1" name="ETHMACTXEN" description="Ethernet Transmission clock&#xa;              enable" />
-      <BitField start="25" size="1" name="ETHMACEN" description="Ethernet MAC clock enable" />
-      <BitField start="22" size="1" name="DMA2EN" description="DMA2 clock enable" />
-      <BitField start="21" size="1" name="DMA1EN" description="DMA1 clock enable" />
-      <BitField start="18" size="1" name="BKPSRAMEN" description="Backup SRAM interface clock&#xa;              enable" />
-      <BitField start="12" size="1" name="CRCEN" description="CRC clock enable" />
-      <BitField start="8" size="1" name="GPIOIEN" description="IO port I clock enable" />
-      <BitField start="7" size="1" name="GPIOHEN" description="IO port H clock enable" />
-      <BitField start="6" size="1" name="GPIOGEN" description="IO port G clock enable" />
-      <BitField start="5" size="1" name="GPIOFEN" description="IO port F clock enable" />
-      <BitField start="4" size="1" name="GPIOEEN" description="IO port E clock enable" />
-      <BitField start="3" size="1" name="GPIODEN" description="IO port D clock enable" />
-      <BitField start="2" size="1" name="GPIOCEN" description="IO port C clock enable" />
-      <BitField start="1" size="1" name="GPIOBEN" description="IO port B clock enable" />
-      <BitField start="0" size="1" name="GPIOAEN" description="IO port A clock enable" />
-    </Register>
-    <Register start="+0x34" size="0" name="AHB2ENR" access="Read/Write" description="AHB2 peripheral clock enable&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="OTGFSEN" description="USB OTG FS clock enable" />
-      <BitField start="6" size="1" name="RNGEN" description="Random number generator clock&#xa;              enable" />
-      <BitField start="0" size="1" name="DCMIEN" description="Camera interface enable" />
-    </Register>
-    <Register start="+0x38" size="0" name="AHB3ENR" access="Read/Write" description="AHB3 peripheral clock enable&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSMCEN" description="Flexible static memory controller module&#xa;              clock enable" />
-    </Register>
-    <Register start="+0x40" size="0" name="APB1ENR" access="Read/Write" description="APB1 peripheral clock enable&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="1" name="DACEN" description="DAC interface clock enable" />
-      <BitField start="28" size="1" name="PWREN" description="Power interface clock&#xa;              enable" />
-      <BitField start="26" size="1" name="CAN2EN" description="CAN 2 clock enable" />
-      <BitField start="25" size="1" name="CAN1EN" description="CAN 1 clock enable" />
-      <BitField start="23" size="1" name="I2C3EN" description="I2C3 clock enable" />
-      <BitField start="22" size="1" name="I2C2EN" description="I2C2 clock enable" />
-      <BitField start="21" size="1" name="I2C1EN" description="I2C1 clock enable" />
-      <BitField start="20" size="1" name="UART5EN" description="UART5 clock enable" />
-      <BitField start="19" size="1" name="UART4EN" description="UART4 clock enable" />
-      <BitField start="18" size="1" name="USART3EN" description="USART3 clock enable" />
-      <BitField start="17" size="1" name="USART2EN" description="USART 2 clock enable" />
-      <BitField start="15" size="1" name="SPI3EN" description="SPI3 clock enable" />
-      <BitField start="14" size="1" name="SPI2EN" description="SPI2 clock enable" />
-      <BitField start="11" size="1" name="WWDGEN" description="Window watchdog clock&#xa;              enable" />
-      <BitField start="8" size="1" name="TIM14EN" description="TIM14 clock enable" />
-      <BitField start="7" size="1" name="TIM13EN" description="TIM13 clock enable" />
-      <BitField start="6" size="1" name="TIM12EN" description="TIM12 clock enable" />
-      <BitField start="5" size="1" name="TIM7EN" description="TIM7 clock enable" />
-      <BitField start="4" size="1" name="TIM6EN" description="TIM6 clock enable" />
-      <BitField start="3" size="1" name="TIM5EN" description="TIM5 clock enable" />
-      <BitField start="2" size="1" name="TIM4EN" description="TIM4 clock enable" />
-      <BitField start="1" size="1" name="TIM3EN" description="TIM3 clock enable" />
-      <BitField start="0" size="1" name="TIM2EN" description="TIM2 clock enable" />
-    </Register>
-    <Register start="+0x44" size="0" name="APB2ENR" access="Read/Write" description="APB2 peripheral clock enable&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="18" size="1" name="TIM11EN" description="TIM11 clock enable" />
-      <BitField start="17" size="1" name="TIM10EN" description="TIM10 clock enable" />
-      <BitField start="16" size="1" name="TIM9EN" description="TIM9 clock enable" />
-      <BitField start="14" size="1" name="SYSCFGEN" description="System configuration controller clock&#xa;              enable" />
-      <BitField start="12" size="1" name="SPI1EN" description="SPI1 clock enable" />
-      <BitField start="11" size="1" name="SDIOEN" description="SDIO clock enable" />
-      <BitField start="10" size="1" name="ADC3EN" description="ADC3 clock enable" />
-      <BitField start="9" size="1" name="ADC2EN" description="ADC2 clock enable" />
-      <BitField start="8" size="1" name="ADC1EN" description="ADC1 clock enable" />
-      <BitField start="5" size="1" name="USART6EN" description="USART6 clock enable" />
-      <BitField start="4" size="1" name="USART1EN" description="USART1 clock enable" />
-      <BitField start="1" size="1" name="TIM8EN" description="TIM8 clock enable" />
-      <BitField start="0" size="1" name="TIM1EN" description="TIM1 clock enable" />
-    </Register>
-    <Register start="+0x50" size="0" name="AHB1LPENR" access="Read/Write" description="AHB1 peripheral clock enable in low power&#xa;          mode register" reset_value="0x7E6791FF" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="1" name="OTGHSULPILPEN" description="USB OTG HS ULPI clock enable during&#xa;              Sleep mode" />
-      <BitField start="29" size="1" name="OTGHSLPEN" description="USB OTG HS clock enable during Sleep&#xa;              mode" />
-      <BitField start="28" size="1" name="ETHMACPTPLPEN" description="Ethernet PTP clock enable during Sleep&#xa;              mode" />
-      <BitField start="27" size="1" name="ETHMACRXLPEN" description="Ethernet reception clock enable during&#xa;              Sleep mode" />
-      <BitField start="26" size="1" name="ETHMACTXLPEN" description="Ethernet transmission clock enable&#xa;              during Sleep mode" />
-      <BitField start="25" size="1" name="ETHMACLPEN" description="Ethernet MAC clock enable during Sleep&#xa;              mode" />
-      <BitField start="22" size="1" name="DMA2LPEN" description="DMA2 clock enable during Sleep&#xa;              mode" />
-      <BitField start="21" size="1" name="DMA1LPEN" description="DMA1 clock enable during Sleep&#xa;              mode" />
-      <BitField start="18" size="1" name="BKPSRAMLPEN" description="Backup SRAM interface clock enable&#xa;              during Sleep mode" />
-      <BitField start="17" size="1" name="SRAM2LPEN" description="SRAM 2 interface clock enable during&#xa;              Sleep mode" />
-      <BitField start="16" size="1" name="SRAM1LPEN" description="SRAM 1interface clock enable during&#xa;              Sleep mode" />
-      <BitField start="15" size="1" name="FLITFLPEN" description="Flash interface clock enable during&#xa;              Sleep mode" />
-      <BitField start="12" size="1" name="CRCLPEN" description="CRC clock enable during Sleep&#xa;              mode" />
-      <BitField start="8" size="1" name="GPIOILPEN" description="IO port I clock enable during Sleep&#xa;              mode" />
-      <BitField start="7" size="1" name="GPIOHLPEN" description="IO port H clock enable during Sleep&#xa;              mode" />
-      <BitField start="6" size="1" name="GPIOGLPEN" description="IO port G clock enable during Sleep&#xa;              mode" />
-      <BitField start="5" size="1" name="GPIOFLPEN" description="IO port F clock enable during Sleep&#xa;              mode" />
-      <BitField start="4" size="1" name="GPIOELPEN" description="IO port E clock enable during Sleep&#xa;              mode" />
-      <BitField start="3" size="1" name="GPIODLPEN" description="IO port D clock enable during Sleep&#xa;              mode" />
-      <BitField start="2" size="1" name="GPIOCLPEN" description="IO port C clock enable during Sleep&#xa;              mode" />
-      <BitField start="1" size="1" name="GPIOBLPEN" description="IO port B clock enable during Sleep&#xa;              mode" />
-      <BitField start="0" size="1" name="GPIOALPEN" description="IO port A clock enable during sleep&#xa;              mode" />
-    </Register>
-    <Register start="+0x54" size="0" name="AHB2LPENR" access="Read/Write" description="AHB2 peripheral clock enable in low power&#xa;          mode register" reset_value="0x000000F1" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="OTGFSLPEN" description="USB OTG FS clock enable during Sleep&#xa;              mode" />
-      <BitField start="6" size="1" name="RNGLPEN" description="Random number generator clock enable&#xa;              during Sleep mode" />
-      <BitField start="0" size="1" name="DCMILPEN" description="Camera interface enable during Sleep&#xa;              mode" />
-    </Register>
-    <Register start="+0x58" size="0" name="AHB3LPENR" access="Read/Write" description="AHB3 peripheral clock enable in low power&#xa;          mode register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSMCLPEN" description="Flexible static memory controller module&#xa;              clock enable during Sleep mode" />
-    </Register>
-    <Register start="+0x60" size="0" name="APB1LPENR" access="Read/Write" description="APB1 peripheral clock enable in low power&#xa;          mode register" reset_value="0x36FEC9FF" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="1" name="DACLPEN" description="DAC interface clock enable during Sleep&#xa;              mode" />
-      <BitField start="28" size="1" name="PWRLPEN" description="Power interface clock enable during&#xa;              Sleep mode" />
-      <BitField start="26" size="1" name="CAN2LPEN" description="CAN 2 clock enable during Sleep&#xa;              mode" />
-      <BitField start="25" size="1" name="CAN1LPEN" description="CAN 1 clock enable during Sleep&#xa;              mode" />
-      <BitField start="23" size="1" name="I2C3LPEN" description="I2C3 clock enable during Sleep&#xa;              mode" />
-      <BitField start="22" size="1" name="I2C2LPEN" description="I2C2 clock enable during Sleep&#xa;              mode" />
-      <BitField start="21" size="1" name="I2C1LPEN" description="I2C1 clock enable during Sleep&#xa;              mode" />
-      <BitField start="20" size="1" name="UART5LPEN" description="UART5 clock enable during Sleep&#xa;              mode" />
-      <BitField start="19" size="1" name="UART4LPEN" description="UART4 clock enable during Sleep&#xa;              mode" />
-      <BitField start="18" size="1" name="USART3LPEN" description="USART3 clock enable during Sleep&#xa;              mode" />
-      <BitField start="17" size="1" name="USART2LPEN" description="USART2 clock enable during Sleep&#xa;              mode" />
-      <BitField start="15" size="1" name="SPI3LPEN" description="SPI3 clock enable during Sleep&#xa;              mode" />
-      <BitField start="14" size="1" name="SPI2LPEN" description="SPI2 clock enable during Sleep&#xa;              mode" />
-      <BitField start="11" size="1" name="WWDGLPEN" description="Window watchdog clock enable during&#xa;              Sleep mode" />
-      <BitField start="8" size="1" name="TIM14LPEN" description="TIM14 clock enable during Sleep&#xa;              mode" />
-      <BitField start="7" size="1" name="TIM13LPEN" description="TIM13 clock enable during Sleep&#xa;              mode" />
-      <BitField start="6" size="1" name="TIM12LPEN" description="TIM12 clock enable during Sleep&#xa;              mode" />
-      <BitField start="5" size="1" name="TIM7LPEN" description="TIM7 clock enable during Sleep&#xa;              mode" />
-      <BitField start="4" size="1" name="TIM6LPEN" description="TIM6 clock enable during Sleep&#xa;              mode" />
-      <BitField start="3" size="1" name="TIM5LPEN" description="TIM5 clock enable during Sleep&#xa;              mode" />
-      <BitField start="2" size="1" name="TIM4LPEN" description="TIM4 clock enable during Sleep&#xa;              mode" />
-      <BitField start="1" size="1" name="TIM3LPEN" description="TIM3 clock enable during Sleep&#xa;              mode" />
-      <BitField start="0" size="1" name="TIM2LPEN" description="TIM2 clock enable during Sleep&#xa;              mode" />
-    </Register>
-    <Register start="+0x64" size="0" name="APB2LPENR" access="Read/Write" description="APB2 peripheral clock enabled in low power&#xa;          mode register" reset_value="0x00075F33" reset_mask="0xFFFFFFFF">
-      <BitField start="18" size="1" name="TIM11LPEN" description="TIM11 clock enable during Sleep&#xa;              mode" />
-      <BitField start="17" size="1" name="TIM10LPEN" description="TIM10 clock enable during Sleep&#xa;              mode" />
-      <BitField start="16" size="1" name="TIM9LPEN" description="TIM9 clock enable during sleep&#xa;              mode" />
-      <BitField start="14" size="1" name="SYSCFGLPEN" description="System configuration controller clock&#xa;              enable during Sleep mode" />
-      <BitField start="12" size="1" name="SPI1LPEN" description="SPI 1 clock enable during Sleep&#xa;              mode" />
-      <BitField start="11" size="1" name="SDIOLPEN" description="SDIO clock enable during Sleep&#xa;              mode" />
-      <BitField start="10" size="1" name="ADC3LPEN" description="ADC 3 clock enable during Sleep&#xa;              mode" />
-      <BitField start="9" size="1" name="ADC2LPEN" description="ADC2 clock enable during Sleep&#xa;              mode" />
-      <BitField start="8" size="1" name="ADC1LPEN" description="ADC1 clock enable during Sleep&#xa;              mode" />
-      <BitField start="5" size="1" name="USART6LPEN" description="USART6 clock enable during Sleep&#xa;              mode" />
-      <BitField start="4" size="1" name="USART1LPEN" description="USART1 clock enable during Sleep&#xa;              mode" />
-      <BitField start="1" size="1" name="TIM8LPEN" description="TIM8 clock enable during Sleep&#xa;              mode" />
-      <BitField start="0" size="1" name="TIM1LPEN" description="TIM1 clock enable during Sleep&#xa;              mode" />
-    </Register>
-    <Register start="+0x70" size="0" name="BDCR" access="Read/Write" description="Backup domain control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="BDRST" description="Backup domain software&#xa;              reset" />
-      <BitField start="15" size="1" name="RTCEN" description="RTC clock enable" />
-      <BitField start="9" size="1" name="RTCSEL1" description="RTC clock source selection" />
-      <BitField start="8" size="1" name="RTCSEL0" description="RTC clock source selection" />
-      <BitField start="2" size="1" name="LSEBYP" description="External low-speed oscillator&#xa;              bypass" />
-      <BitField start="1" size="1" name="LSERDY" description="External low-speed oscillator&#xa;              ready" />
-      <BitField start="0" size="1" name="LSEON" description="External low-speed oscillator&#xa;              enable" />
-    </Register>
-    <Register start="+0x74" size="0" name="CSR" access="Read/Write" description="clock control &amp; status&#xa;          register" reset_value="0x0E000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="LPWRRSTF" description="Low-power reset flag" />
-      <BitField start="30" size="1" name="WWDGRSTF" description="Window watchdog reset flag" />
-      <BitField start="29" size="1" name="WDGRSTF" description="Independent watchdog reset&#xa;              flag" />
-      <BitField start="28" size="1" name="SFTRSTF" description="Software reset flag" />
-      <BitField start="27" size="1" name="PORRSTF" description="POR/PDR reset flag" />
-      <BitField start="26" size="1" name="PADRSTF" description="PIN reset flag" />
-      <BitField start="25" size="1" name="BORRSTF" description="BOR reset flag" />
-      <BitField start="24" size="1" name="RMVF" description="Remove reset flag" />
-      <BitField start="1" size="1" name="LSIRDY" description="Internal low-speed oscillator&#xa;              ready" />
-      <BitField start="0" size="1" name="LSION" description="Internal low-speed oscillator&#xa;              enable" />
-    </Register>
-    <Register start="+0x80" size="0" name="SSCGR" access="Read/Write" description="spread spectrum clock generation&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="SSCGEN" description="Spread spectrum modulation&#xa;              enable" />
-      <BitField start="30" size="1" name="SPREADSEL" description="Spread Select" />
-      <BitField start="13" size="15" name="INCSTEP" description="Incrementation step" />
-      <BitField start="0" size="13" name="MODPER" description="Modulation period" />
-    </Register>
-    <Register start="+0x84" size="0" name="PLLI2SCFGR" access="Read/Write" description="PLLI2S configuration register" reset_value="0x20003000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="3" name="PLLI2SRx" description="PLLI2S division factor for I2S&#xa;              clocks" />
-      <BitField start="6" size="9" name="PLLI2SNx" description="PLLI2S multiplication factor for&#xa;              VCO" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOI" start="0x40022000" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOH" start="0x40021C00" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOG" start="0x40021800" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOF" start="0x40021400" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOE" start="0x40021000" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOD" start="0x40020C00" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOC" start="0x40020800" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOB" start="0x40020400" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0x00000280" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x000000C0" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOA" start="0x40020000" description="General-purpose I/Os">
-    <Register start="+0x0" size="0" name="MODER" access="Read/Write" description="GPIO port mode register" reset_value="0xA8000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="MODER15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="MODER14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="MODER13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="MODER12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="MODER11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="MODER10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="MODER9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="MODER8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="MODER7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="MODER6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="MODER5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="MODER4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="MODER3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="MODER2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="MODER1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="MODER0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x4" size="0" name="OTYPER" access="Read/Write" description="GPIO port output type register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OT15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="OT14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="OT13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="OT12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="OT11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="OT10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="OT9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="OT8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="OT7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="OT6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="OT5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="OT4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="OT3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="OT2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="OT1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="OT0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x8" size="0" name="OSPEEDR" access="Read/Write" description="GPIO port output speed&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="OSPEEDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="OSPEEDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="OSPEEDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="OSPEEDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="OSPEEDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="OSPEEDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="OSPEEDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="OSPEEDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="OSPEEDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="OSPEEDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="OSPEEDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="OSPEEDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="OSPEEDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="OSPEEDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="OSPEEDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="OSPEEDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0xC" size="0" name="PUPDR" access="Read/Write" description="GPIO port pull-up/pull-down&#xa;          register" reset_value="0x64000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="2" name="PUPDR15" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="28" size="2" name="PUPDR14" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="26" size="2" name="PUPDR13" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="24" size="2" name="PUPDR12" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="22" size="2" name="PUPDR11" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="20" size="2" name="PUPDR10" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="18" size="2" name="PUPDR9" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="16" size="2" name="PUPDR8" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="14" size="2" name="PUPDR7" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="12" size="2" name="PUPDR6" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="10" size="2" name="PUPDR5" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="8" size="2" name="PUPDR4" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="6" size="2" name="PUPDR3" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="4" size="2" name="PUPDR2" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="2" size="2" name="PUPDR1" description="Port x configuration bits (y =&#xa;              0..15)" />
-      <BitField start="0" size="2" name="PUPDR0" description="Port x configuration bits (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x10" size="0" name="IDR" access="ReadOnly" description="GPIO port input data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="IDR15" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="IDR14" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="IDR13" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="IDR12" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="IDR11" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="IDR10" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="IDR9" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="IDR8" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="IDR7" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="IDR6" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="IDR5" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="IDR4" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="IDR3" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="IDR2" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="IDR1" description="Port input data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="IDR0" description="Port input data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x14" size="0" name="ODR" access="Read/Write" description="GPIO port output data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ODR15" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="14" size="1" name="ODR14" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="13" size="1" name="ODR13" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="12" size="1" name="ODR12" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="11" size="1" name="ODR11" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="10" size="1" name="ODR10" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="9" size="1" name="ODR9" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="8" size="1" name="ODR8" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="7" size="1" name="ODR7" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="6" size="1" name="ODR6" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="5" size="1" name="ODR5" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="4" size="1" name="ODR4" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="3" size="1" name="ODR3" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="2" size="1" name="ODR2" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="1" size="1" name="ODR1" description="Port output data (y =&#xa;              0..15)" />
-      <BitField start="0" size="1" name="ODR0" description="Port output data (y =&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x18" size="0" name="BSRR" access="WriteOnly" description="GPIO port bit set/reset&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="BR15" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="30" size="1" name="BR14" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="29" size="1" name="BR13" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="28" size="1" name="BR12" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="27" size="1" name="BR11" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="26" size="1" name="BR10" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="25" size="1" name="BR9" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="24" size="1" name="BR8" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="23" size="1" name="BR7" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="22" size="1" name="BR6" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="21" size="1" name="BR5" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="20" size="1" name="BR4" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="19" size="1" name="BR3" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="18" size="1" name="BR2" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="17" size="1" name="BR1" description="Port x reset bit y (y =&#xa;              0..15)" />
-      <BitField start="16" size="1" name="BR0" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="BS15" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="BS14" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="BS13" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="BS12" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="BS11" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="BS10" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="BS9" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="BS8" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="BS7" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="BS6" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="BS5" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="BS4" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="BS3" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="BS2" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="BS1" description="Port x set bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="BS0" description="Port x set bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x1C" size="0" name="LCKR" access="Read/Write" description="GPIO port configuration lock&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="LCKK" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="15" size="1" name="LCK15" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="14" size="1" name="LCK14" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="13" size="1" name="LCK13" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="12" size="1" name="LCK12" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="11" size="1" name="LCK11" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="10" size="1" name="LCK10" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="9" size="1" name="LCK9" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="8" size="1" name="LCK8" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="7" size="1" name="LCK7" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="6" size="1" name="LCK6" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="5" size="1" name="LCK5" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="4" size="1" name="LCK4" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="3" size="1" name="LCK3" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="2" size="1" name="LCK2" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="1" size="1" name="LCK1" description="Port x lock bit y (y=&#xa;              0..15)" />
-      <BitField start="0" size="1" name="LCK0" description="Port x lock bit y (y=&#xa;              0..15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="AFRL" access="Read/Write" description="GPIO alternate function low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRL7" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="24" size="4" name="AFRL6" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="20" size="4" name="AFRL5" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="16" size="4" name="AFRL4" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="12" size="4" name="AFRL3" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="8" size="4" name="AFRL2" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="4" size="4" name="AFRL1" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-      <BitField start="0" size="4" name="AFRL0" description="Alternate function selection for port x&#xa;              bit y (y = 0..7)" />
-    </Register>
-    <Register start="+0x24" size="0" name="AFRH" access="Read/Write" description="GPIO alternate function high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="28" size="4" name="AFRH15" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="24" size="4" name="AFRH14" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="20" size="4" name="AFRH13" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="16" size="4" name="AFRH12" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="12" size="4" name="AFRH11" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="8" size="4" name="AFRH10" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="4" size="4" name="AFRH9" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-      <BitField start="0" size="4" name="AFRH8" description="Alternate function selection for port x&#xa;              bit y (y = 8..15)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCFG" start="0x40013800" description="System configuration controller">
-    <Register start="+0x0" size="0" name="MEMRM" access="Read/Write" description="memory remap register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MEM_MODE" description="MEM_MODE" />
-    </Register>
-    <Register start="+0x4" size="0" name="PMC" access="Read/Write" description="peripheral mode configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="MII_RMII_SEL" description="Ethernet PHY interface&#xa;              selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="EXTICR1" access="Read/Write" description="external interrupt configuration register&#xa;          1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="EXTI3" description="EXTI x configuration (x = 0 to&#xa;              3)" />
-      <BitField start="8" size="4" name="EXTI2" description="EXTI x configuration (x = 0 to&#xa;              3)" />
-      <BitField start="4" size="4" name="EXTI1" description="EXTI x configuration (x = 0 to&#xa;              3)" />
-      <BitField start="0" size="4" name="EXTI0" description="EXTI x configuration (x = 0 to&#xa;              3)" />
-    </Register>
-    <Register start="+0xC" size="0" name="EXTICR2" access="Read/Write" description="external interrupt configuration register&#xa;          2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="EXTI7" description="EXTI x configuration (x = 4 to&#xa;              7)" />
-      <BitField start="8" size="4" name="EXTI6" description="EXTI x configuration (x = 4 to&#xa;              7)" />
-      <BitField start="4" size="4" name="EXTI5" description="EXTI x configuration (x = 4 to&#xa;              7)" />
-      <BitField start="0" size="4" name="EXTI4" description="EXTI x configuration (x = 4 to&#xa;              7)" />
-    </Register>
-    <Register start="+0x10" size="0" name="EXTICR3" access="Read/Write" description="external interrupt configuration register&#xa;          3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="EXTI11" description="EXTI x configuration (x = 8 to&#xa;              11)" />
-      <BitField start="8" size="4" name="EXTI10" description="EXTI10" />
-      <BitField start="4" size="4" name="EXTI9" description="EXTI x configuration (x = 8 to&#xa;              11)" />
-      <BitField start="0" size="4" name="EXTI8" description="EXTI x configuration (x = 8 to&#xa;              11)" />
-    </Register>
-    <Register start="+0x14" size="0" name="EXTICR4" access="Read/Write" description="external interrupt configuration register&#xa;          4" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="EXTI15" description="EXTI x configuration (x = 12 to&#xa;              15)" />
-      <BitField start="8" size="4" name="EXTI14" description="EXTI x configuration (x = 12 to&#xa;              15)" />
-      <BitField start="4" size="4" name="EXTI13" description="EXTI x configuration (x = 12 to&#xa;              15)" />
-      <BitField start="0" size="4" name="EXTI12" description="EXTI x configuration (x = 12 to&#xa;              15)" />
-    </Register>
-    <Register start="+0x20" size="0" name="CMPCR" access="ReadOnly" description="Compensation cell control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="READY" description="READY" />
-      <BitField start="0" size="1" name="CMP_PD" description="Compensation cell&#xa;              power-down" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI1" start="0x40013000" description="Serial peripheral interface">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="BIDIMODE" description="Bidirectional data mode&#xa;              enable" />
-      <BitField start="14" size="1" name="BIDIOE" description="Output enable in bidirectional&#xa;              mode" />
-      <BitField start="13" size="1" name="CRCEN" description="Hardware CRC calculation&#xa;              enable" />
-      <BitField start="12" size="1" name="CRCNEXT" description="CRC transfer next" />
-      <BitField start="11" size="1" name="DFF" description="Data frame format" />
-      <BitField start="10" size="1" name="RXONLY" description="Receive only" />
-      <BitField start="9" size="1" name="SSM" description="Software slave management" />
-      <BitField start="8" size="1" name="SSI" description="Internal slave select" />
-      <BitField start="7" size="1" name="LSBFIRST" description="Frame format" />
-      <BitField start="6" size="1" name="SPE" description="SPI enable" />
-      <BitField start="3" size="3" name="BR" description="Baud rate control" />
-      <BitField start="2" size="1" name="MSTR" description="Master selection" />
-      <BitField start="1" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="0" size="1" name="CPHA" description="Clock phase" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXEIE" description="Tx buffer empty interrupt&#xa;              enable" />
-      <BitField start="6" size="1" name="RXNEIE" description="RX buffer not empty interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="ERRIE" description="Error interrupt enable" />
-      <BitField start="4" size="1" name="FRF" description="Frame format" />
-      <BitField start="2" size="1" name="SSOE" description="SS output enable" />
-      <BitField start="1" size="1" name="TXDMAEN" description="Tx buffer DMA enable" />
-      <BitField start="0" size="1" name="RXDMAEN" description="Rx buffer DMA enable" />
-    </Register>
-    <Register start="+0x8" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="TIFRFE" description="TI frame format error" />
-      <BitField start="7" size="1" name="BSY" description="Busy flag" />
-      <BitField start="6" size="1" name="OVR" description="Overrun flag" />
-      <BitField start="5" size="1" name="MODF" description="Mode fault" />
-      <BitField start="4" size="1" name="CRCERR" description="CRC error flag" />
-      <BitField start="3" size="1" name="UDR" description="Underrun flag" />
-      <BitField start="2" size="1" name="CHSIDE" description="Channel side" />
-      <BitField start="1" size="1" name="TXE" description="Transmit buffer empty" />
-      <BitField start="0" size="1" name="RXNE" description="Receive buffer not empty" />
-    </Register>
-    <Register start="+0xC" size="0" name="DR" access="Read/Write" description="data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DR" description="Data register" />
-    </Register>
-    <Register start="+0x10" size="0" name="CRCPR" access="Read/Write" description="CRC polynomial register" reset_value="0x0007" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CRCPOLY" description="CRC polynomial register" />
-    </Register>
-    <Register start="+0x14" size="0" name="RXCRCR" access="ReadOnly" description="RX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RxCRC" description="Rx CRC register" />
-    </Register>
-    <Register start="+0x18" size="0" name="TXCRCR" access="ReadOnly" description="TX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TxCRC" description="Tx CRC register" />
-    </Register>
-    <Register start="+0x1C" size="0" name="I2SCFGR" access="Read/Write" description="I2S configuration register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="I2SMOD" description="I2S mode selection" />
-      <BitField start="10" size="1" name="I2SE" description="I2S Enable" />
-      <BitField start="8" size="2" name="I2SCFG" description="I2S configuration mode" />
-      <BitField start="7" size="1" name="PCMSYNC" description="PCM frame synchronization" />
-      <BitField start="4" size="2" name="I2SSTD" description="I2S standard selection" />
-      <BitField start="3" size="1" name="CKPOL" description="Steady state clock&#xa;              polarity" />
-      <BitField start="1" size="2" name="DATLEN" description="Data length to be&#xa;              transferred" />
-      <BitField start="0" size="1" name="CHLEN" description="Channel length (number of bits per audio&#xa;              channel)" />
-    </Register>
-    <Register start="+0x20" size="0" name="I2SPR" access="Read/Write" description="I2S prescaler register" reset_value="00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="MCKOE" description="Master clock output enable" />
-      <BitField start="8" size="1" name="ODD" description="Odd factor for the&#xa;              prescaler" />
-      <BitField start="0" size="8" name="I2SDIV" description="I2S Linear prescaler" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI2" start="0x40003800" description="Serial peripheral interface">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="BIDIMODE" description="Bidirectional data mode&#xa;              enable" />
-      <BitField start="14" size="1" name="BIDIOE" description="Output enable in bidirectional&#xa;              mode" />
-      <BitField start="13" size="1" name="CRCEN" description="Hardware CRC calculation&#xa;              enable" />
-      <BitField start="12" size="1" name="CRCNEXT" description="CRC transfer next" />
-      <BitField start="11" size="1" name="DFF" description="Data frame format" />
-      <BitField start="10" size="1" name="RXONLY" description="Receive only" />
-      <BitField start="9" size="1" name="SSM" description="Software slave management" />
-      <BitField start="8" size="1" name="SSI" description="Internal slave select" />
-      <BitField start="7" size="1" name="LSBFIRST" description="Frame format" />
-      <BitField start="6" size="1" name="SPE" description="SPI enable" />
-      <BitField start="3" size="3" name="BR" description="Baud rate control" />
-      <BitField start="2" size="1" name="MSTR" description="Master selection" />
-      <BitField start="1" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="0" size="1" name="CPHA" description="Clock phase" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXEIE" description="Tx buffer empty interrupt&#xa;              enable" />
-      <BitField start="6" size="1" name="RXNEIE" description="RX buffer not empty interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="ERRIE" description="Error interrupt enable" />
-      <BitField start="4" size="1" name="FRF" description="Frame format" />
-      <BitField start="2" size="1" name="SSOE" description="SS output enable" />
-      <BitField start="1" size="1" name="TXDMAEN" description="Tx buffer DMA enable" />
-      <BitField start="0" size="1" name="RXDMAEN" description="Rx buffer DMA enable" />
-    </Register>
-    <Register start="+0x8" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="TIFRFE" description="TI frame format error" />
-      <BitField start="7" size="1" name="BSY" description="Busy flag" />
-      <BitField start="6" size="1" name="OVR" description="Overrun flag" />
-      <BitField start="5" size="1" name="MODF" description="Mode fault" />
-      <BitField start="4" size="1" name="CRCERR" description="CRC error flag" />
-      <BitField start="3" size="1" name="UDR" description="Underrun flag" />
-      <BitField start="2" size="1" name="CHSIDE" description="Channel side" />
-      <BitField start="1" size="1" name="TXE" description="Transmit buffer empty" />
-      <BitField start="0" size="1" name="RXNE" description="Receive buffer not empty" />
-    </Register>
-    <Register start="+0xC" size="0" name="DR" access="Read/Write" description="data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DR" description="Data register" />
-    </Register>
-    <Register start="+0x10" size="0" name="CRCPR" access="Read/Write" description="CRC polynomial register" reset_value="0x0007" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CRCPOLY" description="CRC polynomial register" />
-    </Register>
-    <Register start="+0x14" size="0" name="RXCRCR" access="ReadOnly" description="RX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RxCRC" description="Rx CRC register" />
-    </Register>
-    <Register start="+0x18" size="0" name="TXCRCR" access="ReadOnly" description="TX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TxCRC" description="Tx CRC register" />
-    </Register>
-    <Register start="+0x1C" size="0" name="I2SCFGR" access="Read/Write" description="I2S configuration register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="I2SMOD" description="I2S mode selection" />
-      <BitField start="10" size="1" name="I2SE" description="I2S Enable" />
-      <BitField start="8" size="2" name="I2SCFG" description="I2S configuration mode" />
-      <BitField start="7" size="1" name="PCMSYNC" description="PCM frame synchronization" />
-      <BitField start="4" size="2" name="I2SSTD" description="I2S standard selection" />
-      <BitField start="3" size="1" name="CKPOL" description="Steady state clock&#xa;              polarity" />
-      <BitField start="1" size="2" name="DATLEN" description="Data length to be&#xa;              transferred" />
-      <BitField start="0" size="1" name="CHLEN" description="Channel length (number of bits per audio&#xa;              channel)" />
-    </Register>
-    <Register start="+0x20" size="0" name="I2SPR" access="Read/Write" description="I2S prescaler register" reset_value="00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="MCKOE" description="Master clock output enable" />
-      <BitField start="8" size="1" name="ODD" description="Odd factor for the&#xa;              prescaler" />
-      <BitField start="0" size="8" name="I2SDIV" description="I2S Linear prescaler" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI3" start="0x40003C00" description="Serial peripheral interface">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="BIDIMODE" description="Bidirectional data mode&#xa;              enable" />
-      <BitField start="14" size="1" name="BIDIOE" description="Output enable in bidirectional&#xa;              mode" />
-      <BitField start="13" size="1" name="CRCEN" description="Hardware CRC calculation&#xa;              enable" />
-      <BitField start="12" size="1" name="CRCNEXT" description="CRC transfer next" />
-      <BitField start="11" size="1" name="DFF" description="Data frame format" />
-      <BitField start="10" size="1" name="RXONLY" description="Receive only" />
-      <BitField start="9" size="1" name="SSM" description="Software slave management" />
-      <BitField start="8" size="1" name="SSI" description="Internal slave select" />
-      <BitField start="7" size="1" name="LSBFIRST" description="Frame format" />
-      <BitField start="6" size="1" name="SPE" description="SPI enable" />
-      <BitField start="3" size="3" name="BR" description="Baud rate control" />
-      <BitField start="2" size="1" name="MSTR" description="Master selection" />
-      <BitField start="1" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="0" size="1" name="CPHA" description="Clock phase" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXEIE" description="Tx buffer empty interrupt&#xa;              enable" />
-      <BitField start="6" size="1" name="RXNEIE" description="RX buffer not empty interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="ERRIE" description="Error interrupt enable" />
-      <BitField start="4" size="1" name="FRF" description="Frame format" />
-      <BitField start="2" size="1" name="SSOE" description="SS output enable" />
-      <BitField start="1" size="1" name="TXDMAEN" description="Tx buffer DMA enable" />
-      <BitField start="0" size="1" name="RXDMAEN" description="Rx buffer DMA enable" />
-    </Register>
-    <Register start="+0x8" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="TIFRFE" description="TI frame format error" />
-      <BitField start="7" size="1" name="BSY" description="Busy flag" />
-      <BitField start="6" size="1" name="OVR" description="Overrun flag" />
-      <BitField start="5" size="1" name="MODF" description="Mode fault" />
-      <BitField start="4" size="1" name="CRCERR" description="CRC error flag" />
-      <BitField start="3" size="1" name="UDR" description="Underrun flag" />
-      <BitField start="2" size="1" name="CHSIDE" description="Channel side" />
-      <BitField start="1" size="1" name="TXE" description="Transmit buffer empty" />
-      <BitField start="0" size="1" name="RXNE" description="Receive buffer not empty" />
-    </Register>
-    <Register start="+0xC" size="0" name="DR" access="Read/Write" description="data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DR" description="Data register" />
-    </Register>
-    <Register start="+0x10" size="0" name="CRCPR" access="Read/Write" description="CRC polynomial register" reset_value="0x0007" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CRCPOLY" description="CRC polynomial register" />
-    </Register>
-    <Register start="+0x14" size="0" name="RXCRCR" access="ReadOnly" description="RX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RxCRC" description="Rx CRC register" />
-    </Register>
-    <Register start="+0x18" size="0" name="TXCRCR" access="ReadOnly" description="TX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TxCRC" description="Tx CRC register" />
-    </Register>
-    <Register start="+0x1C" size="0" name="I2SCFGR" access="Read/Write" description="I2S configuration register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="I2SMOD" description="I2S mode selection" />
-      <BitField start="10" size="1" name="I2SE" description="I2S Enable" />
-      <BitField start="8" size="2" name="I2SCFG" description="I2S configuration mode" />
-      <BitField start="7" size="1" name="PCMSYNC" description="PCM frame synchronization" />
-      <BitField start="4" size="2" name="I2SSTD" description="I2S standard selection" />
-      <BitField start="3" size="1" name="CKPOL" description="Steady state clock&#xa;              polarity" />
-      <BitField start="1" size="2" name="DATLEN" description="Data length to be&#xa;              transferred" />
-      <BitField start="0" size="1" name="CHLEN" description="Channel length (number of bits per audio&#xa;              channel)" />
-    </Register>
-    <Register start="+0x20" size="0" name="I2SPR" access="Read/Write" description="I2S prescaler register" reset_value="00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="MCKOE" description="Master clock output enable" />
-      <BitField start="8" size="1" name="ODD" description="Odd factor for the&#xa;              prescaler" />
-      <BitField start="0" size="8" name="I2SDIV" description="I2S Linear prescaler" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S2ext" start="0x40003400" description="Serial peripheral interface">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="BIDIMODE" description="Bidirectional data mode&#xa;              enable" />
-      <BitField start="14" size="1" name="BIDIOE" description="Output enable in bidirectional&#xa;              mode" />
-      <BitField start="13" size="1" name="CRCEN" description="Hardware CRC calculation&#xa;              enable" />
-      <BitField start="12" size="1" name="CRCNEXT" description="CRC transfer next" />
-      <BitField start="11" size="1" name="DFF" description="Data frame format" />
-      <BitField start="10" size="1" name="RXONLY" description="Receive only" />
-      <BitField start="9" size="1" name="SSM" description="Software slave management" />
-      <BitField start="8" size="1" name="SSI" description="Internal slave select" />
-      <BitField start="7" size="1" name="LSBFIRST" description="Frame format" />
-      <BitField start="6" size="1" name="SPE" description="SPI enable" />
-      <BitField start="3" size="3" name="BR" description="Baud rate control" />
-      <BitField start="2" size="1" name="MSTR" description="Master selection" />
-      <BitField start="1" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="0" size="1" name="CPHA" description="Clock phase" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXEIE" description="Tx buffer empty interrupt&#xa;              enable" />
-      <BitField start="6" size="1" name="RXNEIE" description="RX buffer not empty interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="ERRIE" description="Error interrupt enable" />
-      <BitField start="4" size="1" name="FRF" description="Frame format" />
-      <BitField start="2" size="1" name="SSOE" description="SS output enable" />
-      <BitField start="1" size="1" name="TXDMAEN" description="Tx buffer DMA enable" />
-      <BitField start="0" size="1" name="RXDMAEN" description="Rx buffer DMA enable" />
-    </Register>
-    <Register start="+0x8" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="TIFRFE" description="TI frame format error" />
-      <BitField start="7" size="1" name="BSY" description="Busy flag" />
-      <BitField start="6" size="1" name="OVR" description="Overrun flag" />
-      <BitField start="5" size="1" name="MODF" description="Mode fault" />
-      <BitField start="4" size="1" name="CRCERR" description="CRC error flag" />
-      <BitField start="3" size="1" name="UDR" description="Underrun flag" />
-      <BitField start="2" size="1" name="CHSIDE" description="Channel side" />
-      <BitField start="1" size="1" name="TXE" description="Transmit buffer empty" />
-      <BitField start="0" size="1" name="RXNE" description="Receive buffer not empty" />
-    </Register>
-    <Register start="+0xC" size="0" name="DR" access="Read/Write" description="data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DR" description="Data register" />
-    </Register>
-    <Register start="+0x10" size="0" name="CRCPR" access="Read/Write" description="CRC polynomial register" reset_value="0x0007" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CRCPOLY" description="CRC polynomial register" />
-    </Register>
-    <Register start="+0x14" size="0" name="RXCRCR" access="ReadOnly" description="RX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RxCRC" description="Rx CRC register" />
-    </Register>
-    <Register start="+0x18" size="0" name="TXCRCR" access="ReadOnly" description="TX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TxCRC" description="Tx CRC register" />
-    </Register>
-    <Register start="+0x1C" size="0" name="I2SCFGR" access="Read/Write" description="I2S configuration register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="I2SMOD" description="I2S mode selection" />
-      <BitField start="10" size="1" name="I2SE" description="I2S Enable" />
-      <BitField start="8" size="2" name="I2SCFG" description="I2S configuration mode" />
-      <BitField start="7" size="1" name="PCMSYNC" description="PCM frame synchronization" />
-      <BitField start="4" size="2" name="I2SSTD" description="I2S standard selection" />
-      <BitField start="3" size="1" name="CKPOL" description="Steady state clock&#xa;              polarity" />
-      <BitField start="1" size="2" name="DATLEN" description="Data length to be&#xa;              transferred" />
-      <BitField start="0" size="1" name="CHLEN" description="Channel length (number of bits per audio&#xa;              channel)" />
-    </Register>
-    <Register start="+0x20" size="0" name="I2SPR" access="Read/Write" description="I2S prescaler register" reset_value="00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="MCKOE" description="Master clock output enable" />
-      <BitField start="8" size="1" name="ODD" description="Odd factor for the&#xa;              prescaler" />
-      <BitField start="0" size="8" name="I2SDIV" description="I2S Linear prescaler" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S3ext" start="0x40004000" description="Serial peripheral interface">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="BIDIMODE" description="Bidirectional data mode&#xa;              enable" />
-      <BitField start="14" size="1" name="BIDIOE" description="Output enable in bidirectional&#xa;              mode" />
-      <BitField start="13" size="1" name="CRCEN" description="Hardware CRC calculation&#xa;              enable" />
-      <BitField start="12" size="1" name="CRCNEXT" description="CRC transfer next" />
-      <BitField start="11" size="1" name="DFF" description="Data frame format" />
-      <BitField start="10" size="1" name="RXONLY" description="Receive only" />
-      <BitField start="9" size="1" name="SSM" description="Software slave management" />
-      <BitField start="8" size="1" name="SSI" description="Internal slave select" />
-      <BitField start="7" size="1" name="LSBFIRST" description="Frame format" />
-      <BitField start="6" size="1" name="SPE" description="SPI enable" />
-      <BitField start="3" size="3" name="BR" description="Baud rate control" />
-      <BitField start="2" size="1" name="MSTR" description="Master selection" />
-      <BitField start="1" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="0" size="1" name="CPHA" description="Clock phase" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXEIE" description="Tx buffer empty interrupt&#xa;              enable" />
-      <BitField start="6" size="1" name="RXNEIE" description="RX buffer not empty interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="ERRIE" description="Error interrupt enable" />
-      <BitField start="4" size="1" name="FRF" description="Frame format" />
-      <BitField start="2" size="1" name="SSOE" description="SS output enable" />
-      <BitField start="1" size="1" name="TXDMAEN" description="Tx buffer DMA enable" />
-      <BitField start="0" size="1" name="RXDMAEN" description="Rx buffer DMA enable" />
-    </Register>
-    <Register start="+0x8" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="TIFRFE" description="TI frame format error" />
-      <BitField start="7" size="1" name="BSY" description="Busy flag" />
-      <BitField start="6" size="1" name="OVR" description="Overrun flag" />
-      <BitField start="5" size="1" name="MODF" description="Mode fault" />
-      <BitField start="4" size="1" name="CRCERR" description="CRC error flag" />
-      <BitField start="3" size="1" name="UDR" description="Underrun flag" />
-      <BitField start="2" size="1" name="CHSIDE" description="Channel side" />
-      <BitField start="1" size="1" name="TXE" description="Transmit buffer empty" />
-      <BitField start="0" size="1" name="RXNE" description="Receive buffer not empty" />
-    </Register>
-    <Register start="+0xC" size="0" name="DR" access="Read/Write" description="data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DR" description="Data register" />
-    </Register>
-    <Register start="+0x10" size="0" name="CRCPR" access="Read/Write" description="CRC polynomial register" reset_value="0x0007" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CRCPOLY" description="CRC polynomial register" />
-    </Register>
-    <Register start="+0x14" size="0" name="RXCRCR" access="ReadOnly" description="RX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RxCRC" description="Rx CRC register" />
-    </Register>
-    <Register start="+0x18" size="0" name="TXCRCR" access="ReadOnly" description="TX CRC register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TxCRC" description="Tx CRC register" />
-    </Register>
-    <Register start="+0x1C" size="0" name="I2SCFGR" access="Read/Write" description="I2S configuration register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="I2SMOD" description="I2S mode selection" />
-      <BitField start="10" size="1" name="I2SE" description="I2S Enable" />
-      <BitField start="8" size="2" name="I2SCFG" description="I2S configuration mode" />
-      <BitField start="7" size="1" name="PCMSYNC" description="PCM frame synchronization" />
-      <BitField start="4" size="2" name="I2SSTD" description="I2S standard selection" />
-      <BitField start="3" size="1" name="CKPOL" description="Steady state clock&#xa;              polarity" />
-      <BitField start="1" size="2" name="DATLEN" description="Data length to be&#xa;              transferred" />
-      <BitField start="0" size="1" name="CHLEN" description="Channel length (number of bits per audio&#xa;              channel)" />
-    </Register>
-    <Register start="+0x20" size="0" name="I2SPR" access="Read/Write" description="I2S prescaler register" reset_value="00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="MCKOE" description="Master clock output enable" />
-      <BitField start="8" size="1" name="ODD" description="Odd factor for the&#xa;              prescaler" />
-      <BitField start="0" size="8" name="I2SDIV" description="I2S Linear prescaler" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDIO" start="0x40012C00" description="Secure digital input/output&#xa;      interface">
-    <Register start="+0x0" size="0" name="POWER" access="Read/Write" description="power control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PWRCTRL" description="PWRCTRL" />
-    </Register>
-    <Register start="+0x4" size="0" name="CLKCR" access="Read/Write" description="SDI clock control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="HWFC_EN" description="HW Flow Control enable" />
-      <BitField start="13" size="1" name="NEGEDGE" description="SDIO_CK dephasing selection&#xa;              bit" />
-      <BitField start="11" size="2" name="WIDBUS" description="Wide bus mode enable bit" />
-      <BitField start="10" size="1" name="BYPASS" description="Clock divider bypass enable&#xa;              bit" />
-      <BitField start="9" size="1" name="PWRSAV" description="Power saving configuration&#xa;              bit" />
-      <BitField start="8" size="1" name="CLKEN" description="Clock enable bit" />
-      <BitField start="0" size="8" name="CLKDIV" description="Clock divide factor" />
-    </Register>
-    <Register start="+0x8" size="0" name="ARG" access="Read/Write" description="argument register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDARG" description="Command argument" />
-    </Register>
-    <Register start="+0xC" size="0" name="CMD" access="Read/Write" description="command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="CE_ATACMD" description="CE-ATA command" />
-      <BitField start="13" size="1" name="nIEN" description="not Interrupt Enable" />
-      <BitField start="12" size="1" name="ENCMDcompl" description="Enable CMD completion" />
-      <BitField start="11" size="1" name="SDIOSuspend" description="SD I/O suspend command" />
-      <BitField start="10" size="1" name="CPSMEN" description="Command path state machine (CPSM) Enable&#xa;              bit" />
-      <BitField start="9" size="1" name="WAITPEND" description="CPSM Waits for ends of data transfer&#xa;              (CmdPend internal signal)." />
-      <BitField start="8" size="1" name="WAITINT" description="CPSM waits for interrupt&#xa;              request" />
-      <BitField start="6" size="2" name="WAITRESP" description="Wait for response bits" />
-      <BitField start="0" size="6" name="CMDINDEX" description="Command index" />
-    </Register>
-    <Register start="+0x10" size="0" name="RESPCMD" access="ReadOnly" description="command response register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESPCMD" description="Response command index" />
-    </Register>
-    <Register start="+0x14" size="0" name="RESP1" access="ReadOnly" description="response 1..4 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CARDSTATUS1" description="see Table 132." />
-    </Register>
-    <Register start="+0x18" size="0" name="RESP2" access="ReadOnly" description="response 1..4 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CARDSTATUS2" description="see Table 132." />
-    </Register>
-    <Register start="+0x1C" size="0" name="RESP3" access="ReadOnly" description="response 1..4 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CARDSTATUS3" description="see Table 132." />
-    </Register>
-    <Register start="+0x20" size="0" name="RESP4" access="ReadOnly" description="response 1..4 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CARDSTATUS4" description="see Table 132." />
-    </Register>
-    <Register start="+0x24" size="0" name="DTIMER" access="Read/Write" description="data timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATATIME" description="Data timeout period" />
-    </Register>
-    <Register start="+0x28" size="0" name="DLEN" access="Read/Write" description="data length register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="25" name="DATALENGTH" description="Data length value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="DCTRL" access="Read/Write" description="data control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="SDIOEN" description="SD I/O enable functions" />
-      <BitField start="10" size="1" name="RWMOD" description="Read wait mode" />
-      <BitField start="9" size="1" name="RWSTOP" description="Read wait stop" />
-      <BitField start="8" size="1" name="RWSTART" description="Read wait start" />
-      <BitField start="4" size="4" name="DBLOCKSIZE" description="Data block size" />
-      <BitField start="3" size="1" name="DMAEN" description="DMA enable bit" />
-      <BitField start="2" size="1" name="DTMODE" description="Data transfer mode selection 1: Stream&#xa;              or SDIO multibyte data transfer." />
-      <BitField start="1" size="1" name="DTDIR" description="Data transfer direction&#xa;              selection" />
-      <BitField start="0" size="1" name="DTEN" description="DTEN" />
-    </Register>
-    <Register start="+0x30" size="0" name="DCOUNT" access="ReadOnly" description="data counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="25" name="DATACOUNT" description="Data count value" />
-    </Register>
-    <Register start="+0x34" size="0" name="STA" access="ReadOnly" description="status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="CEATAEND" description="CE-ATA command completion signal&#xa;              received for CMD61" />
-      <BitField start="22" size="1" name="SDIOIT" description="SDIO interrupt received" />
-      <BitField start="21" size="1" name="RXDAVL" description="Data available in receive&#xa;              FIFO" />
-      <BitField start="20" size="1" name="TXDAVL" description="Data available in transmit&#xa;              FIFO" />
-      <BitField start="19" size="1" name="RXFIFOE" description="Receive FIFO empty" />
-      <BitField start="18" size="1" name="TXFIFOE" description="Transmit FIFO empty" />
-      <BitField start="17" size="1" name="RXFIFOF" description="Receive FIFO full" />
-      <BitField start="16" size="1" name="TXFIFOF" description="Transmit FIFO full" />
-      <BitField start="15" size="1" name="RXFIFOHF" description="Receive FIFO half full: there are at&#xa;              least 8 words in the FIFO" />
-      <BitField start="14" size="1" name="TXFIFOHE" description="Transmit FIFO half empty: at least 8&#xa;              words can be written into the FIFO" />
-      <BitField start="13" size="1" name="RXACT" description="Data receive in progress" />
-      <BitField start="12" size="1" name="TXACT" description="Data transmit in progress" />
-      <BitField start="11" size="1" name="CMDACT" description="Command transfer in&#xa;              progress" />
-      <BitField start="10" size="1" name="DBCKEND" description="Data block sent/received (CRC check&#xa;              passed)" />
-      <BitField start="9" size="1" name="STBITERR" description="Start bit not detected on all data&#xa;              signals in wide bus mode" />
-      <BitField start="8" size="1" name="DATAEND" description="Data end (data counter, SDIDCOUNT, is&#xa;              zero)" />
-      <BitField start="7" size="1" name="CMDSENT" description="Command sent (no response&#xa;              required)" />
-      <BitField start="6" size="1" name="CMDREND" description="Command response received (CRC check&#xa;              passed)" />
-      <BitField start="5" size="1" name="RXOVERR" description="Received FIFO overrun&#xa;              error" />
-      <BitField start="4" size="1" name="TXUNDERR" description="Transmit FIFO underrun&#xa;              error" />
-      <BitField start="3" size="1" name="DTIMEOUT" description="Data timeout" />
-      <BitField start="2" size="1" name="CTIMEOUT" description="Command response timeout" />
-      <BitField start="1" size="1" name="DCRCFAIL" description="Data block sent/received (CRC check&#xa;              failed)" />
-      <BitField start="0" size="1" name="CCRCFAIL" description="Command response received (CRC check&#xa;              failed)" />
-    </Register>
-    <Register start="+0x38" size="0" name="ICR" access="Read/Write" description="interrupt clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="CEATAENDC" description="CEATAEND flag clear bit" />
-      <BitField start="22" size="1" name="SDIOITC" description="SDIOIT flag clear bit" />
-      <BitField start="10" size="1" name="DBCKENDC" description="DBCKEND flag clear bit" />
-      <BitField start="9" size="1" name="STBITERRC" description="STBITERR flag clear bit" />
-      <BitField start="8" size="1" name="DATAENDC" description="DATAEND flag clear bit" />
-      <BitField start="7" size="1" name="CMDSENTC" description="CMDSENT flag clear bit" />
-      <BitField start="6" size="1" name="CMDRENDC" description="CMDREND flag clear bit" />
-      <BitField start="5" size="1" name="RXOVERRC" description="RXOVERR flag clear bit" />
-      <BitField start="4" size="1" name="TXUNDERRC" description="TXUNDERR flag clear bit" />
-      <BitField start="3" size="1" name="DTIMEOUTC" description="DTIMEOUT flag clear bit" />
-      <BitField start="2" size="1" name="CTIMEOUTC" description="CTIMEOUT flag clear bit" />
-      <BitField start="1" size="1" name="DCRCFAILC" description="DCRCFAIL flag clear bit" />
-      <BitField start="0" size="1" name="CCRCFAILC" description="CCRCFAIL flag clear bit" />
-    </Register>
-    <Register start="+0x3C" size="0" name="MASK" access="Read/Write" description="mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="CEATAENDIE" description="CE-ATA command completion signal&#xa;              received interrupt enable" />
-      <BitField start="22" size="1" name="SDIOITIE" description="SDIO mode interrupt received interrupt&#xa;              enable" />
-      <BitField start="21" size="1" name="RXDAVLIE" description="Data available in Rx FIFO interrupt&#xa;              enable" />
-      <BitField start="20" size="1" name="TXDAVLIE" description="Data available in Tx FIFO interrupt&#xa;              enable" />
-      <BitField start="19" size="1" name="RXFIFOEIE" description="Rx FIFO empty interrupt&#xa;              enable" />
-      <BitField start="18" size="1" name="TXFIFOEIE" description="Tx FIFO empty interrupt&#xa;              enable" />
-      <BitField start="17" size="1" name="RXFIFOFIE" description="Rx FIFO full interrupt&#xa;              enable" />
-      <BitField start="16" size="1" name="TXFIFOFIE" description="Tx FIFO full interrupt&#xa;              enable" />
-      <BitField start="15" size="1" name="RXFIFOHFIE" description="Rx FIFO half full interrupt&#xa;              enable" />
-      <BitField start="14" size="1" name="TXFIFOHEIE" description="Tx FIFO half empty interrupt&#xa;              enable" />
-      <BitField start="13" size="1" name="RXACTIE" description="Data receive acting interrupt&#xa;              enable" />
-      <BitField start="12" size="1" name="TXACTIE" description="Data transmit acting interrupt&#xa;              enable" />
-      <BitField start="11" size="1" name="CMDACTIE" description="Command acting interrupt&#xa;              enable" />
-      <BitField start="10" size="1" name="DBCKENDIE" description="Data block end interrupt&#xa;              enable" />
-      <BitField start="9" size="1" name="STBITERRIE" description="Start bit error interrupt&#xa;              enable" />
-      <BitField start="8" size="1" name="DATAENDIE" description="Data end interrupt enable" />
-      <BitField start="7" size="1" name="CMDSENTIE" description="Command sent interrupt&#xa;              enable" />
-      <BitField start="6" size="1" name="CMDRENDIE" description="Command response received interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXOVERRIE" description="Rx FIFO overrun error interrupt&#xa;              enable" />
-      <BitField start="4" size="1" name="TXUNDERRIE" description="Tx FIFO underrun error interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="DTIMEOUTIE" description="Data timeout interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CTIMEOUTIE" description="Command timeout interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="DCRCFAILIE" description="Data CRC fail interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="CCRCFAILIE" description="Command CRC fail interrupt&#xa;              enable" />
-    </Register>
-    <Register start="+0x48" size="0" name="FIFOCNT" access="ReadOnly" description="FIFO counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="FIFOCOUNT" description="Remaining number of words to be written&#xa;              to or read from the FIFO." />
-    </Register>
-    <Register start="+0x80" size="0" name="FIFO" access="Read/Write" description="data FIFO register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FIFOData" description="Receive and transmit FIFO&#xa;              data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x40012000" description="Analog-to-digital converter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="OVR" description="Overrun" />
-      <BitField start="4" size="1" name="STRT" description="Regular channel start flag" />
-      <BitField start="3" size="1" name="JSTRT" description="Injected channel start&#xa;              flag" />
-      <BitField start="2" size="1" name="JEOC" description="Injected channel end of&#xa;              conversion" />
-      <BitField start="1" size="1" name="EOC" description="Regular channel end of&#xa;              conversion" />
-      <BitField start="0" size="1" name="AWD" description="Analog watchdog flag" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="26" size="1" name="OVRIE" description="Overrun interrupt enable" />
-      <BitField start="24" size="2" name="RES" description="Resolution" />
-      <BitField start="23" size="1" name="AWDEN" description="Analog watchdog enable on regular&#xa;              channels" />
-      <BitField start="22" size="1" name="JAWDEN" description="Analog watchdog enable on injected&#xa;              channels" />
-      <BitField start="13" size="3" name="DISCNUM" description="Discontinuous mode channel&#xa;              count" />
-      <BitField start="12" size="1" name="JDISCEN" description="Discontinuous mode on injected&#xa;              channels" />
-      <BitField start="11" size="1" name="DISCEN" description="Discontinuous mode on regular&#xa;              channels" />
-      <BitField start="10" size="1" name="JAUTO" description="Automatic injected group&#xa;              conversion" />
-      <BitField start="9" size="1" name="AWDSGL" description="Enable the watchdog on a single channel&#xa;              in scan mode" />
-      <BitField start="8" size="1" name="SCAN" description="Scan mode" />
-      <BitField start="7" size="1" name="JEOCIE" description="Interrupt enable for injected&#xa;              channels" />
-      <BitField start="6" size="1" name="AWDIE" description="Analog watchdog interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="EOCIE" description="Interrupt enable for EOC" />
-      <BitField start="0" size="5" name="AWDCH" description="Analog watchdog channel select&#xa;              bits" />
-    </Register>
-    <Register start="+0x8" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="1" name="SWSTART" description="Start conversion of regular&#xa;              channels" />
-      <BitField start="28" size="2" name="EXTEN" description="External trigger enable for regular&#xa;              channels" />
-      <BitField start="24" size="4" name="EXTSEL" description="External event select for regular&#xa;              group" />
-      <BitField start="22" size="1" name="JSWSTART" description="Start conversion of injected&#xa;              channels" />
-      <BitField start="20" size="2" name="JEXTEN" description="External trigger enable for injected&#xa;              channels" />
-      <BitField start="16" size="4" name="JEXTSEL" description="External event select for injected&#xa;              group" />
-      <BitField start="11" size="1" name="ALIGN" description="Data alignment" />
-      <BitField start="10" size="1" name="EOCS" description="End of conversion&#xa;              selection" />
-      <BitField start="9" size="1" name="DDS" description="DMA disable selection (for single ADC&#xa;              mode)" />
-      <BitField start="8" size="1" name="DMA" description="Direct memory access mode (for single&#xa;              ADC mode)" />
-      <BitField start="1" size="1" name="CONT" description="Continuous conversion" />
-      <BitField start="0" size="1" name="ADON" description="A/D Converter ON / OFF" />
-    </Register>
-    <Register start="+0xC" size="0" name="SMPR1" access="Read/Write" description="sample time register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SMPx_x" description="Sample time bits" />
-    </Register>
-    <Register start="+0x10" size="0" name="SMPR2" access="Read/Write" description="sample time register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SMPx_x" description="Sample time bits" />
-    </Register>
-    <Register start="+0x14" size="0" name="JOFR1" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET1" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x18" size="0" name="JOFR2" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET2" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x1C" size="0" name="JOFR3" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET3" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x20" size="0" name="JOFR4" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET4" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x24" size="0" name="HTR" access="Read/Write" description="watchdog higher threshold&#xa;          register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="HT" description="Analog watchdog higher&#xa;              threshold" />
-    </Register>
-    <Register start="+0x28" size="0" name="LTR" access="Read/Write" description="watchdog lower threshold&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="LT" description="Analog watchdog lower&#xa;              threshold" />
-    </Register>
-    <Register start="+0x2C" size="0" name="SQR1" access="Read/Write" description="regular sequence register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="4" name="L" description="Regular channel sequence&#xa;              length" />
-      <BitField start="15" size="5" name="SQ16" description="16th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ15" description="15th conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ14" description="14th conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ13" description="13th conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x30" size="0" name="SQR2" access="Read/Write" description="regular sequence register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="5" name="SQ12" description="12th conversion in regular&#xa;              sequence" />
-      <BitField start="20" size="5" name="SQ11" description="11th conversion in regular&#xa;              sequence" />
-      <BitField start="15" size="5" name="SQ10" description="10th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ9" description="9th conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ8" description="8th conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ7" description="7th conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x34" size="0" name="SQR3" access="Read/Write" description="regular sequence register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="5" name="SQ6" description="6th conversion in regular&#xa;              sequence" />
-      <BitField start="20" size="5" name="SQ5" description="5th conversion in regular&#xa;              sequence" />
-      <BitField start="15" size="5" name="SQ4" description="4th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ3" description="3rd conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ2" description="2nd conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ1" description="1st conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x38" size="0" name="JSQR" access="Read/Write" description="injected sequence register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="2" name="JL" description="Injected sequence length" />
-      <BitField start="15" size="5" name="JSQ4" description="4th conversion in injected&#xa;              sequence" />
-      <BitField start="10" size="5" name="JSQ3" description="3rd conversion in injected&#xa;              sequence" />
-      <BitField start="5" size="5" name="JSQ2" description="2nd conversion in injected&#xa;              sequence" />
-      <BitField start="0" size="5" name="JSQ1" description="1st conversion in injected&#xa;              sequence" />
-    </Register>
-    <Register start="+0x3C" size="0" name="JDR1" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x40" size="0" name="JDR2" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x44" size="0" name="JDR3" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x48" size="0" name="JDR4" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DR" access="ReadOnly" description="regular data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Regular data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC2" start="0x40012100" description="Analog-to-digital converter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="OVR" description="Overrun" />
-      <BitField start="4" size="1" name="STRT" description="Regular channel start flag" />
-      <BitField start="3" size="1" name="JSTRT" description="Injected channel start&#xa;              flag" />
-      <BitField start="2" size="1" name="JEOC" description="Injected channel end of&#xa;              conversion" />
-      <BitField start="1" size="1" name="EOC" description="Regular channel end of&#xa;              conversion" />
-      <BitField start="0" size="1" name="AWD" description="Analog watchdog flag" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="26" size="1" name="OVRIE" description="Overrun interrupt enable" />
-      <BitField start="24" size="2" name="RES" description="Resolution" />
-      <BitField start="23" size="1" name="AWDEN" description="Analog watchdog enable on regular&#xa;              channels" />
-      <BitField start="22" size="1" name="JAWDEN" description="Analog watchdog enable on injected&#xa;              channels" />
-      <BitField start="13" size="3" name="DISCNUM" description="Discontinuous mode channel&#xa;              count" />
-      <BitField start="12" size="1" name="JDISCEN" description="Discontinuous mode on injected&#xa;              channels" />
-      <BitField start="11" size="1" name="DISCEN" description="Discontinuous mode on regular&#xa;              channels" />
-      <BitField start="10" size="1" name="JAUTO" description="Automatic injected group&#xa;              conversion" />
-      <BitField start="9" size="1" name="AWDSGL" description="Enable the watchdog on a single channel&#xa;              in scan mode" />
-      <BitField start="8" size="1" name="SCAN" description="Scan mode" />
-      <BitField start="7" size="1" name="JEOCIE" description="Interrupt enable for injected&#xa;              channels" />
-      <BitField start="6" size="1" name="AWDIE" description="Analog watchdog interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="EOCIE" description="Interrupt enable for EOC" />
-      <BitField start="0" size="5" name="AWDCH" description="Analog watchdog channel select&#xa;              bits" />
-    </Register>
-    <Register start="+0x8" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="1" name="SWSTART" description="Start conversion of regular&#xa;              channels" />
-      <BitField start="28" size="2" name="EXTEN" description="External trigger enable for regular&#xa;              channels" />
-      <BitField start="24" size="4" name="EXTSEL" description="External event select for regular&#xa;              group" />
-      <BitField start="22" size="1" name="JSWSTART" description="Start conversion of injected&#xa;              channels" />
-      <BitField start="20" size="2" name="JEXTEN" description="External trigger enable for injected&#xa;              channels" />
-      <BitField start="16" size="4" name="JEXTSEL" description="External event select for injected&#xa;              group" />
-      <BitField start="11" size="1" name="ALIGN" description="Data alignment" />
-      <BitField start="10" size="1" name="EOCS" description="End of conversion&#xa;              selection" />
-      <BitField start="9" size="1" name="DDS" description="DMA disable selection (for single ADC&#xa;              mode)" />
-      <BitField start="8" size="1" name="DMA" description="Direct memory access mode (for single&#xa;              ADC mode)" />
-      <BitField start="1" size="1" name="CONT" description="Continuous conversion" />
-      <BitField start="0" size="1" name="ADON" description="A/D Converter ON / OFF" />
-    </Register>
-    <Register start="+0xC" size="0" name="SMPR1" access="Read/Write" description="sample time register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SMPx_x" description="Sample time bits" />
-    </Register>
-    <Register start="+0x10" size="0" name="SMPR2" access="Read/Write" description="sample time register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SMPx_x" description="Sample time bits" />
-    </Register>
-    <Register start="+0x14" size="0" name="JOFR1" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET1" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x18" size="0" name="JOFR2" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET2" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x1C" size="0" name="JOFR3" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET3" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x20" size="0" name="JOFR4" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET4" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x24" size="0" name="HTR" access="Read/Write" description="watchdog higher threshold&#xa;          register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="HT" description="Analog watchdog higher&#xa;              threshold" />
-    </Register>
-    <Register start="+0x28" size="0" name="LTR" access="Read/Write" description="watchdog lower threshold&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="LT" description="Analog watchdog lower&#xa;              threshold" />
-    </Register>
-    <Register start="+0x2C" size="0" name="SQR1" access="Read/Write" description="regular sequence register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="4" name="L" description="Regular channel sequence&#xa;              length" />
-      <BitField start="15" size="5" name="SQ16" description="16th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ15" description="15th conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ14" description="14th conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ13" description="13th conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x30" size="0" name="SQR2" access="Read/Write" description="regular sequence register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="5" name="SQ12" description="12th conversion in regular&#xa;              sequence" />
-      <BitField start="20" size="5" name="SQ11" description="11th conversion in regular&#xa;              sequence" />
-      <BitField start="15" size="5" name="SQ10" description="10th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ9" description="9th conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ8" description="8th conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ7" description="7th conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x34" size="0" name="SQR3" access="Read/Write" description="regular sequence register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="5" name="SQ6" description="6th conversion in regular&#xa;              sequence" />
-      <BitField start="20" size="5" name="SQ5" description="5th conversion in regular&#xa;              sequence" />
-      <BitField start="15" size="5" name="SQ4" description="4th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ3" description="3rd conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ2" description="2nd conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ1" description="1st conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x38" size="0" name="JSQR" access="Read/Write" description="injected sequence register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="2" name="JL" description="Injected sequence length" />
-      <BitField start="15" size="5" name="JSQ4" description="4th conversion in injected&#xa;              sequence" />
-      <BitField start="10" size="5" name="JSQ3" description="3rd conversion in injected&#xa;              sequence" />
-      <BitField start="5" size="5" name="JSQ2" description="2nd conversion in injected&#xa;              sequence" />
-      <BitField start="0" size="5" name="JSQ1" description="1st conversion in injected&#xa;              sequence" />
-    </Register>
-    <Register start="+0x3C" size="0" name="JDR1" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x40" size="0" name="JDR2" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x44" size="0" name="JDR3" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x48" size="0" name="JDR4" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DR" access="ReadOnly" description="regular data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Regular data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC3" start="0x40012200" description="Analog-to-digital converter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="OVR" description="Overrun" />
-      <BitField start="4" size="1" name="STRT" description="Regular channel start flag" />
-      <BitField start="3" size="1" name="JSTRT" description="Injected channel start&#xa;              flag" />
-      <BitField start="2" size="1" name="JEOC" description="Injected channel end of&#xa;              conversion" />
-      <BitField start="1" size="1" name="EOC" description="Regular channel end of&#xa;              conversion" />
-      <BitField start="0" size="1" name="AWD" description="Analog watchdog flag" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="26" size="1" name="OVRIE" description="Overrun interrupt enable" />
-      <BitField start="24" size="2" name="RES" description="Resolution" />
-      <BitField start="23" size="1" name="AWDEN" description="Analog watchdog enable on regular&#xa;              channels" />
-      <BitField start="22" size="1" name="JAWDEN" description="Analog watchdog enable on injected&#xa;              channels" />
-      <BitField start="13" size="3" name="DISCNUM" description="Discontinuous mode channel&#xa;              count" />
-      <BitField start="12" size="1" name="JDISCEN" description="Discontinuous mode on injected&#xa;              channels" />
-      <BitField start="11" size="1" name="DISCEN" description="Discontinuous mode on regular&#xa;              channels" />
-      <BitField start="10" size="1" name="JAUTO" description="Automatic injected group&#xa;              conversion" />
-      <BitField start="9" size="1" name="AWDSGL" description="Enable the watchdog on a single channel&#xa;              in scan mode" />
-      <BitField start="8" size="1" name="SCAN" description="Scan mode" />
-      <BitField start="7" size="1" name="JEOCIE" description="Interrupt enable for injected&#xa;              channels" />
-      <BitField start="6" size="1" name="AWDIE" description="Analog watchdog interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="EOCIE" description="Interrupt enable for EOC" />
-      <BitField start="0" size="5" name="AWDCH" description="Analog watchdog channel select&#xa;              bits" />
-    </Register>
-    <Register start="+0x8" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="30" size="1" name="SWSTART" description="Start conversion of regular&#xa;              channels" />
-      <BitField start="28" size="2" name="EXTEN" description="External trigger enable for regular&#xa;              channels" />
-      <BitField start="24" size="4" name="EXTSEL" description="External event select for regular&#xa;              group" />
-      <BitField start="22" size="1" name="JSWSTART" description="Start conversion of injected&#xa;              channels" />
-      <BitField start="20" size="2" name="JEXTEN" description="External trigger enable for injected&#xa;              channels" />
-      <BitField start="16" size="4" name="JEXTSEL" description="External event select for injected&#xa;              group" />
-      <BitField start="11" size="1" name="ALIGN" description="Data alignment" />
-      <BitField start="10" size="1" name="EOCS" description="End of conversion&#xa;              selection" />
-      <BitField start="9" size="1" name="DDS" description="DMA disable selection (for single ADC&#xa;              mode)" />
-      <BitField start="8" size="1" name="DMA" description="Direct memory access mode (for single&#xa;              ADC mode)" />
-      <BitField start="1" size="1" name="CONT" description="Continuous conversion" />
-      <BitField start="0" size="1" name="ADON" description="A/D Converter ON / OFF" />
-    </Register>
-    <Register start="+0xC" size="0" name="SMPR1" access="Read/Write" description="sample time register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SMPx_x" description="Sample time bits" />
-    </Register>
-    <Register start="+0x10" size="0" name="SMPR2" access="Read/Write" description="sample time register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SMPx_x" description="Sample time bits" />
-    </Register>
-    <Register start="+0x14" size="0" name="JOFR1" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET1" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x18" size="0" name="JOFR2" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET2" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x1C" size="0" name="JOFR3" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET3" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x20" size="0" name="JOFR4" access="Read/Write" description="injected channel data offset register&#xa;          x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="JOFFSET4" description="Data offset for injected channel&#xa;              x" />
-    </Register>
-    <Register start="+0x24" size="0" name="HTR" access="Read/Write" description="watchdog higher threshold&#xa;          register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="HT" description="Analog watchdog higher&#xa;              threshold" />
-    </Register>
-    <Register start="+0x28" size="0" name="LTR" access="Read/Write" description="watchdog lower threshold&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="LT" description="Analog watchdog lower&#xa;              threshold" />
-    </Register>
-    <Register start="+0x2C" size="0" name="SQR1" access="Read/Write" description="regular sequence register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="4" name="L" description="Regular channel sequence&#xa;              length" />
-      <BitField start="15" size="5" name="SQ16" description="16th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ15" description="15th conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ14" description="14th conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ13" description="13th conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x30" size="0" name="SQR2" access="Read/Write" description="regular sequence register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="5" name="SQ12" description="12th conversion in regular&#xa;              sequence" />
-      <BitField start="20" size="5" name="SQ11" description="11th conversion in regular&#xa;              sequence" />
-      <BitField start="15" size="5" name="SQ10" description="10th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ9" description="9th conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ8" description="8th conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ7" description="7th conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x34" size="0" name="SQR3" access="Read/Write" description="regular sequence register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="25" size="5" name="SQ6" description="6th conversion in regular&#xa;              sequence" />
-      <BitField start="20" size="5" name="SQ5" description="5th conversion in regular&#xa;              sequence" />
-      <BitField start="15" size="5" name="SQ4" description="4th conversion in regular&#xa;              sequence" />
-      <BitField start="10" size="5" name="SQ3" description="3rd conversion in regular&#xa;              sequence" />
-      <BitField start="5" size="5" name="SQ2" description="2nd conversion in regular&#xa;              sequence" />
-      <BitField start="0" size="5" name="SQ1" description="1st conversion in regular&#xa;              sequence" />
-    </Register>
-    <Register start="+0x38" size="0" name="JSQR" access="Read/Write" description="injected sequence register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="2" name="JL" description="Injected sequence length" />
-      <BitField start="15" size="5" name="JSQ4" description="4th conversion in injected&#xa;              sequence" />
-      <BitField start="10" size="5" name="JSQ3" description="3rd conversion in injected&#xa;              sequence" />
-      <BitField start="5" size="5" name="JSQ2" description="2nd conversion in injected&#xa;              sequence" />
-      <BitField start="0" size="5" name="JSQ1" description="1st conversion in injected&#xa;              sequence" />
-    </Register>
-    <Register start="+0x3C" size="0" name="JDR1" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x40" size="0" name="JDR2" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x44" size="0" name="JDR3" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x48" size="0" name="JDR4" access="ReadOnly" description="injected data register x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="JDATA" description="Injected data" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DR" access="ReadOnly" description="regular data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Regular data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART6" start="0x40011400" description="Universal synchronous asynchronous receiver&#xa;      transmitter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00C00000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CTS" description="CTS flag" />
-      <BitField start="8" size="1" name="LBD" description="LIN break detection flag" />
-      <BitField start="7" size="1" name="TXE" description="Transmit data register&#xa;              empty" />
-      <BitField start="6" size="1" name="TC" description="Transmission complete" />
-      <BitField start="5" size="1" name="RXNE" description="Read data register not&#xa;              empty" />
-      <BitField start="4" size="1" name="IDLE" description="IDLE line detected" />
-      <BitField start="3" size="1" name="ORE" description="Overrun error" />
-      <BitField start="2" size="1" name="NF" description="Noise detected flag" />
-      <BitField start="1" size="1" name="FE" description="Framing error" />
-      <BitField start="0" size="1" name="PE" description="Parity error" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DR" description="Data value" />
-    </Register>
-    <Register start="+0x8" size="0" name="BRR" access="Read/Write" description="Baud rate register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DIV_Mantissa" description="mantissa of USARTDIV" />
-      <BitField start="0" size="4" name="DIV_Fraction" description="fraction of USARTDIV" />
-    </Register>
-    <Register start="+0xC" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OVER8" description="Oversampling mode" />
-      <BitField start="13" size="1" name="UE" description="USART enable" />
-      <BitField start="12" size="1" name="M" description="Word length" />
-      <BitField start="11" size="1" name="WAKE" description="Wakeup method" />
-      <BitField start="10" size="1" name="PCE" description="Parity control enable" />
-      <BitField start="9" size="1" name="PS" description="Parity selection" />
-      <BitField start="8" size="1" name="PEIE" description="PE interrupt enable" />
-      <BitField start="7" size="1" name="TXEIE" description="TXE interrupt enable" />
-      <BitField start="6" size="1" name="TCIE" description="Transmission complete interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXNEIE" description="RXNE interrupt enable" />
-      <BitField start="4" size="1" name="IDLEIE" description="IDLE interrupt enable" />
-      <BitField start="3" size="1" name="TE" description="Transmitter enable" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable" />
-      <BitField start="1" size="1" name="RWU" description="Receiver wakeup" />
-      <BitField start="0" size="1" name="SBK" description="Send break" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="LINEN" description="LIN mode enable" />
-      <BitField start="12" size="2" name="STOP" description="STOP bits" />
-      <BitField start="11" size="1" name="CLKEN" description="Clock enable" />
-      <BitField start="10" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="9" size="1" name="CPHA" description="Clock phase" />
-      <BitField start="8" size="1" name="LBCL" description="Last bit clock pulse" />
-      <BitField start="6" size="1" name="LBDIE" description="LIN break detection interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="LBDL" description="lin break detection length" />
-      <BitField start="0" size="4" name="ADD" description="Address of the USART node" />
-    </Register>
-    <Register start="+0x14" size="0" name="CR3" access="Read/Write" description="Control register 3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="ONEBIT" description="One sample bit method&#xa;              enable" />
-      <BitField start="10" size="1" name="CTSIE" description="CTS interrupt enable" />
-      <BitField start="9" size="1" name="CTSE" description="CTS enable" />
-      <BitField start="8" size="1" name="RTSE" description="RTS enable" />
-      <BitField start="7" size="1" name="DMAT" description="DMA enable transmitter" />
-      <BitField start="6" size="1" name="DMAR" description="DMA enable receiver" />
-      <BitField start="5" size="1" name="SCEN" description="Smartcard mode enable" />
-      <BitField start="4" size="1" name="NACK" description="Smartcard NACK enable" />
-      <BitField start="3" size="1" name="HDSEL" description="Half-duplex selection" />
-      <BitField start="2" size="1" name="IRLP" description="IrDA low-power" />
-      <BitField start="1" size="1" name="IREN" description="IrDA mode enable" />
-      <BitField start="0" size="1" name="EIE" description="Error interrupt enable" />
-    </Register>
-    <Register start="+0x18" size="0" name="GTPR" access="Read/Write" description="Guard time and prescaler&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="GT" description="Guard time value" />
-      <BitField start="0" size="8" name="PSC" description="Prescaler value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART1" start="0x40011000" description="Universal synchronous asynchronous receiver&#xa;      transmitter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00C00000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CTS" description="CTS flag" />
-      <BitField start="8" size="1" name="LBD" description="LIN break detection flag" />
-      <BitField start="7" size="1" name="TXE" description="Transmit data register&#xa;              empty" />
-      <BitField start="6" size="1" name="TC" description="Transmission complete" />
-      <BitField start="5" size="1" name="RXNE" description="Read data register not&#xa;              empty" />
-      <BitField start="4" size="1" name="IDLE" description="IDLE line detected" />
-      <BitField start="3" size="1" name="ORE" description="Overrun error" />
-      <BitField start="2" size="1" name="NF" description="Noise detected flag" />
-      <BitField start="1" size="1" name="FE" description="Framing error" />
-      <BitField start="0" size="1" name="PE" description="Parity error" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DR" description="Data value" />
-    </Register>
-    <Register start="+0x8" size="0" name="BRR" access="Read/Write" description="Baud rate register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DIV_Mantissa" description="mantissa of USARTDIV" />
-      <BitField start="0" size="4" name="DIV_Fraction" description="fraction of USARTDIV" />
-    </Register>
-    <Register start="+0xC" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OVER8" description="Oversampling mode" />
-      <BitField start="13" size="1" name="UE" description="USART enable" />
-      <BitField start="12" size="1" name="M" description="Word length" />
-      <BitField start="11" size="1" name="WAKE" description="Wakeup method" />
-      <BitField start="10" size="1" name="PCE" description="Parity control enable" />
-      <BitField start="9" size="1" name="PS" description="Parity selection" />
-      <BitField start="8" size="1" name="PEIE" description="PE interrupt enable" />
-      <BitField start="7" size="1" name="TXEIE" description="TXE interrupt enable" />
-      <BitField start="6" size="1" name="TCIE" description="Transmission complete interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXNEIE" description="RXNE interrupt enable" />
-      <BitField start="4" size="1" name="IDLEIE" description="IDLE interrupt enable" />
-      <BitField start="3" size="1" name="TE" description="Transmitter enable" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable" />
-      <BitField start="1" size="1" name="RWU" description="Receiver wakeup" />
-      <BitField start="0" size="1" name="SBK" description="Send break" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="LINEN" description="LIN mode enable" />
-      <BitField start="12" size="2" name="STOP" description="STOP bits" />
-      <BitField start="11" size="1" name="CLKEN" description="Clock enable" />
-      <BitField start="10" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="9" size="1" name="CPHA" description="Clock phase" />
-      <BitField start="8" size="1" name="LBCL" description="Last bit clock pulse" />
-      <BitField start="6" size="1" name="LBDIE" description="LIN break detection interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="LBDL" description="lin break detection length" />
-      <BitField start="0" size="4" name="ADD" description="Address of the USART node" />
-    </Register>
-    <Register start="+0x14" size="0" name="CR3" access="Read/Write" description="Control register 3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="ONEBIT" description="One sample bit method&#xa;              enable" />
-      <BitField start="10" size="1" name="CTSIE" description="CTS interrupt enable" />
-      <BitField start="9" size="1" name="CTSE" description="CTS enable" />
-      <BitField start="8" size="1" name="RTSE" description="RTS enable" />
-      <BitField start="7" size="1" name="DMAT" description="DMA enable transmitter" />
-      <BitField start="6" size="1" name="DMAR" description="DMA enable receiver" />
-      <BitField start="5" size="1" name="SCEN" description="Smartcard mode enable" />
-      <BitField start="4" size="1" name="NACK" description="Smartcard NACK enable" />
-      <BitField start="3" size="1" name="HDSEL" description="Half-duplex selection" />
-      <BitField start="2" size="1" name="IRLP" description="IrDA low-power" />
-      <BitField start="1" size="1" name="IREN" description="IrDA mode enable" />
-      <BitField start="0" size="1" name="EIE" description="Error interrupt enable" />
-    </Register>
-    <Register start="+0x18" size="0" name="GTPR" access="Read/Write" description="Guard time and prescaler&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="GT" description="Guard time value" />
-      <BitField start="0" size="8" name="PSC" description="Prescaler value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x40004400" description="Universal synchronous asynchronous receiver&#xa;      transmitter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00C00000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CTS" description="CTS flag" />
-      <BitField start="8" size="1" name="LBD" description="LIN break detection flag" />
-      <BitField start="7" size="1" name="TXE" description="Transmit data register&#xa;              empty" />
-      <BitField start="6" size="1" name="TC" description="Transmission complete" />
-      <BitField start="5" size="1" name="RXNE" description="Read data register not&#xa;              empty" />
-      <BitField start="4" size="1" name="IDLE" description="IDLE line detected" />
-      <BitField start="3" size="1" name="ORE" description="Overrun error" />
-      <BitField start="2" size="1" name="NF" description="Noise detected flag" />
-      <BitField start="1" size="1" name="FE" description="Framing error" />
-      <BitField start="0" size="1" name="PE" description="Parity error" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DR" description="Data value" />
-    </Register>
-    <Register start="+0x8" size="0" name="BRR" access="Read/Write" description="Baud rate register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DIV_Mantissa" description="mantissa of USARTDIV" />
-      <BitField start="0" size="4" name="DIV_Fraction" description="fraction of USARTDIV" />
-    </Register>
-    <Register start="+0xC" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OVER8" description="Oversampling mode" />
-      <BitField start="13" size="1" name="UE" description="USART enable" />
-      <BitField start="12" size="1" name="M" description="Word length" />
-      <BitField start="11" size="1" name="WAKE" description="Wakeup method" />
-      <BitField start="10" size="1" name="PCE" description="Parity control enable" />
-      <BitField start="9" size="1" name="PS" description="Parity selection" />
-      <BitField start="8" size="1" name="PEIE" description="PE interrupt enable" />
-      <BitField start="7" size="1" name="TXEIE" description="TXE interrupt enable" />
-      <BitField start="6" size="1" name="TCIE" description="Transmission complete interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXNEIE" description="RXNE interrupt enable" />
-      <BitField start="4" size="1" name="IDLEIE" description="IDLE interrupt enable" />
-      <BitField start="3" size="1" name="TE" description="Transmitter enable" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable" />
-      <BitField start="1" size="1" name="RWU" description="Receiver wakeup" />
-      <BitField start="0" size="1" name="SBK" description="Send break" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="LINEN" description="LIN mode enable" />
-      <BitField start="12" size="2" name="STOP" description="STOP bits" />
-      <BitField start="11" size="1" name="CLKEN" description="Clock enable" />
-      <BitField start="10" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="9" size="1" name="CPHA" description="Clock phase" />
-      <BitField start="8" size="1" name="LBCL" description="Last bit clock pulse" />
-      <BitField start="6" size="1" name="LBDIE" description="LIN break detection interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="LBDL" description="lin break detection length" />
-      <BitField start="0" size="4" name="ADD" description="Address of the USART node" />
-    </Register>
-    <Register start="+0x14" size="0" name="CR3" access="Read/Write" description="Control register 3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="ONEBIT" description="One sample bit method&#xa;              enable" />
-      <BitField start="10" size="1" name="CTSIE" description="CTS interrupt enable" />
-      <BitField start="9" size="1" name="CTSE" description="CTS enable" />
-      <BitField start="8" size="1" name="RTSE" description="RTS enable" />
-      <BitField start="7" size="1" name="DMAT" description="DMA enable transmitter" />
-      <BitField start="6" size="1" name="DMAR" description="DMA enable receiver" />
-      <BitField start="5" size="1" name="SCEN" description="Smartcard mode enable" />
-      <BitField start="4" size="1" name="NACK" description="Smartcard NACK enable" />
-      <BitField start="3" size="1" name="HDSEL" description="Half-duplex selection" />
-      <BitField start="2" size="1" name="IRLP" description="IrDA low-power" />
-      <BitField start="1" size="1" name="IREN" description="IrDA mode enable" />
-      <BitField start="0" size="1" name="EIE" description="Error interrupt enable" />
-    </Register>
-    <Register start="+0x18" size="0" name="GTPR" access="Read/Write" description="Guard time and prescaler&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="GT" description="Guard time value" />
-      <BitField start="0" size="8" name="PSC" description="Prescaler value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x40004800" description="Universal synchronous asynchronous receiver&#xa;      transmitter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00C00000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CTS" description="CTS flag" />
-      <BitField start="8" size="1" name="LBD" description="LIN break detection flag" />
-      <BitField start="7" size="1" name="TXE" description="Transmit data register&#xa;              empty" />
-      <BitField start="6" size="1" name="TC" description="Transmission complete" />
-      <BitField start="5" size="1" name="RXNE" description="Read data register not&#xa;              empty" />
-      <BitField start="4" size="1" name="IDLE" description="IDLE line detected" />
-      <BitField start="3" size="1" name="ORE" description="Overrun error" />
-      <BitField start="2" size="1" name="NF" description="Noise detected flag" />
-      <BitField start="1" size="1" name="FE" description="Framing error" />
-      <BitField start="0" size="1" name="PE" description="Parity error" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DR" description="Data value" />
-    </Register>
-    <Register start="+0x8" size="0" name="BRR" access="Read/Write" description="Baud rate register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DIV_Mantissa" description="mantissa of USARTDIV" />
-      <BitField start="0" size="4" name="DIV_Fraction" description="fraction of USARTDIV" />
-    </Register>
-    <Register start="+0xC" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OVER8" description="Oversampling mode" />
-      <BitField start="13" size="1" name="UE" description="USART enable" />
-      <BitField start="12" size="1" name="M" description="Word length" />
-      <BitField start="11" size="1" name="WAKE" description="Wakeup method" />
-      <BitField start="10" size="1" name="PCE" description="Parity control enable" />
-      <BitField start="9" size="1" name="PS" description="Parity selection" />
-      <BitField start="8" size="1" name="PEIE" description="PE interrupt enable" />
-      <BitField start="7" size="1" name="TXEIE" description="TXE interrupt enable" />
-      <BitField start="6" size="1" name="TCIE" description="Transmission complete interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXNEIE" description="RXNE interrupt enable" />
-      <BitField start="4" size="1" name="IDLEIE" description="IDLE interrupt enable" />
-      <BitField start="3" size="1" name="TE" description="Transmitter enable" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable" />
-      <BitField start="1" size="1" name="RWU" description="Receiver wakeup" />
-      <BitField start="0" size="1" name="SBK" description="Send break" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="LINEN" description="LIN mode enable" />
-      <BitField start="12" size="2" name="STOP" description="STOP bits" />
-      <BitField start="11" size="1" name="CLKEN" description="Clock enable" />
-      <BitField start="10" size="1" name="CPOL" description="Clock polarity" />
-      <BitField start="9" size="1" name="CPHA" description="Clock phase" />
-      <BitField start="8" size="1" name="LBCL" description="Last bit clock pulse" />
-      <BitField start="6" size="1" name="LBDIE" description="LIN break detection interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="LBDL" description="lin break detection length" />
-      <BitField start="0" size="4" name="ADD" description="Address of the USART node" />
-    </Register>
-    <Register start="+0x14" size="0" name="CR3" access="Read/Write" description="Control register 3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="ONEBIT" description="One sample bit method&#xa;              enable" />
-      <BitField start="10" size="1" name="CTSIE" description="CTS interrupt enable" />
-      <BitField start="9" size="1" name="CTSE" description="CTS enable" />
-      <BitField start="8" size="1" name="RTSE" description="RTS enable" />
-      <BitField start="7" size="1" name="DMAT" description="DMA enable transmitter" />
-      <BitField start="6" size="1" name="DMAR" description="DMA enable receiver" />
-      <BitField start="5" size="1" name="SCEN" description="Smartcard mode enable" />
-      <BitField start="4" size="1" name="NACK" description="Smartcard NACK enable" />
-      <BitField start="3" size="1" name="HDSEL" description="Half-duplex selection" />
-      <BitField start="2" size="1" name="IRLP" description="IrDA low-power" />
-      <BitField start="1" size="1" name="IREN" description="IrDA mode enable" />
-      <BitField start="0" size="1" name="EIE" description="Error interrupt enable" />
-    </Register>
-    <Register start="+0x18" size="0" name="GTPR" access="Read/Write" description="Guard time and prescaler&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="GT" description="Guard time value" />
-      <BitField start="0" size="8" name="PSC" description="Prescaler value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x40007400" description="Digital-to-analog converter">
-    <Register start="+0x0" size="0" name="CR" access="Read/Write" description="control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="1" name="DMAUDRIE2" description="DAC channel2 DMA underrun interrupt&#xa;              enable" />
-      <BitField start="28" size="1" name="DMAEN2" description="DAC channel2 DMA enable" />
-      <BitField start="24" size="4" name="MAMP2" description="DAC channel2 mask/amplitude&#xa;              selector" />
-      <BitField start="22" size="2" name="WAVE2" description="DAC channel2 noise/triangle wave&#xa;              generation enable" />
-      <BitField start="19" size="3" name="TSEL2" description="DAC channel2 trigger&#xa;              selection" />
-      <BitField start="18" size="1" name="TEN2" description="DAC channel2 trigger&#xa;              enable" />
-      <BitField start="17" size="1" name="BOFF2" description="DAC channel2 output buffer&#xa;              disable" />
-      <BitField start="16" size="1" name="EN2" description="DAC channel2 enable" />
-      <BitField start="13" size="1" name="DMAUDRIE1" description="DAC channel1 DMA Underrun Interrupt&#xa;              enable" />
-      <BitField start="12" size="1" name="DMAEN1" description="DAC channel1 DMA enable" />
-      <BitField start="8" size="4" name="MAMP1" description="DAC channel1 mask/amplitude&#xa;              selector" />
-      <BitField start="6" size="2" name="WAVE1" description="DAC channel1 noise/triangle wave&#xa;              generation enable" />
-      <BitField start="3" size="3" name="TSEL1" description="DAC channel1 trigger&#xa;              selection" />
-      <BitField start="2" size="1" name="TEN1" description="DAC channel1 trigger&#xa;              enable" />
-      <BitField start="1" size="1" name="BOFF1" description="DAC channel1 output buffer&#xa;              disable" />
-      <BitField start="0" size="1" name="EN1" description="DAC channel1 enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="SWTRIGR" access="WriteOnly" description="software trigger register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="SWTRIG2" description="DAC channel2 software&#xa;              trigger" />
-      <BitField start="0" size="1" name="SWTRIG1" description="DAC channel1 software&#xa;              trigger" />
-    </Register>
-    <Register start="+0x8" size="0" name="DHR12R1" access="Read/Write" description="channel1 12-bit right-aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DACC1DHR" description="DAC channel1 12-bit right-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0xC" size="0" name="DHR12L1" access="Read/Write" description="channel1 12-bit left aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DACC1DHR" description="DAC channel1 12-bit left-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x10" size="0" name="DHR8R1" access="Read/Write" description="channel1 8-bit right aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DACC1DHR" description="DAC channel1 8-bit right-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x14" size="0" name="DHR12R2" access="Read/Write" description="channel2 12-bit right aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DACC2DHR" description="DAC channel2 12-bit right-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x18" size="0" name="DHR12L2" access="Read/Write" description="channel2 12-bit left aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DACC2DHR" description="DAC channel2 12-bit left-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x1C" size="0" name="DHR8R2" access="Read/Write" description="channel2 8-bit right-aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DACC2DHR" description="DAC channel2 8-bit right-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x20" size="0" name="DHR12RD" access="Read/Write" description="Dual DAC 12-bit right-aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="12" name="DACC2DHR" description="DAC channel2 12-bit right-aligned&#xa;              data" />
-      <BitField start="0" size="12" name="DACC1DHR" description="DAC channel1 12-bit right-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x24" size="0" name="DHR12LD" access="Read/Write" description="DUAL DAC 12-bit left aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="12" name="DACC2DHR" description="DAC channel2 12-bit left-aligned&#xa;              data" />
-      <BitField start="4" size="12" name="DACC1DHR" description="DAC channel1 12-bit left-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x28" size="0" name="DHR8RD" access="Read/Write" description="DUAL DAC 8-bit right aligned data holding&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="DACC2DHR" description="DAC channel2 8-bit right-aligned&#xa;              data" />
-      <BitField start="0" size="8" name="DACC1DHR" description="DAC channel1 8-bit right-aligned&#xa;              data" />
-    </Register>
-    <Register start="+0x2C" size="0" name="DOR1" access="ReadOnly" description="channel1 data output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DACC1DOR" description="DAC channel1 data output" />
-    </Register>
-    <Register start="+0x30" size="0" name="DOR2" access="ReadOnly" description="channel2 data output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DACC2DOR" description="DAC channel2 data output" />
-    </Register>
-    <Register start="+0x34" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="1" name="DMAUDR2" description="DAC channel2 DMA underrun&#xa;              flag" />
-      <BitField start="13" size="1" name="DMAUDR1" description="DAC channel1 DMA underrun&#xa;              flag" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWR" start="0x40007000" description="Power control">
-    <Register start="+0x0" size="0" name="CR" access="Read/Write" description="power control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="FPDS" description="Flash power down in Stop&#xa;              mode" />
-      <BitField start="8" size="1" name="DBP" description="Disable backup domain write&#xa;              protection" />
-      <BitField start="5" size="3" name="PLS" description="PVD level selection" />
-      <BitField start="4" size="1" name="PVDE" description="Power voltage detector&#xa;              enable" />
-      <BitField start="3" size="1" name="CSBF" description="Clear standby flag" />
-      <BitField start="2" size="1" name="CWUF" description="Clear wakeup flag" />
-      <BitField start="1" size="1" name="PDDS" description="Power down deepsleep" />
-      <BitField start="0" size="1" name="LPDS" description="Low-power deep sleep" />
-    </Register>
-    <Register start="+0x4" size="0" name="CSR" access="Read/Write" description="power control/status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WUF" description="Wakeup flag" />
-      <BitField start="1" size="1" name="SBF" description="Standby flag" />
-      <BitField start="2" size="1" name="PVDO" description="PVD output" />
-      <BitField start="3" size="1" name="BRR" description="Backup regulator ready" />
-      <BitField start="8" size="1" name="EWUP" description="Enable WKUP pin" />
-      <BitField start="9" size="1" name="BRE" description="Backup regulator enable" />
-      <BitField start="14" size="1" name="VOSRDY" description="Regulator voltage scaling output&#xa;              selection ready bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C3" start="0x40005C00" description="Inter-integrated circuit">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="SWRST" description="Software reset" />
-      <BitField start="13" size="1" name="ALERT" description="SMBus alert" />
-      <BitField start="12" size="1" name="PEC" description="Packet error checking" />
-      <BitField start="11" size="1" name="POS" description="Acknowledge/PEC Position (for data&#xa;              reception)" />
-      <BitField start="10" size="1" name="ACK" description="Acknowledge enable" />
-      <BitField start="9" size="1" name="STOP" description="Stop generation" />
-      <BitField start="8" size="1" name="START" description="Start generation" />
-      <BitField start="7" size="1" name="NOSTRETCH" description="Clock stretching disable (Slave&#xa;              mode)" />
-      <BitField start="6" size="1" name="ENGC" description="General call enable" />
-      <BitField start="5" size="1" name="ENPEC" description="PEC enable" />
-      <BitField start="4" size="1" name="ENARP" description="ARP enable" />
-      <BitField start="3" size="1" name="SMBTYPE" description="SMBus type" />
-      <BitField start="1" size="1" name="SMBUS" description="SMBus mode" />
-      <BitField start="0" size="1" name="PE" description="Peripheral enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="LAST" description="DMA last transfer" />
-      <BitField start="11" size="1" name="DMAEN" description="DMA requests enable" />
-      <BitField start="10" size="1" name="ITBUFEN" description="Buffer interrupt enable" />
-      <BitField start="9" size="1" name="ITEVTEN" description="Event interrupt enable" />
-      <BitField start="8" size="1" name="ITERREN" description="Error interrupt enable" />
-      <BitField start="0" size="6" name="FREQ" description="Peripheral clock frequency" />
-    </Register>
-    <Register start="+0x8" size="0" name="OAR1" access="Read/Write" description="Own address register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ADDMODE" description="Addressing mode (slave&#xa;              mode)" />
-      <BitField start="8" size="2" name="ADD10" description="Interface address" />
-      <BitField start="1" size="7" name="ADD7" description="Interface address" />
-      <BitField start="0" size="1" name="ADD0" description="Interface address" />
-    </Register>
-    <Register start="+0xC" size="0" name="OAR2" access="Read/Write" description="Own address register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="7" name="ADD2" description="Interface address" />
-      <BitField start="0" size="1" name="ENDUAL" description="Dual addressing mode&#xa;              enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DR" description="8-bit data register" />
-    </Register>
-    <Register start="+0x14" size="0" name="SR1" access="Read/Write" description="Status register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="SMBALERT" description="SMBus alert" />
-      <BitField start="14" size="1" name="TIMEOUT" description="Timeout or Tlow error" />
-      <BitField start="12" size="1" name="PECERR" description="PEC Error in reception" />
-      <BitField start="11" size="1" name="OVR" description="Overrun/Underrun" />
-      <BitField start="10" size="1" name="AF" description="Acknowledge failure" />
-      <BitField start="9" size="1" name="ARLO" description="Arbitration lost (master&#xa;              mode)" />
-      <BitField start="8" size="1" name="BERR" description="Bus error" />
-      <BitField start="7" size="1" name="TxE" description="Data register empty&#xa;              (transmitters)" />
-      <BitField start="6" size="1" name="RxNE" description="Data register not empty&#xa;              (receivers)" />
-      <BitField start="4" size="1" name="STOPF" description="Stop detection (slave&#xa;              mode)" />
-      <BitField start="3" size="1" name="ADD10" description="10-bit header sent (Master&#xa;              mode)" />
-      <BitField start="2" size="1" name="BTF" description="Byte transfer finished" />
-      <BitField start="1" size="1" name="ADDR" description="Address sent (master mode)/matched&#xa;              (slave mode)" />
-      <BitField start="0" size="1" name="SB" description="Start bit (Master mode)" />
-    </Register>
-    <Register start="+0x18" size="0" name="SR2" access="ReadOnly" description="Status register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="PEC" description="acket error checking&#xa;              register" />
-      <BitField start="7" size="1" name="DUALF" description="Dual flag (Slave mode)" />
-      <BitField start="6" size="1" name="SMBHOST" description="SMBus host header (Slave&#xa;              mode)" />
-      <BitField start="5" size="1" name="SMBDEFAULT" description="SMBus device default address (Slave&#xa;              mode)" />
-      <BitField start="4" size="1" name="GENCALL" description="General call address (Slave&#xa;              mode)" />
-      <BitField start="2" size="1" name="TRA" description="Transmitter/receiver" />
-      <BitField start="1" size="1" name="BUSY" description="Bus busy" />
-      <BitField start="0" size="1" name="MSL" description="Master/slave" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCR" access="Read/Write" description="Clock control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="F_S" description="I2C master mode selection" />
-      <BitField start="14" size="1" name="DUTY" description="Fast mode duty cycle" />
-      <BitField start="0" size="12" name="CCR" description="Clock control register in Fast/Standard&#xa;              mode (Master mode)" />
-    </Register>
-    <Register start="+0x20" size="0" name="TRISE" access="Read/Write" description="TRISE register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TRISE" description="Maximum rise time in Fast/Standard mode&#xa;              (Master mode)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C2" start="0x40005800" description="Inter-integrated circuit">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="SWRST" description="Software reset" />
-      <BitField start="13" size="1" name="ALERT" description="SMBus alert" />
-      <BitField start="12" size="1" name="PEC" description="Packet error checking" />
-      <BitField start="11" size="1" name="POS" description="Acknowledge/PEC Position (for data&#xa;              reception)" />
-      <BitField start="10" size="1" name="ACK" description="Acknowledge enable" />
-      <BitField start="9" size="1" name="STOP" description="Stop generation" />
-      <BitField start="8" size="1" name="START" description="Start generation" />
-      <BitField start="7" size="1" name="NOSTRETCH" description="Clock stretching disable (Slave&#xa;              mode)" />
-      <BitField start="6" size="1" name="ENGC" description="General call enable" />
-      <BitField start="5" size="1" name="ENPEC" description="PEC enable" />
-      <BitField start="4" size="1" name="ENARP" description="ARP enable" />
-      <BitField start="3" size="1" name="SMBTYPE" description="SMBus type" />
-      <BitField start="1" size="1" name="SMBUS" description="SMBus mode" />
-      <BitField start="0" size="1" name="PE" description="Peripheral enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="LAST" description="DMA last transfer" />
-      <BitField start="11" size="1" name="DMAEN" description="DMA requests enable" />
-      <BitField start="10" size="1" name="ITBUFEN" description="Buffer interrupt enable" />
-      <BitField start="9" size="1" name="ITEVTEN" description="Event interrupt enable" />
-      <BitField start="8" size="1" name="ITERREN" description="Error interrupt enable" />
-      <BitField start="0" size="6" name="FREQ" description="Peripheral clock frequency" />
-    </Register>
-    <Register start="+0x8" size="0" name="OAR1" access="Read/Write" description="Own address register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ADDMODE" description="Addressing mode (slave&#xa;              mode)" />
-      <BitField start="8" size="2" name="ADD10" description="Interface address" />
-      <BitField start="1" size="7" name="ADD7" description="Interface address" />
-      <BitField start="0" size="1" name="ADD0" description="Interface address" />
-    </Register>
-    <Register start="+0xC" size="0" name="OAR2" access="Read/Write" description="Own address register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="7" name="ADD2" description="Interface address" />
-      <BitField start="0" size="1" name="ENDUAL" description="Dual addressing mode&#xa;              enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DR" description="8-bit data register" />
-    </Register>
-    <Register start="+0x14" size="0" name="SR1" access="Read/Write" description="Status register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="SMBALERT" description="SMBus alert" />
-      <BitField start="14" size="1" name="TIMEOUT" description="Timeout or Tlow error" />
-      <BitField start="12" size="1" name="PECERR" description="PEC Error in reception" />
-      <BitField start="11" size="1" name="OVR" description="Overrun/Underrun" />
-      <BitField start="10" size="1" name="AF" description="Acknowledge failure" />
-      <BitField start="9" size="1" name="ARLO" description="Arbitration lost (master&#xa;              mode)" />
-      <BitField start="8" size="1" name="BERR" description="Bus error" />
-      <BitField start="7" size="1" name="TxE" description="Data register empty&#xa;              (transmitters)" />
-      <BitField start="6" size="1" name="RxNE" description="Data register not empty&#xa;              (receivers)" />
-      <BitField start="4" size="1" name="STOPF" description="Stop detection (slave&#xa;              mode)" />
-      <BitField start="3" size="1" name="ADD10" description="10-bit header sent (Master&#xa;              mode)" />
-      <BitField start="2" size="1" name="BTF" description="Byte transfer finished" />
-      <BitField start="1" size="1" name="ADDR" description="Address sent (master mode)/matched&#xa;              (slave mode)" />
-      <BitField start="0" size="1" name="SB" description="Start bit (Master mode)" />
-    </Register>
-    <Register start="+0x18" size="0" name="SR2" access="ReadOnly" description="Status register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="PEC" description="acket error checking&#xa;              register" />
-      <BitField start="7" size="1" name="DUALF" description="Dual flag (Slave mode)" />
-      <BitField start="6" size="1" name="SMBHOST" description="SMBus host header (Slave&#xa;              mode)" />
-      <BitField start="5" size="1" name="SMBDEFAULT" description="SMBus device default address (Slave&#xa;              mode)" />
-      <BitField start="4" size="1" name="GENCALL" description="General call address (Slave&#xa;              mode)" />
-      <BitField start="2" size="1" name="TRA" description="Transmitter/receiver" />
-      <BitField start="1" size="1" name="BUSY" description="Bus busy" />
-      <BitField start="0" size="1" name="MSL" description="Master/slave" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCR" access="Read/Write" description="Clock control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="F_S" description="I2C master mode selection" />
-      <BitField start="14" size="1" name="DUTY" description="Fast mode duty cycle" />
-      <BitField start="0" size="12" name="CCR" description="Clock control register in Fast/Standard&#xa;              mode (Master mode)" />
-    </Register>
-    <Register start="+0x20" size="0" name="TRISE" access="Read/Write" description="TRISE register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TRISE" description="Maximum rise time in Fast/Standard mode&#xa;              (Master mode)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x40005400" description="Inter-integrated circuit">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="SWRST" description="Software reset" />
-      <BitField start="13" size="1" name="ALERT" description="SMBus alert" />
-      <BitField start="12" size="1" name="PEC" description="Packet error checking" />
-      <BitField start="11" size="1" name="POS" description="Acknowledge/PEC Position (for data&#xa;              reception)" />
-      <BitField start="10" size="1" name="ACK" description="Acknowledge enable" />
-      <BitField start="9" size="1" name="STOP" description="Stop generation" />
-      <BitField start="8" size="1" name="START" description="Start generation" />
-      <BitField start="7" size="1" name="NOSTRETCH" description="Clock stretching disable (Slave&#xa;              mode)" />
-      <BitField start="6" size="1" name="ENGC" description="General call enable" />
-      <BitField start="5" size="1" name="ENPEC" description="PEC enable" />
-      <BitField start="4" size="1" name="ENARP" description="ARP enable" />
-      <BitField start="3" size="1" name="SMBTYPE" description="SMBus type" />
-      <BitField start="1" size="1" name="SMBUS" description="SMBus mode" />
-      <BitField start="0" size="1" name="PE" description="Peripheral enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="LAST" description="DMA last transfer" />
-      <BitField start="11" size="1" name="DMAEN" description="DMA requests enable" />
-      <BitField start="10" size="1" name="ITBUFEN" description="Buffer interrupt enable" />
-      <BitField start="9" size="1" name="ITEVTEN" description="Event interrupt enable" />
-      <BitField start="8" size="1" name="ITERREN" description="Error interrupt enable" />
-      <BitField start="0" size="6" name="FREQ" description="Peripheral clock frequency" />
-    </Register>
-    <Register start="+0x8" size="0" name="OAR1" access="Read/Write" description="Own address register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ADDMODE" description="Addressing mode (slave&#xa;              mode)" />
-      <BitField start="8" size="2" name="ADD10" description="Interface address" />
-      <BitField start="1" size="7" name="ADD7" description="Interface address" />
-      <BitField start="0" size="1" name="ADD0" description="Interface address" />
-    </Register>
-    <Register start="+0xC" size="0" name="OAR2" access="Read/Write" description="Own address register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="7" name="ADD2" description="Interface address" />
-      <BitField start="0" size="1" name="ENDUAL" description="Dual addressing mode&#xa;              enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DR" description="8-bit data register" />
-    </Register>
-    <Register start="+0x14" size="0" name="SR1" access="Read/Write" description="Status register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="SMBALERT" description="SMBus alert" />
-      <BitField start="14" size="1" name="TIMEOUT" description="Timeout or Tlow error" />
-      <BitField start="12" size="1" name="PECERR" description="PEC Error in reception" />
-      <BitField start="11" size="1" name="OVR" description="Overrun/Underrun" />
-      <BitField start="10" size="1" name="AF" description="Acknowledge failure" />
-      <BitField start="9" size="1" name="ARLO" description="Arbitration lost (master&#xa;              mode)" />
-      <BitField start="8" size="1" name="BERR" description="Bus error" />
-      <BitField start="7" size="1" name="TxE" description="Data register empty&#xa;              (transmitters)" />
-      <BitField start="6" size="1" name="RxNE" description="Data register not empty&#xa;              (receivers)" />
-      <BitField start="4" size="1" name="STOPF" description="Stop detection (slave&#xa;              mode)" />
-      <BitField start="3" size="1" name="ADD10" description="10-bit header sent (Master&#xa;              mode)" />
-      <BitField start="2" size="1" name="BTF" description="Byte transfer finished" />
-      <BitField start="1" size="1" name="ADDR" description="Address sent (master mode)/matched&#xa;              (slave mode)" />
-      <BitField start="0" size="1" name="SB" description="Start bit (Master mode)" />
-    </Register>
-    <Register start="+0x18" size="0" name="SR2" access="ReadOnly" description="Status register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="8" name="PEC" description="acket error checking&#xa;              register" />
-      <BitField start="7" size="1" name="DUALF" description="Dual flag (Slave mode)" />
-      <BitField start="6" size="1" name="SMBHOST" description="SMBus host header (Slave&#xa;              mode)" />
-      <BitField start="5" size="1" name="SMBDEFAULT" description="SMBus device default address (Slave&#xa;              mode)" />
-      <BitField start="4" size="1" name="GENCALL" description="General call address (Slave&#xa;              mode)" />
-      <BitField start="2" size="1" name="TRA" description="Transmitter/receiver" />
-      <BitField start="1" size="1" name="BUSY" description="Bus busy" />
-      <BitField start="0" size="1" name="MSL" description="Master/slave" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCR" access="Read/Write" description="Clock control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="F_S" description="I2C master mode selection" />
-      <BitField start="14" size="1" name="DUTY" description="Fast mode duty cycle" />
-      <BitField start="0" size="12" name="CCR" description="Clock control register in Fast/Standard&#xa;              mode (Master mode)" />
-    </Register>
-    <Register start="+0x20" size="0" name="TRISE" access="Read/Write" description="TRISE register" reset_value="0x0002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TRISE" description="Maximum rise time in Fast/Standard mode&#xa;              (Master mode)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="IWDG" start="0x40003000" description="Independent watchdog">
-    <Register start="+0x0" size="0" name="KR" access="WriteOnly" description="Key register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="KEY" description="Key value (write only, read&#xa;              0000h)" />
-    </Register>
-    <Register start="+0x4" size="0" name="PR" access="Read/Write" description="Prescaler register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PR" description="Prescaler divider" />
-    </Register>
-    <Register start="+0x8" size="0" name="RLR" access="Read/Write" description="Reload register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RL" description="Watchdog counter reload&#xa;              value" />
-    </Register>
-    <Register start="+0xC" size="0" name="SR" access="ReadOnly" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RVU" description="Watchdog counter reload value&#xa;              update" />
-      <BitField start="0" size="1" name="PVU" description="Watchdog prescaler value&#xa;              update" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDG" start="0x40002C00" description="Window watchdog">
-    <Register start="+0x0" size="0" name="CR" access="Read/Write" description="Control register" reset_value="0x7F" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="WDGA" description="Activation bit" />
-      <BitField start="0" size="7" name="T" description="7-bit counter (MSB to LSB)" />
-    </Register>
-    <Register start="+0x4" size="0" name="CFR" access="Read/Write" description="Configuration register" reset_value="0x7F" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="EWI" description="Early wakeup interrupt" />
-      <BitField start="8" size="1" name="WDGTB1" description="Timer base" />
-      <BitField start="7" size="1" name="WDGTB0" description="Timer base" />
-      <BitField start="0" size="7" name="W" description="7-bit window value" />
-    </Register>
-    <Register start="+0x8" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EWIF" description="Early wakeup interrupt&#xa;              flag" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40002800" description="Real-time clock">
-    <Register start="+0x0" size="0" name="TR" access="Read/Write" description="time register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="22" size="1" name="PM" description="AM/PM notation" />
-      <BitField start="20" size="2" name="HT" description="Hour tens in BCD format" />
-      <BitField start="16" size="4" name="HU" description="Hour units in BCD format" />
-      <BitField start="12" size="3" name="MNT" description="Minute tens in BCD format" />
-      <BitField start="8" size="4" name="MNU" description="Minute units in BCD format" />
-      <BitField start="4" size="3" name="ST" description="Second tens in BCD format" />
-      <BitField start="0" size="4" name="SU" description="Second units in BCD format" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="date register" reset_value="0x00002101" reset_mask="0xFFFFFFFF">
-      <BitField start="20" size="4" name="YT" description="Year tens in BCD format" />
-      <BitField start="16" size="4" name="YU" description="Year units in BCD format" />
-      <BitField start="13" size="3" name="WDU" description="Week day units" />
-      <BitField start="12" size="1" name="MT" description="Month tens in BCD format" />
-      <BitField start="8" size="4" name="MU" description="Month units in BCD format" />
-      <BitField start="4" size="2" name="DT" description="Date tens in BCD format" />
-      <BitField start="0" size="4" name="DU" description="Date units in BCD format" />
-    </Register>
-    <Register start="+0x8" size="0" name="CR" access="Read/Write" description="control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="COE" description="Calibration output enable" />
-      <BitField start="21" size="2" name="OSEL" description="Output selection" />
-      <BitField start="20" size="1" name="POL" description="Output polarity" />
-      <BitField start="18" size="1" name="BKP" description="Backup" />
-      <BitField start="17" size="1" name="SUB1H" description="Subtract 1 hour (winter time&#xa;              change)" />
-      <BitField start="16" size="1" name="ADD1H" description="Add 1 hour (summer time&#xa;              change)" />
-      <BitField start="15" size="1" name="TSIE" description="Time-stamp interrupt&#xa;              enable" />
-      <BitField start="14" size="1" name="WUTIE" description="Wakeup timer interrupt&#xa;              enable" />
-      <BitField start="13" size="1" name="ALRBIE" description="Alarm B interrupt enable" />
-      <BitField start="12" size="1" name="ALRAIE" description="Alarm A interrupt enable" />
-      <BitField start="11" size="1" name="TSE" description="Time stamp enable" />
-      <BitField start="10" size="1" name="WUTE" description="Wakeup timer enable" />
-      <BitField start="9" size="1" name="ALRBE" description="Alarm B enable" />
-      <BitField start="8" size="1" name="ALRAE" description="Alarm A enable" />
-      <BitField start="7" size="1" name="DCE" description="Coarse digital calibration&#xa;              enable" />
-      <BitField start="6" size="1" name="FMT" description="Hour format" />
-      <BitField start="4" size="1" name="REFCKON" description="Reference clock detection enable (50 or&#xa;              60 Hz)" />
-      <BitField start="3" size="1" name="TSEDGE" description="Time-stamp event active&#xa;              edge" />
-      <BitField start="0" size="3" name="WCKSEL" description="Wakeup clock selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="ISR" access="Read/Write" description="initialization and status&#xa;          register" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALRAWF" description="Alarm A write flag" />
-      <BitField start="1" size="1" name="ALRBWF" description="Alarm B write flag" />
-      <BitField start="2" size="1" name="WUTWF" description="Wakeup timer write flag" />
-      <BitField start="3" size="1" name="SHPF" description="Shift operation pending" />
-      <BitField start="4" size="1" name="INITS" description="Initialization status flag" />
-      <BitField start="5" size="1" name="RSF" description="Registers synchronization&#xa;              flag" />
-      <BitField start="6" size="1" name="INITF" description="Initialization flag" />
-      <BitField start="7" size="1" name="INIT" description="Initialization mode" />
-      <BitField start="8" size="1" name="ALRAF" description="Alarm A flag" />
-      <BitField start="9" size="1" name="ALRBF" description="Alarm B flag" />
-      <BitField start="10" size="1" name="WUTF" description="Wakeup timer flag" />
-      <BitField start="11" size="1" name="TSF" description="Time-stamp flag" />
-      <BitField start="12" size="1" name="TSOVF" description="Time-stamp overflow flag" />
-      <BitField start="13" size="1" name="TAMP1F" description="Tamper detection flag" />
-      <BitField start="14" size="1" name="TAMP2F" description="TAMPER2 detection flag" />
-      <BitField start="16" size="1" name="RECALPF" description="Recalibration pending Flag" />
-    </Register>
-    <Register start="+0x10" size="0" name="PRER" access="Read/Write" description="prescaler register" reset_value="0x007F00FF" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="7" name="PREDIV_A" description="Asynchronous prescaler&#xa;              factor" />
-      <BitField start="0" size="15" name="PREDIV_S" description="Synchronous prescaler&#xa;              factor" />
-    </Register>
-    <Register start="+0x14" size="0" name="WUTR" access="Read/Write" description="wakeup timer register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WUT" description="Wakeup auto-reload value&#xa;              bits" />
-    </Register>
-    <Register start="+0x18" size="0" name="CALIBR" access="Read/Write" description="calibration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="DCS" description="Digital calibration sign" />
-      <BitField start="0" size="5" name="DC" description="Digital calibration" />
-    </Register>
-    <Register start="+0x1C" size="0" name="ALRMAR" access="Read/Write" description="alarm A register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="MSK4" description="Alarm A date mask" />
-      <BitField start="30" size="1" name="WDSEL" description="Week day selection" />
-      <BitField start="28" size="2" name="DT" description="Date tens in BCD format" />
-      <BitField start="24" size="4" name="DU" description="Date units or day in BCD&#xa;              format" />
-      <BitField start="23" size="1" name="MSK3" description="Alarm A hours mask" />
-      <BitField start="22" size="1" name="PM" description="AM/PM notation" />
-      <BitField start="20" size="2" name="HT" description="Hour tens in BCD format" />
-      <BitField start="16" size="4" name="HU" description="Hour units in BCD format" />
-      <BitField start="15" size="1" name="MSK2" description="Alarm A minutes mask" />
-      <BitField start="12" size="3" name="MNT" description="Minute tens in BCD format" />
-      <BitField start="8" size="4" name="MNU" description="Minute units in BCD format" />
-      <BitField start="7" size="1" name="MSK1" description="Alarm A seconds mask" />
-      <BitField start="4" size="3" name="ST" description="Second tens in BCD format" />
-      <BitField start="0" size="4" name="SU" description="Second units in BCD format" />
-    </Register>
-    <Register start="+0x20" size="0" name="ALRMBR" access="Read/Write" description="alarm B register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="MSK4" description="Alarm B date mask" />
-      <BitField start="30" size="1" name="WDSEL" description="Week day selection" />
-      <BitField start="28" size="2" name="DT" description="Date tens in BCD format" />
-      <BitField start="24" size="4" name="DU" description="Date units or day in BCD&#xa;              format" />
-      <BitField start="23" size="1" name="MSK3" description="Alarm B hours mask" />
-      <BitField start="22" size="1" name="PM" description="AM/PM notation" />
-      <BitField start="20" size="2" name="HT" description="Hour tens in BCD format" />
-      <BitField start="16" size="4" name="HU" description="Hour units in BCD format" />
-      <BitField start="15" size="1" name="MSK2" description="Alarm B minutes mask" />
-      <BitField start="12" size="3" name="MNT" description="Minute tens in BCD format" />
-      <BitField start="8" size="4" name="MNU" description="Minute units in BCD format" />
-      <BitField start="7" size="1" name="MSK1" description="Alarm B seconds mask" />
-      <BitField start="4" size="3" name="ST" description="Second tens in BCD format" />
-      <BitField start="0" size="4" name="SU" description="Second units in BCD format" />
-    </Register>
-    <Register start="+0x24" size="0" name="WPR" access="WriteOnly" description="write protection register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="KEY" description="Write protection key" />
-    </Register>
-    <Register start="+0x28" size="0" name="SSR" access="ReadOnly" description="sub second register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SS" description="Sub second value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="SHIFTR" access="WriteOnly" description="shift control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="ADD1S" description="Add one second" />
-      <BitField start="0" size="15" name="SUBFS" description="Subtract a fraction of a&#xa;              second" />
-    </Register>
-    <Register start="+0x30" size="0" name="TSTR" access="ReadOnly" description="time stamp time register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="18" size="1" name="ALARMOUTTYPE" description="AFO_ALARM output type" />
-      <BitField start="17" size="1" name="TSINSEL" description="TIMESTAMP mapping" />
-      <BitField start="16" size="1" name="TAMP1INSEL" description="TAMPER1 mapping" />
-      <BitField start="2" size="1" name="TAMPIE" description="Tamper interrupt enable" />
-      <BitField start="1" size="1" name="TAMP1TRG" description="Active level for tamper 1" />
-      <BitField start="0" size="1" name="TAMP1E" description="Tamper 1 detection enable" />
-    </Register>
-    <Register start="+0x34" size="0" name="TSDR" access="ReadOnly" description="time stamp date register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="3" name="WDU" description="Week day units" />
-      <BitField start="12" size="1" name="MT" description="Month tens in BCD format" />
-      <BitField start="8" size="4" name="MU" description="Month units in BCD format" />
-      <BitField start="4" size="2" name="DT" description="Date tens in BCD format" />
-      <BitField start="0" size="4" name="DU" description="Date units in BCD format" />
-    </Register>
-    <Register start="+0x38" size="0" name="TSSSR" access="ReadOnly" description="timestamp sub second register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SS" description="Sub second value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CALR" access="Read/Write" description="calibration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="CALP" description="Increase frequency of RTC by 488.5&#xa;              ppm" />
-      <BitField start="14" size="1" name="CALW8" description="Use an 8-second calibration cycle&#xa;              period" />
-      <BitField start="13" size="1" name="CALW16" description="Use a 16-second calibration cycle&#xa;              period" />
-      <BitField start="0" size="9" name="CALM" description="Calibration minus" />
-    </Register>
-    <Register start="+0x40" size="0" name="TAFCR" access="Read/Write" description="tamper and alternate function configuration&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="18" size="1" name="ALARMOUTTYPE" description="AFO_ALARM output type" />
-      <BitField start="17" size="1" name="TSINSEL" description="TIMESTAMP mapping" />
-      <BitField start="16" size="1" name="TAMP1INSEL" description="TAMPER1 mapping" />
-      <BitField start="15" size="1" name="TAMPPUDIS" description="TAMPER pull-up disable" />
-      <BitField start="13" size="2" name="TAMPPRCH" description="Tamper precharge duration" />
-      <BitField start="11" size="2" name="TAMPFLT" description="Tamper filter count" />
-      <BitField start="8" size="3" name="TAMPFREQ" description="Tamper sampling frequency" />
-      <BitField start="7" size="1" name="TAMPTS" description="Activate timestamp on tamper detection&#xa;              event" />
-      <BitField start="4" size="1" name="TAMP2TRG" description="Active level for tamper 2" />
-      <BitField start="3" size="1" name="TAMP2E" description="Tamper 2 detection enable" />
-      <BitField start="2" size="1" name="TAMPIE" description="Tamper interrupt enable" />
-      <BitField start="1" size="1" name="TAMP1TRG" description="Active level for tamper 1" />
-      <BitField start="0" size="1" name="TAMP1E" description="Tamper 1 detection enable" />
-    </Register>
-    <Register start="+0x44" size="0" name="ALRMASSR" access="Read/Write" description="alarm A sub second register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="4" name="MASKSS" description="Mask the most-significant bits starting&#xa;              at this bit" />
-      <BitField start="0" size="15" name="SS" description="Sub seconds value" />
-    </Register>
-    <Register start="+0x48" size="0" name="ALRMBSSR" access="Read/Write" description="alarm B sub second register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="4" name="MASKSS" description="Mask the most-significant bits starting&#xa;              at this bit" />
-      <BitField start="0" size="15" name="SS" description="Sub seconds value" />
-    </Register>
-    <Register start="+0x50" size="0" name="BKP0R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x54" size="0" name="BKP1R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x58" size="0" name="BKP2R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x5C" size="0" name="BKP3R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x60" size="0" name="BKP4R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x64" size="0" name="BKP5R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x68" size="0" name="BKP6R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x6C" size="0" name="BKP7R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x70" size="0" name="BKP8R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x74" size="0" name="BKP9R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x78" size="0" name="BKP10R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x7C" size="0" name="BKP11R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x80" size="0" name="BKP12R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x84" size="0" name="BKP13R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x88" size="0" name="BKP14R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x8C" size="0" name="BKP15R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x90" size="0" name="BKP16R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x94" size="0" name="BKP17R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x98" size="0" name="BKP18R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-    <Register start="+0x9C" size="0" name="BKP19R" access="Read/Write" description="backup register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKP" description="BKP" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART4" start="0x40004C00" description="Universal synchronous asynchronous receiver&#xa;      transmitter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00C00000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="LBD" description="LIN break detection flag" />
-      <BitField start="7" size="1" name="TXE" description="Transmit data register&#xa;              empty" />
-      <BitField start="6" size="1" name="TC" description="Transmission complete" />
-      <BitField start="5" size="1" name="RXNE" description="Read data register not&#xa;              empty" />
-      <BitField start="4" size="1" name="IDLE" description="IDLE line detected" />
-      <BitField start="3" size="1" name="ORE" description="Overrun error" />
-      <BitField start="2" size="1" name="NF" description="Noise detected flag" />
-      <BitField start="1" size="1" name="FE" description="Framing error" />
-      <BitField start="0" size="1" name="PE" description="Parity error" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DR" description="Data value" />
-    </Register>
-    <Register start="+0x8" size="0" name="BRR" access="Read/Write" description="Baud rate register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DIV_Mantissa" description="mantissa of USARTDIV" />
-      <BitField start="0" size="4" name="DIV_Fraction" description="fraction of USARTDIV" />
-    </Register>
-    <Register start="+0xC" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OVER8" description="Oversampling mode" />
-      <BitField start="13" size="1" name="UE" description="USART enable" />
-      <BitField start="12" size="1" name="M" description="Word length" />
-      <BitField start="11" size="1" name="WAKE" description="Wakeup method" />
-      <BitField start="10" size="1" name="PCE" description="Parity control enable" />
-      <BitField start="9" size="1" name="PS" description="Parity selection" />
-      <BitField start="8" size="1" name="PEIE" description="PE interrupt enable" />
-      <BitField start="7" size="1" name="TXEIE" description="TXE interrupt enable" />
-      <BitField start="6" size="1" name="TCIE" description="Transmission complete interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXNEIE" description="RXNE interrupt enable" />
-      <BitField start="4" size="1" name="IDLEIE" description="IDLE interrupt enable" />
-      <BitField start="3" size="1" name="TE" description="Transmitter enable" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable" />
-      <BitField start="1" size="1" name="RWU" description="Receiver wakeup" />
-      <BitField start="0" size="1" name="SBK" description="Send break" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="LINEN" description="LIN mode enable" />
-      <BitField start="12" size="2" name="STOP" description="STOP bits" />
-      <BitField start="6" size="1" name="LBDIE" description="LIN break detection interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="LBDL" description="lin break detection length" />
-      <BitField start="0" size="4" name="ADD" description="Address of the USART node" />
-    </Register>
-    <Register start="+0x14" size="0" name="CR3" access="Read/Write" description="Control register 3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="ONEBIT" description="One sample bit method&#xa;              enable" />
-      <BitField start="7" size="1" name="DMAT" description="DMA enable transmitter" />
-      <BitField start="6" size="1" name="DMAR" description="DMA enable receiver" />
-      <BitField start="3" size="1" name="HDSEL" description="Half-duplex selection" />
-      <BitField start="2" size="1" name="IRLP" description="IrDA low-power" />
-      <BitField start="1" size="1" name="IREN" description="IrDA mode enable" />
-      <BitField start="0" size="1" name="EIE" description="Error interrupt enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART5" start="0x40005000" description="Universal synchronous asynchronous receiver&#xa;      transmitter">
-    <Register start="+0x0" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00C00000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="LBD" description="LIN break detection flag" />
-      <BitField start="7" size="1" name="TXE" description="Transmit data register&#xa;              empty" />
-      <BitField start="6" size="1" name="TC" description="Transmission complete" />
-      <BitField start="5" size="1" name="RXNE" description="Read data register not&#xa;              empty" />
-      <BitField start="4" size="1" name="IDLE" description="IDLE line detected" />
-      <BitField start="3" size="1" name="ORE" description="Overrun error" />
-      <BitField start="2" size="1" name="NF" description="Noise detected flag" />
-      <BitField start="1" size="1" name="FE" description="Framing error" />
-      <BitField start="0" size="1" name="PE" description="Parity error" />
-    </Register>
-    <Register start="+0x4" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DR" description="Data value" />
-    </Register>
-    <Register start="+0x8" size="0" name="BRR" access="Read/Write" description="Baud rate register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="12" name="DIV_Mantissa" description="mantissa of USARTDIV" />
-      <BitField start="0" size="4" name="DIV_Fraction" description="fraction of USARTDIV" />
-    </Register>
-    <Register start="+0xC" size="0" name="CR1" access="Read/Write" description="Control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OVER8" description="Oversampling mode" />
-      <BitField start="13" size="1" name="UE" description="USART enable" />
-      <BitField start="12" size="1" name="M" description="Word length" />
-      <BitField start="11" size="1" name="WAKE" description="Wakeup method" />
-      <BitField start="10" size="1" name="PCE" description="Parity control enable" />
-      <BitField start="9" size="1" name="PS" description="Parity selection" />
-      <BitField start="8" size="1" name="PEIE" description="PE interrupt enable" />
-      <BitField start="7" size="1" name="TXEIE" description="TXE interrupt enable" />
-      <BitField start="6" size="1" name="TCIE" description="Transmission complete interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="RXNEIE" description="RXNE interrupt enable" />
-      <BitField start="4" size="1" name="IDLEIE" description="IDLE interrupt enable" />
-      <BitField start="3" size="1" name="TE" description="Transmitter enable" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable" />
-      <BitField start="1" size="1" name="RWU" description="Receiver wakeup" />
-      <BitField start="0" size="1" name="SBK" description="Send break" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR2" access="Read/Write" description="Control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="LINEN" description="LIN mode enable" />
-      <BitField start="12" size="2" name="STOP" description="STOP bits" />
-      <BitField start="6" size="1" name="LBDIE" description="LIN break detection interrupt&#xa;              enable" />
-      <BitField start="5" size="1" name="LBDL" description="lin break detection length" />
-      <BitField start="0" size="4" name="ADD" description="Address of the USART node" />
-    </Register>
-    <Register start="+0x14" size="0" name="CR3" access="Read/Write" description="Control register 3" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="ONEBIT" description="One sample bit method&#xa;              enable" />
-      <BitField start="7" size="1" name="DMAT" description="DMA enable transmitter" />
-      <BitField start="6" size="1" name="DMAR" description="DMA enable receiver" />
-      <BitField start="3" size="1" name="HDSEL" description="Half-duplex selection" />
-      <BitField start="2" size="1" name="IRLP" description="IrDA low-power" />
-      <BitField start="1" size="1" name="IREN" description="IrDA mode enable" />
-      <BitField start="0" size="1" name="EIE" description="Error interrupt enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_ADC" start="0x40012300" description="Common ADC registers">
-    <Register start="+0x0" size="0" name="CSR" access="ReadOnly" description="ADC Common status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="1" name="OVR3" description="Overrun flag of ADC3" />
-      <BitField start="20" size="1" name="STRT3" description="Regular channel Start flag of ADC&#xa;              3" />
-      <BitField start="19" size="1" name="JSTRT3" description="Injected channel Start flag of ADC&#xa;              3" />
-      <BitField start="18" size="1" name="JEOC3" description="Injected channel end of conversion of&#xa;              ADC 3" />
-      <BitField start="17" size="1" name="EOC3" description="End of conversion of ADC 3" />
-      <BitField start="16" size="1" name="AWD3" description="Analog watchdog flag of ADC&#xa;              3" />
-      <BitField start="13" size="1" name="OVR2" description="Overrun flag of ADC 2" />
-      <BitField start="12" size="1" name="STRT2" description="Regular channel Start flag of ADC&#xa;              2" />
-      <BitField start="11" size="1" name="JSTRT2" description="Injected channel Start flag of ADC&#xa;              2" />
-      <BitField start="10" size="1" name="JEOC2" description="Injected channel end of conversion of&#xa;              ADC 2" />
-      <BitField start="9" size="1" name="EOC2" description="End of conversion of ADC 2" />
-      <BitField start="8" size="1" name="AWD2" description="Analog watchdog flag of ADC&#xa;              2" />
-      <BitField start="5" size="1" name="OVR1" description="Overrun flag of ADC 1" />
-      <BitField start="4" size="1" name="STRT1" description="Regular channel Start flag of ADC&#xa;              1" />
-      <BitField start="3" size="1" name="JSTRT1" description="Injected channel Start flag of ADC&#xa;              1" />
-      <BitField start="2" size="1" name="JEOC1" description="Injected channel end of conversion of&#xa;              ADC 1" />
-      <BitField start="1" size="1" name="EOC1" description="End of conversion of ADC 1" />
-      <BitField start="0" size="1" name="AWD1" description="Analog watchdog flag of ADC&#xa;              1" />
-    </Register>
-    <Register start="+0x4" size="0" name="CCR" access="Read/Write" description="ADC common control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="23" size="1" name="TSVREFE" description="Temperature sensor and VREFINT&#xa;              enable" />
-      <BitField start="22" size="1" name="VBATE" description="VBAT enable" />
-      <BitField start="16" size="2" name="ADCPRE" description="ADC prescaler" />
-      <BitField start="14" size="2" name="DMA" description="Direct memory access mode for multi ADC&#xa;              mode" />
-      <BitField start="13" size="1" name="DDS" description="DMA disable selection for multi-ADC&#xa;              mode" />
-      <BitField start="8" size="4" name="DELAY" description="Delay between 2 sampling&#xa;              phases" />
-      <BitField start="0" size="5" name="MULT" description="Multi ADC mode selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="CDR" access="ReadOnly" description="ADC common regular data register for dual&#xa;          and triple modes" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="DATA2" description="2nd data item of a pair of regular&#xa;              conversions" />
-      <BitField start="0" size="16" name="DATA1" description="1st data item of a pair of regular&#xa;              conversions" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM1" start="0x40010000" description="Advanced-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="5" size="2" name="CMS" description="Center-aligned mode&#xa;              selection" />
-      <BitField start="4" size="1" name="DIR" description="Direction" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="OIS4" description="Output Idle state 4" />
-      <BitField start="13" size="1" name="OIS3N" description="Output Idle state 3" />
-      <BitField start="12" size="1" name="OIS3" description="Output Idle state 3" />
-      <BitField start="11" size="1" name="OIS2N" description="Output Idle state 2" />
-      <BitField start="10" size="1" name="OIS2" description="Output Idle state 2" />
-      <BitField start="9" size="1" name="OIS1N" description="Output Idle state 1" />
-      <BitField start="8" size="1" name="OIS1" description="Output Idle state 1" />
-      <BitField start="7" size="1" name="TI1S" description="TI1 selection" />
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-      <BitField start="3" size="1" name="CCDS" description="Capture/compare DMA&#xa;              selection" />
-      <BitField start="2" size="1" name="CCUS" description="Capture/compare control update&#xa;              selection" />
-      <BitField start="0" size="1" name="CCPC" description="Capture/compare preloaded&#xa;              control" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ETP" description="External trigger polarity" />
-      <BitField start="14" size="1" name="ECE" description="External clock enable" />
-      <BitField start="12" size="2" name="ETPS" description="External trigger prescaler" />
-      <BitField start="8" size="4" name="ETF" description="External trigger filter" />
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TDE" description="Trigger DMA request enable" />
-      <BitField start="13" size="1" name="COMDE" description="COM DMA request enable" />
-      <BitField start="12" size="1" name="CC4DE" description="Capture/Compare 4 DMA request&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3DE" description="Capture/Compare 3 DMA request&#xa;              enable" />
-      <BitField start="10" size="1" name="CC2DE" description="Capture/Compare 2 DMA request&#xa;              enable" />
-      <BitField start="9" size="1" name="CC1DE" description="Capture/Compare 1 DMA request&#xa;              enable" />
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="4" size="1" name="CC4IE" description="Capture/Compare 4 interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="CC3IE" description="Capture/Compare 3 interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-      <BitField start="7" size="1" name="BIE" description="Break interrupt enable" />
-      <BitField start="5" size="1" name="COMIE" description="COM interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="CC4OF" description="Capture/Compare 4 overcapture&#xa;              flag" />
-      <BitField start="11" size="1" name="CC3OF" description="Capture/Compare 3 overcapture&#xa;              flag" />
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="7" size="1" name="BIF" description="Break interrupt flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="5" size="1" name="COMIF" description="COM interrupt flag" />
-      <BitField start="4" size="1" name="CC4IF" description="Capture/Compare 4 interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="CC3IF" description="Capture/Compare 3 interrupt&#xa;              flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="BG" description="Break generation" />
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="5" size="1" name="COMG" description="Capture/Compare control update&#xa;              generation" />
-      <BitField start="4" size="1" name="CC4G" description="Capture/compare 4&#xa;              generation" />
-      <BitField start="3" size="1" name="CC3G" description="Capture/compare 3&#xa;              generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC2CE" description="Output Compare 2 clear&#xa;              enable" />
-      <BitField start="12" size="3" name="OC2M" description="Output Compare 2 mode" />
-      <BitField start="11" size="1" name="OC2PE" description="Output Compare 2 preload&#xa;              enable" />
-      <BitField start="10" size="1" name="OC2FE" description="Output Compare 2 fast&#xa;              enable" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="7" size="1" name="OC1CE" description="Output Compare 1 clear&#xa;              enable" />
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Output" access="Read/Write" description="capture/compare mode register 2 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC4CE" description="Output compare 4 clear&#xa;              enable" />
-      <BitField start="12" size="3" name="OC4M" description="Output compare 4 mode" />
-      <BitField start="11" size="1" name="OC4PE" description="Output compare 4 preload&#xa;              enable" />
-      <BitField start="10" size="1" name="OC4FE" description="Output compare 4 fast&#xa;              enable" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="7" size="1" name="OC3CE" description="Output compare 3 clear&#xa;              enable" />
-      <BitField start="4" size="3" name="OC3M" description="Output compare 3 mode" />
-      <BitField start="3" size="1" name="OC3PE" description="Output compare 3 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC3FE" description="Output compare 3 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/Compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Input" access="Read/Write" description="capture/compare mode register 2 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC4F" description="Input capture 4 filter" />
-      <BitField start="10" size="2" name="IC4PSC" description="Input capture 4 prescaler" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="4" size="4" name="IC3F" description="Input capture 3 filter" />
-      <BitField start="2" size="2" name="IC3PSC" description="Input capture 3 prescaler" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="1" name="CC4P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="12" size="1" name="CC4E" description="Capture/Compare 4 output&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3NP" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="10" size="1" name="CC3NE" description="Capture/Compare 3 complementary output&#xa;              enable" />
-      <BitField start="9" size="1" name="CC3P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="8" size="1" name="CC3E" description="Capture/Compare 3 output&#xa;              enable" />
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="6" size="1" name="CC2NE" description="Capture/Compare 2 complementary output&#xa;              enable" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="2" size="1" name="CC1NE" description="Capture/Compare 1 complementary output&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR2" description="Capture/Compare 2 value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CCR3" access="Read/Write" description="capture/compare register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR3" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x40" size="0" name="CCR4" access="Read/Write" description="capture/compare register 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR4" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x48" size="0" name="DCR" access="Read/Write" description="DMA control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="5" name="DBL" description="DMA burst length" />
-      <BitField start="0" size="5" name="DBA" description="DMA base address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMAR" access="Read/Write" description="DMA address for full transfer" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DMAB" description="DMA register for burst&#xa;              accesses" />
-    </Register>
-    <Register start="+0x30" size="0" name="RCR" access="Read/Write" description="repetition counter register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="REP" description="Repetition counter value" />
-    </Register>
-    <Register start="+0x44" size="0" name="BDTR" access="Read/Write" description="break and dead-time register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="MOE" description="Main output enable" />
-      <BitField start="14" size="1" name="AOE" description="Automatic output enable" />
-      <BitField start="13" size="1" name="BKP" description="Break polarity" />
-      <BitField start="12" size="1" name="BKE" description="Break enable" />
-      <BitField start="11" size="1" name="OSSR" description="Off-state selection for Run&#xa;              mode" />
-      <BitField start="10" size="1" name="OSSI" description="Off-state selection for Idle&#xa;              mode" />
-      <BitField start="8" size="2" name="LOCK" description="Lock configuration" />
-      <BitField start="0" size="8" name="DTG" description="Dead-time generator setup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM8" start="0x40010400" description="Advanced-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="5" size="2" name="CMS" description="Center-aligned mode&#xa;              selection" />
-      <BitField start="4" size="1" name="DIR" description="Direction" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="OIS4" description="Output Idle state 4" />
-      <BitField start="13" size="1" name="OIS3N" description="Output Idle state 3" />
-      <BitField start="12" size="1" name="OIS3" description="Output Idle state 3" />
-      <BitField start="11" size="1" name="OIS2N" description="Output Idle state 2" />
-      <BitField start="10" size="1" name="OIS2" description="Output Idle state 2" />
-      <BitField start="9" size="1" name="OIS1N" description="Output Idle state 1" />
-      <BitField start="8" size="1" name="OIS1" description="Output Idle state 1" />
-      <BitField start="7" size="1" name="TI1S" description="TI1 selection" />
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-      <BitField start="3" size="1" name="CCDS" description="Capture/compare DMA&#xa;              selection" />
-      <BitField start="2" size="1" name="CCUS" description="Capture/compare control update&#xa;              selection" />
-      <BitField start="0" size="1" name="CCPC" description="Capture/compare preloaded&#xa;              control" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ETP" description="External trigger polarity" />
-      <BitField start="14" size="1" name="ECE" description="External clock enable" />
-      <BitField start="12" size="2" name="ETPS" description="External trigger prescaler" />
-      <BitField start="8" size="4" name="ETF" description="External trigger filter" />
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TDE" description="Trigger DMA request enable" />
-      <BitField start="13" size="1" name="COMDE" description="COM DMA request enable" />
-      <BitField start="12" size="1" name="CC4DE" description="Capture/Compare 4 DMA request&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3DE" description="Capture/Compare 3 DMA request&#xa;              enable" />
-      <BitField start="10" size="1" name="CC2DE" description="Capture/Compare 2 DMA request&#xa;              enable" />
-      <BitField start="9" size="1" name="CC1DE" description="Capture/Compare 1 DMA request&#xa;              enable" />
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="4" size="1" name="CC4IE" description="Capture/Compare 4 interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="CC3IE" description="Capture/Compare 3 interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-      <BitField start="7" size="1" name="BIE" description="Break interrupt enable" />
-      <BitField start="5" size="1" name="COMIE" description="COM interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="CC4OF" description="Capture/Compare 4 overcapture&#xa;              flag" />
-      <BitField start="11" size="1" name="CC3OF" description="Capture/Compare 3 overcapture&#xa;              flag" />
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="7" size="1" name="BIF" description="Break interrupt flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="5" size="1" name="COMIF" description="COM interrupt flag" />
-      <BitField start="4" size="1" name="CC4IF" description="Capture/Compare 4 interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="CC3IF" description="Capture/Compare 3 interrupt&#xa;              flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="BG" description="Break generation" />
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="5" size="1" name="COMG" description="Capture/Compare control update&#xa;              generation" />
-      <BitField start="4" size="1" name="CC4G" description="Capture/compare 4&#xa;              generation" />
-      <BitField start="3" size="1" name="CC3G" description="Capture/compare 3&#xa;              generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC2CE" description="Output Compare 2 clear&#xa;              enable" />
-      <BitField start="12" size="3" name="OC2M" description="Output Compare 2 mode" />
-      <BitField start="11" size="1" name="OC2PE" description="Output Compare 2 preload&#xa;              enable" />
-      <BitField start="10" size="1" name="OC2FE" description="Output Compare 2 fast&#xa;              enable" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="7" size="1" name="OC1CE" description="Output Compare 1 clear&#xa;              enable" />
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Output" access="Read/Write" description="capture/compare mode register 2 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC4CE" description="Output compare 4 clear&#xa;              enable" />
-      <BitField start="12" size="3" name="OC4M" description="Output compare 4 mode" />
-      <BitField start="11" size="1" name="OC4PE" description="Output compare 4 preload&#xa;              enable" />
-      <BitField start="10" size="1" name="OC4FE" description="Output compare 4 fast&#xa;              enable" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="7" size="1" name="OC3CE" description="Output compare 3 clear&#xa;              enable" />
-      <BitField start="4" size="3" name="OC3M" description="Output compare 3 mode" />
-      <BitField start="3" size="1" name="OC3PE" description="Output compare 3 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC3FE" description="Output compare 3 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/Compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Input" access="Read/Write" description="capture/compare mode register 2 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC4F" description="Input capture 4 filter" />
-      <BitField start="10" size="2" name="IC4PSC" description="Input capture 4 prescaler" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="4" size="4" name="IC3F" description="Input capture 3 filter" />
-      <BitField start="2" size="2" name="IC3PSC" description="Input capture 3 prescaler" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="1" name="CC4P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="12" size="1" name="CC4E" description="Capture/Compare 4 output&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3NP" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="10" size="1" name="CC3NE" description="Capture/Compare 3 complementary output&#xa;              enable" />
-      <BitField start="9" size="1" name="CC3P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="8" size="1" name="CC3E" description="Capture/Compare 3 output&#xa;              enable" />
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="6" size="1" name="CC2NE" description="Capture/Compare 2 complementary output&#xa;              enable" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="2" size="1" name="CC1NE" description="Capture/Compare 1 complementary output&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR2" description="Capture/Compare 2 value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CCR3" access="Read/Write" description="capture/compare register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR3" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x40" size="0" name="CCR4" access="Read/Write" description="capture/compare register 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR4" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x48" size="0" name="DCR" access="Read/Write" description="DMA control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="5" name="DBL" description="DMA burst length" />
-      <BitField start="0" size="5" name="DBA" description="DMA base address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMAR" access="Read/Write" description="DMA address for full transfer" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DMAB" description="DMA register for burst&#xa;              accesses" />
-    </Register>
-    <Register start="+0x30" size="0" name="RCR" access="Read/Write" description="repetition counter register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="REP" description="Repetition counter value" />
-    </Register>
-    <Register start="+0x44" size="0" name="BDTR" access="Read/Write" description="break and dead-time register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="MOE" description="Main output enable" />
-      <BitField start="14" size="1" name="AOE" description="Automatic output enable" />
-      <BitField start="13" size="1" name="BKP" description="Break polarity" />
-      <BitField start="12" size="1" name="BKE" description="Break enable" />
-      <BitField start="11" size="1" name="OSSR" description="Off-state selection for Run&#xa;              mode" />
-      <BitField start="10" size="1" name="OSSI" description="Off-state selection for Idle&#xa;              mode" />
-      <BitField start="8" size="2" name="LOCK" description="Lock configuration" />
-      <BitField start="0" size="8" name="DTG" description="Dead-time generator setup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM2" start="0x40000000" description="General purpose timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="5" size="2" name="CMS" description="Center-aligned mode&#xa;              selection" />
-      <BitField start="4" size="1" name="DIR" description="Direction" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TI1S" description="TI1 selection" />
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-      <BitField start="3" size="1" name="CCDS" description="Capture/compare DMA&#xa;              selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ETP" description="External trigger polarity" />
-      <BitField start="14" size="1" name="ECE" description="External clock enable" />
-      <BitField start="12" size="2" name="ETPS" description="External trigger prescaler" />
-      <BitField start="8" size="4" name="ETF" description="External trigger filter" />
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TDE" description="Trigger DMA request enable" />
-      <BitField start="12" size="1" name="CC4DE" description="Capture/Compare 4 DMA request&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3DE" description="Capture/Compare 3 DMA request&#xa;              enable" />
-      <BitField start="10" size="1" name="CC2DE" description="Capture/Compare 2 DMA request&#xa;              enable" />
-      <BitField start="9" size="1" name="CC1DE" description="Capture/Compare 1 DMA request&#xa;              enable" />
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="4" size="1" name="CC4IE" description="Capture/Compare 4 interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="CC3IE" description="Capture/Compare 3 interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="CC4OF" description="Capture/Compare 4 overcapture&#xa;              flag" />
-      <BitField start="11" size="1" name="CC3OF" description="Capture/Compare 3 overcapture&#xa;              flag" />
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="4" size="1" name="CC4IF" description="Capture/Compare 4 interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="CC3IF" description="Capture/Compare 3 interrupt&#xa;              flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="4" size="1" name="CC4G" description="Capture/compare 4&#xa;              generation" />
-      <BitField start="3" size="1" name="CC3G" description="Capture/compare 3&#xa;              generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC2CE" description="OC2CE" />
-      <BitField start="12" size="3" name="OC2M" description="OC2M" />
-      <BitField start="11" size="1" name="OC2PE" description="OC2PE" />
-      <BitField start="10" size="1" name="OC2FE" description="OC2FE" />
-      <BitField start="8" size="2" name="CC2S" description="CC2S" />
-      <BitField start="7" size="1" name="OC1CE" description="OC1CE" />
-      <BitField start="4" size="3" name="OC1M" description="OC1M" />
-      <BitField start="3" size="1" name="OC1PE" description="OC1PE" />
-      <BitField start="2" size="1" name="OC1FE" description="OC1FE" />
-      <BitField start="0" size="2" name="CC1S" description="CC1S" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Output" access="Read/Write" description="capture/compare mode register 2 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="O24CE" description="O24CE" />
-      <BitField start="12" size="3" name="OC4M" description="OC4M" />
-      <BitField start="11" size="1" name="OC4PE" description="OC4PE" />
-      <BitField start="10" size="1" name="OC4FE" description="OC4FE" />
-      <BitField start="8" size="2" name="CC4S" description="CC4S" />
-      <BitField start="7" size="1" name="OC3CE" description="OC3CE" />
-      <BitField start="4" size="3" name="OC3M" description="OC3M" />
-      <BitField start="3" size="1" name="OC3PE" description="OC3PE" />
-      <BitField start="2" size="1" name="OC3FE" description="OC3FE" />
-      <BitField start="0" size="2" name="CC3S" description="CC3S" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Input" access="Read/Write" description="capture/compare mode register 2 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC4F" description="Input capture 4 filter" />
-      <BitField start="10" size="2" name="IC4PSC" description="Input capture 4 prescaler" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="4" size="4" name="IC3F" description="Input capture 3 filter" />
-      <BitField start="2" size="2" name="IC3PSC" description="Input capture 3 prescaler" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="CC4NP" description="Capture/Compare 4 output&#xa;              Polarity" />
-      <BitField start="13" size="1" name="CC4P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="12" size="1" name="CC4E" description="Capture/Compare 4 output&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3NP" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="9" size="1" name="CC3P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="8" size="1" name="CC3E" description="Capture/Compare 3 output&#xa;              enable" />
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CNT_H" description="High counter value" />
-      <BitField start="0" size="16" name="CNT_L" description="Low counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="ARR_H" description="High Auto-reload value" />
-      <BitField start="0" size="16" name="ARR_L" description="Low Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR1_H" description="High Capture/Compare 1&#xa;              value" />
-      <BitField start="0" size="16" name="CCR1_L" description="Low Capture/Compare 1&#xa;              value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR2_H" description="High Capture/Compare 2&#xa;              value" />
-      <BitField start="0" size="16" name="CCR2_L" description="Low Capture/Compare 2&#xa;              value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CCR3" access="Read/Write" description="capture/compare register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR3_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR3_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x40" size="0" name="CCR4" access="Read/Write" description="capture/compare register 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR4_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR4_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x48" size="0" name="DCR" access="Read/Write" description="DMA control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="5" name="DBL" description="DMA burst length" />
-      <BitField start="0" size="5" name="DBA" description="DMA base address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMAR" access="Read/Write" description="DMA address for full transfer" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DMAB" description="DMA register for burst&#xa;              accesses" />
-    </Register>
-    <Register start="+0x50" size="0" name="OR" access="Read/Write" description="TIM5 option register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="10" size="2" name="ITR1_RMP" description="Timer Input 4 remap" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM3" start="0x40000400" description="General purpose timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="5" size="2" name="CMS" description="Center-aligned mode&#xa;              selection" />
-      <BitField start="4" size="1" name="DIR" description="Direction" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TI1S" description="TI1 selection" />
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-      <BitField start="3" size="1" name="CCDS" description="Capture/compare DMA&#xa;              selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ETP" description="External trigger polarity" />
-      <BitField start="14" size="1" name="ECE" description="External clock enable" />
-      <BitField start="12" size="2" name="ETPS" description="External trigger prescaler" />
-      <BitField start="8" size="4" name="ETF" description="External trigger filter" />
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TDE" description="Trigger DMA request enable" />
-      <BitField start="12" size="1" name="CC4DE" description="Capture/Compare 4 DMA request&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3DE" description="Capture/Compare 3 DMA request&#xa;              enable" />
-      <BitField start="10" size="1" name="CC2DE" description="Capture/Compare 2 DMA request&#xa;              enable" />
-      <BitField start="9" size="1" name="CC1DE" description="Capture/Compare 1 DMA request&#xa;              enable" />
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="4" size="1" name="CC4IE" description="Capture/Compare 4 interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="CC3IE" description="Capture/Compare 3 interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="CC4OF" description="Capture/Compare 4 overcapture&#xa;              flag" />
-      <BitField start="11" size="1" name="CC3OF" description="Capture/Compare 3 overcapture&#xa;              flag" />
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="4" size="1" name="CC4IF" description="Capture/Compare 4 interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="CC3IF" description="Capture/Compare 3 interrupt&#xa;              flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="4" size="1" name="CC4G" description="Capture/compare 4&#xa;              generation" />
-      <BitField start="3" size="1" name="CC3G" description="Capture/compare 3&#xa;              generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC2CE" description="OC2CE" />
-      <BitField start="12" size="3" name="OC2M" description="OC2M" />
-      <BitField start="11" size="1" name="OC2PE" description="OC2PE" />
-      <BitField start="10" size="1" name="OC2FE" description="OC2FE" />
-      <BitField start="8" size="2" name="CC2S" description="CC2S" />
-      <BitField start="7" size="1" name="OC1CE" description="OC1CE" />
-      <BitField start="4" size="3" name="OC1M" description="OC1M" />
-      <BitField start="3" size="1" name="OC1PE" description="OC1PE" />
-      <BitField start="2" size="1" name="OC1FE" description="OC1FE" />
-      <BitField start="0" size="2" name="CC1S" description="CC1S" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Output" access="Read/Write" description="capture/compare mode register 2 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="O24CE" description="O24CE" />
-      <BitField start="12" size="3" name="OC4M" description="OC4M" />
-      <BitField start="11" size="1" name="OC4PE" description="OC4PE" />
-      <BitField start="10" size="1" name="OC4FE" description="OC4FE" />
-      <BitField start="8" size="2" name="CC4S" description="CC4S" />
-      <BitField start="7" size="1" name="OC3CE" description="OC3CE" />
-      <BitField start="4" size="3" name="OC3M" description="OC3M" />
-      <BitField start="3" size="1" name="OC3PE" description="OC3PE" />
-      <BitField start="2" size="1" name="OC3FE" description="OC3FE" />
-      <BitField start="0" size="2" name="CC3S" description="CC3S" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Input" access="Read/Write" description="capture/compare mode register 2 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC4F" description="Input capture 4 filter" />
-      <BitField start="10" size="2" name="IC4PSC" description="Input capture 4 prescaler" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="4" size="4" name="IC3F" description="Input capture 3 filter" />
-      <BitField start="2" size="2" name="IC3PSC" description="Input capture 3 prescaler" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="CC4NP" description="Capture/Compare 4 output&#xa;              Polarity" />
-      <BitField start="13" size="1" name="CC4P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="12" size="1" name="CC4E" description="Capture/Compare 4 output&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3NP" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="9" size="1" name="CC3P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="8" size="1" name="CC3E" description="Capture/Compare 3 output&#xa;              enable" />
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CNT_H" description="High counter value" />
-      <BitField start="0" size="16" name="CNT_L" description="Low counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="ARR_H" description="High Auto-reload value" />
-      <BitField start="0" size="16" name="ARR_L" description="Low Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR1_H" description="High Capture/Compare 1&#xa;              value" />
-      <BitField start="0" size="16" name="CCR1_L" description="Low Capture/Compare 1&#xa;              value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR2_H" description="High Capture/Compare 2&#xa;              value" />
-      <BitField start="0" size="16" name="CCR2_L" description="Low Capture/Compare 2&#xa;              value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CCR3" access="Read/Write" description="capture/compare register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR3_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR3_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x40" size="0" name="CCR4" access="Read/Write" description="capture/compare register 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR4_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR4_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x48" size="0" name="DCR" access="Read/Write" description="DMA control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="5" name="DBL" description="DMA burst length" />
-      <BitField start="0" size="5" name="DBA" description="DMA base address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMAR" access="Read/Write" description="DMA address for full transfer" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DMAB" description="DMA register for burst&#xa;              accesses" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM4" start="0x40000800" description="General purpose timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="5" size="2" name="CMS" description="Center-aligned mode&#xa;              selection" />
-      <BitField start="4" size="1" name="DIR" description="Direction" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TI1S" description="TI1 selection" />
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-      <BitField start="3" size="1" name="CCDS" description="Capture/compare DMA&#xa;              selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ETP" description="External trigger polarity" />
-      <BitField start="14" size="1" name="ECE" description="External clock enable" />
-      <BitField start="12" size="2" name="ETPS" description="External trigger prescaler" />
-      <BitField start="8" size="4" name="ETF" description="External trigger filter" />
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TDE" description="Trigger DMA request enable" />
-      <BitField start="12" size="1" name="CC4DE" description="Capture/Compare 4 DMA request&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3DE" description="Capture/Compare 3 DMA request&#xa;              enable" />
-      <BitField start="10" size="1" name="CC2DE" description="Capture/Compare 2 DMA request&#xa;              enable" />
-      <BitField start="9" size="1" name="CC1DE" description="Capture/Compare 1 DMA request&#xa;              enable" />
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="4" size="1" name="CC4IE" description="Capture/Compare 4 interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="CC3IE" description="Capture/Compare 3 interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="CC4OF" description="Capture/Compare 4 overcapture&#xa;              flag" />
-      <BitField start="11" size="1" name="CC3OF" description="Capture/Compare 3 overcapture&#xa;              flag" />
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="4" size="1" name="CC4IF" description="Capture/Compare 4 interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="CC3IF" description="Capture/Compare 3 interrupt&#xa;              flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="4" size="1" name="CC4G" description="Capture/compare 4&#xa;              generation" />
-      <BitField start="3" size="1" name="CC3G" description="Capture/compare 3&#xa;              generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC2CE" description="OC2CE" />
-      <BitField start="12" size="3" name="OC2M" description="OC2M" />
-      <BitField start="11" size="1" name="OC2PE" description="OC2PE" />
-      <BitField start="10" size="1" name="OC2FE" description="OC2FE" />
-      <BitField start="8" size="2" name="CC2S" description="CC2S" />
-      <BitField start="7" size="1" name="OC1CE" description="OC1CE" />
-      <BitField start="4" size="3" name="OC1M" description="OC1M" />
-      <BitField start="3" size="1" name="OC1PE" description="OC1PE" />
-      <BitField start="2" size="1" name="OC1FE" description="OC1FE" />
-      <BitField start="0" size="2" name="CC1S" description="CC1S" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Output" access="Read/Write" description="capture/compare mode register 2 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="O24CE" description="O24CE" />
-      <BitField start="12" size="3" name="OC4M" description="OC4M" />
-      <BitField start="11" size="1" name="OC4PE" description="OC4PE" />
-      <BitField start="10" size="1" name="OC4FE" description="OC4FE" />
-      <BitField start="8" size="2" name="CC4S" description="CC4S" />
-      <BitField start="7" size="1" name="OC3CE" description="OC3CE" />
-      <BitField start="4" size="3" name="OC3M" description="OC3M" />
-      <BitField start="3" size="1" name="OC3PE" description="OC3PE" />
-      <BitField start="2" size="1" name="OC3FE" description="OC3FE" />
-      <BitField start="0" size="2" name="CC3S" description="CC3S" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Input" access="Read/Write" description="capture/compare mode register 2 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC4F" description="Input capture 4 filter" />
-      <BitField start="10" size="2" name="IC4PSC" description="Input capture 4 prescaler" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="4" size="4" name="IC3F" description="Input capture 3 filter" />
-      <BitField start="2" size="2" name="IC3PSC" description="Input capture 3 prescaler" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="CC4NP" description="Capture/Compare 4 output&#xa;              Polarity" />
-      <BitField start="13" size="1" name="CC4P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="12" size="1" name="CC4E" description="Capture/Compare 4 output&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3NP" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="9" size="1" name="CC3P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="8" size="1" name="CC3E" description="Capture/Compare 3 output&#xa;              enable" />
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CNT_H" description="High counter value" />
-      <BitField start="0" size="16" name="CNT_L" description="Low counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="ARR_H" description="High Auto-reload value" />
-      <BitField start="0" size="16" name="ARR_L" description="Low Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR1_H" description="High Capture/Compare 1&#xa;              value" />
-      <BitField start="0" size="16" name="CCR1_L" description="Low Capture/Compare 1&#xa;              value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR2_H" description="High Capture/Compare 2&#xa;              value" />
-      <BitField start="0" size="16" name="CCR2_L" description="Low Capture/Compare 2&#xa;              value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CCR3" access="Read/Write" description="capture/compare register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR3_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR3_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x40" size="0" name="CCR4" access="Read/Write" description="capture/compare register 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR4_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR4_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x48" size="0" name="DCR" access="Read/Write" description="DMA control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="5" name="DBL" description="DMA burst length" />
-      <BitField start="0" size="5" name="DBA" description="DMA base address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMAR" access="Read/Write" description="DMA address for full transfer" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DMAB" description="DMA register for burst&#xa;              accesses" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM5" start="0x40000C00" description="General-purpose-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="5" size="2" name="CMS" description="Center-aligned mode&#xa;              selection" />
-      <BitField start="4" size="1" name="DIR" description="Direction" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TI1S" description="TI1 selection" />
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-      <BitField start="3" size="1" name="CCDS" description="Capture/compare DMA&#xa;              selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="ETP" description="External trigger polarity" />
-      <BitField start="14" size="1" name="ECE" description="External clock enable" />
-      <BitField start="12" size="2" name="ETPS" description="External trigger prescaler" />
-      <BitField start="8" size="4" name="ETF" description="External trigger filter" />
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TDE" description="Trigger DMA request enable" />
-      <BitField start="12" size="1" name="CC4DE" description="Capture/Compare 4 DMA request&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3DE" description="Capture/Compare 3 DMA request&#xa;              enable" />
-      <BitField start="10" size="1" name="CC2DE" description="Capture/Compare 2 DMA request&#xa;              enable" />
-      <BitField start="9" size="1" name="CC1DE" description="Capture/Compare 1 DMA request&#xa;              enable" />
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="4" size="1" name="CC4IE" description="Capture/Compare 4 interrupt&#xa;              enable" />
-      <BitField start="3" size="1" name="CC3IE" description="Capture/Compare 3 interrupt&#xa;              enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="1" name="CC4OF" description="Capture/Compare 4 overcapture&#xa;              flag" />
-      <BitField start="11" size="1" name="CC3OF" description="Capture/Compare 3 overcapture&#xa;              flag" />
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="4" size="1" name="CC4IF" description="Capture/Compare 4 interrupt&#xa;              flag" />
-      <BitField start="3" size="1" name="CC3IF" description="Capture/Compare 3 interrupt&#xa;              flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="4" size="1" name="CC4G" description="Capture/compare 4&#xa;              generation" />
-      <BitField start="3" size="1" name="CC3G" description="Capture/compare 3&#xa;              generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="OC2CE" description="OC2CE" />
-      <BitField start="12" size="3" name="OC2M" description="OC2M" />
-      <BitField start="11" size="1" name="OC2PE" description="OC2PE" />
-      <BitField start="10" size="1" name="OC2FE" description="OC2FE" />
-      <BitField start="8" size="2" name="CC2S" description="CC2S" />
-      <BitField start="7" size="1" name="OC1CE" description="OC1CE" />
-      <BitField start="4" size="3" name="OC1M" description="OC1M" />
-      <BitField start="3" size="1" name="OC1PE" description="OC1PE" />
-      <BitField start="2" size="1" name="OC1FE" description="OC1FE" />
-      <BitField start="0" size="2" name="CC1S" description="CC1S" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Output" access="Read/Write" description="capture/compare mode register 2 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="O24CE" description="O24CE" />
-      <BitField start="12" size="3" name="OC4M" description="OC4M" />
-      <BitField start="11" size="1" name="OC4PE" description="OC4PE" />
-      <BitField start="10" size="1" name="OC4FE" description="OC4FE" />
-      <BitField start="8" size="2" name="CC4S" description="CC4S" />
-      <BitField start="7" size="1" name="OC3CE" description="OC3CE" />
-      <BitField start="4" size="3" name="OC3M" description="OC3M" />
-      <BitField start="3" size="1" name="OC3PE" description="OC3PE" />
-      <BitField start="2" size="1" name="OC3FE" description="OC3FE" />
-      <BitField start="0" size="2" name="CC3S" description="CC3S" />
-    </Register>
-    <Register start="+0x1C" size="0" name="CCMR2_Input" access="Read/Write" description="capture/compare mode register 2 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="4" name="IC4F" description="Input capture 4 filter" />
-      <BitField start="10" size="2" name="IC4PSC" description="Input capture 4 prescaler" />
-      <BitField start="8" size="2" name="CC4S" description="Capture/Compare 4&#xa;              selection" />
-      <BitField start="4" size="4" name="IC3F" description="Input capture 3 filter" />
-      <BitField start="2" size="2" name="IC3PSC" description="Input capture 3 prescaler" />
-      <BitField start="0" size="2" name="CC3S" description="Capture/compare 3&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="15" size="1" name="CC4NP" description="Capture/Compare 4 output&#xa;              Polarity" />
-      <BitField start="13" size="1" name="CC4P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="12" size="1" name="CC4E" description="Capture/Compare 4 output&#xa;              enable" />
-      <BitField start="11" size="1" name="CC3NP" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="9" size="1" name="CC3P" description="Capture/Compare 3 output&#xa;              Polarity" />
-      <BitField start="8" size="1" name="CC3E" description="Capture/Compare 3 output&#xa;              enable" />
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CNT_H" description="High counter value" />
-      <BitField start="0" size="16" name="CNT_L" description="Low counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="ARR_H" description="High Auto-reload value" />
-      <BitField start="0" size="16" name="ARR_L" description="Low Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR1_H" description="High Capture/Compare 1&#xa;              value" />
-      <BitField start="0" size="16" name="CCR1_L" description="Low Capture/Compare 1&#xa;              value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR2_H" description="High Capture/Compare 2&#xa;              value" />
-      <BitField start="0" size="16" name="CCR2_L" description="Low Capture/Compare 2&#xa;              value" />
-    </Register>
-    <Register start="+0x3C" size="0" name="CCR3" access="Read/Write" description="capture/compare register 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR3_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR3_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x40" size="0" name="CCR4" access="Read/Write" description="capture/compare register 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="CCR4_H" description="High Capture/Compare value" />
-      <BitField start="0" size="16" name="CCR4_L" description="Low Capture/Compare value" />
-    </Register>
-    <Register start="+0x48" size="0" name="DCR" access="Read/Write" description="DMA control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="5" name="DBL" description="DMA burst length" />
-      <BitField start="0" size="5" name="DBA" description="DMA base address" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMAR" access="Read/Write" description="DMA address for full transfer" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DMAB" description="DMA register for burst&#xa;              accesses" />
-    </Register>
-    <Register start="+0x50" size="0" name="OR" access="Read/Write" description="TIM5 option register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="2" name="IT4_RMP" description="Timer Input 4 remap" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM9" start="0x40014000" description="General purpose timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="3" name="OC2M" description="Output Compare 2 mode" />
-      <BitField start="11" size="1" name="OC2PE" description="Output Compare 2 preload&#xa;              enable" />
-      <BitField start="10" size="1" name="OC2FE" description="Output Compare 2 fast&#xa;              enable" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="3" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="3" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR2" description="Capture/Compare 2 value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM12" start="0x40001800" description="General purpose timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-    </Register>
-    <Register start="+0x8" size="0" name="SMCR" access="Read/Write" description="slave mode control register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="MSM" description="Master/Slave mode" />
-      <BitField start="4" size="3" name="TS" description="Trigger selection" />
-      <BitField start="0" size="3" name="SMS" description="Slave mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TIE" description="Trigger interrupt enable" />
-      <BitField start="2" size="1" name="CC2IE" description="Capture/Compare 2 interrupt&#xa;              enable" />
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="10" size="1" name="CC2OF" description="Capture/compare 2 overcapture&#xa;              flag" />
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="6" size="1" name="TIF" description="Trigger interrupt flag" />
-      <BitField start="2" size="1" name="CC2IF" description="Capture/Compare 2 interrupt&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="TG" description="Trigger generation" />
-      <BitField start="2" size="1" name="CC2G" description="Capture/compare 2&#xa;              generation" />
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="3" name="OC2M" description="Output Compare 2 mode" />
-      <BitField start="11" size="1" name="OC2PE" description="Output Compare 2 preload&#xa;              enable" />
-      <BitField start="10" size="1" name="OC2FE" description="Output Compare 2 fast&#xa;              enable" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="3" name="IC2F" description="Input capture 2 filter" />
-      <BitField start="10" size="2" name="IC2PCS" description="Input capture 2 prescaler" />
-      <BitField start="8" size="2" name="CC2S" description="Capture/Compare 2&#xa;              selection" />
-      <BitField start="4" size="3" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="CC2NP" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="5" size="1" name="CC2P" description="Capture/Compare 2 output&#xa;              Polarity" />
-      <BitField start="4" size="1" name="CC2E" description="Capture/Compare 2 output&#xa;              enable" />
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-    <Register start="+0x38" size="0" name="CCR2" access="Read/Write" description="capture/compare register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR2" description="Capture/Compare 2 value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM10" start="0x40014400" description="General-purpose-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM13" start="0x40001C00" description="General-purpose-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM14" start="0x40002000" description="General-purpose-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM11" start="0x40014800" description="General-purpose-timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="2" name="CKD" description="Clock division" />
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1IE" description="Capture/Compare 1 interrupt&#xa;              enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="9" size="1" name="CC1OF" description="Capture/Compare 1 overcapture&#xa;              flag" />
-      <BitField start="1" size="1" name="CC1IF" description="Capture/compare 1 interrupt&#xa;              flag" />
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="CC1G" description="Capture/compare 1&#xa;              generation" />
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Output" access="Read/Write" description="capture/compare mode register 1 (output&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="OC1M" description="Output Compare 1 mode" />
-      <BitField start="3" size="1" name="OC1PE" description="Output Compare 1 preload&#xa;              enable" />
-      <BitField start="2" size="1" name="OC1FE" description="Output Compare 1 fast&#xa;              enable" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x18" size="0" name="CCMR1_Input" access="Read/Write" description="capture/compare mode register 1 (input&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="4" name="IC1F" description="Input capture 1 filter" />
-      <BitField start="2" size="2" name="ICPCS" description="Input capture 1 prescaler" />
-      <BitField start="0" size="2" name="CC1S" description="Capture/Compare 1&#xa;              selection" />
-    </Register>
-    <Register start="+0x20" size="0" name="CCER" access="Read/Write" description="capture/compare enable&#xa;          register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="CC1NP" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="1" size="1" name="CC1P" description="Capture/Compare 1 output&#xa;              Polarity" />
-      <BitField start="0" size="1" name="CC1E" description="Capture/Compare 1 output&#xa;              enable" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Auto-reload value" />
-    </Register>
-    <Register start="+0x34" size="0" name="CCR1" access="Read/Write" description="capture/compare register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCR1" description="Capture/Compare 1 value" />
-    </Register>
-    <Register start="+0x50" size="0" name="OR" access="Read/Write" description="option register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RMP" description="Input 1 remapping&#xa;              capability" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM6" start="0x40001000" description="Basic timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Low counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Low Auto-reload value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIM7" start="0x40001400" description="Basic timers">
-    <Register start="+0x0" size="0" name="CR1" access="Read/Write" description="control register 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="ARPE" description="Auto-reload preload enable" />
-      <BitField start="3" size="1" name="OPM" description="One-pulse mode" />
-      <BitField start="2" size="1" name="URS" description="Update request source" />
-      <BitField start="1" size="1" name="UDIS" description="Update disable" />
-      <BitField start="0" size="1" name="CEN" description="Counter enable" />
-    </Register>
-    <Register start="+0x4" size="0" name="CR2" access="Read/Write" description="control register 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="3" name="MMS" description="Master mode selection" />
-    </Register>
-    <Register start="+0xC" size="0" name="DIER" access="Read/Write" description="DMA/Interrupt enable register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="UDE" description="Update DMA request enable" />
-      <BitField start="0" size="1" name="UIE" description="Update interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="0" name="SR" access="Read/Write" description="status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UIF" description="Update interrupt flag" />
-    </Register>
-    <Register start="+0x14" size="0" name="EGR" access="WriteOnly" description="event generation register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UG" description="Update generation" />
-    </Register>
-    <Register start="+0x24" size="0" name="CNT" access="Read/Write" description="counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Low counter value" />
-    </Register>
-    <Register start="+0x28" size="0" name="PSC" access="Read/Write" description="prescaler" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PSC" description="Prescaler value" />
-    </Register>
-    <Register start="+0x2C" size="0" name="ARR" access="Read/Write" description="auto-reload register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ARR" description="Low Auto-reload value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="Ethernet_MAC" start="0x40028000" description="Ethernet: media access control&#xa;      (MAC)">
-    <Register start="+0x0" size="0" name="MACCR" access="Read/Write" description="Ethernet MAC configuration&#xa;          register" reset_value="0x0008000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="RE" description="RE" />
-      <BitField start="3" size="1" name="TE" description="TE" />
-      <BitField start="4" size="1" name="DC" description="DC" />
-      <BitField start="5" size="2" name="BL" description="BL" />
-      <BitField start="7" size="1" name="APCS" description="APCS" />
-      <BitField start="9" size="1" name="RD" description="RD" />
-      <BitField start="10" size="1" name="IPCO" description="IPCO" />
-      <BitField start="11" size="1" name="DM" description="DM" />
-      <BitField start="12" size="1" name="LM" description="LM" />
-      <BitField start="13" size="1" name="ROD" description="ROD" />
-      <BitField start="14" size="1" name="FES" description="FES" />
-      <BitField start="16" size="1" name="CSD" description="CSD" />
-      <BitField start="17" size="3" name="IFG" description="IFG" />
-      <BitField start="22" size="1" name="JD" description="JD" />
-      <BitField start="23" size="1" name="WD" description="WD" />
-      <BitField start="25" size="1" name="CSTF" description="CSTF" />
-    </Register>
-    <Register start="+0x4" size="0" name="MACFFR" access="Read/Write" description="Ethernet MAC frame filter&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PM" description="no description available" />
-      <BitField start="1" size="1" name="HU" description="no description available" />
-      <BitField start="2" size="1" name="HM" description="no description available" />
-      <BitField start="3" size="1" name="DAIF" description="no description available" />
-      <BitField start="4" size="1" name="RAM" description="no description available" />
-      <BitField start="5" size="1" name="BFD" description="no description available" />
-      <BitField start="6" size="1" name="PCF" description="no description available" />
-      <BitField start="7" size="1" name="SAIF" description="no description available" />
-      <BitField start="8" size="1" name="SAF" description="no description available" />
-      <BitField start="9" size="1" name="HPF" description="no description available" />
-      <BitField start="31" size="1" name="RA" description="no description available" />
-    </Register>
-    <Register start="+0x8" size="0" name="MACHTHR" access="Read/Write" description="Ethernet MAC hash table high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTH" description="no description available" />
-    </Register>
-    <Register start="+0xC" size="0" name="MACHTLR" access="Read/Write" description="Ethernet MAC hash table low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTL" description="no description available" />
-    </Register>
-    <Register start="+0x10" size="0" name="MACMIIAR" access="Read/Write" description="Ethernet MAC MII address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="no description available" />
-      <BitField start="1" size="1" name="MW" description="no description available" />
-      <BitField start="2" size="3" name="CR" description="no description available" />
-      <BitField start="6" size="5" name="MR" description="no description available" />
-      <BitField start="11" size="5" name="PA" description="no description available" />
-    </Register>
-    <Register start="+0x14" size="0" name="MACMIIDR" access="Read/Write" description="Ethernet MAC MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TD" description="no description available" />
-    </Register>
-    <Register start="+0x18" size="0" name="MACFCR" access="Read/Write" description="Ethernet MAC flow control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCB" description="no description available" />
-      <BitField start="1" size="1" name="TFCE" description="no description available" />
-      <BitField start="2" size="1" name="RFCE" description="no description available" />
-      <BitField start="3" size="1" name="UPFD" description="no description available" />
-      <BitField start="4" size="2" name="PLT" description="no description available" />
-      <BitField start="7" size="1" name="ZQPD" description="no description available" />
-      <BitField start="16" size="16" name="PT" description="no description available" />
-    </Register>
-    <Register start="+0x1C" size="0" name="MACVLANTR" access="Read/Write" description="Ethernet MAC VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VLANTI" description="no description available" />
-      <BitField start="16" size="1" name="VLANTC" description="no description available" />
-    </Register>
-    <Register start="+0x2C" size="0" name="MACPMTCSR" access="Read/Write" description="Ethernet MAC PMT control and status&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="no description available" />
-      <BitField start="1" size="1" name="MPE" description="no description available" />
-      <BitField start="2" size="1" name="WFE" description="no description available" />
-      <BitField start="5" size="1" name="MPR" description="no description available" />
-      <BitField start="6" size="1" name="WFR" description="no description available" />
-      <BitField start="9" size="1" name="GU" description="no description available" />
-      <BitField start="31" size="1" name="WFFRPR" description="no description available" />
-    </Register>
-    <Register start="+0x34" size="0" name="MACDBGR" access="ReadOnly" description="Ethernet MAC debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CR" description="CR" />
-      <BitField start="1" size="1" name="CSR" description="CSR" />
-      <BitField start="2" size="1" name="ROR" description="ROR" />
-      <BitField start="3" size="1" name="MCF" description="MCF" />
-      <BitField start="4" size="1" name="MCP" description="MCP" />
-      <BitField start="5" size="1" name="MCFHP" description="MCFHP" />
-    </Register>
-    <Register start="+0x38" size="0" name="MACSR" access="Read/Write" description="Ethernet MAC interrupt status&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="PMTS" description="no description available" />
-      <BitField start="4" size="1" name="MMCS" description="no description available" />
-      <BitField start="5" size="1" name="MMCRS" description="no description available" />
-      <BitField start="6" size="1" name="MMCTS" description="no description available" />
-      <BitField start="9" size="1" name="TSTS" description="no description available" />
-    </Register>
-    <Register start="+0x3C" size="0" name="MACIMR" access="Read/Write" description="Ethernet MAC interrupt mask&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="PMTIM" description="no description available" />
-      <BitField start="9" size="1" name="TSTIM" description="no description available" />
-    </Register>
-    <Register start="+0x40" size="0" name="MACA0HR" access="Read/Write" description="Ethernet MAC address 0 high&#xa;          register" reset_value="0x0010FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MACA0H" description="MAC address0 high" />
-      <BitField start="31" size="1" name="MO" description="Always 1" />
-    </Register>
-    <Register start="+0x44" size="0" name="MACA0LR" access="Read/Write" description="Ethernet MAC address 0 low&#xa;          register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MACA0L" description="0" />
-    </Register>
-    <Register start="+0x48" size="0" name="MACA1HR" access="Read/Write" description="Ethernet MAC address 1 high&#xa;          register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MACA1H" description="no description available" />
-      <BitField start="24" size="6" name="MBC" description="no description available" />
-      <BitField start="30" size="1" name="SA" description="no description available" />
-      <BitField start="31" size="1" name="AE" description="no description available" />
-    </Register>
-    <Register start="+0x4C" size="0" name="MACA1LR" access="Read/Write" description="Ethernet MAC address1 low&#xa;          register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MACA1LR" description="no description available" />
-    </Register>
-    <Register start="+0x50" size="0" name="MACA2HR" access="Read/Write" description="Ethernet MAC address 2 high&#xa;          register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAC2AH" description="no description available" />
-      <BitField start="24" size="6" name="MBC" description="no description available" />
-      <BitField start="30" size="1" name="SA" description="no description available" />
-      <BitField start="31" size="1" name="AE" description="no description available" />
-    </Register>
-    <Register start="+0x54" size="0" name="MACA2LR" access="Read/Write" description="Ethernet MAC address 2 low&#xa;          register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="MACA2L" description="no description available" />
-    </Register>
-    <Register start="+0x58" size="0" name="MACA3HR" access="Read/Write" description="Ethernet MAC address 3 high&#xa;          register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MACA3H" description="no description available" />
-      <BitField start="24" size="6" name="MBC" description="no description available" />
-      <BitField start="30" size="1" name="SA" description="no description available" />
-      <BitField start="31" size="1" name="AE" description="no description available" />
-    </Register>
-    <Register start="+0x5C" size="0" name="MACA3LR" access="Read/Write" description="Ethernet MAC address 3 low&#xa;          register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MBCA3L" description="no description available" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="Ethernet_MMC" start="0x40028100" description="Ethernet: MAC management counters">
-    <Register start="+0x0" size="0" name="MMCCR" access="Read/Write" description="Ethernet MMC control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CR" description="no description available" />
-      <BitField start="1" size="1" name="CSR" description="no description available" />
-      <BitField start="2" size="1" name="ROR" description="no description available" />
-      <BitField start="3" size="1" name="MCF" description="no description available" />
-      <BitField start="4" size="1" name="MCP" description="no description available" />
-      <BitField start="5" size="1" name="MCFHP" description="no description available" />
-    </Register>
-    <Register start="+0x4" size="0" name="MMCRIR" access="Read/Write" description="Ethernet MMC receive interrupt&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="RFCES" description="no description available" />
-      <BitField start="6" size="1" name="RFAES" description="no description available" />
-      <BitField start="17" size="1" name="RGUFS" description="no description available" />
-    </Register>
-    <Register start="+0x8" size="0" name="MMCTIR" access="ReadOnly" description="Ethernet MMC transmit interrupt&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TGFSCS" description="no description available" />
-      <BitField start="15" size="1" name="TGFMSCS" description="no description available" />
-      <BitField start="21" size="1" name="TGFS" description="no description available" />
-    </Register>
-    <Register start="+0xC" size="0" name="MMCRIMR" access="Read/Write" description="Ethernet MMC receive interrupt mask&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="RFCEM" description="no description available" />
-      <BitField start="6" size="1" name="RFAEM" description="no description available" />
-      <BitField start="17" size="1" name="RGUFM" description="no description available" />
-    </Register>
-    <Register start="+0x10" size="0" name="MMCTIMR" access="Read/Write" description="Ethernet MMC transmit interrupt mask&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="14" size="1" name="TGFSCM" description="no description available" />
-      <BitField start="15" size="1" name="TGFMSCM" description="no description available" />
-      <BitField start="16" size="1" name="TGFM" description="no description available" />
-    </Register>
-    <Register start="+0x4C" size="0" name="MMCTGFSCCR" access="ReadOnly" description="Ethernet MMC transmitted good frames after a&#xa;          single collision counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TGFSCC" description="no description available" />
-    </Register>
-    <Register start="+0x50" size="0" name="MMCTGFMSCCR" access="ReadOnly" description="Ethernet MMC transmitted good frames after&#xa;          more than a single collision" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TGFMSCC" description="no description available" />
-    </Register>
-    <Register start="+0x68" size="0" name="MMCTGFCR" access="ReadOnly" description="Ethernet MMC transmitted good frames counter&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TGFC" description="HTL" />
-    </Register>
-    <Register start="+0x94" size="0" name="MMCRFCECR" access="ReadOnly" description="Ethernet MMC received frames with CRC error&#xa;          counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RFCFC" description="no description available" />
-    </Register>
-    <Register start="+0x98" size="0" name="MMCRFAECR" access="ReadOnly" description="Ethernet MMC received frames with alignment&#xa;          error counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RFAEC" description="no description available" />
-    </Register>
-    <Register start="+0xC4" size="0" name="MMCRGUFCR" access="ReadOnly" description="MMC received good unicast frames counter&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RGUFC" description="no description available" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="Ethernet_PTP" start="0x40028700" description="Ethernet: Precision time protocol">
-    <Register start="+0x0" size="0" name="PTPTSCR" access="Read/Write" description="Ethernet PTP time stamp control&#xa;          register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSE" description="no description available" />
-      <BitField start="1" size="1" name="TSFCU" description="no description available" />
-      <BitField start="10" size="1" name="TSPTPPSV2E" description="no description available" />
-      <BitField start="11" size="1" name="TSSPTPOEFE" description="no description available" />
-      <BitField start="12" size="1" name="TSSIPV6FE" description="no description available" />
-      <BitField start="13" size="1" name="TSSIPV4FE" description="no description available" />
-      <BitField start="14" size="1" name="TSSEME" description="no description available" />
-      <BitField start="15" size="1" name="TSSMRME" description="no description available" />
-      <BitField start="16" size="2" name="TSCNT" description="no description available" />
-      <BitField start="18" size="1" name="TSPFFMAE" description="no description available" />
-      <BitField start="2" size="1" name="TSSTI" description="no description available" />
-      <BitField start="3" size="1" name="TSSTU" description="no description available" />
-      <BitField start="4" size="1" name="TSITE" description="no description available" />
-      <BitField start="5" size="1" name="TTSARU" description="no description available" />
-      <BitField start="8" size="1" name="TSSARFE" description="no description available" />
-      <BitField start="9" size="1" name="TSSSR" description="no description available" />
-    </Register>
-    <Register start="+0x4" size="0" name="PTPSSIR" access="Read/Write" description="Ethernet PTP subsecond increment&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="STSSI" description="no description available" />
-    </Register>
-    <Register start="+0x8" size="0" name="PTPTSHR" access="ReadOnly" description="Ethernet PTP time stamp high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STS" description="no description available" />
-    </Register>
-    <Register start="+0xC" size="0" name="PTPTSLR" access="ReadOnly" description="Ethernet PTP time stamp low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="STSS" description="no description available" />
-      <BitField start="31" size="1" name="STPNS" description="no description available" />
-    </Register>
-    <Register start="+0x10" size="0" name="PTPTSHUR" access="Read/Write" description="Ethernet PTP time stamp high update&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSUS" description="no description available" />
-    </Register>
-    <Register start="+0x14" size="0" name="PTPTSLUR" access="Read/Write" description="Ethernet PTP time stamp low update&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSUSS" description="no description available" />
-      <BitField start="31" size="1" name="TSUPNS" description="no description available" />
-    </Register>
-    <Register start="+0x18" size="0" name="PTPTSAR" access="Read/Write" description="Ethernet PTP time stamp addend&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSA" description="no description available" />
-    </Register>
-    <Register start="+0x1C" size="0" name="PTPTTHR" access="Read/Write" description="Ethernet PTP target time high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TTSH" description="0" />
-    </Register>
-    <Register start="+0x20" size="0" name="PTPTTLR" access="Read/Write" description="Ethernet PTP target time low&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TTSL" description="no description available" />
-    </Register>
-    <Register start="+0x28" size="0" name="PTPTSSR" access="ReadOnly" description="Ethernet PTP time stamp status&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSO" description="no description available" />
-      <BitField start="1" size="1" name="TSTTR" description="no description available" />
-    </Register>
-    <Register start="+0x2C" size="0" name="PTPPPSCR" access="ReadOnly" description="Ethernet PTP PPS control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSO" description="TSSO" />
-      <BitField start="1" size="1" name="TSTTR" description="TSTTR" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="Ethernet_DMA" start="0x40029000" description="Ethernet: DMA controller operation">
-    <Register start="+0x0" size="0" name="DMABMR" access="Read/Write" description="Ethernet DMA bus mode register" reset_value="0x00002101" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR" description="no description available" />
-      <BitField start="1" size="1" name="DA" description="no description available" />
-      <BitField start="2" size="5" name="DSL" description="no description available" />
-      <BitField start="7" size="1" name="EDFE" description="no description available" />
-      <BitField start="8" size="6" name="PBL" description="no description available" />
-      <BitField start="14" size="2" name="RTPR" description="no description available" />
-      <BitField start="16" size="1" name="FB" description="no description available" />
-      <BitField start="17" size="6" name="RDP" description="no description available" />
-      <BitField start="23" size="1" name="USP" description="no description available" />
-      <BitField start="24" size="1" name="FPM" description="no description available" />
-      <BitField start="25" size="1" name="AAB" description="no description available" />
-      <BitField start="26" size="1" name="MB" description="no description available" />
-    </Register>
-    <Register start="+0x4" size="0" name="DMATPDR" access="Read/Write" description="Ethernet DMA transmit poll demand&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TPD" description="no description available" />
-    </Register>
-    <Register start="+0x8" size="0" name="DMARPDR" access="Read/Write" description="EHERNET DMA receive poll demand&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RPD" description="RPD" />
-    </Register>
-    <Register start="+0xC" size="0" name="DMARDLAR" access="Read/Write" description="Ethernet DMA receive descriptor list address&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="no description available" />
-    </Register>
-    <Register start="+0x10" size="0" name="DMATDLAR" access="Read/Write" description="Ethernet DMA transmit descriptor list&#xa;          address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STL" description="no description available" />
-    </Register>
-    <Register start="+0x14" size="0" name="DMASR" access="Read/Write" description="Ethernet DMA status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TS" description="no description available" />
-      <BitField start="1" size="1" name="TPSS" description="no description available" />
-      <BitField start="2" size="1" name="TBUS" description="no description available" />
-      <BitField start="3" size="1" name="TJTS" description="no description available" />
-      <BitField start="4" size="1" name="ROS" description="no description available" />
-      <BitField start="5" size="1" name="TUS" description="no description available" />
-      <BitField start="6" size="1" name="RS" description="no description available" />
-      <BitField start="7" size="1" name="RBUS" description="no description available" />
-      <BitField start="8" size="1" name="RPSS" description="no description available" />
-      <BitField start="9" size="1" name="PWTS" description="no description available" />
-      <BitField start="10" size="1" name="ETS" description="no description available" />
-      <BitField start="13" size="1" name="FBES" description="no description available" />
-      <BitField start="14" size="1" name="ERS" description="no description available" />
-      <BitField start="15" size="1" name="AIS" description="no description available" />
-      <BitField start="16" size="1" name="NIS" description="no description available" />
-      <BitField start="17" size="3" name="RPS" description="no description available" />
-      <BitField start="20" size="3" name="TPS" description="no description available" />
-      <BitField start="23" size="3" name="EBS" description="no description available" />
-      <BitField start="27" size="1" name="MMCS" description="no description available" />
-      <BitField start="28" size="1" name="PMTS" description="no description available" />
-      <BitField start="29" size="1" name="TSTS" description="no description available" />
-    </Register>
-    <Register start="+0x18" size="0" name="DMAOMR" access="Read/Write" description="Ethernet DMA operation mode&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="SR" description="SR" />
-      <BitField start="2" size="1" name="OSF" description="OSF" />
-      <BitField start="3" size="2" name="RTC" description="RTC" />
-      <BitField start="6" size="1" name="FUGF" description="FUGF" />
-      <BitField start="7" size="1" name="FEF" description="FEF" />
-      <BitField start="13" size="1" name="ST" description="ST" />
-      <BitField start="14" size="3" name="TTC" description="TTC" />
-      <BitField start="20" size="1" name="FTF" description="FTF" />
-      <BitField start="21" size="1" name="TSF" description="TSF" />
-      <BitField start="24" size="1" name="DFRF" description="DFRF" />
-      <BitField start="25" size="1" name="RSF" description="RSF" />
-      <BitField start="26" size="1" name="DTCEFD" description="DTCEFD" />
-    </Register>
-    <Register start="+0x1C" size="0" name="DMAIER" access="Read/Write" description="Ethernet DMA interrupt enable&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIE" description="no description available" />
-      <BitField start="1" size="1" name="TPSIE" description="no description available" />
-      <BitField start="2" size="1" name="TBUIE" description="no description available" />
-      <BitField start="3" size="1" name="TJTIE" description="no description available" />
-      <BitField start="4" size="1" name="ROIE" description="no description available" />
-      <BitField start="5" size="1" name="TUIE" description="no description available" />
-      <BitField start="6" size="1" name="RIE" description="no description available" />
-      <BitField start="7" size="1" name="RBUIE" description="no description available" />
-      <BitField start="8" size="1" name="RPSIE" description="no description available" />
-      <BitField start="9" size="1" name="RWTIE" description="no description available" />
-      <BitField start="10" size="1" name="ETIE" description="no description available" />
-      <BitField start="13" size="1" name="FBEIE" description="no description available" />
-      <BitField start="14" size="1" name="ERIE" description="no description available" />
-      <BitField start="15" size="1" name="AISE" description="no description available" />
-      <BitField start="16" size="1" name="NISE" description="no description available" />
-    </Register>
-    <Register start="+0x20" size="0" name="DMAMFBOCR" access="Read/Write" description="Ethernet DMA missed frame and buffer&#xa;          overflow counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MFC" description="no description available" />
-      <BitField start="16" size="1" name="OMFC" description="no description available" />
-      <BitField start="17" size="11" name="MFA" description="no description available" />
-      <BitField start="28" size="1" name="OFOC" description="no description available" />
-    </Register>
-    <Register start="+0x24" size="0" name="DMARSWTR" access="Read/Write" description="Ethernet DMA receive status watchdog timer&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RSWTC" description="RSWTC" />
-    </Register>
-    <Register start="+0x48" size="0" name="DMACHTDR" access="ReadOnly" description="Ethernet DMA current host transmit&#xa;          descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTDAP" description="HTDAP" />
-    </Register>
-    <Register start="+0x4C" size="0" name="DMACHRDR" access="ReadOnly" description="Ethernet DMA current host receive descriptor&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRDAP" description="HRDAP" />
-    </Register>
-    <Register start="+0x50" size="0" name="DMACHTBAR" access="ReadOnly" description="Ethernet DMA current host transmit buffer&#xa;          address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTBAP" description="no description available" />
-    </Register>
-    <Register start="+0x54" size="0" name="DMACHRBAR" access="ReadOnly" description="Ethernet DMA current host receive buffer&#xa;          address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRBAP" description="no description available" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CRC" start="0x40023000" description="Cryptographic processor">
-    <Register start="+0x0" size="0" name="DR" access="Read/Write" description="Data register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DR" description="Data Register" />
-    </Register>
-    <Register start="+0x4" size="0" name="IDR" access="Read/Write" description="Independent Data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IDR" description="Independent Data register" />
-    </Register>
-    <Register start="+0x8" size="0" name="CR" access="WriteOnly" description="Control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CR" description="Control regidter" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_FS_GLOBAL" start="0x50000000" description="USB on the go full speed">
-    <Register start="+0x0" size="0" name="FS_GOTGCTL" access="Read/Write" description="OTG_FS control and status register&#xa;          (OTG_FS_GOTGCTL)" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SRQSCS" description="Session request success" />
-      <BitField start="1" size="1" name="SRQ" description="Session request" />
-      <BitField start="8" size="1" name="HNGSCS" description="Host negotiation success" />
-      <BitField start="9" size="1" name="HNPRQ" description="HNP request" />
-      <BitField start="10" size="1" name="HSHNPEN" description="Host set HNP enable" />
-      <BitField start="11" size="1" name="DHNPEN" description="Device HNP enabled" />
-      <BitField start="16" size="1" name="CIDSTS" description="Connector ID status" />
-      <BitField start="17" size="1" name="DBCT" description="Long/short debounce time" />
-      <BitField start="18" size="1" name="ASVLD" description="A-session valid" />
-      <BitField start="19" size="1" name="BSVLD" description="B-session valid" />
-    </Register>
-    <Register start="+0x4" size="0" name="FS_GOTGINT" access="Read/Write" description="OTG_FS interrupt register&#xa;          (OTG_FS_GOTGINT)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="SEDET" description="Session end detected" />
-      <BitField start="8" size="1" name="SRSSCHG" description="Session request success status&#xa;              change" />
-      <BitField start="9" size="1" name="HNSSCHG" description="Host negotiation success status&#xa;              change" />
-      <BitField start="17" size="1" name="HNGDET" description="Host negotiation detected" />
-      <BitField start="18" size="1" name="ADTOCHG" description="A-device timeout change" />
-      <BitField start="19" size="1" name="DBCDNE" description="Debounce done" />
-    </Register>
-    <Register start="+0x8" size="0" name="FS_GAHBCFG" access="Read/Write" description="OTG_FS AHB configuration register&#xa;          (OTG_FS_GAHBCFG)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GINT" description="Global interrupt mask" />
-      <BitField start="7" size="1" name="TXFELVL" description="TxFIFO empty level" />
-      <BitField start="8" size="1" name="PTXFELVL" description="Periodic TxFIFO empty&#xa;              level" />
-    </Register>
-    <Register start="+0xC" size="0" name="FS_GUSBCFG" access="Read/Write" description="OTG_FS USB configuration register&#xa;          (OTG_FS_GUSBCFG)" reset_value="0x00000A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="TOCAL" description="FS timeout calibration" />
-      <BitField start="6" size="1" name="PHYSEL" description="Full Speed serial transceiver&#xa;              select" />
-      <BitField start="8" size="1" name="SRPCAP" description="SRP-capable" />
-      <BitField start="9" size="1" name="HNPCAP" description="HNP-capable" />
-      <BitField start="10" size="4" name="TRDT" description="USB turnaround time" />
-      <BitField start="29" size="1" name="FHMOD" description="Force host mode" />
-      <BitField start="30" size="1" name="FDMOD" description="Force device mode" />
-      <BitField start="31" size="1" name="CTXPKT" description="Corrupt Tx packet" />
-    </Register>
-    <Register start="+0x10" size="0" name="FS_GRSTCTL" access="Read/Write" description="OTG_FS reset register&#xa;          (OTG_FS_GRSTCTL)" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSRST" description="Core soft reset" />
-      <BitField start="1" size="1" name="HSRST" description="HCLK soft reset" />
-      <BitField start="2" size="1" name="FCRST" description="Host frame counter reset" />
-      <BitField start="4" size="1" name="RXFFLSH" description="RxFIFO flush" />
-      <BitField start="5" size="1" name="TXFFLSH" description="TxFIFO flush" />
-      <BitField start="6" size="5" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="31" size="1" name="AHBIDL" description="AHB master idle" />
-    </Register>
-    <Register start="+0x14" size="0" name="FS_GINTSTS" access="Read/Write" description="OTG_FS core interrupt register&#xa;          (OTG_FS_GINTSTS)" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMOD" description="Current mode of operation" />
-      <BitField start="1" size="1" name="MMIS" description="Mode mismatch interrupt" />
-      <BitField start="2" size="1" name="OTGINT" description="OTG interrupt" />
-      <BitField start="3" size="1" name="SOF" description="Start of frame" />
-      <BitField start="4" size="1" name="RXFLVL" description="RxFIFO non-empty" />
-      <BitField start="5" size="1" name="NPTXFE" description="Non-periodic TxFIFO empty" />
-      <BitField start="6" size="1" name="GINAKEFF" description="Global IN non-periodic NAK&#xa;              effective" />
-      <BitField start="7" size="1" name="GOUTNAKEFF" description="Global OUT NAK effective" />
-      <BitField start="10" size="1" name="ESUSP" description="Early suspend" />
-      <BitField start="11" size="1" name="USBSUSP" description="USB suspend" />
-      <BitField start="12" size="1" name="USBRST" description="USB reset" />
-      <BitField start="13" size="1" name="ENUMDNE" description="Enumeration done" />
-      <BitField start="14" size="1" name="ISOODRP" description="Isochronous OUT packet dropped&#xa;              interrupt" />
-      <BitField start="15" size="1" name="EOPF" description="End of periodic frame&#xa;              interrupt" />
-      <BitField start="18" size="1" name="IEPINT" description="IN endpoint interrupt" />
-      <BitField start="19" size="1" name="OEPINT" description="OUT endpoint interrupt" />
-      <BitField start="20" size="1" name="IISOIXFR" description="Incomplete isochronous IN&#xa;              transfer" />
-      <BitField start="21" size="1" name="IPXFR_INCOMPISOOUT" description="Incomplete periodic transfer(Host&#xa;              mode)/Incomplete isochronous OUT transfer(Device&#xa;              mode)" />
-      <BitField start="24" size="1" name="HPRTINT" description="Host port interrupt" />
-      <BitField start="25" size="1" name="HCINT" description="Host channels interrupt" />
-      <BitField start="26" size="1" name="PTXFE" description="Periodic TxFIFO empty" />
-      <BitField start="28" size="1" name="CIDSCHG" description="Connector ID status change" />
-      <BitField start="29" size="1" name="DISCINT" description="Disconnect detected&#xa;              interrupt" />
-      <BitField start="30" size="1" name="SRQINT" description="Session request/new session detected&#xa;              interrupt" />
-      <BitField start="31" size="1" name="WKUPINT" description="Resume/remote wakeup detected&#xa;              interrupt" />
-    </Register>
-    <Register start="+0x18" size="0" name="FS_GINTMSK" access="Read/Write" description="OTG_FS interrupt mask register&#xa;          (OTG_FS_GINTMSK)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="MMISM" description="Mode mismatch interrupt&#xa;              mask" />
-      <BitField start="2" size="1" name="OTGINT" description="OTG interrupt mask" />
-      <BitField start="3" size="1" name="SOFM" description="Start of frame mask" />
-      <BitField start="4" size="1" name="RXFLVLM" description="Receive FIFO non-empty&#xa;              mask" />
-      <BitField start="5" size="1" name="NPTXFEM" description="Non-periodic TxFIFO empty&#xa;              mask" />
-      <BitField start="6" size="1" name="GINAKEFFM" description="Global non-periodic IN NAK effective&#xa;              mask" />
-      <BitField start="7" size="1" name="GONAKEFFM" description="Global OUT NAK effective&#xa;              mask" />
-      <BitField start="10" size="1" name="ESUSPM" description="Early suspend mask" />
-      <BitField start="11" size="1" name="USBSUSPM" description="USB suspend mask" />
-      <BitField start="12" size="1" name="USBRST" description="USB reset mask" />
-      <BitField start="13" size="1" name="ENUMDNEM" description="Enumeration done mask" />
-      <BitField start="14" size="1" name="ISOODRPM" description="Isochronous OUT packet dropped interrupt&#xa;              mask" />
-      <BitField start="15" size="1" name="EOPFM" description="End of periodic frame interrupt&#xa;              mask" />
-      <BitField start="17" size="1" name="EPMISM" description="Endpoint mismatch interrupt&#xa;              mask" />
-      <BitField start="18" size="1" name="IEPINT" description="IN endpoints interrupt&#xa;              mask" />
-      <BitField start="19" size="1" name="OEPINT" description="OUT endpoints interrupt&#xa;              mask" />
-      <BitField start="20" size="1" name="IISOIXFRM" description="Incomplete isochronous IN transfer&#xa;              mask" />
-      <BitField start="21" size="1" name="IPXFRM_IISOOXFRM" description="Incomplete periodic transfer mask(Host&#xa;              mode)/Incomplete isochronous OUT transfer mask(Device&#xa;              mode)" />
-      <BitField start="24" size="1" name="PRTIM" description="Host port interrupt mask" />
-      <BitField start="25" size="1" name="HCIM" description="Host channels interrupt&#xa;              mask" />
-      <BitField start="26" size="1" name="PTXFEM" description="Periodic TxFIFO empty mask" />
-      <BitField start="28" size="1" name="CIDSCHGM" description="Connector ID status change&#xa;              mask" />
-      <BitField start="29" size="1" name="DISCINT" description="Disconnect detected interrupt&#xa;              mask" />
-      <BitField start="30" size="1" name="SRQIM" description="Session request/new session detected&#xa;              interrupt mask" />
-      <BitField start="31" size="1" name="WUIM" description="Resume/remote wakeup detected interrupt&#xa;              mask" />
-    </Register>
-    <Register start="+0x1C" size="0" name="FS_GRXSTSR_Device" access="ReadOnly" description="OTG_FS Receive status debug read(Device&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="4" size="11" name="BCNT" description="Byte count" />
-      <BitField start="15" size="2" name="DPID" description="Data PID" />
-      <BitField start="17" size="4" name="PKTSTS" description="Packet status" />
-      <BitField start="21" size="4" name="FRMNUM" description="Frame number" />
-    </Register>
-    <Register start="+0x1C" size="0" name="FS_GRXSTSR_Host" access="ReadOnly" description="OTG_FS Receive status debug read(Host&#xa;          mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="4" size="11" name="BCNT" description="Byte count" />
-      <BitField start="15" size="2" name="DPID" description="Data PID" />
-      <BitField start="17" size="4" name="PKTSTS" description="Packet status" />
-      <BitField start="21" size="4" name="FRMNUM" description="Frame number" />
-    </Register>
-    <Register start="+0x24" size="0" name="FS_GRXFSIZ" access="Read/Write" description="OTG_FS Receive FIFO size register&#xa;          (OTG_FS_GRXFSIZ)" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXFD" description="RxFIFO depth" />
-    </Register>
-    <Register start="+0x28" size="0" name="FS_GNPTXFSIZ_Device" access="Read/Write" description="OTG_FS non-periodic transmit FIFO size&#xa;          register (Device mode)" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TX0FSA" description="Endpoint 0 transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="TX0FD" description="Endpoint 0 TxFIFO depth" />
-    </Register>
-    <Register start="+0x28" size="0" name="FS_GNPTXFSIZ_Host" access="Read/Write" description="OTG_FS non-periodic transmit FIFO size&#xa;          register (Host mode)" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NPTXFSA" description="Non-periodic transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="NPTXFD" description="Non-periodic TxFIFO depth" />
-    </Register>
-    <Register start="+0x2C" size="0" name="FS_GNPTXSTS" access="ReadOnly" description="OTG_FS non-periodic transmit FIFO/queue&#xa;          status register (OTG_FS_GNPTXSTS)" reset_value="0x00080200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NPTXFSAV" description="Non-periodic TxFIFO space&#xa;              available" />
-      <BitField start="16" size="8" name="NPTQXSAV" description="Non-periodic transmit request queue&#xa;              space available" />
-      <BitField start="24" size="7" name="NPTXQTOP" description="Top of the non-periodic transmit request&#xa;              queue" />
-    </Register>
-    <Register start="+0x38" size="0" name="FS_GCCFG" access="Read/Write" description="OTG_FS general core configuration register&#xa;          (OTG_FS_GCCFG)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="PWRDWN" description="Power down" />
-      <BitField start="18" size="1" name="VBUSASEN" description="Enable the VBUS sensing&#xa;              device" />
-      <BitField start="19" size="1" name="VBUSBSEN" description="Enable the VBUS sensing&#xa;              device" />
-      <BitField start="20" size="1" name="SOFOUTEN" description="SOF output enable" />
-    </Register>
-    <Register start="+0x3C" size="0" name="FS_CID" access="Read/Write" description="core ID register" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PRODUCT_ID" description="Product ID field" />
-    </Register>
-    <Register start="+0x100" size="0" name="FS_HPTXFSIZ" access="Read/Write" description="OTG_FS Host periodic transmit FIFO size&#xa;          register (OTG_FS_HPTXFSIZ)" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PTXSA" description="Host periodic TxFIFO start&#xa;              address" />
-      <BitField start="16" size="16" name="PTXFSIZ" description="Host periodic TxFIFO depth" />
-    </Register>
-    <Register start="+0x104" size="0" name="FS_DIEPTXF1" access="Read/Write" description="OTG_FS device IN endpoint transmit FIFO size&#xa;          register (OTG_FS_DIEPTXF2)" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFO2 transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x108" size="0" name="FS_DIEPTXF2" access="Read/Write" description="OTG_FS device IN endpoint transmit FIFO size&#xa;          register (OTG_FS_DIEPTXF3)" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFO3 transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x10C" size="0" name="FS_DIEPTXF3" access="Read/Write" description="OTG_FS device IN endpoint transmit FIFO size&#xa;          register (OTG_FS_DIEPTXF4)" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFO4 transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_FS_HOST" start="0x50000400" description="USB on the go full speed">
-    <Register start="+0x0" size="0" name="FS_HCFG" access="Read/Write" description="OTG_FS host configuration register&#xa;          (OTG_FS_HCFG)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="FSLSPCS" description="FS/LS PHY clock select" />
-      <BitField start="2" size="1" name="FSLSS" description="FS- and LS-only support" />
-    </Register>
-    <Register start="+0x4" size="0" name="HFIR" access="Read/Write" description="OTG_FS Host frame interval&#xa;          register" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FRIVL" description="Frame interval" />
-    </Register>
-    <Register start="+0x8" size="0" name="FS_HFNUM" access="ReadOnly" description="OTG_FS host frame number/frame time&#xa;          remaining register (OTG_FS_HFNUM)" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FRNUM" description="Frame number" />
-      <BitField start="16" size="16" name="FTREM" description="Frame time remaining" />
-    </Register>
-    <Register start="+0x10" size="0" name="FS_HPTXSTS" access="Read/Write" description="OTG_FS_Host periodic transmit FIFO/queue&#xa;          status register (OTG_FS_HPTXSTS)" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PTXFSAVL" description="Periodic transmit data FIFO space&#xa;              available" />
-      <BitField start="16" size="8" name="PTXQSAV" description="Periodic transmit request queue space&#xa;              available" />
-      <BitField start="24" size="8" name="PTXQTOP" description="Top of the periodic transmit request&#xa;              queue" />
-    </Register>
-    <Register start="+0x14" size="0" name="HAINT" access="ReadOnly" description="OTG_FS Host all channels interrupt&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HAINT" description="Channel interrupts" />
-    </Register>
-    <Register start="+0x18" size="0" name="HAINTMSK" access="Read/Write" description="OTG_FS host all channels interrupt mask&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HAINTM" description="Channel interrupt mask" />
-    </Register>
-    <Register start="+0x40" size="0" name="FS_HPRT" access="Read/Write" description="OTG_FS host port control and status register&#xa;          (OTG_FS_HPRT)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCSTS" description="Port connect status" />
-      <BitField start="1" size="1" name="PCDET" description="Port connect detected" />
-      <BitField start="2" size="1" name="PENA" description="Port enable" />
-      <BitField start="3" size="1" name="PENCHNG" description="Port enable/disable change" />
-      <BitField start="4" size="1" name="POCA" description="Port overcurrent active" />
-      <BitField start="5" size="1" name="POCCHNG" description="Port overcurrent change" />
-      <BitField start="6" size="1" name="PRES" description="Port resume" />
-      <BitField start="7" size="1" name="PSUSP" description="Port suspend" />
-      <BitField start="8" size="1" name="PRST" description="Port reset" />
-      <BitField start="10" size="2" name="PLSTS" description="Port line status" />
-      <BitField start="12" size="1" name="PPWR" description="Port power" />
-      <BitField start="13" size="4" name="PTCTL" description="Port test control" />
-      <BitField start="17" size="2" name="PSPD" description="Port speed" />
-    </Register>
-    <Register start="+0x100" size="0" name="FS_HCCHAR0" access="Read/Write" description="OTG_FS host channel-0 characteristics&#xa;          register (OTG_FS_HCCHAR0)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x120" size="0" name="FS_HCCHAR1" access="Read/Write" description="OTG_FS host channel-1 characteristics&#xa;          register (OTG_FS_HCCHAR1)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x140" size="0" name="FS_HCCHAR2" access="Read/Write" description="OTG_FS host channel-2 characteristics&#xa;          register (OTG_FS_HCCHAR2)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x160" size="0" name="FS_HCCHAR3" access="Read/Write" description="OTG_FS host channel-3 characteristics&#xa;          register (OTG_FS_HCCHAR3)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x180" size="0" name="FS_HCCHAR4" access="Read/Write" description="OTG_FS host channel-4 characteristics&#xa;          register (OTG_FS_HCCHAR4)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x1A0" size="0" name="FS_HCCHAR5" access="Read/Write" description="OTG_FS host channel-5 characteristics&#xa;          register (OTG_FS_HCCHAR5)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x1C0" size="0" name="FS_HCCHAR6" access="Read/Write" description="OTG_FS host channel-6 characteristics&#xa;          register (OTG_FS_HCCHAR6)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x1E0" size="0" name="FS_HCCHAR7" access="Read/Write" description="OTG_FS host channel-7 characteristics&#xa;          register (OTG_FS_HCCHAR7)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MCNT" description="Multicount" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x108" size="0" name="FS_HCINT0" access="Read/Write" description="OTG_FS host channel-0 interrupt register&#xa;          (OTG_FS_HCINT0)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x128" size="0" name="FS_HCINT1" access="Read/Write" description="OTG_FS host channel-1 interrupt register&#xa;          (OTG_FS_HCINT1)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x148" size="0" name="FS_HCINT2" access="Read/Write" description="OTG_FS host channel-2 interrupt register&#xa;          (OTG_FS_HCINT2)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x168" size="0" name="FS_HCINT3" access="Read/Write" description="OTG_FS host channel-3 interrupt register&#xa;          (OTG_FS_HCINT3)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x188" size="0" name="FS_HCINT4" access="Read/Write" description="OTG_FS host channel-4 interrupt register&#xa;          (OTG_FS_HCINT4)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x1A8" size="0" name="FS_HCINT5" access="Read/Write" description="OTG_FS host channel-5 interrupt register&#xa;          (OTG_FS_HCINT5)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x1C8" size="0" name="FS_HCINT6" access="Read/Write" description="OTG_FS host channel-6 interrupt register&#xa;          (OTG_FS_HCINT6)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x1E8" size="0" name="FS_HCINT7" access="Read/Write" description="OTG_FS host channel-7 interrupt register&#xa;          (OTG_FS_HCINT7)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x10C" size="0" name="FS_HCINTMSK0" access="Read/Write" description="OTG_FS host channel-0 mask register&#xa;          (OTG_FS_HCINTMSK0)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x12C" size="0" name="FS_HCINTMSK1" access="Read/Write" description="OTG_FS host channel-1 mask register&#xa;          (OTG_FS_HCINTMSK1)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x14C" size="0" name="FS_HCINTMSK2" access="Read/Write" description="OTG_FS host channel-2 mask register&#xa;          (OTG_FS_HCINTMSK2)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x16C" size="0" name="FS_HCINTMSK3" access="Read/Write" description="OTG_FS host channel-3 mask register&#xa;          (OTG_FS_HCINTMSK3)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x18C" size="0" name="FS_HCINTMSK4" access="Read/Write" description="OTG_FS host channel-4 mask register&#xa;          (OTG_FS_HCINTMSK4)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x1AC" size="0" name="FS_HCINTMSK5" access="Read/Write" description="OTG_FS host channel-5 mask register&#xa;          (OTG_FS_HCINTMSK5)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x1CC" size="0" name="FS_HCINTMSK6" access="Read/Write" description="OTG_FS host channel-6 mask register&#xa;          (OTG_FS_HCINTMSK6)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x1EC" size="0" name="FS_HCINTMSK7" access="Read/Write" description="OTG_FS host channel-7 mask register&#xa;          (OTG_FS_HCINTMSK7)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x110" size="0" name="FS_HCTSIZ0" access="Read/Write" description="OTG_FS host channel-0 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x130" size="0" name="FS_HCTSIZ1" access="Read/Write" description="OTG_FS host channel-1 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x150" size="0" name="FS_HCTSIZ2" access="Read/Write" description="OTG_FS host channel-2 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x170" size="0" name="FS_HCTSIZ3" access="Read/Write" description="OTG_FS host channel-3 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x190" size="0" name="FS_HCTSIZ4" access="Read/Write" description="OTG_FS host channel-x transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x1B0" size="0" name="FS_HCTSIZ5" access="Read/Write" description="OTG_FS host channel-5 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x1D0" size="0" name="FS_HCTSIZ6" access="Read/Write" description="OTG_FS host channel-6 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x1F0" size="0" name="FS_HCTSIZ7" access="Read/Write" description="OTG_FS host channel-7 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_FS_DEVICE" start="0x50000800" description="USB on the go full speed">
-    <Register start="+0x0" size="0" name="FS_DCFG" access="Read/Write" description="OTG_FS device configuration register&#xa;          (OTG_FS_DCFG)" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="DSPD" description="Device speed" />
-      <BitField start="2" size="1" name="NZLSOHSK" description="Non-zero-length status OUT&#xa;              handshake" />
-      <BitField start="4" size="7" name="DAD" description="Device address" />
-      <BitField start="11" size="2" name="PFIVL" description="Periodic frame interval" />
-    </Register>
-    <Register start="+0x4" size="0" name="FS_DCTL" access="Read/Write" description="OTG_FS device control register&#xa;          (OTG_FS_DCTL)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RWUSIG" description="Remote wakeup signaling" />
-      <BitField start="1" size="1" name="SDIS" description="Soft disconnect" />
-      <BitField start="2" size="1" name="GINSTS" description="Global IN NAK status" />
-      <BitField start="3" size="1" name="GONSTS" description="Global OUT NAK status" />
-      <BitField start="4" size="3" name="TCTL" description="Test control" />
-      <BitField start="7" size="1" name="SGINAK" description="Set global IN NAK" />
-      <BitField start="8" size="1" name="CGINAK" description="Clear global IN NAK" />
-      <BitField start="9" size="1" name="SGONAK" description="Set global OUT NAK" />
-      <BitField start="10" size="1" name="CGONAK" description="Clear global OUT NAK" />
-      <BitField start="11" size="1" name="POPRGDNE" description="Power-on programming done" />
-    </Register>
-    <Register start="+0x8" size="0" name="FS_DSTS" access="ReadOnly" description="OTG_FS device status register&#xa;          (OTG_FS_DSTS)" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPSTS" description="Suspend status" />
-      <BitField start="1" size="2" name="ENUMSPD" description="Enumerated speed" />
-      <BitField start="3" size="1" name="EERR" description="Erratic error" />
-      <BitField start="8" size="14" name="FNSOF" description="Frame number of the received&#xa;              SOF" />
-    </Register>
-    <Register start="+0x10" size="0" name="FS_DIEPMSK" access="Read/Write" description="OTG_FS device IN endpoint common interrupt&#xa;          mask register (OTG_FS_DIEPMSK)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed interrupt&#xa;              mask" />
-      <BitField start="1" size="1" name="EPDM" description="Endpoint disabled interrupt&#xa;              mask" />
-      <BitField start="3" size="1" name="TOM" description="Timeout condition mask (Non-isochronous&#xa;              endpoints)" />
-      <BitField start="4" size="1" name="ITTXFEMSK" description="IN token received when TxFIFO empty&#xa;              mask" />
-      <BitField start="5" size="1" name="INEPNMM" description="IN token received with EP mismatch&#xa;              mask" />
-      <BitField start="6" size="1" name="INEPNEM" description="IN endpoint NAK effective&#xa;              mask" />
-    </Register>
-    <Register start="+0x14" size="0" name="FS_DOEPMSK" access="Read/Write" description="OTG_FS device OUT endpoint common interrupt&#xa;          mask register (OTG_FS_DOEPMSK)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed interrupt&#xa;              mask" />
-      <BitField start="1" size="1" name="EPDM" description="Endpoint disabled interrupt&#xa;              mask" />
-      <BitField start="3" size="1" name="STUPM" description="SETUP phase done mask" />
-      <BitField start="4" size="1" name="OTEPDM" description="OUT token received when endpoint&#xa;              disabled mask" />
-    </Register>
-    <Register start="+0x18" size="0" name="FS_DAINT" access="ReadOnly" description="OTG_FS device all endpoints interrupt&#xa;          register (OTG_FS_DAINT)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="IEPINT" description="IN endpoint interrupt bits" />
-      <BitField start="16" size="16" name="OEPINT" description="OUT endpoint interrupt&#xa;              bits" />
-    </Register>
-    <Register start="+0x1C" size="0" name="FS_DAINTMSK" access="Read/Write" description="OTG_FS all endpoints interrupt mask register&#xa;          (OTG_FS_DAINTMSK)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="IEPM" description="IN EP interrupt mask bits" />
-      <BitField start="16" size="16" name="OEPINT" description="OUT endpoint interrupt&#xa;              bits" />
-    </Register>
-    <Register start="+0x28" size="0" name="DVBUSDIS" access="Read/Write" description="OTG_FS device VBUS discharge time&#xa;          register" reset_value="0x000017D7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VBUSDT" description="Device VBUS discharge time" />
-    </Register>
-    <Register start="+0x2C" size="0" name="DVBUSPULSE" access="Read/Write" description="OTG_FS device VBUS pulsing time&#xa;          register" reset_value="0x000005B8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DVBUSP" description="Device VBUS pulsing time" />
-    </Register>
-    <Register start="+0x34" size="0" name="DIEPEMPMSK" access="Read/Write" description="OTG_FS device IN endpoint FIFO empty&#xa;          interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask&#xa;              bits" />
-    </Register>
-    <Register start="+0x100" size="0" name="FS_DIEPCTL0" access="Read/Write" description="OTG_FS device control IN endpoint 0 control&#xa;          register (OTG_FS_DIEPCTL0)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="STALL" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x120" size="0" name="DIEPCTL1" access="Read/Write" description="OTG device endpoint-1 control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="29" size="1" name="SODDFRM_SD1PID" description="SODDFRM/SD1PID" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="SD0PID/SEVNFRM" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="22" size="4" name="TXFNUM" description="TXFNUM" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="EONUM/DPID" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="11" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x140" size="0" name="DIEPCTL2" access="Read/Write" description="OTG device endpoint-2 control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="29" size="1" name="SODDFRM" description="SODDFRM" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="SD0PID/SEVNFRM" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="22" size="4" name="TXFNUM" description="TXFNUM" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="EONUM/DPID" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="11" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x160" size="0" name="DIEPCTL3" access="Read/Write" description="OTG device endpoint-3 control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="29" size="1" name="SODDFRM" description="SODDFRM" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="SD0PID/SEVNFRM" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="22" size="4" name="TXFNUM" description="TXFNUM" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="EONUM/DPID" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="11" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x300" size="0" name="DOEPCTL0" access="Read/Write" description="device endpoint-0 control&#xa;          register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="20" size="1" name="SNPM" description="SNPM" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="2" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x320" size="0" name="DOEPCTL1" access="Read/Write" description="device endpoint-1 control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="29" size="1" name="SODDFRM" description="SODDFRM" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="SD0PID/SEVNFRM" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="20" size="1" name="SNPM" description="SNPM" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="EONUM/DPID" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="11" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x340" size="0" name="DOEPCTL2" access="Read/Write" description="device endpoint-2 control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="29" size="1" name="SODDFRM" description="SODDFRM" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="SD0PID/SEVNFRM" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="20" size="1" name="SNPM" description="SNPM" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="EONUM/DPID" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="11" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x360" size="0" name="DOEPCTL3" access="Read/Write" description="device endpoint-3 control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="EPENA" description="EPENA" />
-      <BitField start="30" size="1" name="EPDIS" description="EPDIS" />
-      <BitField start="29" size="1" name="SODDFRM" description="SODDFRM" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="SD0PID/SEVNFRM" />
-      <BitField start="27" size="1" name="SNAK" description="SNAK" />
-      <BitField start="26" size="1" name="CNAK" description="CNAK" />
-      <BitField start="21" size="1" name="Stall" description="Stall" />
-      <BitField start="20" size="1" name="SNPM" description="SNPM" />
-      <BitField start="18" size="2" name="EPTYP" description="EPTYP" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAKSTS" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="EONUM/DPID" />
-      <BitField start="15" size="1" name="USBAEP" description="USBAEP" />
-      <BitField start="0" size="11" name="MPSIZ" description="MPSIZ" />
-    </Register>
-    <Register start="+0x108" size="0" name="DIEPINT0" access="Read/Write" description="device endpoint-x interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXFE" description="TXFE" />
-      <BitField start="6" size="1" name="INEPNE" description="INEPNE" />
-      <BitField start="4" size="1" name="ITTXFE" description="ITTXFE" />
-      <BitField start="3" size="1" name="TOC" description="TOC" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x128" size="0" name="DIEPINT1" access="Read/Write" description="device endpoint-1 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXFE" description="TXFE" />
-      <BitField start="6" size="1" name="INEPNE" description="INEPNE" />
-      <BitField start="4" size="1" name="ITTXFE" description="ITTXFE" />
-      <BitField start="3" size="1" name="TOC" description="TOC" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x148" size="0" name="DIEPINT2" access="Read/Write" description="device endpoint-2 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXFE" description="TXFE" />
-      <BitField start="6" size="1" name="INEPNE" description="INEPNE" />
-      <BitField start="4" size="1" name="ITTXFE" description="ITTXFE" />
-      <BitField start="3" size="1" name="TOC" description="TOC" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x168" size="0" name="DIEPINT3" access="Read/Write" description="device endpoint-3 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="TXFE" description="TXFE" />
-      <BitField start="6" size="1" name="INEPNE" description="INEPNE" />
-      <BitField start="4" size="1" name="ITTXFE" description="ITTXFE" />
-      <BitField start="3" size="1" name="TOC" description="TOC" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x308" size="0" name="DOEPINT0" access="Read/Write" description="device endpoint-0 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="B2BSTUP" description="B2BSTUP" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OTEPDIS" />
-      <BitField start="3" size="1" name="STUP" description="STUP" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x328" size="0" name="DOEPINT1" access="Read/Write" description="device endpoint-1 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="B2BSTUP" description="B2BSTUP" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OTEPDIS" />
-      <BitField start="3" size="1" name="STUP" description="STUP" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x348" size="0" name="DOEPINT2" access="Read/Write" description="device endpoint-2 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="B2BSTUP" description="B2BSTUP" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OTEPDIS" />
-      <BitField start="3" size="1" name="STUP" description="STUP" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x368" size="0" name="DOEPINT3" access="Read/Write" description="device endpoint-3 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="B2BSTUP" description="B2BSTUP" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OTEPDIS" />
-      <BitField start="3" size="1" name="STUP" description="STUP" />
-      <BitField start="1" size="1" name="EPDISD" description="EPDISD" />
-      <BitField start="0" size="1" name="XFRC" description="XFRC" />
-    </Register>
-    <Register start="+0x110" size="0" name="DIEPTSIZ0" access="Read/Write" description="device endpoint-0 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="19" size="2" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="7" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x310" size="0" name="DOEPTSIZ0" access="Read/Write" description="device OUT endpoint-0 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="STUPCNT" description="SETUP packet count" />
-      <BitField start="19" size="1" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="7" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x130" size="0" name="DIEPTSIZ1" access="Read/Write" description="device endpoint-1 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x150" size="0" name="DIEPTSIZ2" access="Read/Write" description="device endpoint-2 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x170" size="0" name="DIEPTSIZ3" access="Read/Write" description="device endpoint-3 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x118" size="0" name="DTXFSTS0" access="ReadOnly" description="OTG_FS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              available" />
-    </Register>
-    <Register start="+0x138" size="0" name="DTXFSTS1" access="ReadOnly" description="OTG_FS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              available" />
-    </Register>
-    <Register start="+0x158" size="0" name="DTXFSTS2" access="ReadOnly" description="OTG_FS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              available" />
-    </Register>
-    <Register start="+0x178" size="0" name="DTXFSTS3" access="ReadOnly" description="OTG_FS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              available" />
-    </Register>
-    <Register start="+0x330" size="0" name="DOEPTSIZ1" access="Read/Write" description="device OUT endpoint-1 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x350" size="0" name="DOEPTSIZ2" access="Read/Write" description="device OUT endpoint-2 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-    </Register>
-    <Register start="+0x370" size="0" name="DOEPTSIZ3" access="Read/Write" description="device OUT endpoint-3 transfer size&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_FS_PWRCLK" start="0x50000E00" description="USB on the go full speed">
-    <Register start="+0x0" size="0" name="FS_PCGCCTL" access="Read/Write" description="OTG_FS power and clock gating control&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STPPCLK" description="Stop PHY clock" />
-      <BitField start="1" size="1" name="GATEHCLK" description="Gate HCLK" />
-      <BitField start="4" size="1" name="PHYSUSP" description="PHY Suspended" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN1" start="0x40006400" description="Controller area network">
-    <Register start="+0x0" size="0" name="MCR" access="Read/Write" description="master control register" reset_value="0x00010002" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="DBF" description="DBF" />
-      <BitField start="15" size="1" name="RESET" description="RESET" />
-      <BitField start="7" size="1" name="TTCM" description="TTCM" />
-      <BitField start="6" size="1" name="ABOM" description="ABOM" />
-      <BitField start="5" size="1" name="AWUM" description="AWUM" />
-      <BitField start="4" size="1" name="NART" description="NART" />
-      <BitField start="3" size="1" name="RFLM" description="RFLM" />
-      <BitField start="2" size="1" name="TXFP" description="TXFP" />
-      <BitField start="1" size="1" name="SLEEP" description="SLEEP" />
-      <BitField start="0" size="1" name="INRQ" description="INRQ" />
-    </Register>
-    <Register start="+0x4" size="0" name="MSR" access="Read/Write" description="master status register" reset_value="0x00000C02" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="RX" description="RX" />
-      <BitField start="10" size="1" name="SAMP" description="SAMP" />
-      <BitField start="9" size="1" name="RXM" description="RXM" />
-      <BitField start="8" size="1" name="TXM" description="TXM" />
-      <BitField start="4" size="1" name="SLAKI" description="SLAKI" />
-      <BitField start="3" size="1" name="WKUI" description="WKUI" />
-      <BitField start="2" size="1" name="ERRI" description="ERRI" />
-      <BitField start="1" size="1" name="SLAK" description="SLAK" />
-      <BitField start="0" size="1" name="INAK" description="INAK" />
-    </Register>
-    <Register start="+0x8" size="0" name="TSR" access="Read/Write" description="transmit status register" reset_value="0x1C000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="LOW2" description="Lowest priority flag for mailbox&#xa;              2" />
-      <BitField start="30" size="1" name="LOW1" description="Lowest priority flag for mailbox&#xa;              1" />
-      <BitField start="29" size="1" name="LOW0" description="Lowest priority flag for mailbox&#xa;              0" />
-      <BitField start="28" size="1" name="TME2" description="Lowest priority flag for mailbox&#xa;              2" />
-      <BitField start="27" size="1" name="TME1" description="Lowest priority flag for mailbox&#xa;              1" />
-      <BitField start="26" size="1" name="TME0" description="Lowest priority flag for mailbox&#xa;              0" />
-      <BitField start="24" size="2" name="CODE" description="CODE" />
-      <BitField start="23" size="1" name="ABRQ2" description="ABRQ2" />
-      <BitField start="19" size="1" name="TERR2" description="TERR2" />
-      <BitField start="18" size="1" name="ALST2" description="ALST2" />
-      <BitField start="17" size="1" name="TXOK2" description="TXOK2" />
-      <BitField start="16" size="1" name="RQCP2" description="RQCP2" />
-      <BitField start="15" size="1" name="ABRQ1" description="ABRQ1" />
-      <BitField start="11" size="1" name="TERR1" description="TERR1" />
-      <BitField start="10" size="1" name="ALST1" description="ALST1" />
-      <BitField start="9" size="1" name="TXOK1" description="TXOK1" />
-      <BitField start="8" size="1" name="RQCP1" description="RQCP1" />
-      <BitField start="7" size="1" name="ABRQ0" description="ABRQ0" />
-      <BitField start="3" size="1" name="TERR0" description="TERR0" />
-      <BitField start="2" size="1" name="ALST0" description="ALST0" />
-      <BitField start="1" size="1" name="TXOK0" description="TXOK0" />
-      <BitField start="0" size="1" name="RQCP0" description="RQCP0" />
-    </Register>
-    <Register start="+0xC" size="0" name="RF0R" access="Read/Write" description="receive FIFO 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="RFOM0" description="RFOM0" />
-      <BitField start="4" size="1" name="FOVR0" description="FOVR0" />
-      <BitField start="3" size="1" name="FULL0" description="FULL0" />
-      <BitField start="0" size="2" name="FMP0" description="FMP0" />
-    </Register>
-    <Register start="+0x10" size="0" name="RF1R" access="Read/Write" description="receive FIFO 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="RFOM1" description="RFOM1" />
-      <BitField start="4" size="1" name="FOVR1" description="FOVR1" />
-      <BitField start="3" size="1" name="FULL1" description="FULL1" />
-      <BitField start="0" size="2" name="FMP1" description="FMP1" />
-    </Register>
-    <Register start="+0x14" size="0" name="IER" access="Read/Write" description="interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="SLKIE" description="SLKIE" />
-      <BitField start="16" size="1" name="WKUIE" description="WKUIE" />
-      <BitField start="15" size="1" name="ERRIE" description="ERRIE" />
-      <BitField start="11" size="1" name="LECIE" description="LECIE" />
-      <BitField start="10" size="1" name="BOFIE" description="BOFIE" />
-      <BitField start="9" size="1" name="EPVIE" description="EPVIE" />
-      <BitField start="8" size="1" name="EWGIE" description="EWGIE" />
-      <BitField start="6" size="1" name="FOVIE1" description="FOVIE1" />
-      <BitField start="5" size="1" name="FFIE1" description="FFIE1" />
-      <BitField start="4" size="1" name="FMPIE1" description="FMPIE1" />
-      <BitField start="3" size="1" name="FOVIE0" description="FOVIE0" />
-      <BitField start="2" size="1" name="FFIE0" description="FFIE0" />
-      <BitField start="1" size="1" name="FMPIE0" description="FMPIE0" />
-      <BitField start="0" size="1" name="TMEIE" description="TMEIE" />
-    </Register>
-    <Register start="+0x18" size="0" name="ESR" access="Read/Write" description="interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="REC" description="REC" />
-      <BitField start="16" size="8" name="TEC" description="TEC" />
-      <BitField start="4" size="3" name="LEC" description="LEC" />
-      <BitField start="2" size="1" name="BOFF" description="BOFF" />
-      <BitField start="1" size="1" name="EPVF" description="EPVF" />
-      <BitField start="0" size="1" name="EWGF" description="EWGF" />
-    </Register>
-    <Register start="+0x1C" size="0" name="BTR" access="Read/Write" description="bit timing register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="SILM" description="SILM" />
-      <BitField start="30" size="1" name="LBKM" description="LBKM" />
-      <BitField start="24" size="2" name="SJW" description="SJW" />
-      <BitField start="20" size="3" name="TS2" description="TS2" />
-      <BitField start="16" size="4" name="TS1" description="TS1" />
-      <BitField start="0" size="10" name="BRP" description="BRP" />
-    </Register>
-    <Register start="+0x180" size="0" name="TI0R" access="Read/Write" description="TX mailbox identifier register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-      <BitField start="0" size="1" name="TXRQ" description="TXRQ" />
-    </Register>
-    <Register start="+0x184" size="0" name="TDT0R" access="Read/Write" description="mailbox data length control and time stamp&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="1" name="TGT" description="TGT" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x188" size="0" name="TDL0R" access="Read/Write" description="mailbox data low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x18C" size="0" name="TDH0R" access="Read/Write" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x190" size="0" name="TI1R" access="Read/Write" description="mailbox identifier register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-      <BitField start="0" size="1" name="TXRQ" description="TXRQ" />
-    </Register>
-    <Register start="+0x194" size="0" name="TDT1R" access="Read/Write" description="mailbox data length control and time stamp&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="1" name="TGT" description="TGT" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x198" size="0" name="TDL1R" access="Read/Write" description="mailbox data low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x19C" size="0" name="TDH1R" access="Read/Write" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x1A0" size="0" name="TI2R" access="Read/Write" description="mailbox identifier register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-      <BitField start="0" size="1" name="TXRQ" description="TXRQ" />
-    </Register>
-    <Register start="+0x1A4" size="0" name="TDT2R" access="Read/Write" description="mailbox data length control and time stamp&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="1" name="TGT" description="TGT" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x1A8" size="0" name="TDL2R" access="Read/Write" description="mailbox data low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x1AC" size="0" name="TDH2R" access="Read/Write" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x1B0" size="0" name="RI0R" access="ReadOnly" description="receive FIFO mailbox identifier&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-    </Register>
-    <Register start="+0x1B4" size="0" name="RDT0R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="8" name="FMI" description="FMI" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x1B8" size="0" name="RDL0R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x1BC" size="0" name="RDH0R" access="ReadOnly" description="receive FIFO mailbox data high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x1C0" size="0" name="RI1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-    </Register>
-    <Register start="+0x1C4" size="0" name="RDT1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="8" name="FMI" description="FMI" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x1C8" size="0" name="RDL1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x1CC" size="0" name="RDH1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x200" size="0" name="FMR" access="Read/Write" description="filter master register" reset_value="0x2A1C0E01" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="6" name="CAN2SB" description="CAN2SB" />
-      <BitField start="0" size="1" name="FINIT" description="FINIT" />
-    </Register>
-    <Register start="+0x204" size="0" name="FM1R" access="Read/Write" description="filter mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FBM0" description="Filter mode" />
-      <BitField start="1" size="1" name="FBM1" description="Filter mode" />
-      <BitField start="2" size="1" name="FBM2" description="Filter mode" />
-      <BitField start="3" size="1" name="FBM3" description="Filter mode" />
-      <BitField start="4" size="1" name="FBM4" description="Filter mode" />
-      <BitField start="5" size="1" name="FBM5" description="Filter mode" />
-      <BitField start="6" size="1" name="FBM6" description="Filter mode" />
-      <BitField start="7" size="1" name="FBM7" description="Filter mode" />
-      <BitField start="8" size="1" name="FBM8" description="Filter mode" />
-      <BitField start="9" size="1" name="FBM9" description="Filter mode" />
-      <BitField start="10" size="1" name="FBM10" description="Filter mode" />
-      <BitField start="11" size="1" name="FBM11" description="Filter mode" />
-      <BitField start="12" size="1" name="FBM12" description="Filter mode" />
-      <BitField start="13" size="1" name="FBM13" description="Filter mode" />
-      <BitField start="14" size="1" name="FBM14" description="Filter mode" />
-      <BitField start="15" size="1" name="FBM15" description="Filter mode" />
-      <BitField start="16" size="1" name="FBM16" description="Filter mode" />
-      <BitField start="17" size="1" name="FBM17" description="Filter mode" />
-      <BitField start="18" size="1" name="FBM18" description="Filter mode" />
-      <BitField start="19" size="1" name="FBM19" description="Filter mode" />
-      <BitField start="20" size="1" name="FBM20" description="Filter mode" />
-      <BitField start="21" size="1" name="FBM21" description="Filter mode" />
-      <BitField start="22" size="1" name="FBM22" description="Filter mode" />
-      <BitField start="23" size="1" name="FBM23" description="Filter mode" />
-      <BitField start="24" size="1" name="FBM24" description="Filter mode" />
-      <BitField start="25" size="1" name="FBM25" description="Filter mode" />
-      <BitField start="26" size="1" name="FBM26" description="Filter mode" />
-      <BitField start="27" size="1" name="FBM27" description="Filter mode" />
-    </Register>
-    <Register start="+0x20C" size="0" name="FS1R" access="Read/Write" description="filter scale register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSC0" description="Filter scale configuration" />
-      <BitField start="1" size="1" name="FSC1" description="Filter scale configuration" />
-      <BitField start="2" size="1" name="FSC2" description="Filter scale configuration" />
-      <BitField start="3" size="1" name="FSC3" description="Filter scale configuration" />
-      <BitField start="4" size="1" name="FSC4" description="Filter scale configuration" />
-      <BitField start="5" size="1" name="FSC5" description="Filter scale configuration" />
-      <BitField start="6" size="1" name="FSC6" description="Filter scale configuration" />
-      <BitField start="7" size="1" name="FSC7" description="Filter scale configuration" />
-      <BitField start="8" size="1" name="FSC8" description="Filter scale configuration" />
-      <BitField start="9" size="1" name="FSC9" description="Filter scale configuration" />
-      <BitField start="10" size="1" name="FSC10" description="Filter scale configuration" />
-      <BitField start="11" size="1" name="FSC11" description="Filter scale configuration" />
-      <BitField start="12" size="1" name="FSC12" description="Filter scale configuration" />
-      <BitField start="13" size="1" name="FSC13" description="Filter scale configuration" />
-      <BitField start="14" size="1" name="FSC14" description="Filter scale configuration" />
-      <BitField start="15" size="1" name="FSC15" description="Filter scale configuration" />
-      <BitField start="16" size="1" name="FSC16" description="Filter scale configuration" />
-      <BitField start="17" size="1" name="FSC17" description="Filter scale configuration" />
-      <BitField start="18" size="1" name="FSC18" description="Filter scale configuration" />
-      <BitField start="19" size="1" name="FSC19" description="Filter scale configuration" />
-      <BitField start="20" size="1" name="FSC20" description="Filter scale configuration" />
-      <BitField start="21" size="1" name="FSC21" description="Filter scale configuration" />
-      <BitField start="22" size="1" name="FSC22" description="Filter scale configuration" />
-      <BitField start="23" size="1" name="FSC23" description="Filter scale configuration" />
-      <BitField start="24" size="1" name="FSC24" description="Filter scale configuration" />
-      <BitField start="25" size="1" name="FSC25" description="Filter scale configuration" />
-      <BitField start="26" size="1" name="FSC26" description="Filter scale configuration" />
-      <BitField start="27" size="1" name="FSC27" description="Filter scale configuration" />
-    </Register>
-    <Register start="+0x214" size="0" name="FFA1R" access="Read/Write" description="filter FIFO assignment&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FFA0" description="Filter FIFO assignment for filter&#xa;              0" />
-      <BitField start="1" size="1" name="FFA1" description="Filter FIFO assignment for filter&#xa;              1" />
-      <BitField start="2" size="1" name="FFA2" description="Filter FIFO assignment for filter&#xa;              2" />
-      <BitField start="3" size="1" name="FFA3" description="Filter FIFO assignment for filter&#xa;              3" />
-      <BitField start="4" size="1" name="FFA4" description="Filter FIFO assignment for filter&#xa;              4" />
-      <BitField start="5" size="1" name="FFA5" description="Filter FIFO assignment for filter&#xa;              5" />
-      <BitField start="6" size="1" name="FFA6" description="Filter FIFO assignment for filter&#xa;              6" />
-      <BitField start="7" size="1" name="FFA7" description="Filter FIFO assignment for filter&#xa;              7" />
-      <BitField start="8" size="1" name="FFA8" description="Filter FIFO assignment for filter&#xa;              8" />
-      <BitField start="9" size="1" name="FFA9" description="Filter FIFO assignment for filter&#xa;              9" />
-      <BitField start="10" size="1" name="FFA10" description="Filter FIFO assignment for filter&#xa;              10" />
-      <BitField start="11" size="1" name="FFA11" description="Filter FIFO assignment for filter&#xa;              11" />
-      <BitField start="12" size="1" name="FFA12" description="Filter FIFO assignment for filter&#xa;              12" />
-      <BitField start="13" size="1" name="FFA13" description="Filter FIFO assignment for filter&#xa;              13" />
-      <BitField start="14" size="1" name="FFA14" description="Filter FIFO assignment for filter&#xa;              14" />
-      <BitField start="15" size="1" name="FFA15" description="Filter FIFO assignment for filter&#xa;              15" />
-      <BitField start="16" size="1" name="FFA16" description="Filter FIFO assignment for filter&#xa;              16" />
-      <BitField start="17" size="1" name="FFA17" description="Filter FIFO assignment for filter&#xa;              17" />
-      <BitField start="18" size="1" name="FFA18" description="Filter FIFO assignment for filter&#xa;              18" />
-      <BitField start="19" size="1" name="FFA19" description="Filter FIFO assignment for filter&#xa;              19" />
-      <BitField start="20" size="1" name="FFA20" description="Filter FIFO assignment for filter&#xa;              20" />
-      <BitField start="21" size="1" name="FFA21" description="Filter FIFO assignment for filter&#xa;              21" />
-      <BitField start="22" size="1" name="FFA22" description="Filter FIFO assignment for filter&#xa;              22" />
-      <BitField start="23" size="1" name="FFA23" description="Filter FIFO assignment for filter&#xa;              23" />
-      <BitField start="24" size="1" name="FFA24" description="Filter FIFO assignment for filter&#xa;              24" />
-      <BitField start="25" size="1" name="FFA25" description="Filter FIFO assignment for filter&#xa;              25" />
-      <BitField start="26" size="1" name="FFA26" description="Filter FIFO assignment for filter&#xa;              26" />
-      <BitField start="27" size="1" name="FFA27" description="Filter FIFO assignment for filter&#xa;              27" />
-    </Register>
-    <Register start="+0x21C" size="0" name="FA1R" access="Read/Write" description="filter activation register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FACT0" description="Filter active" />
-      <BitField start="1" size="1" name="FACT1" description="Filter active" />
-      <BitField start="2" size="1" name="FACT2" description="Filter active" />
-      <BitField start="3" size="1" name="FACT3" description="Filter active" />
-      <BitField start="4" size="1" name="FACT4" description="Filter active" />
-      <BitField start="5" size="1" name="FACT5" description="Filter active" />
-      <BitField start="6" size="1" name="FACT6" description="Filter active" />
-      <BitField start="7" size="1" name="FACT7" description="Filter active" />
-      <BitField start="8" size="1" name="FACT8" description="Filter active" />
-      <BitField start="9" size="1" name="FACT9" description="Filter active" />
-      <BitField start="10" size="1" name="FACT10" description="Filter active" />
-      <BitField start="11" size="1" name="FACT11" description="Filter active" />
-      <BitField start="12" size="1" name="FACT12" description="Filter active" />
-      <BitField start="13" size="1" name="FACT13" description="Filter active" />
-      <BitField start="14" size="1" name="FACT14" description="Filter active" />
-      <BitField start="15" size="1" name="FACT15" description="Filter active" />
-      <BitField start="16" size="1" name="FACT16" description="Filter active" />
-      <BitField start="17" size="1" name="FACT17" description="Filter active" />
-      <BitField start="18" size="1" name="FACT18" description="Filter active" />
-      <BitField start="19" size="1" name="FACT19" description="Filter active" />
-      <BitField start="20" size="1" name="FACT20" description="Filter active" />
-      <BitField start="21" size="1" name="FACT21" description="Filter active" />
-      <BitField start="22" size="1" name="FACT22" description="Filter active" />
-      <BitField start="23" size="1" name="FACT23" description="Filter active" />
-      <BitField start="24" size="1" name="FACT24" description="Filter active" />
-      <BitField start="25" size="1" name="FACT25" description="Filter active" />
-      <BitField start="26" size="1" name="FACT26" description="Filter active" />
-      <BitField start="27" size="1" name="FACT27" description="Filter active" />
-    </Register>
-    <Register start="+0x240" size="0" name="F0R1" access="Read/Write" description="Filter bank 0 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x244" size="0" name="F0R2" access="Read/Write" description="Filter bank 0 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x248" size="0" name="F1R1" access="Read/Write" description="Filter bank 1 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x24C" size="0" name="F1R2" access="Read/Write" description="Filter bank 1 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x250" size="0" name="F2R1" access="Read/Write" description="Filter bank 2 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x254" size="0" name="F2R2" access="Read/Write" description="Filter bank 2 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x258" size="0" name="F3R1" access="Read/Write" description="Filter bank 3 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x25C" size="0" name="F3R2" access="Read/Write" description="Filter bank 3 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x260" size="0" name="F4R1" access="Read/Write" description="Filter bank 4 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x264" size="0" name="F4R2" access="Read/Write" description="Filter bank 4 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x268" size="0" name="F5R1" access="Read/Write" description="Filter bank 5 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x26C" size="0" name="F5R2" access="Read/Write" description="Filter bank 5 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x270" size="0" name="F6R1" access="Read/Write" description="Filter bank 6 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x274" size="0" name="F6R2" access="Read/Write" description="Filter bank 6 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x278" size="0" name="F7R1" access="Read/Write" description="Filter bank 7 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x27C" size="0" name="F7R2" access="Read/Write" description="Filter bank 7 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x280" size="0" name="F8R1" access="Read/Write" description="Filter bank 8 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x284" size="0" name="F8R2" access="Read/Write" description="Filter bank 8 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x288" size="0" name="F9R1" access="Read/Write" description="Filter bank 9 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x28C" size="0" name="F9R2" access="Read/Write" description="Filter bank 9 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x290" size="0" name="F10R1" access="Read/Write" description="Filter bank 10 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x294" size="0" name="F10R2" access="Read/Write" description="Filter bank 10 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x298" size="0" name="F11R1" access="Read/Write" description="Filter bank 11 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x29C" size="0" name="F11R2" access="Read/Write" description="Filter bank 11 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2A0" size="0" name="F12R1" access="Read/Write" description="Filter bank 4 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2A4" size="0" name="F12R2" access="Read/Write" description="Filter bank 12 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2A8" size="0" name="F13R1" access="Read/Write" description="Filter bank 13 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2AC" size="0" name="F13R2" access="Read/Write" description="Filter bank 13 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2B0" size="0" name="F14R1" access="Read/Write" description="Filter bank 14 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2B4" size="0" name="F14R2" access="Read/Write" description="Filter bank 14 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2B8" size="0" name="F15R1" access="Read/Write" description="Filter bank 15 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2BC" size="0" name="F15R2" access="Read/Write" description="Filter bank 15 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2C0" size="0" name="F16R1" access="Read/Write" description="Filter bank 16 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2C4" size="0" name="F16R2" access="Read/Write" description="Filter bank 16 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2C8" size="0" name="F17R1" access="Read/Write" description="Filter bank 17 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2CC" size="0" name="F17R2" access="Read/Write" description="Filter bank 17 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2D0" size="0" name="F18R1" access="Read/Write" description="Filter bank 18 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2D4" size="0" name="F18R2" access="Read/Write" description="Filter bank 18 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2D8" size="0" name="F19R1" access="Read/Write" description="Filter bank 19 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2DC" size="0" name="F19R2" access="Read/Write" description="Filter bank 19 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2E0" size="0" name="F20R1" access="Read/Write" description="Filter bank 20 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2E4" size="0" name="F20R2" access="Read/Write" description="Filter bank 20 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2E8" size="0" name="F21R1" access="Read/Write" description="Filter bank 21 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2EC" size="0" name="F21R2" access="Read/Write" description="Filter bank 21 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2F0" size="0" name="F22R1" access="Read/Write" description="Filter bank 22 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2F4" size="0" name="F22R2" access="Read/Write" description="Filter bank 22 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2F8" size="0" name="F23R1" access="Read/Write" description="Filter bank 23 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2FC" size="0" name="F23R2" access="Read/Write" description="Filter bank 23 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x300" size="0" name="F24R1" access="Read/Write" description="Filter bank 24 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x304" size="0" name="F24R2" access="Read/Write" description="Filter bank 24 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x308" size="0" name="F25R1" access="Read/Write" description="Filter bank 25 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x30C" size="0" name="F25R2" access="Read/Write" description="Filter bank 25 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x310" size="0" name="F26R1" access="Read/Write" description="Filter bank 26 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x314" size="0" name="F26R2" access="Read/Write" description="Filter bank 26 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x318" size="0" name="F27R1" access="Read/Write" description="Filter bank 27 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x31C" size="0" name="F27R2" access="Read/Write" description="Filter bank 27 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN2" start="0x40006800" description="Controller area network">
-    <Register start="+0x0" size="0" name="MCR" access="Read/Write" description="master control register" reset_value="0x00010002" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="DBF" description="DBF" />
-      <BitField start="15" size="1" name="RESET" description="RESET" />
-      <BitField start="7" size="1" name="TTCM" description="TTCM" />
-      <BitField start="6" size="1" name="ABOM" description="ABOM" />
-      <BitField start="5" size="1" name="AWUM" description="AWUM" />
-      <BitField start="4" size="1" name="NART" description="NART" />
-      <BitField start="3" size="1" name="RFLM" description="RFLM" />
-      <BitField start="2" size="1" name="TXFP" description="TXFP" />
-      <BitField start="1" size="1" name="SLEEP" description="SLEEP" />
-      <BitField start="0" size="1" name="INRQ" description="INRQ" />
-    </Register>
-    <Register start="+0x4" size="0" name="MSR" access="Read/Write" description="master status register" reset_value="0x00000C02" reset_mask="0xFFFFFFFF">
-      <BitField start="11" size="1" name="RX" description="RX" />
-      <BitField start="10" size="1" name="SAMP" description="SAMP" />
-      <BitField start="9" size="1" name="RXM" description="RXM" />
-      <BitField start="8" size="1" name="TXM" description="TXM" />
-      <BitField start="4" size="1" name="SLAKI" description="SLAKI" />
-      <BitField start="3" size="1" name="WKUI" description="WKUI" />
-      <BitField start="2" size="1" name="ERRI" description="ERRI" />
-      <BitField start="1" size="1" name="SLAK" description="SLAK" />
-      <BitField start="0" size="1" name="INAK" description="INAK" />
-    </Register>
-    <Register start="+0x8" size="0" name="TSR" access="Read/Write" description="transmit status register" reset_value="0x1C000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="LOW2" description="Lowest priority flag for mailbox&#xa;              2" />
-      <BitField start="30" size="1" name="LOW1" description="Lowest priority flag for mailbox&#xa;              1" />
-      <BitField start="29" size="1" name="LOW0" description="Lowest priority flag for mailbox&#xa;              0" />
-      <BitField start="28" size="1" name="TME2" description="Lowest priority flag for mailbox&#xa;              2" />
-      <BitField start="27" size="1" name="TME1" description="Lowest priority flag for mailbox&#xa;              1" />
-      <BitField start="26" size="1" name="TME0" description="Lowest priority flag for mailbox&#xa;              0" />
-      <BitField start="24" size="2" name="CODE" description="CODE" />
-      <BitField start="23" size="1" name="ABRQ2" description="ABRQ2" />
-      <BitField start="19" size="1" name="TERR2" description="TERR2" />
-      <BitField start="18" size="1" name="ALST2" description="ALST2" />
-      <BitField start="17" size="1" name="TXOK2" description="TXOK2" />
-      <BitField start="16" size="1" name="RQCP2" description="RQCP2" />
-      <BitField start="15" size="1" name="ABRQ1" description="ABRQ1" />
-      <BitField start="11" size="1" name="TERR1" description="TERR1" />
-      <BitField start="10" size="1" name="ALST1" description="ALST1" />
-      <BitField start="9" size="1" name="TXOK1" description="TXOK1" />
-      <BitField start="8" size="1" name="RQCP1" description="RQCP1" />
-      <BitField start="7" size="1" name="ABRQ0" description="ABRQ0" />
-      <BitField start="3" size="1" name="TERR0" description="TERR0" />
-      <BitField start="2" size="1" name="ALST0" description="ALST0" />
-      <BitField start="1" size="1" name="TXOK0" description="TXOK0" />
-      <BitField start="0" size="1" name="RQCP0" description="RQCP0" />
-    </Register>
-    <Register start="+0xC" size="0" name="RF0R" access="Read/Write" description="receive FIFO 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="RFOM0" description="RFOM0" />
-      <BitField start="4" size="1" name="FOVR0" description="FOVR0" />
-      <BitField start="3" size="1" name="FULL0" description="FULL0" />
-      <BitField start="0" size="2" name="FMP0" description="FMP0" />
-    </Register>
-    <Register start="+0x10" size="0" name="RF1R" access="Read/Write" description="receive FIFO 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="RFOM1" description="RFOM1" />
-      <BitField start="4" size="1" name="FOVR1" description="FOVR1" />
-      <BitField start="3" size="1" name="FULL1" description="FULL1" />
-      <BitField start="0" size="2" name="FMP1" description="FMP1" />
-    </Register>
-    <Register start="+0x14" size="0" name="IER" access="Read/Write" description="interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="SLKIE" description="SLKIE" />
-      <BitField start="16" size="1" name="WKUIE" description="WKUIE" />
-      <BitField start="15" size="1" name="ERRIE" description="ERRIE" />
-      <BitField start="11" size="1" name="LECIE" description="LECIE" />
-      <BitField start="10" size="1" name="BOFIE" description="BOFIE" />
-      <BitField start="9" size="1" name="EPVIE" description="EPVIE" />
-      <BitField start="8" size="1" name="EWGIE" description="EWGIE" />
-      <BitField start="6" size="1" name="FOVIE1" description="FOVIE1" />
-      <BitField start="5" size="1" name="FFIE1" description="FFIE1" />
-      <BitField start="4" size="1" name="FMPIE1" description="FMPIE1" />
-      <BitField start="3" size="1" name="FOVIE0" description="FOVIE0" />
-      <BitField start="2" size="1" name="FFIE0" description="FFIE0" />
-      <BitField start="1" size="1" name="FMPIE0" description="FMPIE0" />
-      <BitField start="0" size="1" name="TMEIE" description="TMEIE" />
-    </Register>
-    <Register start="+0x18" size="0" name="ESR" access="Read/Write" description="interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="REC" description="REC" />
-      <BitField start="16" size="8" name="TEC" description="TEC" />
-      <BitField start="4" size="3" name="LEC" description="LEC" />
-      <BitField start="2" size="1" name="BOFF" description="BOFF" />
-      <BitField start="1" size="1" name="EPVF" description="EPVF" />
-      <BitField start="0" size="1" name="EWGF" description="EWGF" />
-    </Register>
-    <Register start="+0x1C" size="0" name="BTR" access="Read/Write" description="bit timing register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="31" size="1" name="SILM" description="SILM" />
-      <BitField start="30" size="1" name="LBKM" description="LBKM" />
-      <BitField start="24" size="2" name="SJW" description="SJW" />
-      <BitField start="20" size="3" name="TS2" description="TS2" />
-      <BitField start="16" size="4" name="TS1" description="TS1" />
-      <BitField start="0" size="10" name="BRP" description="BRP" />
-    </Register>
-    <Register start="+0x180" size="0" name="TI0R" access="Read/Write" description="TX mailbox identifier register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-      <BitField start="0" size="1" name="TXRQ" description="TXRQ" />
-    </Register>
-    <Register start="+0x184" size="0" name="TDT0R" access="Read/Write" description="mailbox data length control and time stamp&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="1" name="TGT" description="TGT" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x188" size="0" name="TDL0R" access="Read/Write" description="mailbox data low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x18C" size="0" name="TDH0R" access="Read/Write" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x190" size="0" name="TI1R" access="Read/Write" description="mailbox identifier register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-      <BitField start="0" size="1" name="TXRQ" description="TXRQ" />
-    </Register>
-    <Register start="+0x194" size="0" name="TDT1R" access="Read/Write" description="mailbox data length control and time stamp&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="1" name="TGT" description="TGT" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x198" size="0" name="TDL1R" access="Read/Write" description="mailbox data low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x19C" size="0" name="TDH1R" access="Read/Write" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x1A0" size="0" name="TI2R" access="Read/Write" description="mailbox identifier register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-      <BitField start="0" size="1" name="TXRQ" description="TXRQ" />
-    </Register>
-    <Register start="+0x1A4" size="0" name="TDT2R" access="Read/Write" description="mailbox data length control and time stamp&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="1" name="TGT" description="TGT" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x1A8" size="0" name="TDL2R" access="Read/Write" description="mailbox data low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x1AC" size="0" name="TDH2R" access="Read/Write" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x1B0" size="0" name="RI0R" access="ReadOnly" description="receive FIFO mailbox identifier&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-    </Register>
-    <Register start="+0x1B4" size="0" name="RDT0R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="8" name="FMI" description="FMI" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x1B8" size="0" name="RDL0R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x1BC" size="0" name="RDH0R" access="ReadOnly" description="receive FIFO mailbox data high&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x1C0" size="0" name="RI1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="21" size="11" name="STID" description="STID" />
-      <BitField start="3" size="18" name="EXID" description="EXID" />
-      <BitField start="2" size="1" name="IDE" description="IDE" />
-      <BitField start="1" size="1" name="RTR" description="RTR" />
-    </Register>
-    <Register start="+0x1C4" size="0" name="RDT1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="16" name="TIME" description="TIME" />
-      <BitField start="8" size="8" name="FMI" description="FMI" />
-      <BitField start="0" size="4" name="DLC" description="DLC" />
-    </Register>
-    <Register start="+0x1C8" size="0" name="RDL1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA3" description="DATA3" />
-      <BitField start="16" size="8" name="DATA2" description="DATA2" />
-      <BitField start="8" size="8" name="DATA1" description="DATA1" />
-      <BitField start="0" size="8" name="DATA0" description="DATA0" />
-    </Register>
-    <Register start="+0x1CC" size="0" name="RDH1R" access="ReadOnly" description="mailbox data high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="8" name="DATA7" description="DATA7" />
-      <BitField start="16" size="8" name="DATA6" description="DATA6" />
-      <BitField start="8" size="8" name="DATA5" description="DATA5" />
-      <BitField start="0" size="8" name="DATA4" description="DATA4" />
-    </Register>
-    <Register start="+0x200" size="0" name="FMR" access="Read/Write" description="filter master register" reset_value="0x2A1C0E01" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="6" name="CAN2SB" description="CAN2SB" />
-      <BitField start="0" size="1" name="FINIT" description="FINIT" />
-    </Register>
-    <Register start="+0x204" size="0" name="FM1R" access="Read/Write" description="filter mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FBM0" description="Filter mode" />
-      <BitField start="1" size="1" name="FBM1" description="Filter mode" />
-      <BitField start="2" size="1" name="FBM2" description="Filter mode" />
-      <BitField start="3" size="1" name="FBM3" description="Filter mode" />
-      <BitField start="4" size="1" name="FBM4" description="Filter mode" />
-      <BitField start="5" size="1" name="FBM5" description="Filter mode" />
-      <BitField start="6" size="1" name="FBM6" description="Filter mode" />
-      <BitField start="7" size="1" name="FBM7" description="Filter mode" />
-      <BitField start="8" size="1" name="FBM8" description="Filter mode" />
-      <BitField start="9" size="1" name="FBM9" description="Filter mode" />
-      <BitField start="10" size="1" name="FBM10" description="Filter mode" />
-      <BitField start="11" size="1" name="FBM11" description="Filter mode" />
-      <BitField start="12" size="1" name="FBM12" description="Filter mode" />
-      <BitField start="13" size="1" name="FBM13" description="Filter mode" />
-      <BitField start="14" size="1" name="FBM14" description="Filter mode" />
-      <BitField start="15" size="1" name="FBM15" description="Filter mode" />
-      <BitField start="16" size="1" name="FBM16" description="Filter mode" />
-      <BitField start="17" size="1" name="FBM17" description="Filter mode" />
-      <BitField start="18" size="1" name="FBM18" description="Filter mode" />
-      <BitField start="19" size="1" name="FBM19" description="Filter mode" />
-      <BitField start="20" size="1" name="FBM20" description="Filter mode" />
-      <BitField start="21" size="1" name="FBM21" description="Filter mode" />
-      <BitField start="22" size="1" name="FBM22" description="Filter mode" />
-      <BitField start="23" size="1" name="FBM23" description="Filter mode" />
-      <BitField start="24" size="1" name="FBM24" description="Filter mode" />
-      <BitField start="25" size="1" name="FBM25" description="Filter mode" />
-      <BitField start="26" size="1" name="FBM26" description="Filter mode" />
-      <BitField start="27" size="1" name="FBM27" description="Filter mode" />
-    </Register>
-    <Register start="+0x20C" size="0" name="FS1R" access="Read/Write" description="filter scale register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSC0" description="Filter scale configuration" />
-      <BitField start="1" size="1" name="FSC1" description="Filter scale configuration" />
-      <BitField start="2" size="1" name="FSC2" description="Filter scale configuration" />
-      <BitField start="3" size="1" name="FSC3" description="Filter scale configuration" />
-      <BitField start="4" size="1" name="FSC4" description="Filter scale configuration" />
-      <BitField start="5" size="1" name="FSC5" description="Filter scale configuration" />
-      <BitField start="6" size="1" name="FSC6" description="Filter scale configuration" />
-      <BitField start="7" size="1" name="FSC7" description="Filter scale configuration" />
-      <BitField start="8" size="1" name="FSC8" description="Filter scale configuration" />
-      <BitField start="9" size="1" name="FSC9" description="Filter scale configuration" />
-      <BitField start="10" size="1" name="FSC10" description="Filter scale configuration" />
-      <BitField start="11" size="1" name="FSC11" description="Filter scale configuration" />
-      <BitField start="12" size="1" name="FSC12" description="Filter scale configuration" />
-      <BitField start="13" size="1" name="FSC13" description="Filter scale configuration" />
-      <BitField start="14" size="1" name="FSC14" description="Filter scale configuration" />
-      <BitField start="15" size="1" name="FSC15" description="Filter scale configuration" />
-      <BitField start="16" size="1" name="FSC16" description="Filter scale configuration" />
-      <BitField start="17" size="1" name="FSC17" description="Filter scale configuration" />
-      <BitField start="18" size="1" name="FSC18" description="Filter scale configuration" />
-      <BitField start="19" size="1" name="FSC19" description="Filter scale configuration" />
-      <BitField start="20" size="1" name="FSC20" description="Filter scale configuration" />
-      <BitField start="21" size="1" name="FSC21" description="Filter scale configuration" />
-      <BitField start="22" size="1" name="FSC22" description="Filter scale configuration" />
-      <BitField start="23" size="1" name="FSC23" description="Filter scale configuration" />
-      <BitField start="24" size="1" name="FSC24" description="Filter scale configuration" />
-      <BitField start="25" size="1" name="FSC25" description="Filter scale configuration" />
-      <BitField start="26" size="1" name="FSC26" description="Filter scale configuration" />
-      <BitField start="27" size="1" name="FSC27" description="Filter scale configuration" />
-    </Register>
-    <Register start="+0x214" size="0" name="FFA1R" access="Read/Write" description="filter FIFO assignment&#xa;          register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FFA0" description="Filter FIFO assignment for filter&#xa;              0" />
-      <BitField start="1" size="1" name="FFA1" description="Filter FIFO assignment for filter&#xa;              1" />
-      <BitField start="2" size="1" name="FFA2" description="Filter FIFO assignment for filter&#xa;              2" />
-      <BitField start="3" size="1" name="FFA3" description="Filter FIFO assignment for filter&#xa;              3" />
-      <BitField start="4" size="1" name="FFA4" description="Filter FIFO assignment for filter&#xa;              4" />
-      <BitField start="5" size="1" name="FFA5" description="Filter FIFO assignment for filter&#xa;              5" />
-      <BitField start="6" size="1" name="FFA6" description="Filter FIFO assignment for filter&#xa;              6" />
-      <BitField start="7" size="1" name="FFA7" description="Filter FIFO assignment for filter&#xa;              7" />
-      <BitField start="8" size="1" name="FFA8" description="Filter FIFO assignment for filter&#xa;              8" />
-      <BitField start="9" size="1" name="FFA9" description="Filter FIFO assignment for filter&#xa;              9" />
-      <BitField start="10" size="1" name="FFA10" description="Filter FIFO assignment for filter&#xa;              10" />
-      <BitField start="11" size="1" name="FFA11" description="Filter FIFO assignment for filter&#xa;              11" />
-      <BitField start="12" size="1" name="FFA12" description="Filter FIFO assignment for filter&#xa;              12" />
-      <BitField start="13" size="1" name="FFA13" description="Filter FIFO assignment for filter&#xa;              13" />
-      <BitField start="14" size="1" name="FFA14" description="Filter FIFO assignment for filter&#xa;              14" />
-      <BitField start="15" size="1" name="FFA15" description="Filter FIFO assignment for filter&#xa;              15" />
-      <BitField start="16" size="1" name="FFA16" description="Filter FIFO assignment for filter&#xa;              16" />
-      <BitField start="17" size="1" name="FFA17" description="Filter FIFO assignment for filter&#xa;              17" />
-      <BitField start="18" size="1" name="FFA18" description="Filter FIFO assignment for filter&#xa;              18" />
-      <BitField start="19" size="1" name="FFA19" description="Filter FIFO assignment for filter&#xa;              19" />
-      <BitField start="20" size="1" name="FFA20" description="Filter FIFO assignment for filter&#xa;              20" />
-      <BitField start="21" size="1" name="FFA21" description="Filter FIFO assignment for filter&#xa;              21" />
-      <BitField start="22" size="1" name="FFA22" description="Filter FIFO assignment for filter&#xa;              22" />
-      <BitField start="23" size="1" name="FFA23" description="Filter FIFO assignment for filter&#xa;              23" />
-      <BitField start="24" size="1" name="FFA24" description="Filter FIFO assignment for filter&#xa;              24" />
-      <BitField start="25" size="1" name="FFA25" description="Filter FIFO assignment for filter&#xa;              25" />
-      <BitField start="26" size="1" name="FFA26" description="Filter FIFO assignment for filter&#xa;              26" />
-      <BitField start="27" size="1" name="FFA27" description="Filter FIFO assignment for filter&#xa;              27" />
-    </Register>
-    <Register start="+0x21C" size="0" name="FA1R" access="Read/Write" description="filter activation register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FACT0" description="Filter active" />
-      <BitField start="1" size="1" name="FACT1" description="Filter active" />
-      <BitField start="2" size="1" name="FACT2" description="Filter active" />
-      <BitField start="3" size="1" name="FACT3" description="Filter active" />
-      <BitField start="4" size="1" name="FACT4" description="Filter active" />
-      <BitField start="5" size="1" name="FACT5" description="Filter active" />
-      <BitField start="6" size="1" name="FACT6" description="Filter active" />
-      <BitField start="7" size="1" name="FACT7" description="Filter active" />
-      <BitField start="8" size="1" name="FACT8" description="Filter active" />
-      <BitField start="9" size="1" name="FACT9" description="Filter active" />
-      <BitField start="10" size="1" name="FACT10" description="Filter active" />
-      <BitField start="11" size="1" name="FACT11" description="Filter active" />
-      <BitField start="12" size="1" name="FACT12" description="Filter active" />
-      <BitField start="13" size="1" name="FACT13" description="Filter active" />
-      <BitField start="14" size="1" name="FACT14" description="Filter active" />
-      <BitField start="15" size="1" name="FACT15" description="Filter active" />
-      <BitField start="16" size="1" name="FACT16" description="Filter active" />
-      <BitField start="17" size="1" name="FACT17" description="Filter active" />
-      <BitField start="18" size="1" name="FACT18" description="Filter active" />
-      <BitField start="19" size="1" name="FACT19" description="Filter active" />
-      <BitField start="20" size="1" name="FACT20" description="Filter active" />
-      <BitField start="21" size="1" name="FACT21" description="Filter active" />
-      <BitField start="22" size="1" name="FACT22" description="Filter active" />
-      <BitField start="23" size="1" name="FACT23" description="Filter active" />
-      <BitField start="24" size="1" name="FACT24" description="Filter active" />
-      <BitField start="25" size="1" name="FACT25" description="Filter active" />
-      <BitField start="26" size="1" name="FACT26" description="Filter active" />
-      <BitField start="27" size="1" name="FACT27" description="Filter active" />
-    </Register>
-    <Register start="+0x240" size="0" name="F0R1" access="Read/Write" description="Filter bank 0 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x244" size="0" name="F0R2" access="Read/Write" description="Filter bank 0 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x248" size="0" name="F1R1" access="Read/Write" description="Filter bank 1 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x24C" size="0" name="F1R2" access="Read/Write" description="Filter bank 1 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x250" size="0" name="F2R1" access="Read/Write" description="Filter bank 2 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x254" size="0" name="F2R2" access="Read/Write" description="Filter bank 2 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x258" size="0" name="F3R1" access="Read/Write" description="Filter bank 3 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x25C" size="0" name="F3R2" access="Read/Write" description="Filter bank 3 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x260" size="0" name="F4R1" access="Read/Write" description="Filter bank 4 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x264" size="0" name="F4R2" access="Read/Write" description="Filter bank 4 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x268" size="0" name="F5R1" access="Read/Write" description="Filter bank 5 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x26C" size="0" name="F5R2" access="Read/Write" description="Filter bank 5 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x270" size="0" name="F6R1" access="Read/Write" description="Filter bank 6 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x274" size="0" name="F6R2" access="Read/Write" description="Filter bank 6 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x278" size="0" name="F7R1" access="Read/Write" description="Filter bank 7 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x27C" size="0" name="F7R2" access="Read/Write" description="Filter bank 7 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x280" size="0" name="F8R1" access="Read/Write" description="Filter bank 8 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x284" size="0" name="F8R2" access="Read/Write" description="Filter bank 8 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x288" size="0" name="F9R1" access="Read/Write" description="Filter bank 9 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x28C" size="0" name="F9R2" access="Read/Write" description="Filter bank 9 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x290" size="0" name="F10R1" access="Read/Write" description="Filter bank 10 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x294" size="0" name="F10R2" access="Read/Write" description="Filter bank 10 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x298" size="0" name="F11R1" access="Read/Write" description="Filter bank 11 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x29C" size="0" name="F11R2" access="Read/Write" description="Filter bank 11 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2A0" size="0" name="F12R1" access="Read/Write" description="Filter bank 4 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2A4" size="0" name="F12R2" access="Read/Write" description="Filter bank 12 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2A8" size="0" name="F13R1" access="Read/Write" description="Filter bank 13 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2AC" size="0" name="F13R2" access="Read/Write" description="Filter bank 13 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2B0" size="0" name="F14R1" access="Read/Write" description="Filter bank 14 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2B4" size="0" name="F14R2" access="Read/Write" description="Filter bank 14 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2B8" size="0" name="F15R1" access="Read/Write" description="Filter bank 15 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2BC" size="0" name="F15R2" access="Read/Write" description="Filter bank 15 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2C0" size="0" name="F16R1" access="Read/Write" description="Filter bank 16 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2C4" size="0" name="F16R2" access="Read/Write" description="Filter bank 16 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2C8" size="0" name="F17R1" access="Read/Write" description="Filter bank 17 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2CC" size="0" name="F17R2" access="Read/Write" description="Filter bank 17 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2D0" size="0" name="F18R1" access="Read/Write" description="Filter bank 18 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2D4" size="0" name="F18R2" access="Read/Write" description="Filter bank 18 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2D8" size="0" name="F19R1" access="Read/Write" description="Filter bank 19 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2DC" size="0" name="F19R2" access="Read/Write" description="Filter bank 19 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2E0" size="0" name="F20R1" access="Read/Write" description="Filter bank 20 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2E4" size="0" name="F20R2" access="Read/Write" description="Filter bank 20 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2E8" size="0" name="F21R1" access="Read/Write" description="Filter bank 21 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2EC" size="0" name="F21R2" access="Read/Write" description="Filter bank 21 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2F0" size="0" name="F22R1" access="Read/Write" description="Filter bank 22 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2F4" size="0" name="F22R2" access="Read/Write" description="Filter bank 22 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2F8" size="0" name="F23R1" access="Read/Write" description="Filter bank 23 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x2FC" size="0" name="F23R2" access="Read/Write" description="Filter bank 23 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x300" size="0" name="F24R1" access="Read/Write" description="Filter bank 24 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x304" size="0" name="F24R2" access="Read/Write" description="Filter bank 24 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x308" size="0" name="F25R1" access="Read/Write" description="Filter bank 25 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x30C" size="0" name="F25R2" access="Read/Write" description="Filter bank 25 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x310" size="0" name="F26R1" access="Read/Write" description="Filter bank 26 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x314" size="0" name="F26R2" access="Read/Write" description="Filter bank 26 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x318" size="0" name="F27R1" access="Read/Write" description="Filter bank 27 register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-    <Register start="+0x31C" size="0" name="F27R2" access="Read/Write" description="Filter bank 27 register 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FB0" description="Filter bits" />
-      <BitField start="1" size="1" name="FB1" description="Filter bits" />
-      <BitField start="2" size="1" name="FB2" description="Filter bits" />
-      <BitField start="3" size="1" name="FB3" description="Filter bits" />
-      <BitField start="4" size="1" name="FB4" description="Filter bits" />
-      <BitField start="5" size="1" name="FB5" description="Filter bits" />
-      <BitField start="6" size="1" name="FB6" description="Filter bits" />
-      <BitField start="7" size="1" name="FB7" description="Filter bits" />
-      <BitField start="8" size="1" name="FB8" description="Filter bits" />
-      <BitField start="9" size="1" name="FB9" description="Filter bits" />
-      <BitField start="10" size="1" name="FB10" description="Filter bits" />
-      <BitField start="11" size="1" name="FB11" description="Filter bits" />
-      <BitField start="12" size="1" name="FB12" description="Filter bits" />
-      <BitField start="13" size="1" name="FB13" description="Filter bits" />
-      <BitField start="14" size="1" name="FB14" description="Filter bits" />
-      <BitField start="15" size="1" name="FB15" description="Filter bits" />
-      <BitField start="16" size="1" name="FB16" description="Filter bits" />
-      <BitField start="17" size="1" name="FB17" description="Filter bits" />
-      <BitField start="18" size="1" name="FB18" description="Filter bits" />
-      <BitField start="19" size="1" name="FB19" description="Filter bits" />
-      <BitField start="20" size="1" name="FB20" description="Filter bits" />
-      <BitField start="21" size="1" name="FB21" description="Filter bits" />
-      <BitField start="22" size="1" name="FB22" description="Filter bits" />
-      <BitField start="23" size="1" name="FB23" description="Filter bits" />
-      <BitField start="24" size="1" name="FB24" description="Filter bits" />
-      <BitField start="25" size="1" name="FB25" description="Filter bits" />
-      <BitField start="26" size="1" name="FB26" description="Filter bits" />
-      <BitField start="27" size="1" name="FB27" description="Filter bits" />
-      <BitField start="28" size="1" name="FB28" description="Filter bits" />
-      <BitField start="29" size="1" name="FB29" description="Filter bits" />
-      <BitField start="30" size="1" name="FB30" description="Filter bits" />
-      <BitField start="31" size="1" name="FB31" description="Filter bits" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FLASH" start="0x40023C00" description="FLASH">
-    <Register start="+0x0" size="0" name="ACR" access="Read/Write" description="Flash access control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LATENCY" description="Latency" />
-      <BitField start="8" size="1" name="PRFTEN" description="Prefetch enable" />
-      <BitField start="9" size="1" name="ICEN" description="Instruction cache enable" />
-      <BitField start="10" size="1" name="DCEN" description="Data cache enable" />
-      <BitField start="11" size="1" name="ICRST" description="Instruction cache reset" />
-      <BitField start="12" size="1" name="DCRST" description="Data cache reset" />
-    </Register>
-    <Register start="+0x4" size="0" name="KEYR" access="WriteOnly" description="Flash key register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="KEY" description="FPEC key" />
-    </Register>
-    <Register start="+0x8" size="0" name="OPTKEYR" access="WriteOnly" description="Flash option key register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OPTKEY" description="Option byte key" />
-    </Register>
-    <Register start="+0xC" size="0" name="SR" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOP" description="End of operation" />
-      <BitField start="1" size="1" name="OPERR" description="Operation error" />
-      <BitField start="4" size="1" name="WRPERR" description="Write protection error" />
-      <BitField start="5" size="1" name="PGAERR" description="Programming alignment&#xa;              error" />
-      <BitField start="6" size="1" name="PGPERR" description="Programming parallelism&#xa;              error" />
-      <BitField start="7" size="1" name="PGSERR" description="Programming sequence error" />
-      <BitField start="16" size="1" name="BSY" description="Busy" />
-    </Register>
-    <Register start="+0x10" size="0" name="CR" access="Read/Write" description="Control register" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PG" description="Programming" />
-      <BitField start="1" size="1" name="SER" description="Sector Erase" />
-      <BitField start="2" size="1" name="MER" description="Mass Erase" />
-      <BitField start="3" size="4" name="SNB" description="Sector number" />
-      <BitField start="8" size="2" name="PSIZE" description="Program size" />
-      <BitField start="16" size="1" name="STRT" description="Start" />
-      <BitField start="24" size="1" name="EOPIE" description="End of operation interrupt&#xa;              enable" />
-      <BitField start="25" size="1" name="ERRIE" description="Error interrupt enable" />
-      <BitField start="31" size="1" name="LOCK" description="Lock" />
-    </Register>
-    <Register start="+0x14" size="0" name="OPTCR" access="Read/Write" description="Flash option control register" reset_value="0x00000014" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OPTLOCK" description="Option lock" />
-      <BitField start="1" size="1" name="OPTSTRT" description="Option start" />
-      <BitField start="2" size="2" name="BOR_LEV" description="BOR reset Level" />
-      <BitField start="5" size="1" name="WDG_SW" description="WDG_SW User option bytes" />
-      <BitField start="6" size="1" name="nRST_STOP" description="nRST_STOP User option&#xa;              bytes" />
-      <BitField start="7" size="1" name="nRST_STDBY" description="nRST_STDBY User option&#xa;              bytes" />
-      <BitField start="8" size="8" name="RDP" description="Read protect" />
-      <BitField start="16" size="12" name="nWRP" description="Not write protect" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EXTI" start="0x40013C00" description="External interrupt/event&#xa;      controller">
-    <Register start="+0x0" size="0" name="IMR" access="Read/Write" description="Interrupt mask register&#xa;          (EXTI_IMR)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0" description="Interrupt Mask on line 0" />
-      <BitField start="1" size="1" name="MR1" description="Interrupt Mask on line 1" />
-      <BitField start="2" size="1" name="MR2" description="Interrupt Mask on line 2" />
-      <BitField start="3" size="1" name="MR3" description="Interrupt Mask on line 3" />
-      <BitField start="4" size="1" name="MR4" description="Interrupt Mask on line 4" />
-      <BitField start="5" size="1" name="MR5" description="Interrupt Mask on line 5" />
-      <BitField start="6" size="1" name="MR6" description="Interrupt Mask on line 6" />
-      <BitField start="7" size="1" name="MR7" description="Interrupt Mask on line 7" />
-      <BitField start="8" size="1" name="MR8" description="Interrupt Mask on line 8" />
-      <BitField start="9" size="1" name="MR9" description="Interrupt Mask on line 9" />
-      <BitField start="10" size="1" name="MR10" description="Interrupt Mask on line 10" />
-      <BitField start="11" size="1" name="MR11" description="Interrupt Mask on line 11" />
-      <BitField start="12" size="1" name="MR12" description="Interrupt Mask on line 12" />
-      <BitField start="13" size="1" name="MR13" description="Interrupt Mask on line 13" />
-      <BitField start="14" size="1" name="MR14" description="Interrupt Mask on line 14" />
-      <BitField start="15" size="1" name="MR15" description="Interrupt Mask on line 15" />
-      <BitField start="16" size="1" name="MR16" description="Interrupt Mask on line 16" />
-      <BitField start="17" size="1" name="MR17" description="Interrupt Mask on line 17" />
-      <BitField start="18" size="1" name="MR18" description="Interrupt Mask on line 18" />
-      <BitField start="19" size="1" name="MR19" description="Interrupt Mask on line 19" />
-      <BitField start="20" size="1" name="MR20" description="Interrupt Mask on line 20" />
-      <BitField start="21" size="1" name="MR21" description="Interrupt Mask on line 21" />
-      <BitField start="22" size="1" name="MR22" description="Interrupt Mask on line 22" />
-    </Register>
-    <Register start="+0x4" size="0" name="EMR" access="Read/Write" description="Event mask register (EXTI_EMR)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0" description="Event Mask on line 0" />
-      <BitField start="1" size="1" name="MR1" description="Event Mask on line 1" />
-      <BitField start="2" size="1" name="MR2" description="Event Mask on line 2" />
-      <BitField start="3" size="1" name="MR3" description="Event Mask on line 3" />
-      <BitField start="4" size="1" name="MR4" description="Event Mask on line 4" />
-      <BitField start="5" size="1" name="MR5" description="Event Mask on line 5" />
-      <BitField start="6" size="1" name="MR6" description="Event Mask on line 6" />
-      <BitField start="7" size="1" name="MR7" description="Event Mask on line 7" />
-      <BitField start="8" size="1" name="MR8" description="Event Mask on line 8" />
-      <BitField start="9" size="1" name="MR9" description="Event Mask on line 9" />
-      <BitField start="10" size="1" name="MR10" description="Event Mask on line 10" />
-      <BitField start="11" size="1" name="MR11" description="Event Mask on line 11" />
-      <BitField start="12" size="1" name="MR12" description="Event Mask on line 12" />
-      <BitField start="13" size="1" name="MR13" description="Event Mask on line 13" />
-      <BitField start="14" size="1" name="MR14" description="Event Mask on line 14" />
-      <BitField start="15" size="1" name="MR15" description="Event Mask on line 15" />
-      <BitField start="16" size="1" name="MR16" description="Event Mask on line 16" />
-      <BitField start="17" size="1" name="MR17" description="Event Mask on line 17" />
-      <BitField start="18" size="1" name="MR18" description="Event Mask on line 18" />
-      <BitField start="19" size="1" name="MR19" description="Event Mask on line 19" />
-      <BitField start="20" size="1" name="MR20" description="Event Mask on line 20" />
-      <BitField start="21" size="1" name="MR21" description="Event Mask on line 21" />
-      <BitField start="22" size="1" name="MR22" description="Event Mask on line 22" />
-    </Register>
-    <Register start="+0x8" size="0" name="RTSR" access="Read/Write" description="Rising Trigger selection register&#xa;          (EXTI_RTSR)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR0" description="Rising trigger event configuration of&#xa;              line 0" />
-      <BitField start="1" size="1" name="TR1" description="Rising trigger event configuration of&#xa;              line 1" />
-      <BitField start="2" size="1" name="TR2" description="Rising trigger event configuration of&#xa;              line 2" />
-      <BitField start="3" size="1" name="TR3" description="Rising trigger event configuration of&#xa;              line 3" />
-      <BitField start="4" size="1" name="TR4" description="Rising trigger event configuration of&#xa;              line 4" />
-      <BitField start="5" size="1" name="TR5" description="Rising trigger event configuration of&#xa;              line 5" />
-      <BitField start="6" size="1" name="TR6" description="Rising trigger event configuration of&#xa;              line 6" />
-      <BitField start="7" size="1" name="TR7" description="Rising trigger event configuration of&#xa;              line 7" />
-      <BitField start="8" size="1" name="TR8" description="Rising trigger event configuration of&#xa;              line 8" />
-      <BitField start="9" size="1" name="TR9" description="Rising trigger event configuration of&#xa;              line 9" />
-      <BitField start="10" size="1" name="TR10" description="Rising trigger event configuration of&#xa;              line 10" />
-      <BitField start="11" size="1" name="TR11" description="Rising trigger event configuration of&#xa;              line 11" />
-      <BitField start="12" size="1" name="TR12" description="Rising trigger event configuration of&#xa;              line 12" />
-      <BitField start="13" size="1" name="TR13" description="Rising trigger event configuration of&#xa;              line 13" />
-      <BitField start="14" size="1" name="TR14" description="Rising trigger event configuration of&#xa;              line 14" />
-      <BitField start="15" size="1" name="TR15" description="Rising trigger event configuration of&#xa;              line 15" />
-      <BitField start="16" size="1" name="TR16" description="Rising trigger event configuration of&#xa;              line 16" />
-      <BitField start="17" size="1" name="TR17" description="Rising trigger event configuration of&#xa;              line 17" />
-      <BitField start="18" size="1" name="TR18" description="Rising trigger event configuration of&#xa;              line 18" />
-      <BitField start="19" size="1" name="TR19" description="Rising trigger event configuration of&#xa;              line 19" />
-      <BitField start="20" size="1" name="TR20" description="Rising trigger event configuration of&#xa;              line 20" />
-      <BitField start="21" size="1" name="TR21" description="Rising trigger event configuration of&#xa;              line 21" />
-      <BitField start="22" size="1" name="TR22" description="Rising trigger event configuration of&#xa;              line 22" />
-    </Register>
-    <Register start="+0xC" size="0" name="FTSR" access="Read/Write" description="Falling Trigger selection register&#xa;          (EXTI_FTSR)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR0" description="Falling trigger event configuration of&#xa;              line 0" />
-      <BitField start="1" size="1" name="TR1" description="Falling trigger event configuration of&#xa;              line 1" />
-      <BitField start="2" size="1" name="TR2" description="Falling trigger event configuration of&#xa;              line 2" />
-      <BitField start="3" size="1" name="TR3" description="Falling trigger event configuration of&#xa;              line 3" />
-      <BitField start="4" size="1" name="TR4" description="Falling trigger event configuration of&#xa;              line 4" />
-      <BitField start="5" size="1" name="TR5" description="Falling trigger event configuration of&#xa;              line 5" />
-      <BitField start="6" size="1" name="TR6" description="Falling trigger event configuration of&#xa;              line 6" />
-      <BitField start="7" size="1" name="TR7" description="Falling trigger event configuration of&#xa;              line 7" />
-      <BitField start="8" size="1" name="TR8" description="Falling trigger event configuration of&#xa;              line 8" />
-      <BitField start="9" size="1" name="TR9" description="Falling trigger event configuration of&#xa;              line 9" />
-      <BitField start="10" size="1" name="TR10" description="Falling trigger event configuration of&#xa;              line 10" />
-      <BitField start="11" size="1" name="TR11" description="Falling trigger event configuration of&#xa;              line 11" />
-      <BitField start="12" size="1" name="TR12" description="Falling trigger event configuration of&#xa;              line 12" />
-      <BitField start="13" size="1" name="TR13" description="Falling trigger event configuration of&#xa;              line 13" />
-      <BitField start="14" size="1" name="TR14" description="Falling trigger event configuration of&#xa;              line 14" />
-      <BitField start="15" size="1" name="TR15" description="Falling trigger event configuration of&#xa;              line 15" />
-      <BitField start="16" size="1" name="TR16" description="Falling trigger event configuration of&#xa;              line 16" />
-      <BitField start="17" size="1" name="TR17" description="Falling trigger event configuration of&#xa;              line 17" />
-      <BitField start="18" size="1" name="TR18" description="Falling trigger event configuration of&#xa;              line 18" />
-      <BitField start="19" size="1" name="TR19" description="Falling trigger event configuration of&#xa;              line 19" />
-      <BitField start="20" size="1" name="TR20" description="Falling trigger event configuration of&#xa;              line 20" />
-      <BitField start="21" size="1" name="TR21" description="Falling trigger event configuration of&#xa;              line 21" />
-      <BitField start="22" size="1" name="TR22" description="Falling trigger event configuration of&#xa;              line 22" />
-    </Register>
-    <Register start="+0x10" size="0" name="SWIER" access="Read/Write" description="Software interrupt event register&#xa;          (EXTI_SWIER)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWIER0" description="Software Interrupt on line&#xa;              0" />
-      <BitField start="1" size="1" name="SWIER1" description="Software Interrupt on line&#xa;              1" />
-      <BitField start="2" size="1" name="SWIER2" description="Software Interrupt on line&#xa;              2" />
-      <BitField start="3" size="1" name="SWIER3" description="Software Interrupt on line&#xa;              3" />
-      <BitField start="4" size="1" name="SWIER4" description="Software Interrupt on line&#xa;              4" />
-      <BitField start="5" size="1" name="SWIER5" description="Software Interrupt on line&#xa;              5" />
-      <BitField start="6" size="1" name="SWIER6" description="Software Interrupt on line&#xa;              6" />
-      <BitField start="7" size="1" name="SWIER7" description="Software Interrupt on line&#xa;              7" />
-      <BitField start="8" size="1" name="SWIER8" description="Software Interrupt on line&#xa;              8" />
-      <BitField start="9" size="1" name="SWIER9" description="Software Interrupt on line&#xa;              9" />
-      <BitField start="10" size="1" name="SWIER10" description="Software Interrupt on line&#xa;              10" />
-      <BitField start="11" size="1" name="SWIER11" description="Software Interrupt on line&#xa;              11" />
-      <BitField start="12" size="1" name="SWIER12" description="Software Interrupt on line&#xa;              12" />
-      <BitField start="13" size="1" name="SWIER13" description="Software Interrupt on line&#xa;              13" />
-      <BitField start="14" size="1" name="SWIER14" description="Software Interrupt on line&#xa;              14" />
-      <BitField start="15" size="1" name="SWIER15" description="Software Interrupt on line&#xa;              15" />
-      <BitField start="16" size="1" name="SWIER16" description="Software Interrupt on line&#xa;              16" />
-      <BitField start="17" size="1" name="SWIER17" description="Software Interrupt on line&#xa;              17" />
-      <BitField start="18" size="1" name="SWIER18" description="Software Interrupt on line&#xa;              18" />
-      <BitField start="19" size="1" name="SWIER19" description="Software Interrupt on line&#xa;              19" />
-      <BitField start="20" size="1" name="SWIER20" description="Software Interrupt on line&#xa;              20" />
-      <BitField start="21" size="1" name="SWIER21" description="Software Interrupt on line&#xa;              21" />
-      <BitField start="22" size="1" name="SWIER22" description="Software Interrupt on line&#xa;              22" />
-    </Register>
-    <Register start="+0x14" size="0" name="PR" access="Read/Write" description="Pending register (EXTI_PR)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PR0" description="Pending bit 0" />
-      <BitField start="1" size="1" name="PR1" description="Pending bit 1" />
-      <BitField start="2" size="1" name="PR2" description="Pending bit 2" />
-      <BitField start="3" size="1" name="PR3" description="Pending bit 3" />
-      <BitField start="4" size="1" name="PR4" description="Pending bit 4" />
-      <BitField start="5" size="1" name="PR5" description="Pending bit 5" />
-      <BitField start="6" size="1" name="PR6" description="Pending bit 6" />
-      <BitField start="7" size="1" name="PR7" description="Pending bit 7" />
-      <BitField start="8" size="1" name="PR8" description="Pending bit 8" />
-      <BitField start="9" size="1" name="PR9" description="Pending bit 9" />
-      <BitField start="10" size="1" name="PR10" description="Pending bit 10" />
-      <BitField start="11" size="1" name="PR11" description="Pending bit 11" />
-      <BitField start="12" size="1" name="PR12" description="Pending bit 12" />
-      <BitField start="13" size="1" name="PR13" description="Pending bit 13" />
-      <BitField start="14" size="1" name="PR14" description="Pending bit 14" />
-      <BitField start="15" size="1" name="PR15" description="Pending bit 15" />
-      <BitField start="16" size="1" name="PR16" description="Pending bit 16" />
-      <BitField start="17" size="1" name="PR17" description="Pending bit 17" />
-      <BitField start="18" size="1" name="PR18" description="Pending bit 18" />
-      <BitField start="19" size="1" name="PR19" description="Pending bit 19" />
-      <BitField start="20" size="1" name="PR20" description="Pending bit 20" />
-      <BitField start="21" size="1" name="PR21" description="Pending bit 21" />
-      <BitField start="22" size="1" name="PR22" description="Pending bit 22" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_HS_GLOBAL" start="0x40040000" description="USB on the go high speed">
-    <Register start="+0x0" size="4" name="OTG_HS_GOTGCTL" access="Read/Write" description="OTG_HS control and status&#xa;          register" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SRQSCS" description="Session request success" />
-      <BitField start="1" size="1" name="SRQ" description="Session request" />
-      <BitField start="8" size="1" name="HNGSCS" description="Host negotiation success" />
-      <BitField start="9" size="1" name="HNPRQ" description="HNP request" />
-      <BitField start="10" size="1" name="HSHNPEN" description="Host set HNP enable" />
-      <BitField start="11" size="1" name="DHNPEN" description="Device HNP enabled" />
-      <BitField start="16" size="1" name="CIDSTS" description="Connector ID status" />
-      <BitField start="17" size="1" name="DBCT" description="Long/short debounce time" />
-      <BitField start="18" size="1" name="ASVLD" description="A-session valid" />
-      <BitField start="19" size="1" name="BSVLD" description="B-session valid" />
-    </Register>
-    <Register start="+0x4" size="4" name="OTG_HS_GOTGINT" access="Read/Write" description="OTG_HS interrupt register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="SEDET" description="Session end detected" />
-      <BitField start="8" size="1" name="SRSSCHG" description="Session request success status&#xa;              change" />
-      <BitField start="9" size="1" name="HNSSCHG" description="Host negotiation success status&#xa;              change" />
-      <BitField start="17" size="1" name="HNGDET" description="Host negotiation detected" />
-      <BitField start="18" size="1" name="ADTOCHG" description="A-device timeout change" />
-      <BitField start="19" size="1" name="DBCDNE" description="Debounce done" />
-    </Register>
-    <Register start="+0x8" size="4" name="OTG_HS_GAHBCFG" access="Read/Write" description="OTG_HS AHB configuration&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GINT" description="Global interrupt mask" />
-      <BitField start="1" size="4" name="HBSTLEN" description="Burst length/type" />
-      <BitField start="5" size="1" name="DMAEN" description="DMA enable" />
-      <BitField start="7" size="1" name="TXFELVL" description="TxFIFO empty level" />
-      <BitField start="8" size="1" name="PTXFELVL" description="Periodic TxFIFO empty&#xa;              level" />
-    </Register>
-    <Register start="+0xC" size="4" name="OTG_HS_GUSBCFG" access="Read/Write" description="OTG_HS USB configuration&#xa;          register" reset_value="0x00000A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="TOCAL" description="FS timeout calibration" />
-      <BitField start="6" size="1" name="PHYSEL" description="USB 2.0 high-speed ULPI PHY or USB 1.1&#xa;              full-speed serial transceiver select" />
-      <BitField start="8" size="1" name="SRPCAP" description="SRP-capable" />
-      <BitField start="9" size="1" name="HNPCAP" description="HNP-capable" />
-      <BitField start="10" size="4" name="TRDT" description="USB turnaround time" />
-      <BitField start="15" size="1" name="PHYLPCS" description="PHY Low-power clock select" />
-      <BitField start="17" size="1" name="ULPIFSLS" description="ULPI FS/LS select" />
-      <BitField start="18" size="1" name="ULPIAR" description="ULPI Auto-resume" />
-      <BitField start="19" size="1" name="ULPICSM" description="ULPI Clock SuspendM" />
-      <BitField start="20" size="1" name="ULPIEVBUSD" description="ULPI External VBUS Drive" />
-      <BitField start="21" size="1" name="ULPIEVBUSI" description="ULPI external VBUS&#xa;              indicator" />
-      <BitField start="22" size="1" name="TSDPS" description="TermSel DLine pulsing&#xa;              selection" />
-      <BitField start="23" size="1" name="PCCI" description="Indicator complement" />
-      <BitField start="24" size="1" name="PTCI" description="Indicator pass through" />
-      <BitField start="25" size="1" name="ULPIIPD" description="ULPI interface protect&#xa;              disable" />
-      <BitField start="29" size="1" name="FHMOD" description="Forced host mode" />
-      <BitField start="30" size="1" name="FDMOD" description="Forced peripheral mode" />
-      <BitField start="31" size="1" name="CTXPKT" description="Corrupt Tx packet" />
-    </Register>
-    <Register start="+0x10" size="4" name="OTG_HS_GRSTCTL" access="Read/Write" description="OTG_HS reset register" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSRST" description="Core soft reset" />
-      <BitField start="1" size="1" name="HSRST" description="HCLK soft reset" />
-      <BitField start="2" size="1" name="FCRST" description="Host frame counter reset" />
-      <BitField start="4" size="1" name="RXFFLSH" description="RxFIFO flush" />
-      <BitField start="5" size="1" name="TXFFLSH" description="TxFIFO flush" />
-      <BitField start="6" size="5" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="30" size="1" name="DMAREQ" description="DMA request signal" />
-      <BitField start="31" size="1" name="AHBIDL" description="AHB master idle" />
-    </Register>
-    <Register start="+0x14" size="4" name="OTG_HS_GINTSTS" access="Read/Write" description="OTG_HS core interrupt register" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMOD" description="Current mode of operation" />
-      <BitField start="1" size="1" name="MMIS" description="Mode mismatch interrupt" />
-      <BitField start="2" size="1" name="OTGINT" description="OTG interrupt" />
-      <BitField start="3" size="1" name="SOF" description="Start of frame" />
-      <BitField start="4" size="1" name="RXFLVL" description="RxFIFO nonempty" />
-      <BitField start="5" size="1" name="NPTXFE" description="Nonperiodic TxFIFO empty" />
-      <BitField start="6" size="1" name="GINAKEFF" description="Global IN nonperiodic NAK&#xa;              effective" />
-      <BitField start="7" size="1" name="BOUTNAKEFF" description="Global OUT NAK effective" />
-      <BitField start="10" size="1" name="ESUSP" description="Early suspend" />
-      <BitField start="11" size="1" name="USBSUSP" description="USB suspend" />
-      <BitField start="12" size="1" name="USBRST" description="USB reset" />
-      <BitField start="13" size="1" name="ENUMDNE" description="Enumeration done" />
-      <BitField start="14" size="1" name="ISOODRP" description="Isochronous OUT packet dropped&#xa;              interrupt" />
-      <BitField start="15" size="1" name="EOPF" description="End of periodic frame&#xa;              interrupt" />
-      <BitField start="18" size="1" name="IEPINT" description="IN endpoint interrupt" />
-      <BitField start="19" size="1" name="OEPINT" description="OUT endpoint interrupt" />
-      <BitField start="20" size="1" name="IISOIXFR" description="Incomplete isochronous IN&#xa;              transfer" />
-      <BitField start="21" size="1" name="PXFR_INCOMPISOOUT" description="Incomplete periodic&#xa;              transfer" />
-      <BitField start="22" size="1" name="DATAFSUSP" description="Data fetch suspended" />
-      <BitField start="24" size="1" name="HPRTINT" description="Host port interrupt" />
-      <BitField start="25" size="1" name="HCINT" description="Host channels interrupt" />
-      <BitField start="26" size="1" name="PTXFE" description="Periodic TxFIFO empty" />
-      <BitField start="28" size="1" name="CIDSCHG" description="Connector ID status change" />
-      <BitField start="29" size="1" name="DISCINT" description="Disconnect detected&#xa;              interrupt" />
-      <BitField start="30" size="1" name="SRQINT" description="Session request/new session detected&#xa;              interrupt" />
-      <BitField start="31" size="1" name="WKUINT" description="Resume/remote wakeup detected&#xa;              interrupt" />
-    </Register>
-    <Register start="+0x18" size="4" name="OTG_HS_GINTMSK" access="Read/Write" description="OTG_HS interrupt mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="MMISM" description="Mode mismatch interrupt&#xa;              mask" />
-      <BitField start="2" size="1" name="OTGINT" description="OTG interrupt mask" />
-      <BitField start="3" size="1" name="SOFM" description="Start of frame mask" />
-      <BitField start="4" size="1" name="RXFLVLM" description="Receive FIFO nonempty mask" />
-      <BitField start="5" size="1" name="NPTXFEM" description="Nonperiodic TxFIFO empty&#xa;              mask" />
-      <BitField start="6" size="1" name="GINAKEFFM" description="Global nonperiodic IN NAK effective&#xa;              mask" />
-      <BitField start="7" size="1" name="GONAKEFFM" description="Global OUT NAK effective&#xa;              mask" />
-      <BitField start="10" size="1" name="ESUSPM" description="Early suspend mask" />
-      <BitField start="11" size="1" name="USBSUSPM" description="USB suspend mask" />
-      <BitField start="12" size="1" name="USBRST" description="USB reset mask" />
-      <BitField start="13" size="1" name="ENUMDNEM" description="Enumeration done mask" />
-      <BitField start="14" size="1" name="ISOODRPM" description="Isochronous OUT packet dropped interrupt&#xa;              mask" />
-      <BitField start="15" size="1" name="EOPFM" description="End of periodic frame interrupt&#xa;              mask" />
-      <BitField start="17" size="1" name="EPMISM" description="Endpoint mismatch interrupt&#xa;              mask" />
-      <BitField start="18" size="1" name="IEPINT" description="IN endpoints interrupt&#xa;              mask" />
-      <BitField start="19" size="1" name="OEPINT" description="OUT endpoints interrupt&#xa;              mask" />
-      <BitField start="20" size="1" name="IISOIXFRM" description="Incomplete isochronous IN transfer&#xa;              mask" />
-      <BitField start="21" size="1" name="PXFRM_IISOOXFRM" description="Incomplete periodic transfer&#xa;              mask" />
-      <BitField start="22" size="1" name="FSUSPM" description="Data fetch suspended mask" />
-      <BitField start="24" size="1" name="PRTIM" description="Host port interrupt mask" />
-      <BitField start="25" size="1" name="HCIM" description="Host channels interrupt&#xa;              mask" />
-      <BitField start="26" size="1" name="PTXFEM" description="Periodic TxFIFO empty mask" />
-      <BitField start="28" size="1" name="CIDSCHGM" description="Connector ID status change&#xa;              mask" />
-      <BitField start="29" size="1" name="DISCINT" description="Disconnect detected interrupt&#xa;              mask" />
-      <BitField start="30" size="1" name="SRQIM" description="Session request/new session detected&#xa;              interrupt mask" />
-      <BitField start="31" size="1" name="WUIM" description="Resume/remote wakeup detected interrupt&#xa;              mask" />
-    </Register>
-    <Register start="+0x1C" size="4" name="OTG_HS_GRXSTSR_Host" access="ReadOnly" description="OTG_HS Receive status debug read register&#xa;          (host mode)" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CHNUM" description="Channel number" />
-      <BitField start="4" size="11" name="BCNT" description="Byte count" />
-      <BitField start="15" size="2" name="DPID" description="Data PID" />
-      <BitField start="17" size="4" name="PKTSTS" description="Packet status" />
-    </Register>
-    <Register start="+0x20" size="4" name="OTG_HS_GRXSTSP_Host" access="ReadOnly" description="OTG_HS status read and pop register (host&#xa;          mode)" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CHNUM" description="Channel number" />
-      <BitField start="4" size="11" name="BCNT" description="Byte count" />
-      <BitField start="15" size="2" name="DPID" description="Data PID" />
-      <BitField start="17" size="4" name="PKTSTS" description="Packet status" />
-    </Register>
-    <Register start="+0x24" size="4" name="OTG_HS_GRXFSIZ" access="Read/Write" description="OTG_HS Receive FIFO size&#xa;          register" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXFD" description="RxFIFO depth" />
-    </Register>
-    <Register start="+0x28" size="4" name="OTG_HS_GNPTXFSIZ_Host" access="Read/Write" description="OTG_HS nonperiodic transmit FIFO size&#xa;          register (host mode)" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NPTXFSA" description="Nonperiodic transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="NPTXFD" description="Nonperiodic TxFIFO depth" />
-    </Register>
-    <Register start="+0x28" size="4" name="OTG_HS_TX0FSIZ_Peripheral" access="Read/Write" description="Endpoint 0 transmit FIFO size (peripheral&#xa;          mode)" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TX0FSA" description="Endpoint 0 transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="TX0FD" description="Endpoint 0 TxFIFO depth" />
-    </Register>
-    <Register start="+0x2C" size="4" name="OTG_HS_GNPTXSTS" access="ReadOnly" description="OTG_HS nonperiodic transmit FIFO/queue&#xa;          status register" reset_value="0x00080200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NPTXFSAV" description="Nonperiodic TxFIFO space&#xa;              available" />
-      <BitField start="16" size="8" name="NPTQXSAV" description="Nonperiodic transmit request queue space&#xa;              available" />
-      <BitField start="24" size="7" name="NPTXQTOP" description="Top of the nonperiodic transmit request&#xa;              queue" />
-    </Register>
-    <Register start="+0x38" size="4" name="OTG_HS_GCCFG" access="Read/Write" description="OTG_HS general core configuration&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="PWRDWN" description="Power down" />
-      <BitField start="17" size="1" name="I2CPADEN" description="Enable I2C bus connection for the&#xa;              external I2C PHY interface" />
-      <BitField start="18" size="1" name="VBUSASEN" description="Enable the VBUS sensing&#xa;              device" />
-      <BitField start="19" size="1" name="VBUSBSEN" description="Enable the VBUS sensing device" />
-      <BitField start="20" size="1" name="SOFOUTEN" description="SOF output enable" />
-      <BitField start="21" size="1" name="NOVBUSSENS" description="VBUS sensing disable&#xa;              option" />
-    </Register>
-    <Register start="+0x3C" size="4" name="OTG_HS_CID" access="Read/Write" description="OTG_HS core ID register" reset_value="0x00001200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PRODUCT_ID" description="Product ID field" />
-    </Register>
-    <Register start="+0x100" size="4" name="OTG_HS_HPTXFSIZ" access="Read/Write" description="OTG_HS Host periodic transmit FIFO size&#xa;          register" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PTXSA" description="Host periodic TxFIFO start&#xa;              address" />
-      <BitField start="16" size="16" name="PTXFD" description="Host periodic TxFIFO depth" />
-    </Register>
-    <Register start="+0x104" size="4" name="OTG_HS_DIEPTXF1" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x108" size="4" name="OTG_HS_DIEPTXF2" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x11C" size="4" name="OTG_HS_DIEPTXF3" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x120" size="4" name="OTG_HS_DIEPTXF4" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x124" size="4" name="OTG_HS_DIEPTXF5" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x128" size="4" name="OTG_HS_DIEPTXF6" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x12C" size="4" name="OTG_HS_DIEPTXF7" access="Read/Write" description="OTG_HS device IN endpoint transmit FIFO size&#xa;          register" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start&#xa;              address" />
-      <BitField start="16" size="16" name="INEPTXFD" description="IN endpoint TxFIFO depth" />
-    </Register>
-    <Register start="+0x1C" size="4" name="OTG_HS_GRXSTSR_Peripheral" access="ReadOnly" description="OTG_HS Receive status debug read register&#xa;          (peripheral mode mode)" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="4" size="11" name="BCNT" description="Byte count" />
-      <BitField start="15" size="2" name="DPID" description="Data PID" />
-      <BitField start="17" size="4" name="PKTSTS" description="Packet status" />
-      <BitField start="21" size="4" name="FRMNUM" description="Frame number" />
-    </Register>
-    <Register start="+0x20" size="4" name="OTG_HS_GRXSTSP_Peripheral" access="ReadOnly" description="OTG_HS status read and pop register&#xa;          (peripheral mode)" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="4" size="11" name="BCNT" description="Byte count" />
-      <BitField start="15" size="2" name="DPID" description="Data PID" />
-      <BitField start="17" size="4" name="PKTSTS" description="Packet status" />
-      <BitField start="21" size="4" name="FRMNUM" description="Frame number" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_HS_HOST" start="0x40040400" description="USB on the go high speed">
-    <Register start="+0x0" size="4" name="OTG_HS_HCFG" access="Read/Write" description="OTG_HS host configuration&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="FSLSPCS" description="FS/LS PHY clock select" />
-      <BitField start="2" size="1" name="FSLSS" description="FS- and LS-only support" />
-    </Register>
-    <Register start="+0x4" size="4" name="OTG_HS_HFIR" access="Read/Write" description="OTG_HS Host frame interval&#xa;          register" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FRIVL" description="Frame interval" />
-    </Register>
-    <Register start="+0x8" size="4" name="OTG_HS_HFNUM" access="ReadOnly" description="OTG_HS host frame number/frame time&#xa;          remaining register" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FRNUM" description="Frame number" />
-      <BitField start="16" size="16" name="FTREM" description="Frame time remaining" />
-    </Register>
-    <Register start="+0x10" size="4" name="OTG_HS_HPTXSTS" access="Read/Write" description="OTG_HS_Host periodic transmit FIFO/queue&#xa;          status register" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PTXFSAVL" description="Periodic transmit data FIFO space&#xa;              available" />
-      <BitField start="16" size="8" name="PTXQSAV" description="Periodic transmit request queue space&#xa;              available" />
-      <BitField start="24" size="8" name="PTXQTOP" description="Top of the periodic transmit request&#xa;              queue" />
-    </Register>
-    <Register start="+0x14" size="4" name="OTG_HS_HAINT" access="ReadOnly" description="OTG_HS Host all channels interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HAINT" description="Channel interrupts" />
-    </Register>
-    <Register start="+0x18" size="4" name="OTG_HS_HAINTMSK" access="Read/Write" description="OTG_HS host all channels interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HAINTM" description="Channel interrupt mask" />
-    </Register>
-    <Register start="+0x40" size="4" name="OTG_HS_HPRT" access="Read/Write" description="OTG_HS host port control and status&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCSTS" description="Port connect status" />
-      <BitField start="1" size="1" name="PCDET" description="Port connect detected" />
-      <BitField start="2" size="1" name="PENA" description="Port enable" />
-      <BitField start="3" size="1" name="PENCHNG" description="Port enable/disable change" />
-      <BitField start="4" size="1" name="POCA" description="Port overcurrent active" />
-      <BitField start="5" size="1" name="POCCHNG" description="Port overcurrent change" />
-      <BitField start="6" size="1" name="PRES" description="Port resume" />
-      <BitField start="7" size="1" name="PSUSP" description="Port suspend" />
-      <BitField start="8" size="1" name="PRST" description="Port reset" />
-      <BitField start="10" size="2" name="PLSTS" description="Port line status" />
-      <BitField start="12" size="1" name="PPWR" description="Port power" />
-      <BitField start="13" size="4" name="PTCTL" description="Port test control" />
-      <BitField start="17" size="2" name="PSPD" description="Port speed" />
-    </Register>
-    <Register start="+0x100" size="4" name="OTG_HS_HCCHAR0" access="Read/Write" description="OTG_HS host channel-0 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x120" size="4" name="OTG_HS_HCCHAR1" access="Read/Write" description="OTG_HS host channel-1 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x140" size="4" name="OTG_HS_HCCHAR2" access="Read/Write" description="OTG_HS host channel-2 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x160" size="4" name="OTG_HS_HCCHAR3" access="Read/Write" description="OTG_HS host channel-3 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x180" size="4" name="OTG_HS_HCCHAR4" access="Read/Write" description="OTG_HS host channel-4 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x1A0" size="4" name="OTG_HS_HCCHAR5" access="Read/Write" description="OTG_HS host channel-5 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="OTG_HS_HCCHAR6" access="Read/Write" description="OTG_HS host channel-6 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x1E0" size="4" name="OTG_HS_HCCHAR7" access="Read/Write" description="OTG_HS host channel-7 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x200" size="4" name="OTG_HS_HCCHAR8" access="Read/Write" description="OTG_HS host channel-8 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x220" size="4" name="OTG_HS_HCCHAR9" access="Read/Write" description="OTG_HS host channel-9 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x240" size="4" name="OTG_HS_HCCHAR10" access="Read/Write" description="OTG_HS host channel-10 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x260" size="4" name="OTG_HS_HCCHAR11" access="Read/Write" description="OTG_HS host channel-11 characteristics&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="11" size="4" name="EPNUM" description="Endpoint number" />
-      <BitField start="15" size="1" name="EPDIR" description="Endpoint direction" />
-      <BitField start="17" size="1" name="LSDEV" description="Low-speed device" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="2" name="MC" description="Multi Count (MC) / Error Count&#xa;              (EC)" />
-      <BitField start="22" size="7" name="DAD" description="Device address" />
-      <BitField start="29" size="1" name="ODDFRM" description="Odd frame" />
-      <BitField start="30" size="1" name="CHDIS" description="Channel disable" />
-      <BitField start="31" size="1" name="CHENA" description="Channel enable" />
-    </Register>
-    <Register start="+0x104" size="4" name="OTG_HS_HCSPLT0" access="Read/Write" description="OTG_HS host channel-0 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x124" size="4" name="OTG_HS_HCSPLT1" access="Read/Write" description="OTG_HS host channel-1 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x144" size="4" name="OTG_HS_HCSPLT2" access="Read/Write" description="OTG_HS host channel-2 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x164" size="4" name="OTG_HS_HCSPLT3" access="Read/Write" description="OTG_HS host channel-3 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x184" size="4" name="OTG_HS_HCSPLT4" access="Read/Write" description="OTG_HS host channel-4 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x1A4" size="4" name="OTG_HS_HCSPLT5" access="Read/Write" description="OTG_HS host channel-5 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x1C4" size="4" name="OTG_HS_HCSPLT6" access="Read/Write" description="OTG_HS host channel-6 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x1E4" size="4" name="OTG_HS_HCSPLT7" access="Read/Write" description="OTG_HS host channel-7 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x204" size="4" name="OTG_HS_HCSPLT8" access="Read/Write" description="OTG_HS host channel-8 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x224" size="4" name="OTG_HS_HCSPLT9" access="Read/Write" description="OTG_HS host channel-9 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x244" size="4" name="OTG_HS_HCSPLT10" access="Read/Write" description="OTG_HS host channel-10 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x264" size="4" name="OTG_HS_HCSPLT11" access="Read/Write" description="OTG_HS host channel-11 split control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PRTADDR" description="Port address" />
-      <BitField start="7" size="7" name="HUBADDR" description="Hub address" />
-      <BitField start="14" size="2" name="XACTPOS" description="XACTPOS" />
-      <BitField start="16" size="1" name="COMPLSPLT" description="Do complete split" />
-      <BitField start="31" size="1" name="SPLITEN" description="Split enable" />
-    </Register>
-    <Register start="+0x108" size="4" name="OTG_HS_HCINT0" access="Read/Write" description="OTG_HS host channel-11 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x128" size="4" name="OTG_HS_HCINT1" access="Read/Write" description="OTG_HS host channel-1 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x148" size="4" name="OTG_HS_HCINT2" access="Read/Write" description="OTG_HS host channel-2 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x168" size="4" name="OTG_HS_HCINT3" access="Read/Write" description="OTG_HS host channel-3 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x188" size="4" name="OTG_HS_HCINT4" access="Read/Write" description="OTG_HS host channel-4 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="OTG_HS_HCINT5" access="Read/Write" description="OTG_HS host channel-5 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x1C8" size="4" name="OTG_HS_HCINT6" access="Read/Write" description="OTG_HS host channel-6 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x1E8" size="4" name="OTG_HS_HCINT7" access="Read/Write" description="OTG_HS host channel-7 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x208" size="4" name="OTG_HS_HCINT8" access="Read/Write" description="OTG_HS host channel-8 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x228" size="4" name="OTG_HS_HCINT9" access="Read/Write" description="OTG_HS host channel-9 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x248" size="4" name="OTG_HS_HCINT10" access="Read/Write" description="OTG_HS host channel-10 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x268" size="4" name="OTG_HS_HCINT11" access="Read/Write" description="OTG_HS host channel-11 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed" />
-      <BitField start="1" size="1" name="CHH" description="Channel halted" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALL" description="STALL response received&#xa;              interrupt" />
-      <BitField start="4" size="1" name="NAK" description="NAK response received&#xa;              interrupt" />
-      <BitField start="5" size="1" name="ACK" description="ACK response received/transmitted&#xa;              interrupt" />
-      <BitField start="6" size="1" name="NYET" description="Response received&#xa;              interrupt" />
-      <BitField start="7" size="1" name="TXERR" description="Transaction error" />
-      <BitField start="8" size="1" name="BBERR" description="Babble error" />
-      <BitField start="9" size="1" name="FRMOR" description="Frame overrun" />
-      <BitField start="10" size="1" name="DTERR" description="Data toggle error" />
-    </Register>
-    <Register start="+0x10C" size="4" name="OTG_HS_HCINTMSK0" access="Read/Write" description="OTG_HS host channel-11 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x12C" size="4" name="OTG_HS_HCINTMSK1" access="Read/Write" description="OTG_HS host channel-1 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x14C" size="4" name="OTG_HS_HCINTMSK2" access="Read/Write" description="OTG_HS host channel-2 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x16C" size="4" name="OTG_HS_HCINTMSK3" access="Read/Write" description="OTG_HS host channel-3 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x18C" size="4" name="OTG_HS_HCINTMSK4" access="Read/Write" description="OTG_HS host channel-4 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="OTG_HS_HCINTMSK5" access="Read/Write" description="OTG_HS host channel-5 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x1CC" size="4" name="OTG_HS_HCINTMSK6" access="Read/Write" description="OTG_HS host channel-6 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x1EC" size="4" name="OTG_HS_HCINTMSK7" access="Read/Write" description="OTG_HS host channel-7 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x20C" size="4" name="OTG_HS_HCINTMSK8" access="Read/Write" description="OTG_HS host channel-8 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x22C" size="4" name="OTG_HS_HCINTMSK9" access="Read/Write" description="OTG_HS host channel-9 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x24C" size="4" name="OTG_HS_HCINTMSK10" access="Read/Write" description="OTG_HS host channel-10 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x26C" size="4" name="OTG_HS_HCINTMSK11" access="Read/Write" description="OTG_HS host channel-11 interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed mask" />
-      <BitField start="1" size="1" name="CHHM" description="Channel halted mask" />
-      <BitField start="2" size="1" name="AHBERR" description="AHB error" />
-      <BitField start="3" size="1" name="STALLM" description="STALL response received interrupt&#xa;              mask" />
-      <BitField start="4" size="1" name="NAKM" description="NAK response received interrupt&#xa;              mask" />
-      <BitField start="5" size="1" name="ACKM" description="ACK response received/transmitted&#xa;              interrupt mask" />
-      <BitField start="6" size="1" name="NYET" description="response received interrupt&#xa;              mask" />
-      <BitField start="7" size="1" name="TXERRM" description="Transaction error mask" />
-      <BitField start="8" size="1" name="BBERRM" description="Babble error mask" />
-      <BitField start="9" size="1" name="FRMORM" description="Frame overrun mask" />
-      <BitField start="10" size="1" name="DTERRM" description="Data toggle error mask" />
-    </Register>
-    <Register start="+0x110" size="4" name="OTG_HS_HCTSIZ0" access="Read/Write" description="OTG_HS host channel-11 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x130" size="4" name="OTG_HS_HCTSIZ1" access="Read/Write" description="OTG_HS host channel-1 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x150" size="4" name="OTG_HS_HCTSIZ2" access="Read/Write" description="OTG_HS host channel-2 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x170" size="4" name="OTG_HS_HCTSIZ3" access="Read/Write" description="OTG_HS host channel-3 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x190" size="4" name="OTG_HS_HCTSIZ4" access="Read/Write" description="OTG_HS host channel-4 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="OTG_HS_HCTSIZ5" access="Read/Write" description="OTG_HS host channel-5 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x1D0" size="4" name="OTG_HS_HCTSIZ6" access="Read/Write" description="OTG_HS host channel-6 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x1F0" size="4" name="OTG_HS_HCTSIZ7" access="Read/Write" description="OTG_HS host channel-7 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x210" size="4" name="OTG_HS_HCTSIZ8" access="Read/Write" description="OTG_HS host channel-8 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x230" size="4" name="OTG_HS_HCTSIZ9" access="Read/Write" description="OTG_HS host channel-9 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x250" size="4" name="OTG_HS_HCTSIZ10" access="Read/Write" description="OTG_HS host channel-10 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x270" size="4" name="OTG_HS_HCTSIZ11" access="Read/Write" description="OTG_HS host channel-11 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="DPID" description="Data PID" />
-    </Register>
-    <Register start="+0x114" size="4" name="OTG_HS_HCDMA0" access="Read/Write" description="OTG_HS host channel-0 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x134" size="4" name="OTG_HS_HCDMA1" access="Read/Write" description="OTG_HS host channel-1 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x154" size="4" name="OTG_HS_HCDMA2" access="Read/Write" description="OTG_HS host channel-2 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x174" size="4" name="OTG_HS_HCDMA3" access="Read/Write" description="OTG_HS host channel-3 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x194" size="4" name="OTG_HS_HCDMA4" access="Read/Write" description="OTG_HS host channel-4 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="OTG_HS_HCDMA5" access="Read/Write" description="OTG_HS host channel-5 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x1D4" size="4" name="OTG_HS_HCDMA6" access="Read/Write" description="OTG_HS host channel-6 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x1F4" size="4" name="OTG_HS_HCDMA7" access="Read/Write" description="OTG_HS host channel-7 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x214" size="4" name="OTG_HS_HCDMA8" access="Read/Write" description="OTG_HS host channel-8 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x234" size="4" name="OTG_HS_HCDMA9" access="Read/Write" description="OTG_HS host channel-9 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x254" size="4" name="OTG_HS_HCDMA10" access="Read/Write" description="OTG_HS host channel-10 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x274" size="4" name="OTG_HS_HCDMA11" access="Read/Write" description="OTG_HS host channel-11 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_HS_DEVICE" start="0x40040800" description="USB on the go high speed">
-    <Register start="+0x0" size="4" name="OTG_HS_DCFG" access="Read/Write" description="OTG_HS device configuration&#xa;          register" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="DSPD" description="Device speed" />
-      <BitField start="2" size="1" name="NZLSOHSK" description="Nonzero-length status OUT&#xa;              handshake" />
-      <BitField start="4" size="7" name="DAD" description="Device address" />
-      <BitField start="11" size="2" name="PFIVL" description="Periodic (micro)frame&#xa;              interval" />
-      <BitField start="24" size="2" name="PERSCHIVL" description="Periodic scheduling&#xa;              interval" />
-    </Register>
-    <Register start="+0x4" size="4" name="OTG_HS_DCTL" access="Read/Write" description="OTG_HS device control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RWUSIG" description="Remote wakeup signaling" />
-      <BitField start="1" size="1" name="SDIS" description="Soft disconnect" />
-      <BitField start="2" size="1" name="GINSTS" description="Global IN NAK status" />
-      <BitField start="3" size="1" name="GONSTS" description="Global OUT NAK status" />
-      <BitField start="4" size="3" name="TCTL" description="Test control" />
-      <BitField start="7" size="1" name="SGINAK" description="Set global IN NAK" />
-      <BitField start="8" size="1" name="CGINAK" description="Clear global IN NAK" />
-      <BitField start="9" size="1" name="SGONAK" description="Set global OUT NAK" />
-      <BitField start="10" size="1" name="CGONAK" description="Clear global OUT NAK" />
-      <BitField start="11" size="1" name="POPRGDNE" description="Power-on programming done" />
-    </Register>
-    <Register start="+0x8" size="4" name="OTG_HS_DSTS" access="ReadOnly" description="OTG_HS device status register" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPSTS" description="Suspend status" />
-      <BitField start="1" size="2" name="ENUMSPD" description="Enumerated speed" />
-      <BitField start="3" size="1" name="EERR" description="Erratic error" />
-      <BitField start="8" size="14" name="FNSOF" description="Frame number of the received&#xa;              SOF" />
-    </Register>
-    <Register start="+0x10" size="4" name="OTG_HS_DIEPMSK" access="Read/Write" description="OTG_HS device IN endpoint common interrupt&#xa;          mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed interrupt&#xa;              mask" />
-      <BitField start="1" size="1" name="EPDM" description="Endpoint disabled interrupt&#xa;              mask" />
-      <BitField start="3" size="1" name="TOM" description="Timeout condition mask (nonisochronous&#xa;              endpoints)" />
-      <BitField start="4" size="1" name="ITTXFEMSK" description="IN token received when TxFIFO empty&#xa;              mask" />
-      <BitField start="5" size="1" name="INEPNMM" description="IN token received with EP mismatch&#xa;              mask" />
-      <BitField start="6" size="1" name="INEPNEM" description="IN endpoint NAK effective&#xa;              mask" />
-      <BitField start="8" size="1" name="TXFURM" description="FIFO underrun mask" />
-      <BitField start="9" size="1" name="BIM" description="BNA interrupt mask" />
-    </Register>
-    <Register start="+0x14" size="4" name="OTG_HS_DOEPMSK" access="Read/Write" description="OTG_HS device OUT endpoint common interrupt&#xa;          mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed interrupt&#xa;              mask" />
-      <BitField start="1" size="1" name="EPDM" description="Endpoint disabled interrupt&#xa;              mask" />
-      <BitField start="3" size="1" name="STUPM" description="SETUP phase done mask" />
-      <BitField start="4" size="1" name="OTEPDM" description="OUT token received when endpoint&#xa;              disabled mask" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets received&#xa;              mask" />
-      <BitField start="8" size="1" name="OPEM" description="OUT packet error mask" />
-      <BitField start="9" size="1" name="BOIM" description="BNA interrupt mask" />
-    </Register>
-    <Register start="+0x18" size="4" name="OTG_HS_DAINT" access="ReadOnly" description="OTG_HS device all endpoints interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="IEPINT" description="IN endpoint interrupt bits" />
-      <BitField start="16" size="16" name="OEPINT" description="OUT endpoint interrupt&#xa;              bits" />
-    </Register>
-    <Register start="+0x1C" size="4" name="OTG_HS_DAINTMSK" access="Read/Write" description="OTG_HS all endpoints interrupt mask&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="IEPM" description="IN EP interrupt mask bits" />
-      <BitField start="16" size="16" name="OEPM" description="OUT EP interrupt mask bits" />
-    </Register>
-    <Register start="+0x28" size="4" name="OTG_HS_DVBUSDIS" access="Read/Write" description="OTG_HS device VBUS discharge time&#xa;          register" reset_value="0x000017D7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VBUSDT" description="Device VBUS discharge time" />
-    </Register>
-    <Register start="+0x2C" size="4" name="OTG_HS_DVBUSPULSE" access="Read/Write" description="OTG_HS device VBUS pulsing time&#xa;          register" reset_value="0x000005B8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DVBUSP" description="Device VBUS pulsing time" />
-    </Register>
-    <Register start="+0x30" size="4" name="OTG_HS_DTHRCTL" access="Read/Write" description="OTG_HS Device threshold control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NONISOTHREN" description="Nonisochronous IN endpoints threshold&#xa;              enable" />
-      <BitField start="1" size="1" name="ISOTHREN" description="ISO IN endpoint threshold&#xa;              enable" />
-      <BitField start="2" size="9" name="TXTHRLEN" description="Transmit threshold length" />
-      <BitField start="16" size="1" name="RXTHREN" description="Receive threshold enable" />
-      <BitField start="17" size="9" name="RXTHRLEN" description="Receive threshold length" />
-      <BitField start="27" size="1" name="ARPEN" description="Arbiter parking enable" />
-    </Register>
-    <Register start="+0x34" size="4" name="OTG_HS_DIEPEMPMSK" access="Read/Write" description="OTG_HS device IN endpoint FIFO empty&#xa;          interrupt mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask&#xa;              bits" />
-    </Register>
-    <Register start="+0x38" size="4" name="OTG_HS_DEACHINT" access="Read/Write" description="OTG_HS device each endpoint interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="IEP1INT" description="IN endpoint 1interrupt bit" />
-      <BitField start="17" size="1" name="OEP1INT" description="OUT endpoint 1 interrupt&#xa;              bit" />
-    </Register>
-    <Register start="+0x3C" size="4" name="OTG_HS_DEACHINTMSK" access="Read/Write" description="OTG_HS device each endpoint interrupt&#xa;          register mask" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="IEP1INTM" description="IN Endpoint 1 interrupt mask&#xa;              bit" />
-      <BitField start="17" size="1" name="OEP1INTM" description="OUT Endpoint 1 interrupt mask&#xa;              bit" />
-    </Register>
-    <Register start="+0x40" size="4" name="OTG_HS_DIEPEACHMSK1" access="Read/Write" description="OTG_HS device each in endpoint-1 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed interrupt&#xa;              mask" />
-      <BitField start="1" size="1" name="EPDM" description="Endpoint disabled interrupt&#xa;              mask" />
-      <BitField start="3" size="1" name="TOM" description="Timeout condition mask (nonisochronous&#xa;              endpoints)" />
-      <BitField start="4" size="1" name="ITTXFEMSK" description="IN token received when TxFIFO empty&#xa;              mask" />
-      <BitField start="5" size="1" name="INEPNMM" description="IN token received with EP mismatch&#xa;              mask" />
-      <BitField start="6" size="1" name="INEPNEM" description="IN endpoint NAK effective&#xa;              mask" />
-      <BitField start="8" size="1" name="TXFURM" description="FIFO underrun mask" />
-      <BitField start="9" size="1" name="BIM" description="BNA interrupt mask" />
-      <BitField start="13" size="1" name="NAKM" description="NAK interrupt mask" />
-    </Register>
-    <Register start="+0x80" size="4" name="OTG_HS_DOEPEACHMSK1" access="Read/Write" description="OTG_HS device each OUT endpoint-1 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRCM" description="Transfer completed interrupt&#xa;              mask" />
-      <BitField start="1" size="1" name="EPDM" description="Endpoint disabled interrupt&#xa;              mask" />
-      <BitField start="3" size="1" name="TOM" description="Timeout condition mask" />
-      <BitField start="4" size="1" name="ITTXFEMSK" description="IN token received when TxFIFO empty&#xa;              mask" />
-      <BitField start="5" size="1" name="INEPNMM" description="IN token received with EP mismatch&#xa;              mask" />
-      <BitField start="6" size="1" name="INEPNEM" description="IN endpoint NAK effective&#xa;              mask" />
-      <BitField start="8" size="1" name="TXFURM" description="OUT packet error mask" />
-      <BitField start="9" size="1" name="BIM" description="BNA interrupt mask" />
-      <BitField start="12" size="1" name="BERRM" description="Bubble error interrupt&#xa;              mask" />
-      <BitField start="13" size="1" name="NAKM" description="NAK interrupt mask" />
-      <BitField start="14" size="1" name="NYETM" description="NYET interrupt mask" />
-    </Register>
-    <Register start="+0x100" size="4" name="OTG_HS_DIEPCTL0" access="Read/Write" description="OTG device endpoint-0 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x120" size="4" name="OTG_HS_DIEPCTL1" access="Read/Write" description="OTG device endpoint-1 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x140" size="4" name="OTG_HS_DIEPCTL2" access="Read/Write" description="OTG device endpoint-2 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x160" size="4" name="OTG_HS_DIEPCTL3" access="Read/Write" description="OTG device endpoint-3 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x180" size="4" name="OTG_HS_DIEPCTL4" access="Read/Write" description="OTG device endpoint-4 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x1A0" size="4" name="OTG_HS_DIEPCTL5" access="Read/Write" description="OTG device endpoint-5 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="OTG_HS_DIEPCTL6" access="Read/Write" description="OTG device endpoint-6 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x1E0" size="4" name="OTG_HS_DIEPCTL7" access="Read/Write" description="OTG device endpoint-7 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even/odd frame" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="22" size="4" name="TXFNUM" description="TxFIFO number" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x108" size="4" name="OTG_HS_DIEPINT0" access="Read/Write" description="OTG device endpoint-0 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x128" size="4" name="OTG_HS_DIEPINT1" access="Read/Write" description="OTG device endpoint-1 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x148" size="4" name="OTG_HS_DIEPINT2" access="Read/Write" description="OTG device endpoint-2 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x168" size="4" name="OTG_HS_DIEPINT3" access="Read/Write" description="OTG device endpoint-3 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x188" size="4" name="OTG_HS_DIEPINT4" access="Read/Write" description="OTG device endpoint-4 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="OTG_HS_DIEPINT5" access="Read/Write" description="OTG device endpoint-5 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x1C8" size="4" name="OTG_HS_DIEPINT6" access="Read/Write" description="OTG device endpoint-6 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x1E8" size="4" name="OTG_HS_DIEPINT7" access="Read/Write" description="OTG device endpoint-7 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="TOC" description="Timeout condition" />
-      <BitField start="4" size="1" name="ITTXFE" description="IN token received when TxFIFO is&#xa;              empty" />
-      <BitField start="6" size="1" name="INEPNE" description="IN endpoint NAK effective" />
-      <BitField start="7" size="1" name="TXFE" description="Transmit FIFO empty" />
-      <BitField start="8" size="1" name="TXFIFOUDRN" description="Transmit Fifo Underrun" />
-      <BitField start="9" size="1" name="BNA" description="Buffer not available&#xa;              interrupt" />
-      <BitField start="11" size="1" name="PKTDRPSTS" description="Packet dropped status" />
-      <BitField start="12" size="1" name="BERR" description="Babble error interrupt" />
-      <BitField start="13" size="1" name="NAK" description="NAK interrupt" />
-    </Register>
-    <Register start="+0x110" size="4" name="OTG_HS_DIEPTSIZ0" access="Read/Write" description="OTG_HS device IN endpoint 0 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="2" name="PKTCNT" description="Packet count" />
-    </Register>
-    <Register start="+0x114" size="4" name="OTG_HS_DIEPDMA1" access="Read/Write" description="OTG_HS device endpoint-1 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x134" size="4" name="OTG_HS_DIEPDMA2" access="Read/Write" description="OTG_HS device endpoint-2 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x154" size="4" name="OTG_HS_DIEPDMA3" access="Read/Write" description="OTG_HS device endpoint-3 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x174" size="4" name="OTG_HS_DIEPDMA4" access="Read/Write" description="OTG_HS device endpoint-4 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x194" size="4" name="OTG_HS_DIEPDMA5" access="Read/Write" description="OTG_HS device endpoint-5 DMA address&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DMAADDR" description="DMA address" />
-    </Register>
-    <Register start="+0x118" size="4" name="OTG_HS_DTXFSTS0" access="ReadOnly" description="OTG_HS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              avail" />
-    </Register>
-    <Register start="+0x138" size="4" name="OTG_HS_DTXFSTS1" access="ReadOnly" description="OTG_HS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              avail" />
-    </Register>
-    <Register start="+0x158" size="4" name="OTG_HS_DTXFSTS2" access="ReadOnly" description="OTG_HS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              avail" />
-    </Register>
-    <Register start="+0x178" size="4" name="OTG_HS_DTXFSTS3" access="ReadOnly" description="OTG_HS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              avail" />
-    </Register>
-    <Register start="+0x198" size="4" name="OTG_HS_DTXFSTS4" access="ReadOnly" description="OTG_HS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              avail" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="OTG_HS_DTXFSTS5" access="ReadOnly" description="OTG_HS device IN endpoint transmit FIFO&#xa;          status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INEPTFSAV" description="IN endpoint TxFIFO space&#xa;              avail" />
-    </Register>
-    <Register start="+0x130" size="4" name="OTG_HS_DIEPTSIZ1" access="Read/Write" description="OTG_HS device endpoint transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-    </Register>
-    <Register start="+0x150" size="4" name="OTG_HS_DIEPTSIZ2" access="Read/Write" description="OTG_HS device endpoint transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-    </Register>
-    <Register start="+0x170" size="4" name="OTG_HS_DIEPTSIZ3" access="Read/Write" description="OTG_HS device endpoint transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-    </Register>
-    <Register start="+0x190" size="4" name="OTG_HS_DIEPTSIZ4" access="Read/Write" description="OTG_HS device endpoint transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="OTG_HS_DIEPTSIZ5" access="Read/Write" description="OTG_HS device endpoint transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="MCNT" description="Multi count" />
-    </Register>
-    <Register start="+0x300" size="4" name="OTG_HS_DOEPCTL0" access="Read/Write" description="OTG_HS device control OUT endpoint 0 control&#xa;          register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="1" name="SNPM" description="Snoop mode" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x320" size="4" name="OTG_HS_DOEPCTL1" access="Read/Write" description="OTG device endpoint-1 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even odd frame/Endpoint data&#xa;              PID" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="1" name="SNPM" description="Snoop mode" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even&#xa;              frame" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x340" size="4" name="OTG_HS_DOEPCTL2" access="Read/Write" description="OTG device endpoint-2 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even odd frame/Endpoint data&#xa;              PID" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="1" name="SNPM" description="Snoop mode" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even&#xa;              frame" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x360" size="4" name="OTG_HS_DOEPCTL3" access="Read/Write" description="OTG device endpoint-3 control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="MPSIZ" description="Maximum packet size" />
-      <BitField start="15" size="1" name="USBAEP" description="USB active endpoint" />
-      <BitField start="16" size="1" name="EONUM_DPID" description="Even odd frame/Endpoint data&#xa;              PID" />
-      <BitField start="17" size="1" name="NAKSTS" description="NAK status" />
-      <BitField start="18" size="2" name="EPTYP" description="Endpoint type" />
-      <BitField start="20" size="1" name="SNPM" description="Snoop mode" />
-      <BitField start="21" size="1" name="Stall" description="STALL handshake" />
-      <BitField start="26" size="1" name="CNAK" description="Clear NAK" />
-      <BitField start="27" size="1" name="SNAK" description="Set NAK" />
-      <BitField start="28" size="1" name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even&#xa;              frame" />
-      <BitField start="29" size="1" name="SODDFRM" description="Set odd frame" />
-      <BitField start="30" size="1" name="EPDIS" description="Endpoint disable" />
-      <BitField start="31" size="1" name="EPENA" description="Endpoint enable" />
-    </Register>
-    <Register start="+0x308" size="4" name="OTG_HS_DOEPINT0" access="Read/Write" description="OTG_HS device endpoint-0 interrupt&#xa;          register" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x328" size="4" name="OTG_HS_DOEPINT1" access="Read/Write" description="OTG_HS device endpoint-1 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x348" size="4" name="OTG_HS_DOEPINT2" access="Read/Write" description="OTG_HS device endpoint-2 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x368" size="4" name="OTG_HS_DOEPINT3" access="Read/Write" description="OTG_HS device endpoint-3 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x388" size="4" name="OTG_HS_DOEPINT4" access="Read/Write" description="OTG_HS device endpoint-4 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x3A8" size="4" name="OTG_HS_DOEPINT5" access="Read/Write" description="OTG_HS device endpoint-5 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x3C8" size="4" name="OTG_HS_DOEPINT6" access="Read/Write" description="OTG_HS device endpoint-6 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x3E8" size="4" name="OTG_HS_DOEPINT7" access="Read/Write" description="OTG_HS device endpoint-7 interrupt&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XFRC" description="Transfer completed&#xa;              interrupt" />
-      <BitField start="1" size="1" name="EPDISD" description="Endpoint disabled&#xa;              interrupt" />
-      <BitField start="3" size="1" name="STUP" description="SETUP phase done" />
-      <BitField start="4" size="1" name="OTEPDIS" description="OUT token received when endpoint&#xa;              disabled" />
-      <BitField start="6" size="1" name="B2BSTUP" description="Back-to-back SETUP packets&#xa;              received" />
-      <BitField start="14" size="1" name="NYET" description="NYET interrupt" />
-    </Register>
-    <Register start="+0x310" size="4" name="OTG_HS_DOEPTSIZ0" access="Read/Write" description="OTG_HS device endpoint-1 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="1" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="STUPCNT" description="SETUP packet count" />
-    </Register>
-    <Register start="+0x330" size="4" name="OTG_HS_DOEPTSIZ1" access="Read/Write" description="OTG_HS device endpoint-2 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-    </Register>
-    <Register start="+0x350" size="4" name="OTG_HS_DOEPTSIZ2" access="Read/Write" description="OTG_HS device endpoint-3 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-    </Register>
-    <Register start="+0x370" size="4" name="OTG_HS_DOEPTSIZ3" access="Read/Write" description="OTG_HS device endpoint-4 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-    </Register>
-    <Register start="+0x390" size="4" name="OTG_HS_DOEPTSIZ4" access="Read/Write" description="OTG_HS device endpoint-5 transfer size&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="19" name="XFRSIZ" description="Transfer size" />
-      <BitField start="19" size="10" name="PKTCNT" description="Packet count" />
-      <BitField start="29" size="2" name="RXDPID_STUPCNT" description="Received data PID/SETUP packet&#xa;              count" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OTG_HS_PWRCLK" start="0x40040E00" description="USB on the go high speed">
-    <Register start="+0x0" size="4" name="OTG_HS_PCGCR" access="Read/Write" description="Power and clock gating control&#xa;          register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STPPCLK" description="Stop PHY clock" />
-      <BitField start="1" size="1" name="GATEHCLK" description="Gate HCLK" />
-      <BitField start="4" size="1" name="PHYSUSP" description="PHY suspended" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E000" description="Nested Vectored Interrupt&#xa;      Controller">
-    <Register start="+0x4" size="0" name="ICTR" access="ReadOnly" description="Interrupt Controller Type&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="INTLINESNUM" description="Total number of interrupt lines in&#xa;              groups" />
-    </Register>
-    <Register start="+0xF00" size="0" name="STIR" access="WriteOnly" description="Software Triggered Interrupt&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="INTID" description="interrupt to be triggered" />
-    </Register>
-    <Register start="+0x100" size="0" name="ISER0" access="Read/Write" description="Interrupt Set-Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SETENA" description="SETENA" />
-    </Register>
-    <Register start="+0x104" size="0" name="ISER1" access="Read/Write" description="Interrupt Set-Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SETENA" description="SETENA" />
-    </Register>
-    <Register start="+0x108" size="0" name="ISER2" access="Read/Write" description="Interrupt Set-Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SETENA" description="SETENA" />
-    </Register>
-    <Register start="+0x180" size="0" name="ICER0" access="Read/Write" description="Interrupt Clear-Enable&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLRENA" description="CLRENA" />
-    </Register>
-    <Register start="+0x184" size="0" name="ICER1" access="Read/Write" description="Interrupt Clear-Enable&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLRENA" description="CLRENA" />
-    </Register>
-    <Register start="+0x188" size="0" name="ICER2" access="Read/Write" description="Interrupt Clear-Enable&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLRENA" description="CLRENA" />
-    </Register>
-    <Register start="+0x200" size="0" name="ISPR0" access="Read/Write" description="Interrupt Set-Pending Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SETPEND" description="SETPEND" />
-    </Register>
-    <Register start="+0x204" size="0" name="ISPR1" access="Read/Write" description="Interrupt Set-Pending Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SETPEND" description="SETPEND" />
-    </Register>
-    <Register start="+0x208" size="0" name="ISPR2" access="Read/Write" description="Interrupt Set-Pending Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SETPEND" description="SETPEND" />
-    </Register>
-    <Register start="+0x280" size="0" name="ICPR0" access="Read/Write" description="Interrupt Clear-Pending&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLRPEND" description="CLRPEND" />
-    </Register>
-    <Register start="+0x284" size="0" name="ICPR1" access="Read/Write" description="Interrupt Clear-Pending&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLRPEND" description="CLRPEND" />
-    </Register>
-    <Register start="+0x288" size="0" name="ICPR2" access="Read/Write" description="Interrupt Clear-Pending&#xa;          Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLRPEND" description="CLRPEND" />
-    </Register>
-    <Register start="+0x300" size="0" name="IABR0" access="ReadOnly" description="Interrupt Active Bit Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACTIVE" description="ACTIVE" />
-    </Register>
-    <Register start="+0x304" size="0" name="IABR1" access="ReadOnly" description="Interrupt Active Bit Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACTIVE" description="ACTIVE" />
-    </Register>
-    <Register start="+0x308" size="0" name="IABR2" access="ReadOnly" description="Interrupt Active Bit Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACTIVE" description="ACTIVE" />
-    </Register>
-    <Register start="+0x400" size="0" name="IPR0" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x404" size="0" name="IPR1" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x408" size="0" name="IPR2" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x40C" size="0" name="IPR3" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x410" size="0" name="IPR4" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x414" size="0" name="IPR5" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x418" size="0" name="IPR6" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x41C" size="0" name="IPR7" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x420" size="0" name="IPR8" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x424" size="0" name="IPR9" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x428" size="0" name="IPR10" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x42C" size="0" name="IPR11" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x430" size="0" name="IPR12" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x434" size="0" name="IPR13" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x438" size="0" name="IPR14" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x43C" size="0" name="IPR15" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x440" size="0" name="IPR16" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x444" size="0" name="IPR17" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x448" size="0" name="IPR18" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-    <Register start="+0x44C" size="0" name="IPR19" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="IPR_N0" description="IPR_N0" />
-      <BitField start="8" size="8" name="IPR_N1" description="IPR_N1" />
-      <BitField start="16" size="8" name="IPR_N2" description="IPR_N2" />
-      <BitField start="24" size="8" name="IPR_N3" description="IPR_N3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FPU" description="Floating Point Unit">
-    <Register name="CPACR" start="0xE000ED88" description="Coprocessor Access Control Register">
-      <BitField name="CP11" start="22" size="2" description="Access privileges for coprocessor 11" />
-      <BitField name="CP10" start="20" size="2" description="Access privileges for coprocessor 10" />
-    </Register>
-    <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register">
-      <BitField name="ASPEN" start="31" size="1" description="Automatic State Preservation" />
-      <BitField name="LSPEN" start="30" size="1" description="Lazy State Preservation Enabled" />
-      <BitField name="MONRDY" start="8" size="1" description="Monitor Ready" />
-      <BitField name="BFRDY" start="6" size="1" description="BusFault Ready" />
-      <BitField name="MMRDY" start="5" size="1" description="MemManage Ready" />
-      <BitField name="HFRDY" start="4" size="1" description="HardFault Ready" />
-      <BitField name="THREAD" start="3" size="1" description="Thread Mode Allocated Stack Frame" />
-      <BitField name="USER" start="1" size="1" description="User Allocated Stack Frame" />
-      <BitField name="LSPACT" start="0" size="1" description="Lazy State Preservation Active" />
-    </Register>
-    <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register">
-      <BitField name="ADDRESSS" start="3" size="29" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" />
-    </Register>
-    <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Status Control Register">
-      <BitField name="N" start="31" size="1" description="Negative condition code flag" />
-      <BitField name="Z" start="30" size="1" description="Zero condition code flag" />
-      <BitField name="C" start="29" size="1" description="Carry condition code flag" />
-      <BitField name="V" start="28" size="1" description="Overflow condition code flag" />
-      <BitField name="AHP" start="26" size="1" description="Alternative half-precision control bit" />
-      <BitField name="DN" start="25" size="1" description="Default NaN mode control bit" />
-      <BitField name="FZ" start="24" size="1" description="Flush-to-zero mode control bit" />
-      <BitField name="RMode" start="22" size="2" description="Rounding Mode control field" />
-      <BitField name="IDC" start="7" size="1" description="Input Denormal cumulative exception bit" />
-      <BitField name="IXC" start="4" size="1" description="Inexact cumulative exception bit" />
-      <BitField name="UFC" start="3" size="1" description="Underflow cumulative exception bit" />
-      <BitField name="OFC" start="2" size="1" description="Overflow cumulative exception bit" />
-      <BitField name="DZC" start="1" size="1" description="Division by Zero cumulative exception bit" />
-      <BitField name="IOC" start="0" size="1" description="Invalid Operation cumulative exception bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc/ses/stm32f4/STM32F40x_Vectors.s b/examples/device/cdc_msc/ses/stm32f4/STM32F40x_Vectors.s
deleted file mode 100644
index e9e0392b..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/STM32F40x_Vectors.s
+++ /dev/null
@@ -1,817 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Dummy_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Dummy_Handler
-
-  .weak TAMP_STAMP_IRQHandler
-  .thumb_set TAMP_STAMP_IRQHandler,Dummy_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Dummy_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Dummy_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Dummy_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Dummy_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Dummy_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Dummy_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream0_IRQHandler
-  .thumb_set DMA1_Stream0_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream1_IRQHandler
-  .thumb_set DMA1_Stream1_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream2_IRQHandler
-  .thumb_set DMA1_Stream2_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream3_IRQHandler
-  .thumb_set DMA1_Stream3_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream4_IRQHandler
-  .thumb_set DMA1_Stream4_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream5_IRQHandler
-  .thumb_set DMA1_Stream5_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream6_IRQHandler
-  .thumb_set DMA1_Stream6_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Dummy_Handler
-
-  .weak CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Dummy_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Dummy_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Dummy_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Dummy_Handler
-
-  .weak TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Dummy_Handler
-
-  .weak TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Dummy_Handler
-
-  .weak TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Dummy_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Dummy_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Dummy_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Dummy_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Dummy_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Dummy_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Dummy_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Dummy_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Dummy_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Dummy_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Dummy_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Dummy_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Dummy_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Dummy_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Dummy_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Dummy_Handler
-
-  .weak OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Dummy_Handler
-
-  .weak TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Dummy_Handler
-
-  .weak TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Dummy_Handler
-
-  .weak TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Dummy_Handler
-
-  .weak TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Dummy_Handler
-
-  .weak DMA1_Stream7_IRQHandler
-  .thumb_set DMA1_Stream7_IRQHandler,Dummy_Handler
-
-  .weak FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Dummy_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Dummy_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Dummy_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Dummy_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Dummy_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Dummy_Handler
-
-  .weak TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Dummy_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream0_IRQHandler
-  .thumb_set DMA2_Stream0_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream1_IRQHandler
-  .thumb_set DMA2_Stream1_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream2_IRQHandler
-  .thumb_set DMA2_Stream2_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream3_IRQHandler
-  .thumb_set DMA2_Stream3_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream4_IRQHandler
-  .thumb_set DMA2_Stream4_IRQHandler,Dummy_Handler
-
-  .weak ETH_IRQHandler
-  .thumb_set ETH_IRQHandler,Dummy_Handler
-
-  .weak ETH_WKUP_IRQHandler
-  .thumb_set ETH_WKUP_IRQHandler,Dummy_Handler
-
-  .weak CAN2_TX_IRQHandler
-  .thumb_set CAN2_TX_IRQHandler,Dummy_Handler
-
-  .weak CAN2_RX0_IRQHandler
-  .thumb_set CAN2_RX0_IRQHandler,Dummy_Handler
-
-  .weak CAN2_RX1_IRQHandler
-  .thumb_set CAN2_RX1_IRQHandler,Dummy_Handler
-
-  .weak CAN2_SCE_IRQHandler
-  .thumb_set CAN2_SCE_IRQHandler,Dummy_Handler
-
-  .weak OTG_FS_IRQHandler
-  .thumb_set OTG_FS_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream5_IRQHandler
-  .thumb_set DMA2_Stream5_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream6_IRQHandler
-  .thumb_set DMA2_Stream6_IRQHandler,Dummy_Handler
-
-  .weak DMA2_Stream7_IRQHandler
-  .thumb_set DMA2_Stream7_IRQHandler,Dummy_Handler
-
-  .weak USART6_IRQHandler
-  .thumb_set USART6_IRQHandler,Dummy_Handler
-
-  .weak I2C3_EV_IRQHandler
-  .thumb_set I2C3_EV_IRQHandler,Dummy_Handler
-
-  .weak I2C3_ER_IRQHandler
-  .thumb_set I2C3_ER_IRQHandler,Dummy_Handler
-
-  .weak OTG_HS_EP1_OUT_IRQHandler
-  .thumb_set OTG_HS_EP1_OUT_IRQHandler,Dummy_Handler
-
-  .weak OTG_HS_EP1_IN_IRQHandler
-  .thumb_set OTG_HS_EP1_IN_IRQHandler,Dummy_Handler
-
-  .weak OTG_HS_WKUP_IRQHandler
-  .thumb_set OTG_HS_WKUP_IRQHandler,Dummy_Handler
-
-  .weak OTG_HS_IRQHandler
-  .thumb_set OTG_HS_IRQHandler,Dummy_Handler
-
-  .weak DCMI_IRQHandler
-  .thumb_set DCMI_IRQHandler,Dummy_Handler
-
-  .weak FPU_IRQHandler
-  .thumb_set FPU_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak WWDG_IRQHandler
-WWDG_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PVD_IRQHandler
-PVD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TAMP_STAMP_IRQHandler
-TAMP_STAMP_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_WKUP_IRQHandler
-RTC_WKUP_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RCC_IRQHandler
-RCC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI0_IRQHandler
-EXTI0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI1_IRQHandler
-EXTI1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI2_IRQHandler
-EXTI2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI3_IRQHandler
-EXTI3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI4_IRQHandler
-EXTI4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream0_IRQHandler
-DMA1_Stream0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream1_IRQHandler
-DMA1_Stream1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream2_IRQHandler
-DMA1_Stream2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream3_IRQHandler
-DMA1_Stream3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream4_IRQHandler
-DMA1_Stream4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream5_IRQHandler
-DMA1_Stream5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream6_IRQHandler
-DMA1_Stream6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN1_TX_IRQHandler
-CAN1_TX_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN1_RX0_IRQHandler
-CAN1_RX0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN1_RX1_IRQHandler
-CAN1_RX1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN1_SCE_IRQHandler
-CAN1_SCE_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI9_5_IRQHandler
-EXTI9_5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM1_BRK_TIM9_IRQHandler
-TIM1_BRK_TIM9_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM1_UP_TIM10_IRQHandler
-TIM1_UP_TIM10_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM1_CC_IRQHandler
-TIM1_CC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM2_IRQHandler
-TIM2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM3_IRQHandler
-TIM3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM4_IRQHandler
-TIM4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_EV_IRQHandler
-I2C1_EV_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_ER_IRQHandler
-I2C1_ER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_EV_IRQHandler
-I2C2_EV_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_ER_IRQHandler
-I2C2_ER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI1_IRQHandler
-SPI1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI2_IRQHandler
-SPI2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART1_IRQHandler
-USART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_IRQHandler
-USART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART3_IRQHandler
-USART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EXTI15_10_IRQHandler
-EXTI15_10_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_Alarm_IRQHandler
-RTC_Alarm_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak OTG_FS_WKUP_IRQHandler
-OTG_FS_WKUP_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM8_BRK_TIM12_IRQHandler
-TIM8_BRK_TIM12_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM8_UP_TIM13_IRQHandler
-TIM8_UP_TIM13_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM8_CC_IRQHandler
-TIM8_CC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA1_Stream7_IRQHandler
-DMA1_Stream7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FSMC_IRQHandler
-FSMC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDIO_IRQHandler
-SDIO_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM5_IRQHandler
-TIM5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI3_IRQHandler
-SPI3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART4_IRQHandler
-UART4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART5_IRQHandler
-UART5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM6_DAC_IRQHandler
-TIM6_DAC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIM7_IRQHandler
-TIM7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream0_IRQHandler
-DMA2_Stream0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream1_IRQHandler
-DMA2_Stream1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream2_IRQHandler
-DMA2_Stream2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream3_IRQHandler
-DMA2_Stream3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream4_IRQHandler
-DMA2_Stream4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETH_IRQHandler
-ETH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETH_WKUP_IRQHandler
-ETH_WKUP_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN2_TX_IRQHandler
-CAN2_TX_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN2_RX0_IRQHandler
-CAN2_RX0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN2_RX1_IRQHandler
-CAN2_RX1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN2_SCE_IRQHandler
-CAN2_SCE_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak OTG_FS_IRQHandler
-OTG_FS_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream5_IRQHandler
-DMA2_Stream5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream6_IRQHandler
-DMA2_Stream6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA2_Stream7_IRQHandler
-DMA2_Stream7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART6_IRQHandler
-USART6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C3_EV_IRQHandler
-I2C3_EV_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C3_ER_IRQHandler
-I2C3_ER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak OTG_HS_EP1_IN_IRQHandler
-OTG_HS_EP1_IN_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak OTG_HS_WKUP_IRQHandler
-OTG_HS_WKUP_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak OTG_HS_IRQHandler
-OTG_HS_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DCMI_IRQHandler
-DCMI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FPU_IRQHandler
-FPU_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMP_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Stream0_IRQHandler
-  .word DMA1_Stream1_IRQHandler
-  .word DMA1_Stream2_IRQHandler
-  .word DMA1_Stream3_IRQHandler
-  .word DMA1_Stream4_IRQHandler
-  .word DMA1_Stream5_IRQHandler
-  .word DMA1_Stream6_IRQHandler
-  .word ADC_IRQHandler
-  .word CAN1_TX_IRQHandler
-  .word CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_TIM9_IRQHandler
-  .word TIM1_UP_TIM10_IRQHandler
-  .word TIM1_TRG_COM_TIM11_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word OTG_FS_WKUP_IRQHandler
-  .word TIM8_BRK_TIM12_IRQHandler
-  .word TIM8_UP_TIM13_IRQHandler
-  .word TIM8_TRG_COM_TIM14_IRQHandler
-  .word TIM8_CC_IRQHandler
-  .word DMA1_Stream7_IRQHandler
-  .word FSMC_IRQHandler
-  .word SDIO_IRQHandler
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_DAC_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Stream0_IRQHandler
-  .word DMA2_Stream1_IRQHandler
-  .word DMA2_Stream2_IRQHandler
-  .word DMA2_Stream3_IRQHandler
-  .word DMA2_Stream4_IRQHandler
-  .word ETH_IRQHandler
-  .word ETH_WKUP_IRQHandler
-  .word CAN2_TX_IRQHandler
-  .word CAN2_RX0_IRQHandler
-  .word CAN2_RX1_IRQHandler
-  .word CAN2_SCE_IRQHandler
-  .word OTG_FS_IRQHandler
-  .word DMA2_Stream5_IRQHandler
-  .word DMA2_Stream6_IRQHandler
-  .word DMA2_Stream7_IRQHandler
-  .word USART6_IRQHandler
-  .word I2C3_EV_IRQHandler
-  .word I2C3_ER_IRQHandler
-  .word OTG_HS_EP1_OUT_IRQHandler
-  .word OTG_HS_EP1_IN_IRQHandler
-  .word OTG_HS_WKUP_IRQHandler
-  .word OTG_HS_IRQHandler
-  .word DCMI_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word FPU_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Startup.s b/examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Startup.s
deleted file mode 100644
index 42415cbb..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Startup.s
+++ /dev/null
@@ -1,125 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Target.js b/examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/STM32F4xx_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc/ses/stm32f4/flash_placement.xml b/examples/device/cdc_msc/ses/stm32f4/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc/ses/stm32f4/stm32f4.emProject b/examples/device/cdc_msc/ses/stm32f4/stm32f4.emProject
deleted file mode 100644
index 23b31347..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/stm32f4.emProject
+++ /dev/null
@@ -1,87 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="stm32f4" target="8" version="2">
-  <project Name="stm32f4">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="STM32F407VG"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="256"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="ROM;0x08000000;0x00100000;RAM;0x10000000;0x00010000;RAM;0x20000000;0x00020000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="STM32F407VG"
-      arm_target_interface_type="SWD"
-      c_preprocessor_definitions="STM32F407xx;__STM32F4xx_FAMILY;__STM32F407_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_STM32F4;HSE_VALUE=8000000"
-      c_user_include_directories="../../src;$(rootDir)/src;$(rootDir)/hw;$(rootDir)/hw/mcu/st/cmsis;$(rootDir)/hw/mcu/st/stm32lib/CMSIS/STM32F4xx/Include"
-      debug_register_definition_file="$(ProjectDir)/STM32F40x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/STM32F407VG_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceHeaderFile=$(PackagesDir)/STM32F4xx/CMSIS/Device/Include/stm32f4xx.h;DeviceLibraryIdentifier=M4lf;DeviceSystemFile=$(PackagesDir)/STM32F4xx/CMSIS/Device/Source/system_stm32f4xx.c;DeviceVectorsFile=$(PackagesDir)/STM32F4xx/Source/STM32F40x_Vectors.s;DeviceFamily=STM32F4xx;DeviceSubFamily=STM32F407;Target=STM32F407VG;Placement=Flash;rootDir=../../../../.."
-      package_dependencies="STM32F4xx"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="STM32F4xx_Startup.s" />
-      <file file_name="STM32F40x_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="STM32F4xx_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-    </folder>
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <folder Name="stm32f407disco">
-          <file file_name="../../../../../hw/bsp/stm32f407disco/stm32f407disco.c" />
-        </folder>
-        <file file_name="../../../../../hw/bsp/board.h" />
-      </folder>
-      <folder Name="mcu">
-        <folder Name="st">
-          <folder Name="system-init">
-            <file file_name="../../../../../hw/mcu/st/system-init/system_stm32f4xx.c" />
-          </folder>
-          <folder Name="stm32lib" />
-        </folder>
-      </folder>
-    </folder>
-    <configuration
-      Name="stm32f407disco"
-      c_preprocessor_definitions="BOARD_STM32F407G_DISC1" />
-  </project>
-  <configuration
-    Name="stm32f407disco"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/device/cdc_msc/ses/stm32f4/thumb_crt0.s b/examples/device/cdc_msc/ses/stm32f4/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc/ses/stm32f4/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc_freertos/ses/cdc_msc_hid_freertos.emProject b/examples/device/cdc_msc_freertos/ses/cdc_msc_hid_freertos.emProject
deleted file mode 100644
index acd8e98c..00000000
--- a/examples/device/cdc_msc_freertos/ses/cdc_msc_hid_freertos.emProject
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="cdc_msc_hid_freertos" target="8" version="2">
-  <import file_name="nrf5x/nrf5x.emProject" />
-  <import file_name="samd21/samd21.emProject" />
-  <import file_name="samd51/samd51.emProject" />
-  <import file_name="lpc175x_6x/lpc175x_6x.emProject" />
-</solution>
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/FreeRTOSConfig.h
deleted file mode 100644
index 5d3ba479..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/FreeRTOSConfig.h
+++ /dev/null
@@ -1,134 +0,0 @@
-#ifndef __FREERTOS_CONFIG__H
-#define __FREERTOS_CONFIG__H
-
-//--------------------------------------------------------------------+
-// See http://www.freertos.org/a00110.html.
-//--------------------------------------------------------------------+
-#include "chip.h"
-
-#define configCPU_CLOCK_HZ                   SystemCoreClock
-
-#if 0
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX
-  // TODO remove
-  #include "lpc43xx_cgu.h"
-  #define configCPU_CLOCK_HZ                   CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE)
-#endif
-#endif
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    (8)
-#define configMINIMAL_STACK_SIZE                (128 )
-#define configTOTAL_HEAP_SIZE                   ( ( size_t ) ( 16*1024 ) )
-#define configMAX_TASK_NAME_LEN                 32
-#define configUSE_16_BIT_TICKS      		        0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             0
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               10 // used to name queue/semaphore with debugger
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        1
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           1
-#define configCHECK_FOR_STACK_OVERFLOW         2
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              ( configMAX_PRIORITIES - 3 )
-#define configTIMER_QUEUE_LENGTH               10
-#define configTIMER_TASK_STACK_DEPTH	         configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      0
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* Define to trap errors during development. */
-
-// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
-
-static inline void configASSERT_breakpoint(void)
-{
-  // Cortex M CoreDebug->DHCSR
-  volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL);
-
-  // Only halt mcu if debugger is attached
-  if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n");
-}
-
-#else
-#define configASSERT_breakpoint()
-#endif
-
-
-#define configASSERT( x )                      if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); configASSERT_breakpoint(); }
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behaviour configuration.
-//--------------------------------------------------------------------+
-/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in mcu_variant.h */
-#ifdef __NVIC_PRIO_BITS
-	#define configPRIO_BITS       __NVIC_PRIO_BITS
-#else
-  #error "This port requires __NVIC_PRIO_BITS to be defined"
-#endif
-
-
-/* The lowest interrupt priority that can be used in a call to a "set priority"
-function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  0x1f
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif /* __FREERTOS_CONFIG__H */
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1700_Startup.s b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1700_Startup.s
deleted file mode 100644
index f039ad93..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1700_Startup.s
+++ /dev/null
@@ -1,109 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1700_Target.js b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1700_Target.js
deleted file mode 100644
index 7f945a3d..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1700_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1769_MemoryMap.xml b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1769_MemoryMap.xml
deleted file mode 100644
index d9c07aea..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC1769_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC1769">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x2007C000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC176x5x_Registers.xml b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC176x5x_Registers.xml
deleted file mode 100644
index fd38966b..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC176x5x_Registers.xml
+++ /dev/null
@@ -1,11058 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC176x5x" description="LPC176x/LPC175x M3">
-  <RegisterGroup name="WDT" start="0x40000000" description="Watchdog Timer (WDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="STOP" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
-        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, cleared by software." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag.  Cleared by software." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="Count" description="Watchdog time-out interval." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="Count" description="Counter timer value." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLKSEL" description="Selects source of WDT clock">
-        <Enum name="IRC" start="0x0" description="IRC" />
-        <Enum name="PCLK" start="0x1" description="Peripheral clock" />
-        <Enum name="RTCOSC" start="0x2" description="RTC oscillator" />
-      </BitField>
-      <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.">
-        <Enum name="UNLOCKED" start="0" description="This bit is set to 0 on any reset. It cannot be cleared by software." />
-        <Enum name="LOCKED" start="1" description="Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;cannot be modified." />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40004000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40008000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40010000" description="UART1  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
-        <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
-        <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="MODEM" start="0x0" description="4   - Modem Interrupt." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="VALID" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM1) ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI" start="0x40020000" description="SPI ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
-        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
-      </BitField>
-      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
-        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
-        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
-      </BitField>
-      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
-        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
-        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
-      </BitField>
-      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
-        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
-        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
-      </BitField>
-      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
-        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
-        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
-      </BitField>
-      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
-        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
-        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
-      </BitField>
-      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
-        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
-        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
-        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
-        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
-        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
-        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
-        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
-        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
-        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
-      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC)  ">
-    <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
-        <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-        <Enum name="NO_EFFECT_" start="0" description="No effect." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
-        <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-      </BitField>
-    </Register>
-    <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
-    <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0INT" description="Port 0 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="P2INT" description="Port 2 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PINCONNECT" start="0x4002C000" description="Pin connect block">
-    <Register start="+0x000" size="4" name="PINSEL0" access="Read/Write" description="Pin function select register 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_0" description="Pin function select P0.0.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.0" />
-        <Enum name="RD1" start="0x1" description="RD1" />
-        <Enum name="TXD3" start="0x2" description="TXD3" />
-        <Enum name="SDA1" start="0x3" description="SDA1" />
-      </BitField>
-      <BitField start="2" size="2" name="P0_1" description="Pin function select P0.1.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.1" />
-        <Enum name="TD1" start="0x1" description="TD1" />
-        <Enum name="RXD3" start="0x2" description="RXD3" />
-        <Enum name="SCL1" start="0x3" description="SCL1" />
-      </BitField>
-      <BitField start="4" size="2" name="P0_2" description="Pin function select P0.2.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.2" />
-        <Enum name="TXD0" start="0x1" description="TXD0" />
-        <Enum name="AD0" start="0x2" description="AD0.7" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="P0_3" description="Pin function select P0.3.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.3." />
-        <Enum name="RXD0" start="0x1" description="RXD0" />
-        <Enum name="AD0" start="0x2" description="AD0.6" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_4" description="Pin function select P0.4.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.4." />
-        <Enum name="I2SRX_CLK" start="0x1" description="I2SRX_CLK" />
-        <Enum name="RD2" start="0x2" description="RD2" />
-        <Enum name="CAP2" start="0x3" description="CAP2.0" />
-      </BitField>
-      <BitField start="10" size="2" name="P0_5" description="Pin function select P0.5.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.5." />
-        <Enum name="I2SRX_WS" start="0x1" description="I2SRX_WS" />
-        <Enum name="TD2" start="0x2" description="TD2" />
-        <Enum name="CAP2" start="0x3" description="CAP2.1" />
-      </BitField>
-      <BitField start="12" size="2" name="P0_6" description="Pin function select P0.6.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.6." />
-        <Enum name="I2SRX_SDA" start="0x1" description="I2SRX_SDA" />
-        <Enum name="SSEL1" start="0x2" description="SSEL1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.0" />
-      </BitField>
-      <BitField start="14" size="2" name="P0_7" description="Pin function select P0.7.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.7." />
-        <Enum name="I2STX_CLK" start="0x1" description="I2STX_CLK" />
-        <Enum name="SCK1" start="0x2" description="SCK1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.1" />
-      </BitField>
-      <BitField start="16" size="2" name="P0_8" description="Pin function select P0.8.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.8." />
-        <Enum name="I2STX_WS" start="0x1" description="I2STX_WS" />
-        <Enum name="MISO1" start="0x2" description="MISO1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.2" />
-      </BitField>
-      <BitField start="18" size="2" name="P0_9" description="Pin function select P0.9.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.9" />
-        <Enum name="I2STX_SDA" start="0x1" description="I2STX_SDA" />
-        <Enum name="MOSI1" start="0x2" description="MOSI1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.3" />
-      </BitField>
-      <BitField start="20" size="2" name="P0_10" description="Pin function select P0.10.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.10" />
-        <Enum name="TXD2" start="0x1" description="TXD2" />
-        <Enum name="SDA2" start="0x2" description="SDA2" />
-        <Enum name="MAT3" start="0x3" description="MAT3.0" />
-      </BitField>
-      <BitField start="22" size="2" name="P0_11" description="Pin function select P0.11.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.11" />
-        <Enum name="RXD2" start="0x1" description="RXD2" />
-        <Enum name="SCL2" start="0x2" description="SCL2" />
-        <Enum name="MAT3" start="0x3" description="MAT3.1" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P0_15" description="Pin function select P0.15.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.15" />
-        <Enum name="TXD1" start="0x1" description="TXD1" />
-        <Enum name="SCK0" start="0x2" description="SCK0" />
-        <Enum name="SCK" start="0x3" description="SCK" />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="PINSEL1" access="Read/Write" description="Pin function select register 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_16" description="Pin function select P0.16.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.16" />
-        <Enum name="RXD1" start="0x1" description="RXD1" />
-        <Enum name="SSEL0" start="0x2" description="SSEL0" />
-        <Enum name="SSEL" start="0x3" description="SSEL" />
-      </BitField>
-      <BitField start="2" size="2" name="P0_17" description="Pin function select P0.17.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.17" />
-        <Enum name="CTS1" start="0x1" description="CTS1" />
-        <Enum name="MISO0" start="0x2" description="MISO0" />
-        <Enum name="MISO" start="0x3" description="MISO" />
-      </BitField>
-      <BitField start="4" size="2" name="P0_18" description="Pin function select P0.18.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.18" />
-        <Enum name="DCD1" start="0x1" description="DCD1" />
-        <Enum name="MOSI0" start="0x2" description="MOSI0" />
-        <Enum name="MOSI" start="0x3" description="MOSI" />
-      </BitField>
-      <BitField start="6" size="2" name="P0_19" description="Pin function select P019.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.19." />
-        <Enum name="DSR1" start="0x1" description="DSR1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="SDA1" start="0x3" description="SDA1" />
-      </BitField>
-      <BitField start="8" size="2" name="P0_20" description="Pin function select P0.20.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.20." />
-        <Enum name="DTR1" start="0x1" description="DTR1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="SCL1" start="0x3" description="SCL1" />
-      </BitField>
-      <BitField start="10" size="2" name="P0_21" description="Pin function select P0.21.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0.21." />
-        <Enum name="RI1" start="0x1" description="RI1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RD1" start="0x3" description="RD1" />
-      </BitField>
-      <BitField start="12" size="2" name="P0_22" description="Pin function select P022">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.22." />
-        <Enum name="RTS1" start="0x1" description="RTS1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="TD1" start="0x3" description="TD1" />
-      </BitField>
-      <BitField start="14" size="2" name="P0_23" description="Pin function select P023.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.23." />
-        <Enum name="AD0" start="0x1" description="AD0.0" />
-        <Enum name="I2SRX_CLK" start="0x2" description="I2SRX_CLK" />
-        <Enum name="CAP3" start="0x3" description="CAP3.0" />
-      </BitField>
-      <BitField start="16" size="2" name="P0_24" description="Pin function select P0.24.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.24." />
-        <Enum name="AD0" start="0x1" description="AD0.1" />
-        <Enum name="I2SRX_WS" start="0x2" description="I2SRX_WS" />
-        <Enum name="CAP3" start="0x3" description="CAP3.1" />
-      </BitField>
-      <BitField start="18" size="2" name="P0_25" description="Pin function select P0.25.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.25" />
-        <Enum name="AD0" start="0x1" description="AD0.2" />
-        <Enum name="I2SRX_SDA" start="0x2" description="I2SRX_SDA" />
-        <Enum name="TXD3" start="0x3" description="TXD3" />
-      </BitField>
-      <BitField start="20" size="2" name="P0_26" description="Pin function select P0.26.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.26" />
-        <Enum name="AD0" start="0x1" description="AD0.3" />
-        <Enum name="AOUT" start="0x2" description="AOUT" />
-        <Enum name="RXD3" start="0x3" description="RXD3" />
-      </BitField>
-      <BitField start="22" size="2" name="P0_27" description="Pin function select P0.27.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.27" />
-        <Enum name="SDA0" start="0x1" description="SDA0" />
-        <Enum name="USB_SDA" start="0x2" description="USB_SDA" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="2" name="P0_28" description="Pin function select P0.28.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.28" />
-        <Enum name="SCL0" start="0x1" description="SCL0" />
-        <Enum name="USB_SCL" start="0x2" description="USB_SCL" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="26" size="2" name="P0_29" description="Pin function select P0.29">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.29" />
-        <Enum name="USB_DP" start="0x1" description="USB_D+" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="28" size="2" name="P0_30" description="Pin function select P0.30.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.30" />
-        <Enum name="USB_DM" start="0x1" description="USB_D-" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="PINSEL2" access="Read/Write" description="Pin function select register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_0" description="Pin function select P1.0.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.0" />
-        <Enum name="ENET_TXD0" start="0x1" description="ENET_TXD0" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P1_1" description="Pin function select P1.1.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.1" />
-        <Enum name="ENET_TXD1" start="0x1" description="ENET_TXD1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="P1_4" description="Pin function select P1.4.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.4." />
-        <Enum name="ENET_TX_EN" start="0x1" description="ENET_TX_EN" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="2" name="P1_8" description="Pin function select P1.8.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.8." />
-        <Enum name="ENET_CRS" start="0x1" description="ENET_CRS" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="18" size="2" name="P1_9" description="Pin function select P1.9.">
-        <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.9" />
-        <Enum name="ENET_RXD0" start="0x1" description="ENET_RXD0" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="20" size="2" name="P1_10" description="Pin function select P1.10.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.10" />
-        <Enum name="ENET_RXD1" start="0x1" description="ENET_RXD1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="2" name="P1_14" description="Pin function select P1.14.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.14" />
-        <Enum name="ENET_RX_ER" start="0x1" description="ENET_RX_ER" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P1_15" description="Pin function select P1.15.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.15" />
-        <Enum name="ENET_REF_CLK" start="0x1" description="ENET_REF_CLK" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="4" name="PINSEL3" access="Read/Write" description="Pin function select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_16" description="Pin function select P1.16.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.16" />
-        <Enum name="ENET_MDC" start="0x1" description="ENET_MDC" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P1_17" description="Pin function select P1.17.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.17" />
-        <Enum name="ENET_MDIO" start="0x1" description="ENET_MDIO" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="P1_18" description="Pin function select P1.18.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.18" />
-        <Enum name="USB_UP_LED" start="0x1" description="USB_UP_LED" />
-        <Enum name="PWM1" start="0x2" description="PWM1.1" />
-        <Enum name="CAP1" start="0x3" description="CAP1.0" />
-      </BitField>
-      <BitField start="6" size="2" name="P1_19" description="Pin function select P1.19.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.19." />
-        <Enum name="MCOA0" start="0x1" description="MCOA0" />
-        <Enum name="USB_PPWR" start="0x2" description="USB_PPWR" />
-        <Enum name="CAP1" start="0x3" description="CAP1.1" />
-      </BitField>
-      <BitField start="8" size="2" name="P1_20" description="Pin function select P1.20.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.20." />
-        <Enum name="MCI0" start="0x1" description="MCI0" />
-        <Enum name="PWM1" start="0x2" description="PWM1.2" />
-        <Enum name="SCK0" start="0x3" description="SCK0" />
-      </BitField>
-      <BitField start="10" size="2" name="P1_21" description="Pin function select P1.21.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.21." />
-        <Enum name="MCABORT" start="0x1" description="MCABORT" />
-        <Enum name="PWM1" start="0x2" description="PWM1.3" />
-        <Enum name="SSEL0" start="0x3" description="SSEL0" />
-      </BitField>
-      <BitField start="12" size="2" name="P1_22" description="Pin function select P1.22">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.22." />
-        <Enum name="MCOB0" start="0x1" description="MCOB0" />
-        <Enum name="USB_PWRD" start="0x2" description="USB_PWRD" />
-        <Enum name="MAT1" start="0x3" description="MAT1.0" />
-      </BitField>
-      <BitField start="14" size="2" name="P1_23" description="Pin function select P1.23.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.23." />
-        <Enum name="MCI1" start="0x1" description="MCI1" />
-        <Enum name="PWM1" start="0x2" description="PWM1.4" />
-        <Enum name="MISO0" start="0x3" description="MISO0" />
-      </BitField>
-      <BitField start="16" size="2" name="P1_24" description="Pin function select P1.24.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.24." />
-        <Enum name="MCI2" start="0x1" description="MCI2" />
-        <Enum name="PWM1" start="0x2" description="PWM1.5" />
-        <Enum name="MOSI0" start="0x3" description="MOSI0" />
-      </BitField>
-      <BitField start="18" size="2" name="P1_25" description="Pin function select P1.25.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.25" />
-        <Enum name="MCOA1" start="0x1" description="MCOA1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="MAT1" start="0x3" description="MAT1.1" />
-      </BitField>
-      <BitField start="20" size="2" name="P1_26" description="Pin function select P1.26.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.26" />
-        <Enum name="MCOB1" start="0x1" description="MCOB1" />
-        <Enum name="PWM1" start="0x2" description="PWM1.6" />
-        <Enum name="CAP0" start="0x3" description="CAP0.0" />
-      </BitField>
-      <BitField start="22" size="2" name="P1_27" description="Pin function select P1.27.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.27" />
-        <Enum name="CLKOUT" start="0x1" description="CLKOUT" />
-        <Enum name="USB_OVRCR" start="0x2" description="USB_OVRCR" />
-        <Enum name="CAP0" start="0x3" description="CAP0.1" />
-      </BitField>
-      <BitField start="24" size="2" name="P1_28" description="Pin function select P1.28.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.28" />
-        <Enum name="MCOA2" start="0x1" description="MCOA2" />
-        <Enum name="PCAP1" start="0x2" description="PCAP1.0" />
-        <Enum name="MAT0" start="0x3" description="MAT0.0" />
-      </BitField>
-      <BitField start="26" size="2" name="P1_29" description="Pin function select P1.29">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.29" />
-        <Enum name="MCOB2" start="0x1" description="MCOB2" />
-        <Enum name="PCAP1" start="0x2" description="PCAP1.1" />
-        <Enum name="MAT0" start="0x3" description="MAT0.1" />
-      </BitField>
-      <BitField start="28" size="2" name="P1_30" description="Pin function select P1.30.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.30" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="VBUS" start="0x2" description="VBUS" />
-        <Enum name="AD0" start="0x3" description="AD0.4" />
-      </BitField>
-      <BitField start="30" size="2" name="P1_31" description="Pin function select P1.31.">
-        <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.31" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SCK1" start="0x2" description="SCK1" />
-        <Enum name="AD0" start="0x3" description="AD0.5" />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="4" name="PINSEL4" access="Read/Write" description="Pin function select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P2_0" description="Pin function select P2.0.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.0" />
-        <Enum name="PWM1" start="0x1" description="PWM1.1" />
-        <Enum name="TXD1" start="0x2" description="TXD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P2_1" description="Pin function select P2.1.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.1" />
-        <Enum name="PWM1" start="0x1" description="PWM1.2" />
-        <Enum name="RXD1" start="0x2" description="RXD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="P2_2" description="Pin function select P2.2.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.2" />
-        <Enum name="PWM1" start="0x1" description="PWM1.3" />
-        <Enum name="CTS1" start="0x2" description="CTS1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="P2_3" description="Pin function select P2.3.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.3." />
-        <Enum name="PWM1" start="0x1" description="PWM1.4" />
-        <Enum name="DCD1" start="0x2" description="DCD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="2" name="P2_4" description="Pin function select P2.4.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.4." />
-        <Enum name="PWM1" start="0x1" description="PWM1.5" />
-        <Enum name="DSR1" start="0x2" description="DSR1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="2" name="P2_5" description="Pin function select P2.5.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.5." />
-        <Enum name="PWM1" start="0x1" description="PWM1.6" />
-        <Enum name="DTR1" start="0x2" description="DTR1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="12" size="2" name="P2_6" description="Pin function select P2.6.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.6." />
-        <Enum name="PCAP1" start="0x1" description="PCAP1.0" />
-        <Enum name="RI1" start="0x2" description="RI1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="14" size="2" name="P2_7" description="Pin function select P2.7.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.7." />
-        <Enum name="RD2" start="0x1" description="RD2" />
-        <Enum name="RTS1" start="0x2" description="RTS1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="16" size="2" name="P2_8" description="Pin function select P2.8.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.8." />
-        <Enum name="TD2" start="0x1" description="TD2" />
-        <Enum name="TXD2" start="0x2" description="TXD2" />
-        <Enum name="ENET_MDC" start="0x3" description="ENET_MDC" />
-      </BitField>
-      <BitField start="18" size="2" name="P2_9" description="Pin function select P2.9.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.9" />
-        <Enum name="USB_CONNECT" start="0x1" description="USB_CONNECT" />
-        <Enum name="RXD2" start="0x2" description="RXD2" />
-        <Enum name="ENET_MDIO" start="0x3" description="ENET_MDIO" />
-      </BitField>
-      <BitField start="20" size="2" name="P2_10" description="Pin function select P2.10.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.10" />
-        <Enum name="EINT0" start="0x1" description="EINT0" />
-        <Enum name="NMI" start="0x2" description="NMI" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="22" size="2" name="P2_11" description="Pin function select P2.11.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.11" />
-        <Enum name="EINT1" start="0x1" description="EINT1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_CLK" start="0x3" description="I2STX_CLK" />
-      </BitField>
-      <BitField start="24" size="2" name="P2_12" description="Pin function select P2.12.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.12" />
-        <Enum name="EINT2" start="0x1" description="EINT2" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_WS" start="0x3" description="I2STX_WS" />
-      </BitField>
-      <BitField start="26" size="2" name="P2_13" description="Pin function select P2.13.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.13" />
-        <Enum name="EINT3" start="0x1" description="EINT3" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_SDA" start="0x3" description="I2STX_SDA" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PINSEL7" access="Read/Write" description="Pin function select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="18" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="2" name="P3_25" description="Pin function select P3.25.">
-        <Enum name="GPIO_P3" start="0x0" description="GPIO P3.25" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="MAT0" start="0x2" description="MAT0.0" />
-        <Enum name="PWM1" start="0x3" description="PWM1.2" />
-      </BitField>
-      <BitField start="20" size="2" name="P3_26" description="Pin function select P3.26.">
-        <Enum name="GPIO_P3" start="0x0" description="GPIO P3.26" />
-        <Enum name="STCLK" start="0x1" description="STCLK" />
-        <Enum name="MAT0" start="0x2" description="MAT0.1" />
-        <Enum name="PWM1" start="0x3" description="PWM1.3" />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="PINSEL9" access="Read/Write" description="Pin function select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="2" name="P4_28" description="Pin function select P4.28.">
-        <Enum name="GPIO_P4" start="0x0" description="GPIO P4.28" />
-        <Enum name="RX_MCLK" start="0x1" description="RX_MCLK" />
-        <Enum name="MAT2" start="0x2" description="MAT2.0" />
-        <Enum name="TXD3" start="0x3" description="TXD3" />
-      </BitField>
-      <BitField start="26" size="2" name="P4_29" description="Pin function select P4.29.">
-        <Enum name="GPIO_P4" start="0x0" description="GPIO P4.29" />
-        <Enum name="TX_MCLK" start="0x1" description="TX_MCLK" />
-        <Enum name="MAT2" start="0x2" description="MAT2.1" />
-        <Enum name="RXD3" start="0x3" description="RXD3" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="PINSEL10" access="Read/Write" description="Pin function select register 10" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
-      <BitField start="3" size="1" name="TPIUCTRL" description="TPIU interface pins control.">
-        <Enum name="DISABLED" start="0" description="Disabled. TPIU interface is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
-    </Register>
-    <Register start="+0x040" size="4" name="PINMODE0" access="Read/Write" description="Pin mode select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_00MODE" description="Port 0 pin 0 on-chip pull-up/down resistor control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P0_01MODE" description="Port 0 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P0_02MODE" description="Port 0 pin 2 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.2 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.2 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.2 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.2 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P0_03MODE" description="Port 0 pin 3 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.3 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.3 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.3 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.3 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_04MODE" description="Port 0 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P0_05MODE" description="Port 0 pin 5 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.5 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.5 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.5 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.5 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P0_06MODE" description="Port 0 pin 6 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.6 pin has a pull-up resistor enabled." />
-        <Enum name="DISABLED" start="0x1" description="Disabled. Repeater. P0.6 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.6 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.6 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P0_07MODE" description="Port 0 pin 7 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.7 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.7 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.7 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.7 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P0_08MODE" description="Port 0 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P0_09MODE" description="Port 0 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P0_10MODE" description="Port 0 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P0_11MODE" description="Port 0 pin 11 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.11 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.11 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.11 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.11 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P0_15MODE" description="Port 0 pin 15 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.15 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.15 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.15 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.15 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x044" size="4" name="PINMODE1" access="Read/Write" description="Pin mode select register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_16MODE" description="Port 1 pin 16 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.16 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.16 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.16 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.16 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P0_17MODE" description="Port 1 pin 17 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.17 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.17 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.17 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.17 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P0_18MODE" description="Port 1 pin 18 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.18 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.18 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.18 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.18 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P0_19MODE" description="Port 1 pin 19 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.19 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.19 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.19 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.19 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_20MODE" description="Port 1 pin 20 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.20 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.20 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.20 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.20 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P0_21MODE" description="Port 1 pin 21 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.21 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.21 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.21 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.21 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P0_22MODE" description="Port 1 pin 22 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.22 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.22 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.22 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.22 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P0_23MODE" description="Port 1 pin 23 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.23 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.23 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.23 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.23 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P0_24MODE" description="Port 1 pin 24 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.24 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.24 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.24 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.24 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P0_25MODE" description="Port 1 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P0_26MODE" description="Port 1 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="PINMODE2" access="Read/Write" description="Pin mode select register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_00MODE" description="Port 1 pin 0 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P1_01MODE" description="Port 1 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="P1_04MODE" description="Port 1 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="2" name="P1_08MODE" description="Port 1 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P1_09MODE" description="Port 1 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P1_10MODE" description="Port 1 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="2" name="P1_14MODE" description="Port 1 pin 14 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.14 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.14 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.14 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.14 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="30" size="2" name="P1_15MODE" description="Port 1 pin 15 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.15 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.15 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.15 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.15 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x04C" size="4" name="PINMODE3" access="Read/Write" description="Pin mode select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_16MODE" description="Port 1 pin 16 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.16 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.16 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.16 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.16 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P1_17MODE" description="Port 1 pin 17 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.17 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.17 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.17 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.17 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P1_18MODE" description="Port 1 pin 18 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.18 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.18 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.18 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.18 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P1_19MODE" description="Port 1 pin 19 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.19 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.19 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.19 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.19 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P1_20MODE" description="Port 1 pin 20 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.20 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.20 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.20 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.20 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P1_21MODE" description="Port 1 pin 21 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.21 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.21 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.21 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.21 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P1_22MODE" description="Port 1 pin 22 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.22 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.22 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.22 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.22 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P1_23MODE" description="Port 1 pin 23 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.23 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.23 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.23 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.23 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P1_24MODE" description="Port 1 pin 24 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.24 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.24 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.24 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.24 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P1_25MODE" description="Port 1 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P1_26MODE" description="Port 1 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P1_27MODE" description="Port 1 pin 27 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.27 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.27 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.27 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.27 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="2" name="P1_28MODE" description="Port 1 pin 28 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.28 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.28 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.28 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.28 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P1_29MODE" description="Port 1 pin 29 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.29 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.29 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.29 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.29 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="2" name="P1_30MODE" description="Port 1 pin 30 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.30 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.30 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.30 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.30 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="30" size="2" name="P1_31MODE" description="Port 1 pin 31 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.31 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.31 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.31 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.31 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x050" size="4" name="PINMODE4" access="Read/Write" description="Pin mode select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P2_00MODE" description="Port 2 pin 0 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P2_01MODE" description="Port 2 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P2_02MODE" description="Port 2 pin 2 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.2 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.2 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.2 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.2 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P2_03MODE" description="Port 2 pin 3 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.3 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.3 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.3 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.3 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P2_04MODE" description="Port 2 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P2_05MODE" description="Port 2 pin 5 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.5 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.5 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.5 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.5 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P2_06MODE" description="Port 2 pin 6 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.6 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.6 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.6 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.6 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P2_07MODE" description="Port 2 pin 7 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.7 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.7 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.7 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.7 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P2_08MODE" description="Port 2 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P2_09MODE" description="Port 2 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P2_10MODE" description="Port 2 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P2_11MODE" description="Port 2 pin 11 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.11 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.11 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.11 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.11 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="2" name="P2_12MODE" description="Port 2 pin 12 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.12 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.12 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.12 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.12 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P2_13MODE" description="Port 2 pin 13 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.13 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.13 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.13 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.13 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="PINMODE7" access="Read/Write" description="Pin mode select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="P3_25MODE" description="Port 3 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P3.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P3.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P3_26MODE" description="Port 3 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P3.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P3.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x064" size="4" name="PINMODE9" access="Read/Write" description="Pin mode select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="2" name="P4_28MODE" description="Port 4 pin 28 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.28 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P4.28 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P4.28 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.28 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P4_29MODE" description="Port 4 pin 29 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.29 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P4.29 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P4.29 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.29 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="PINMODE_OD0" access="Read/Write" description="Open drain mode control register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_00OD" description="Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P0_01OD" description="Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.1 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="1" name="P0_02OD" description="Port 0 pin 2 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.2 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.2 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="3" size="1" name="P0_03OD" description="Port 0 pin 3 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.3 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.3 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="4" size="1" name="P0_04OD" description="Port 0 pin 4 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="1" name="P0_05OD" description="Port 0 pin 5 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.5 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.5 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="6" size="1" name="P0_06OD" description="Port 0 pin 6 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.6 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.6 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="7" size="1" name="P0_07OD" description="Port 0 pin 7 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.7 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.7 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="8" size="1" name="P0_08OD" description="Port 0 pin 8 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P0_09OD" description="Port 0 pin 9 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P0_10OD" description="Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="1" name="P0_11OD" description="Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.11 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.11 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="P0_15OD" description="Port 0 pin 15 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.15 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.15 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="16" size="1" name="P0_16OD" description="Port 0 pin 16 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.16 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.16 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="17" size="1" name="P0_17OD" description="Port 0 pin 17 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.17 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.17 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="18" size="1" name="P0_18OD" description="Port 0 pin 18 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.18 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.18 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="19" size="1" name="P0_19OD" description="Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.19 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.19 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="20" size="1" name="P0_20OD" description="Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.20 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.20 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="21" size="1" name="P0_21OD" description="Port 0 pin 21 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.21 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.21 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="22" size="1" name="P0_22OD" description="Port 0 pin 22 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.22 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.22 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="23" size="1" name="P0_23OD" description="Port 0 pin 23 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="24" size="1" name="P0_24OD" description="Port 0 pin 24open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="25" size="1" name="P0_25OD" description="Port 0 pin 25 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P0_26OD" description="Port 0 pin 26 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.26 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.26 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="27" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="P0_29OD" description="Port 0 pin 29 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.29 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.29 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="30" size="1" name="P0_30OD" description="Port 0 pin 30 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.30 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.30 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="PINMODE_OD1" access="Read/Write" description="Open drain mode control register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P1_00OD" description="Port 1 pin 0 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P1.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P1_01OD" description="Port 1 pin 1 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.1 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="P1_04OD" description="Port 1 pin 4 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="P1_08OD" description="Port 1 pin 8 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P1_09OD" description="Port 1 pin 9 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P1_10OD" description="Port 1 pin 10 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="P1_14OD" description="Port 1 pin 14 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.14 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.14 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="15" size="1" name="P1_15OD" description="Port 1 pin 15 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.15 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.15 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="16" size="1" name="P1_16OD" description="Port 1 pin 16 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.16 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.16 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="17" size="1" name="P1_17OD" description="Port 1 pin 17 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.17 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.17 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="18" size="1" name="P1_18OD" description="Port 1 pin 18 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.18 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.18 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="19" size="1" name="P1_19OD" description="Port 1 pin 19 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.19 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.19 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="20" size="1" name="P1_20OD" description="Port 1 pin 20open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.20 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.20 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="21" size="1" name="P1_21OD" description="Port 1 pin 21 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.21 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.21 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="22" size="1" name="P1_22OD" description="Port 1 pin 22 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.22 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.22 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="23" size="1" name="P1_23OD" description="Port 1 pin 23 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="24" size="1" name="P1_24OD" description="Port 1 pin 24open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.24 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.24 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="25" size="1" name="P1_25OD" description="Port 1 pin 25 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P1_26OD" description="Port 1 pin 26 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.26 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.26 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="27" size="1" name="P1_27OD" description="Port 1 pin 27 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.27 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.27 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="28" size="1" name="P1_28OD" description="Port 1 pin 28 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.28 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.28 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="29" size="1" name="P1_29OD" description="Port 1 pin 29 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.29 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.29 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="30" size="1" name="P1_30OD" description="Port 1 pin 30 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.30 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.30 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="31" size="1" name="P1_31OD" description="Port 1 pin 31 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P1.31 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.31 pin is in the open drain mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x070" size="4" name="PINMODE_OD2" access="Read/Write" description="Open drain mode control register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_00OD" description="Port 2 pin 0 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P2.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P2_01OD" description="Port 2 pin 1 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.1p in is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="1" name="P2_02OD" description="Port 2 pin 2 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.2 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.2 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="3" size="1" name="P2_03OD" description="Port 2 pin 3 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.3 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.3 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="4" size="1" name="P2_04OD" description="Port 2 pin 4 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="1" name="P2_05OD" description="Port 2 pin 5 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.5 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.5 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="6" size="1" name="P2_06OD" description="Port 2 pin 6 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.6 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.6 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="7" size="1" name="P2_07OD" description="Port 2 pin 7 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.7 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.7 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="8" size="1" name="P2_08OD" description="Port 2 pin 8 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P2_09OD" description="Port 2 pin 9 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P2_10OD" description="Port 2 pin 10 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="1" name="P2_11OD" description="Port 2 pin 11 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.11 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.11 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="12" size="1" name="P2_12OD" description="Port 2 pin 12 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.12 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.12 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="13" size="1" name="P2_13OD" description="Port 2 pin 13 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.13 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.13 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x074" size="4" name="PINMODE_OD3" access="Read/Write" description="Open drain mode control register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="25" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="1" name="P3_25OD" description="Port 3 pin 25 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P3.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P3.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P3_26OD" description="Port 3 pin 26 open drain mode control, see P3.25OD" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x078" size="4" name="PINMODE_OD4" access="Read/Write" description="Open drain mode control register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="28" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="P4_28OD" description="Port 4 pin 28 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P4.28 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P4.28 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="29" size="1" name="P4_29OD" description="Port 4 pin 29 open drain mode control, see P4.28OD" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x07C" size="4" name="I2CPADCFG" access="Read/Write" description="I2C Pin Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDADRV0" description="Drive mode control for the SDA0 pin, P0.27.">
-        <Enum name="STANDARD" start="0" description="Standard. The SDA0 pin is in the standard drive mode." />
-        <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode." />
-      </BitField>
-      <BitField start="1" size="1" name="SDAI2C0" description="I 2C filter mode control for the SDA0 pin, P0.27.">
-        <Enum name="ENABLED" start="0" description="Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SCLDRV0" description="Drive mode control for the SCL0 pin, P0.28.">
-        <Enum name="STANDARD" start="0" description="Standard. The SCL0 pin is in the standard drive mode." />
-        <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode." />
-      </BitField>
-      <BitField start="3" size="1" name="SCLI2C0" description="I 2C filter mode control for the SCL0 pin, P0.28.">
-        <Enum name="ENABLED" start="0" description="Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
-        <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
-      </BitField>
-      <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="21" size="1" name="PDN" description="Power down mode">
-        <Enum name="POWERED" start="1" description="The A/D converter is operational." />
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
-        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
-        <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
-        <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
-        <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
-        <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
-        <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
-        <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
-      </BitField>
-      <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
-        <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
-        <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
-      <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
-      <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
-      <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
-      <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
-      <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
-      <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
-      <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
-      <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
-      <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
-      <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
-      <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
-      <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
-      <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
-      <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
-      <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
-      <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
-    <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAF" start="0x4003C000" description=" CAN controller acceptance filter ">
-    <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
-      <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
-      <BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
-        <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
-        <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
-    </Register>
-    <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCAN" start="0x40040000" description="Central CAN controller ">
-    <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
-      <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
-      <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
-      <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
-      <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
-      <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
-      <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN1" start="0x40044000" description="CAN1 controller ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN2" start="0x40048000" description="CAN1 controller ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x4008C000" description=" Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
-        <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
-        <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
-        <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
-        <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA access">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x40090000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x40094000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400B0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTER" access="Read/Write" description="Digital filter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
-      <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
-      <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
-      <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
-      <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
-      <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
-      <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
-      <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
-      <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
-      <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
-      <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
-      <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x400FC000" description="System and clock control">
-    <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0x303A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.">
-        <Enum name="1CLK" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock." />
-        <Enum name="2CLK" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock." />
-        <Enum name="3CLK" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock." />
-        <Enum name="4CLK" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock." />
-        <Enum name="5CLK" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only." />
-        <Enum name="6CLK" start="0x5" description="Flash accesses use 6 CPU clocks. This safe setting will work under any conditions." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="PLL0CON" access="Read/Write" description="PLL0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE0" description="PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register." />
-      <BitField start="1" size="1" name="PLLC0" description="PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="PLL0CFG" access="Read/Write" description="PLL0 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MSEL0" description="PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1.  Note: Not all values of M are needed, and therefore some are not supported by hardware." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="8" name="NSEL0" description="PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x088" size="4" name="PLL0STAT" access="ReadOnly" description="PLL0 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MSEL0" description="Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="8" name="NSEL0" description="Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider." />
-      <BitField start="24" size="1" name="PLLE0_STAT" description="Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered." />
-      <BitField start="25" size="1" name="PLLC0_STAT" description="Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered." />
-      <BitField start="26" size="1" name="PLOCK0" description="Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details." />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x08C" size="4" name="PLL0FEED" access="WriteOnly" description="PLL0 Feed Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLL0FEED" description="The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0" size="4" name="PLL1CON" access="Read/Write" description="PLL1 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE1" description="PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency." />
-      <BitField start="1" size="1" name="PLLC1" description="PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A4" size="4" name="PLL1CFG" access="Read/Write" description="PLL1 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL1" description="PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations." />
-      <BitField start="5" size="2" name="PSEL1" description="PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A8" size="4" name="PLL1STAT" access="ReadOnly" description="PLL1 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL1" description="Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1." />
-      <BitField start="5" size="2" name="PSEL1" description="Read-back for the PLL1 Divider value. This is the value currently used by PLL1." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE1_STAT" description="Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="PLLC1_STAT" description="Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="10" size="1" name="PLOCK1" description="Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0AC" size="4" name="PLL1FEED" access="WriteOnly" description="PLL1 Feed Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLL1FEED" description="The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode." />
-      <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode." />
-      <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit." />
-      <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0C4" size="4" name="PCONP" access="Read/Write" description="Power Control for Peripherals Register" reset_value="0x03BE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
-      <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
-      <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
-      <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
-      <BitField start="7" size="1" name="PCI2C0" description="The I2C0 interface power/clock control bit." />
-      <BitField start="8" size="1" name="PCSPI" description="The SPI interface power/clock control bit." />
-      <BitField start="9" size="1" name="PCRTC" description="The RTC power/clock control bit." />
-      <BitField start="10" size="1" name="PCSSP1" description="The SSP 1 interface power/clock control bit." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN." />
-      <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
-      <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
-      <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
-      <BitField start="16" size="1" name="PCRIT" description="Repetitive Interrupt Timer power/clock control bit." />
-      <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM" />
-      <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
-      <BitField start="19" size="1" name="PCI2C1" description="The I2C1 interface power/clock control bit." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="PCSSP0" description="The SSP0 interface power/clock control bit." />
-      <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
-      <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
-      <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
-      <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
-      <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
-      <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
-      <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
-      <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
-    </Register>
-    <Register start="+0x104" size="4" name="CCLKCFG" access="Read/Write" description="CPU Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCLKSEL" description="Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x108" size="4" name="USBCLKCFG" access="Read/Write" description="USB Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="USBSEL" description="Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output.  Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLKSRC" description="Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.">
-        <Enum name="SELECTS_THE_INTERNAL" start="0x0" description="Selects the Internal RC oscillator as the PLL0 clock source (default)." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the PLL0 clock source.  Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates &gt; 100 kBit/s." />
-        <Enum name="SELECTS_THE_RTC_OSCI" start="0x2" description="Selects the RTC oscillator as the PLL0 clock source." />
-        <Enum name="RESERVED" start="0x3" description="Reserved, do not use this setting." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
-      <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTMODE0" description="External interrupt 0 EINT0 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT0." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT0 is edge sensitive." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTMODE1" description="External interrupt 1 EINT1 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT1." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT1 is edge sensitive." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTMODE2" description="External interrupt 2 EINT2 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT2." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT2 is edge sensitive." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTMODE3" description="External interrupt 3 EINT3 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT3." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT3 is edge sensitive." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt 0 EINT0 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt 1 EINT1 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt 2 EINT2 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt 3 EINT3 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
-      <BitField start="1" size="1" name="EXTR" description="Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR." />
-      <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
-      <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System control and status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="OSCRANGE" description="Main oscillator range select.">
-        <Enum name="LOW" start="0" description="Low. The frequency range of the main oscillator is 1 MHz to 20 MHz." />
-        <Enum name="HIGH" start="1" description="High. The frequency range of the main oscillator is 15 MHz to 25 MHz." />
-      </BitField>
-      <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The main oscillator is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
-      </BitField>
-      <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
-        <Enum name="NOT_READY" start="0" description="Not ready. The main oscillator is not ready to be used as a clock source." />
-        <Enum name="READY" start="1" description="Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="PCLKSEL0" access="Read/Write" description="Peripheral Clock Selection register 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PCLK_WDT" description="Peripheral clock selection for WDT.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="2" size="2" name="PCLK_TIMER0" description="Peripheral clock selection for TIMER0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="4" size="2" name="PCLK_TIMER1" description="Peripheral clock selection for TIMER1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="6" size="2" name="PCLK_UART0" description="Peripheral clock selection for UART0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="8" size="2" name="PCLK_UART1" description="Peripheral clock selection for UART1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="2" name="PCLK_PWM1" description="Peripheral clock selection for PWM1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="14" size="2" name="PCLK_I2C0" description="Peripheral clock selection for I2C0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="16" size="2" name="PCLK_SPI" description="Peripheral clock selection for SPI.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="18" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="20" size="2" name="PCLK_SSP1" description="Peripheral clock selection for SSP1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="22" size="2" name="PCLK_DAC" description="Peripheral clock selection for DAC.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="24" size="2" name="PCLK_ADC" description="Peripheral clock selection for ADC.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="26" size="2" name="PCLK_CAN1" description="Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6." />
-      </BitField>
-      <BitField start="28" size="2" name="PCLK_CAN2" description="Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6," />
-      </BitField>
-      <BitField start="30" size="2" name="PCLK_ACF" description="Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6" />
-      </BitField>
-    </Register>
-    <Register start="+0x1AC" size="4" name="PCLKSEL1" access="Read/Write" description="Peripheral Clock Selection register 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PCLK_QEI" description="Peripheral clock selection for the Quadrature Encoder Interface.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="2" size="2" name="PCLK_GPIOINT" description="Peripheral clock selection for GPIO interrupts.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="4" size="2" name="PCLK_PCB" description="Peripheral clock selection for the Pin Connect block.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="6" size="2" name="PCLK_I2C1" description="Peripheral clock selection for I2C1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="8" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="2" name="PCLK_SSP0" description="Peripheral clock selection for SSP0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="12" size="2" name="PCLK_TIMER2" description="Peripheral clock selection for TIMER2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="14" size="2" name="PCLK_TIMER3" description="Peripheral clock selection for TIMER3.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="16" size="2" name="PCLK_UART2" description="Peripheral clock selection for UART2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="18" size="2" name="PCLK_UART3" description="Peripheral clock selection for UART3.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="20" size="2" name="PCLK_I2C2" description="Peripheral clock selection for I2C2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="22" size="2" name="PCLK_I2S" description="Peripheral clock selection for I2S.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="24" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="26" size="2" name="PCLK_RIT" description="Peripheral clock selection for Repetitive Interrupt Timer.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="28" size="2" name="PCLK_SYSCON" description="Peripheral clock selection for the System Control block.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="30" size="2" name="PCLK_MC" description="Peripheral clock selection for the Motor Control PWM.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
-      <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
-      <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
-      <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
-      <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
-      <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
-      <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
-      <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMASEL08" description="Selects the DMA request for GPDMA input 8: 0 - uart0 tx  1 - Timer 0 match 0 is selected." />
-      <BitField start="1" size="1" name="DMASEL09" description="Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected." />
-      <BitField start="2" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - uart1 tx  is selected. 1 - Timer 1 match 0 is selected." />
-      <BitField start="3" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - uart1 rx  is selected. 1 - Timer 1 match 1 is selected." />
-      <BitField start="4" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - uart2 tx  is selected. 1 - Timer 2 match 0 is selected." />
-      <BitField start="5" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - uart2 rx  is selected. 1 - Timer 2 match 1 is selected." />
-      <BitField start="6" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - uart3 tx  is selected. 1 - I2S channel 0 is selected." />
-      <BitField start="7" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.">
-        <Enum name="SELECTS_THE_CPU_CLOC" start="0x0" description="Selects the CPU clock as the CLKOUT source." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the CLKOUT source." />
-        <Enum name="SELECTS_THE_INTERNAL" start="0x2" description="Selects the Internal RC oscillator as the CLKOUT source." />
-        <Enum name="SELECTS_THE_USB_CLOC" start="0x3" description="Selects the USB clock as the CLKOUT source." />
-        <Enum name="SELECTS_THE_RTC_OSCI" start="0x4" description="Selects the RTC oscillator as the CLKOUT source." />
-      </BitField>
-      <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16." />
-      <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
-      <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMAC" start="0x50000000" description="Ethernet">
-    <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
-      <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
-      <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
-      <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
-      <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
-      <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
-      <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
-      <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
-      <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
-      <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
-      <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
-      <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
-      <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
-      <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
-      <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
-      <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
-      <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
-      <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
-      <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
-      <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
-      <BitField start="3" size="29" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
-      <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
-      <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
-      <BitField start="6" size="9" name="RESERVED" description="Unused" />
-      <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
-      <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
-      <BitField start="13" size="19" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
-      <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
-      <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
-      <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
-      <BitField start="4" size="28" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
-      <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
-      <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
-      <BitField start="2" size="1" name="RESERVED" description="Unused" />
-      <BitField start="3" size="1" name="REGRESET" description="When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
-      <BitField start="4" size="1" name="TXRESET" description="When a  1  is written, the transmit datapath is reset." />
-      <BitField start="5" size="1" name="RXRESET" description="When a  1  is written, the receive datapath is reset." />
-      <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
-      <BitField start="7" size="1" name="PASSRXFILTER" description="When set to  1 , disables receive filtering i.e. all frames received are written to memory." />
-      <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
-      <BitField start="9" size="1" name="RMII" description="When set to  1 , RMII mode is selected; if 0, MII mode is selected." />
-      <BitField start="10" size="1" name="FULLDUPLEX" description="When set to  1 , indicates full duplex operation." />
-      <BitField start="11" size="21" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
-      <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
-    </Register>
-    <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
-      <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
-    </Register>
-    <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
-    </Register>
-    <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
-    </Register>
-    <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
-      <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
-      <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
-      <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
-      <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
-      <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
-      <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
-      <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
-      <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
-      <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
-      <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
-      <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
-      <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
-      <BitField start="20" size="12" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
-      <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
-      <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
-      <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
-      <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
-      <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
-      <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
-      <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
-      <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
-      <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
-      <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-      <BitField start="31" size="1" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
-      <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
-    </Register>
-    <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
-      <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
-      <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
-      <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
-      <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
-      <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
-      <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
-      <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
-      <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
-      <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
-      <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
-      <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
-      <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
-      <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
-      <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
-      <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
-      <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
-      <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="RESERVED" description="Unused" />
-      <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x50004000" description="General purpose DMA controller">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
-      <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x50008000" description="USB device/host/OTG controller">
-    <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR" description="Timer time-out." />
-      <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
-      <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
-      <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="INTCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="STCTRL" access="Read/Write" description="OTG Status and Control and USB port select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PORT_FUNC" description="Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
-      <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
-      <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
-      <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
-      <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
-    </Register>
-    <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
-      <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
-      <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
-      <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
-      <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
-      <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
-      <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
-        <Enum name="READ" start="0x02" description="Read" />
-        <Enum name="WRITE" start="0x01" description="Write" />
-        <Enum name="COMMAND" start="0x05" description="Command" />
-      </BitField>
-      <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RX_DATA" description="Data received." />
-    </Register>
-    <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
-    </Register>
-    <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
-        <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
-        <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
-      </BitField>
-      <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
-        <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
-        <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-    </Register>
-    <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-    </Register>
-    <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-    </Register>
-    <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-    </Register>
-    <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-    </Register>
-    <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-    </Register>
-    <Register start="+0x248" size="4" name="EPIND" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 &lt;=  xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-    </Register>
-    <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
-      <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
-    </Register>
-    <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-    </Register>
-    <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RXDATA" description="Receive data." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_WO" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="TXDATA" description="Transmit data." />
-      <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
-      <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
-        <Enum name="NOT_COMPLETE" start="0" description="Transaction has not completed." />
-        <Enum name="COMPLETE" start="1" description="Transaction completed." />
-      </BitField>
-      <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
-        <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
-        <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
-      </BitField>
-      <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="ACKNOWLEDGE_RCVD" start="0" description="Last transmission received an acknowledge." />
-        <Enum name="NO_ACKNOWLEDGE_RCVD" start="1" description="Last transmission did not receive an acknowledge." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="BUSY" start="0" description="Master transmitter does not need data." />
-        <Enum name="NEED_DATA" start="1" description="Master transmitter needs data." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
-        <Enum name="BUSY" start="0" description="Slave transmitter does not need data." />
-        <Enum name="NEED_DATA" start="1" description="Slave transmitter needs data." />
-      </BitField>
-      <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
-      <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
-      <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
-      <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
-        <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
-        <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
-      </BitField>
-      <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
-        <Enum name="DATA" start="0" description="RX FIFO contains data." />
-        <Enum name="EMPTY" start="1" description="RX FIFO is empty" />
-      </BitField>
-      <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
-        <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
-        <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
-      </BitField>
-      <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
-        <Enum name="VALID_DATA" start="0" description="TX FIFO contains valid data." />
-        <Enum name="EMPTY" start="1" description="TX FIFO is empty" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
-        <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
-        <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
-        <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
-        <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
-      </BitField>
-      <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
-        <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
-        <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
-        <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
-        <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
-        <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
-        <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
-        <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
-        <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
-      </BitField>
-      <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
-        <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
-        <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
-      </BitField>
-      <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
-        <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
-        <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
-      </BitField>
-      <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
-        <Enum name="NO_RESET" start="0" description="No reset." />
-        <Enum name="RESET" start="1" description="Reset the I2C to idle state. Self clearing." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="USBCLKCTRL" access="Read/Write" description="USB Clock Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable.   Enables the usbclk input to the device controller" />
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PORTSEL_CLK_EN" description="Port select register clock enable." />
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB clock enable" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="OTGCLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
-        <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
-        <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
-        <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
-        <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
-        <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
-        <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
-        <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
-        <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
-        <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
-        <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="USBCLKST" access="ReadOnly" description="USB Clock Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock on. The usbclk input to the device controller is active&#x9;." />
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PORTSEL_CLK_ON" description="Port select register clock on." />
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB clock on." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="OTGCLKST" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
-        <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
-        <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
-        <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
-        <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
-        <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
-        <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
-        <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
-        <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
-        <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
-        <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO" start="0x2009C000" description="General Purpose I/O ">
-    <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="WDT" start="4" size="4" />
-      <BitField name="TIMER0" start="12" size="4" />
-      <BitField name="TIMER1" start="20" size="4" />
-      <BitField name="TIMER2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="TIMER3" start="4" size="4" />
-      <BitField name="UART0" start="12" size="4" />
-      <BitField name="UART1" start="20" size="4" />
-      <BitField name="UART2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="UART3" start="4" size="4" />
-      <BitField name="PWM1" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="I2C2" start="4" size="4" />
-      <BitField name="SPI" start="12" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="PLL0" start="4" size="4" />
-      <BitField name="RTC" start="12" size="4" />
-      <BitField name="EINT0" start="20" size="4" />
-      <BitField name="EINT1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="EINT2" start="4" size="4" />
-      <BitField name="EINT3" start="12" size="4" />
-      <BitField name="ADC" start="20" size="4" />
-      <BitField name="BOD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USB" start="4" size="4" />
-      <BitField name="CAN" start="12" size="4" />
-      <BitField name="DMA" start="20" size="4" />
-      <BitField name="I2S" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="ENET" start="4" size="4" />
-      <BitField name="RIT" start="12" size="4" />
-      <BitField name="MCPWM" start="20" size="4" />
-      <BitField name="QEI" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PLL1" start="4" size="4" />
-      <BitField name="USBActivity" start="12" size="4" />
-      <BitField name="CANActivity" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYS_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYS_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYS_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYS_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC176x5x_Vectors.s b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC176x5x_Vectors.s
deleted file mode 100644
index c5fae131..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/LPC176x5x_Vectors.s
+++ /dev/null
@@ -1,418 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak WDT_IRQHandler
-  .thumb_set WDT_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak UART0_IRQHandler
-  .thumb_set UART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak UART2_IRQHandler
-  .thumb_set UART2_IRQHandler,Dummy_Handler
-
-  .weak UART3_IRQHandler
-  .thumb_set UART3_IRQHandler,Dummy_Handler
-
-  .weak PWM1_IRQHandler
-  .thumb_set PWM1_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Dummy_Handler
-
-  .weak SPI_IRQHandler
-  .thumb_set SPI_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak PLL0_IRQHandler
-  .thumb_set PLL0_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak EINT0_IRQHandler
-  .thumb_set EINT0_IRQHandler,Dummy_Handler
-
-  .weak EINT1_IRQHandler
-  .thumb_set EINT1_IRQHandler,Dummy_Handler
-
-  .weak EINT2_IRQHandler
-  .thumb_set EINT2_IRQHandler,Dummy_Handler
-
-  .weak EINT3_IRQHandler
-  .thumb_set EINT3_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak BOD_IRQHandler
-  .thumb_set BOD_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak CAN_IRQHandler
-  .thumb_set CAN_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak I2S_IRQHandler
-  .thumb_set I2S_IRQHandler,Dummy_Handler
-
-  .weak ENET_IRQHandler
-  .thumb_set ENET_IRQHandler,Dummy_Handler
-
-  .weak RIT_IRQHandler
-  .thumb_set RIT_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-  .weak PLL1_IRQHandler
-  .thumb_set PLL1_IRQHandler,Dummy_Handler
-
-  .weak USBActivity_IRQHandler
-  .thumb_set USBActivity_IRQHandler,Dummy_Handler
-
-  .weak CANActivity_IRQHandler
-  .thumb_set CANActivity_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak WDT_IRQHandler
-WDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART0_IRQHandler
-UART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART2_IRQHandler
-UART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART3_IRQHandler
-UART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM1_IRQHandler
-PWM1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_IRQHandler
-I2C2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI_IRQHandler
-SPI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PLL0_IRQHandler
-PLL0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT0_IRQHandler
-EINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT1_IRQHandler
-EINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT2_IRQHandler
-EINT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT3_IRQHandler
-EINT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_IRQHandler
-BOD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN_IRQHandler
-CAN_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S_IRQHandler
-I2S_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ENET_IRQHandler
-ENET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RIT_IRQHandler
-RIT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PLL1_IRQHandler
-PLL1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USBActivity_IRQHandler
-USBActivity_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CANActivity_IRQHandler
-CANActivity_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WDT_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word UART0_IRQHandler
-  .word UART1_IRQHandler
-  .word UART2_IRQHandler
-  .word UART3_IRQHandler
-  .word PWM1_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word SPI_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word PLL0_IRQHandler
-  .word RTC_IRQHandler
-  .word EINT0_IRQHandler
-  .word EINT1_IRQHandler
-  .word EINT2_IRQHandler
-  .word EINT3_IRQHandler
-  .word ADC_IRQHandler
-  .word BOD_IRQHandler
-  .word USB_IRQHandler
-  .word CAN_IRQHandler
-  .word DMA_IRQHandler
-  .word I2S_IRQHandler
-  .word ENET_IRQHandler
-  .word RIT_IRQHandler
-  .word MCPWM_IRQHandler
-  .word QEI_IRQHandler
-  .word PLL1_IRQHandler
-  .word USBActivity_IRQHandler
-  .word CANActivity_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/flash_placement.xml b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/lpc175x_6x.emProject b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/lpc175x_6x.emProject
deleted file mode 100644
index 691f8c3b..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/lpc175x_6x.emProject
+++ /dev/null
@@ -1,137 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc175x_6x" target="8" version="2">
-  <project Name="lpc175x_6x">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4357 Cortex-M4"
-      arm_architecture="v7M"
-      arm_core_type="Cortex-M3"
-      arm_endian="Little"
-      arm_fp_abi="Soft"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC1769"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="No"
-      c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X"
-      c_user_include_directories=".;../../src;$(rootDir)/hw;$(rootDir)/src;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/inc;$(rootDir)/lib/FreeRTOS-Kernel/include;$(rootDir)/lib/FreeRTOS-Kernel/portable/GCC/ARM_CM3"
-      debug_register_definition_file="LPC176x5x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="LPC1769_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../.."
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/LPC1700_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="lpcxpresso1769">
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_driver">
-            <folder Name="lpc_chip_175x_6x">
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/chip_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/clock_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc_driver/lpc_chip_175x_6x/src/uart_17xx_40xx.c" />
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC1700_Startup.s" />
-      <file file_name="LPC1700_Target.js" />
-      <file file_name="LPC1769_MemoryMap.xml" />
-      <file file_name="LPC176x5x_Registers.xml" />
-      <file file_name="LPC176x5x_Vectors.s" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder Name="lib">
-      <folder Name="FreeRTOS">
-        <folder Name="Source">
-          <folder Name="include">
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/croutine.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/deprecated_definitions.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/event_groups.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/FreeRTOS.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/list.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/message_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_prototypes.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_wrappers.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/portable.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/projdefs.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/queue.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/semphr.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stack_macros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/StackMacros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stream_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/task.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/timers.h" />
-          </folder>
-          <folder Name="portable">
-            <folder Name="GCC">
-              <folder Name="ARM_CM3">
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM3/port.c" />
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM3/portmacro.h" />
-              </folder>
-            </folder>
-            <folder Name="MemMang">
-              <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/MemMang/heap_4.c" />
-            </folder>
-          </folder>
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/list.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/queue.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/tasks.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/timers.c" />
-        </folder>
-        <file file_name="../../../../../lib/FreeRTOS/freertos_hook.c" />
-      </folder>
-    </folder>
-    <configuration
-      Name="LPCXpresso 1769"
-      c_preprocessor_definitions="BOARD_LPCXPRESSO1769" />
-  </project>
-  <configuration Name="LPCXpresso 1769" />
-</solution>
diff --git a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/thumb_crt0.s b/examples/device/cdc_msc_freertos/ses/lpc175x_6x/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc_freertos/ses/lpc175x_6x/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc_freertos/ses/nrf5x/flash_placement.xml b/examples/device/cdc_msc_freertos/ses/nrf5x/flash_placement.xml
deleted file mode 100644
index 951d2371..00000000
--- a/examples/device/cdc_msc_freertos/ses/nrf5x/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc_freertos/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml b/examples/device/cdc_msc_freertos/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml
deleted file mode 100644
index cc4056c0..00000000
--- a/examples/device/cdc_msc_freertos/ses/nrf5x/nRF52840_xxAA_MemoryMap.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="nRF52840_xxAA">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00100000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20000000" size="0x00040000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc_freertos/ses/nrf5x/nRF_Target.js b/examples/device/cdc_msc_freertos/ses/nrf5x/nRF_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc_freertos/ses/nrf5x/nRF_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc_freertos/ses/nrf5x/nrf52840_Registers.xml b/examples/device/cdc_msc_freertos/ses/nrf5x/nrf52840_Registers.xml
deleted file mode 100644
index 39f861f9..00000000
--- a/examples/device/cdc_msc_freertos/ses/nrf5x/nrf52840_Registers.xml
+++ /dev/null
@@ -1,22310 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="nrf52840" description="nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller ">
-  <RegisterGroup name="FICR" start="0x10000000" description="Factory information configuration registers">
-    <Register start="+0x010" size="4" name="CODEPAGESIZE" access="ReadOnly" description="Code memory page size" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CODEPAGESIZE" description="Code memory page size" />
-    </Register>
-    <Register start="+0x014" size="4" name="CODESIZE" access="ReadOnly" description="Code memory size" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CODESIZE" description="Code memory size in number of pages" />
-    </Register>
-    <Register start="+0x060+0" size="4" name="DEVICEID[0]" access="ReadOnly" description="Description collection[0]:  Device identifier" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEID" description="64 bit unique device identifier" />
-    </Register>
-    <Register start="+0x060+4" size="4" name="DEVICEID[1]" access="ReadOnly" description="Description collection[0]:  Device identifier" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEID" description="64 bit unique device identifier" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="ER[0]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="ER[1]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="ER[2]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="ER[3]" access="ReadOnly" description="Description collection[0]:  Encryption root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ER" description="Encryption root, word 0" />
-    </Register>
-    <Register start="+0x090+0" size="4" name="IR[0]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x090+4" size="4" name="IR[1]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x090+8" size="4" name="IR[2]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x090+12" size="4" name="IR[3]" access="ReadOnly" description="Description collection[0]:  Identity Root, word 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IR" description="Identity Root, word 0" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="DEVICEADDRTYPE" access="ReadOnly" description="Device address type" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEVICEADDRTYPE" description="Device address type">
-        <Enum name="Public" start="0" description="Public address" />
-        <Enum name="Random" start="1" description="Random address" />
-      </BitField>
-    </Register>
-    <Register start="+0x0A4+0" size="4" name="DEVICEADDR[0]" access="ReadOnly" description="Description collection[0]:  Device address 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEADDR" description="48 bit device address" />
-    </Register>
-    <Register start="+0x0A4+4" size="4" name="DEVICEADDR[1]" access="ReadOnly" description="Description collection[0]:  Device address 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DEVICEADDR" description="48 bit device address" />
-    </Register>
-    <Register start="+0x100+0x000" size="4" name="INFO.PART" access="ReadOnly" description="Part code" reset_value="0x00052840" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PART" description="Part code">
-        <Enum name="N52840" start="0x52840" description="nRF52840" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x004" size="4" name="INFO.VARIANT" access="ReadOnly" description="Part variant (hardware version and production configuration)" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VARIANT" description="Part variant (hardware version and production configuration). Encoded as ASCII.">
-        <Enum name="AAAA" start="0x41414141" description="AAAA" />
-        <Enum name="AAAB" start="0x41414142" description="AAAB" />
-        <Enum name="AABA" start="0x41414241" description="AABA" />
-        <Enum name="AABB" start="0x41414242" description="AABB" />
-        <Enum name="AAB0" start="0x41414230" description="AAB0" />
-        <Enum name="ABBA" start="0x41424241" description="ABBA" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x008" size="4" name="INFO.PACKAGE" access="ReadOnly" description="Package option" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PACKAGE" description="Package option">
-        <Enum name="QI" start="0x2004" description="QIxx - 73-pin aQFN" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x00C" size="4" name="INFO.RAM" access="ReadOnly" description="RAM variant" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RAM" description="RAM variant">
-        <Enum name="K16" start="0x10" description="16 kByte RAM" />
-        <Enum name="K32" start="0x20" description="32 kByte RAM" />
-        <Enum name="K64" start="0x40" description="64 kByte RAM" />
-        <Enum name="K128" start="0x80" description="128 kByte RAM" />
-        <Enum name="K256" start="0x100" description="256 kByte RAM" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x010" size="4" name="INFO.FLASH" access="ReadOnly" description="Flash variant" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FLASH" description="Flash variant">
-        <Enum name="K128" start="0x80" description="128 kByte FLASH" />
-        <Enum name="K256" start="0x100" description="256 kByte FLASH" />
-        <Enum name="K512" start="0x200" description="512 kByte FLASH" />
-        <Enum name="K1024" start="0x400" description="1 MByte FLASH" />
-        <Enum name="K2048" start="0x800" description="2 MByte FLASH" />
-        <Enum name="Unspecified" start="0xFFFFFFFF" description="Unspecified" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0x014+0" size="4" name="INFO.UNUSED0[0]" access="Read/Write" description="Description collection[0]: Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0x014+4" size="4" name="INFO.UNUSED0[1]" access="Read/Write" description="Description collection[0]: Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0x014+8" size="4" name="INFO.UNUSED0[2]" access="Read/Write" description="Description collection[0]: Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x404+0x000" size="4" name="TEMP.A0" access="ReadOnly" description="Slope definition A0" reset_value="0xFFFFF320" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x004" size="4" name="TEMP.A1" access="ReadOnly" description="Slope definition A1" reset_value="0xFFFFF343" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x008" size="4" name="TEMP.A2" access="ReadOnly" description="Slope definition A2" reset_value="0xFFFFF35D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x00C" size="4" name="TEMP.A3" access="ReadOnly" description="Slope definition A3" reset_value="0xFFFFF400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x010" size="4" name="TEMP.A4" access="ReadOnly" description="Slope definition A4" reset_value="0xFFFFF452" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x014" size="4" name="TEMP.A5" access="ReadOnly" description="Slope definition A5" reset_value="0xFFFFF37B" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A" description="A (slope definition) register." />
-    </Register>
-    <Register start="+0x404+0x018" size="4" name="TEMP.B0" access="ReadOnly" description="Y-intercept B0" reset_value="0xFFFF3FCC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x01C" size="4" name="TEMP.B1" access="ReadOnly" description="Y-intercept B1" reset_value="0xFFFF3F98" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x020" size="4" name="TEMP.B2" access="ReadOnly" description="Y-intercept B2" reset_value="0xFFFF3F98" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x024" size="4" name="TEMP.B3" access="ReadOnly" description="Y-intercept B3" reset_value="0xFFFF0012" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x028" size="4" name="TEMP.B4" access="ReadOnly" description="Y-intercept B4" reset_value="0xFFFF004D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x02C" size="4" name="TEMP.B5" access="ReadOnly" description="Y-intercept B5" reset_value="0xFFFF3E10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B" description="B (y-intercept)" />
-    </Register>
-    <Register start="+0x404+0x030" size="4" name="TEMP.T0" access="ReadOnly" description="Segment end T0" reset_value="0xFFFFFFE2" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x034" size="4" name="TEMP.T1" access="ReadOnly" description="Segment end T1" reset_value="0xFFFFFF00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x038" size="4" name="TEMP.T2" access="ReadOnly" description="Segment end T2" reset_value="0xFFFFFF14" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x03C" size="4" name="TEMP.T3" access="ReadOnly" description="Segment end T3" reset_value="0xFFFFFF19" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x404+0x040" size="4" name="TEMP.T4" access="ReadOnly" description="Segment end T4" reset_value="0xFFFFFF50" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T" description="T (segment end) register" />
-    </Register>
-    <Register start="+0x450+0x000" size="4" name="NFC.TAGHEADER0" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFF5F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MFGID" description="Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F" />
-      <BitField start="8" size="8" name="UD1" description="Unique identifier byte 1" />
-      <BitField start="16" size="8" name="UD2" description="Unique identifier byte 2" />
-      <BitField start="24" size="8" name="UD3" description="Unique identifier byte 3" />
-    </Register>
-    <Register start="+0x450+0x004" size="4" name="NFC.TAGHEADER1" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="UD4" description="Unique identifier byte 4" />
-      <BitField start="8" size="8" name="UD5" description="Unique identifier byte 5" />
-      <BitField start="16" size="8" name="UD6" description="Unique identifier byte 6" />
-      <BitField start="24" size="8" name="UD7" description="Unique identifier byte 7" />
-    </Register>
-    <Register start="+0x450+0x008" size="4" name="NFC.TAGHEADER2" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="UD8" description="Unique identifier byte 8" />
-      <BitField start="8" size="8" name="UD9" description="Unique identifier byte 9" />
-      <BitField start="16" size="8" name="UD10" description="Unique identifier byte 10" />
-      <BitField start="24" size="8" name="UD11" description="Unique identifier byte 11" />
-    </Register>
-    <Register start="+0x450+0x00C" size="4" name="NFC.TAGHEADER3" access="ReadOnly" description="Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="UD12" description="Unique identifier byte 12" />
-      <BitField start="8" size="8" name="UD13" description="Unique identifier byte 13" />
-      <BitField start="16" size="8" name="UD14" description="Unique identifier byte 14" />
-      <BitField start="24" size="8" name="UD15" description="Unique identifier byte 15" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UICR" start="0x10001000" description="User information configuration registers">
-    <Register start="+0x000" size="4" name="UNUSED0" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="UNUSED1" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="UNUSED2" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="UNUSED3" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014+0" size="4" name="NRFFW[0]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+4" size="4" name="NRFFW[1]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+8" size="4" name="NRFFW[2]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+12" size="4" name="NRFFW[3]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+16" size="4" name="NRFFW[4]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+20" size="4" name="NRFFW[5]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+24" size="4" name="NRFFW[6]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+28" size="4" name="NRFFW[7]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+32" size="4" name="NRFFW[8]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+36" size="4" name="NRFFW[9]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+40" size="4" name="NRFFW[10]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+44" size="4" name="NRFFW[11]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+48" size="4" name="NRFFW[12]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+52" size="4" name="NRFFW[13]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x014+56" size="4" name="NRFFW[14]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic firmware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFFW" description="Reserved for Nordic firmware design" />
-    </Register>
-    <Register start="+0x050+0" size="4" name="NRFHW[0]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+4" size="4" name="NRFHW[1]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+8" size="4" name="NRFHW[2]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+12" size="4" name="NRFHW[3]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+16" size="4" name="NRFHW[4]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+20" size="4" name="NRFHW[5]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+24" size="4" name="NRFHW[6]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+28" size="4" name="NRFHW[7]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+32" size="4" name="NRFHW[8]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+36" size="4" name="NRFHW[9]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+40" size="4" name="NRFHW[10]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x050+44" size="4" name="NRFHW[11]" access="Read/Write" description="Description collection[0]:  Reserved for Nordic hardware design" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="NRFHW" description="Reserved for Nordic hardware design" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="CUSTOMER[0]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="CUSTOMER[1]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="CUSTOMER[2]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="CUSTOMER[3]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="CUSTOMER[4]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="CUSTOMER[5]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="CUSTOMER[6]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="CUSTOMER[7]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="CUSTOMER[8]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="CUSTOMER[9]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="CUSTOMER[10]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="CUSTOMER[11]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="CUSTOMER[12]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="CUSTOMER[13]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="CUSTOMER[14]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="CUSTOMER[15]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="CUSTOMER[16]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+68" size="4" name="CUSTOMER[17]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+72" size="4" name="CUSTOMER[18]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+76" size="4" name="CUSTOMER[19]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+80" size="4" name="CUSTOMER[20]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+84" size="4" name="CUSTOMER[21]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+88" size="4" name="CUSTOMER[22]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+92" size="4" name="CUSTOMER[23]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+96" size="4" name="CUSTOMER[24]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+100" size="4" name="CUSTOMER[25]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+104" size="4" name="CUSTOMER[26]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+108" size="4" name="CUSTOMER[27]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+112" size="4" name="CUSTOMER[28]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+116" size="4" name="CUSTOMER[29]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+120" size="4" name="CUSTOMER[30]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x080+124" size="4" name="CUSTOMER[31]" access="Read/Write" description="Description collection[0]:  Reserved for customer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CUSTOMER" description="Reserved for customer" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PSELRESET[0]" access="Read/Write" description="Description collection[0]:  Mapping of the nRESET function" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number of PORT onto which nRESET is exposed" />
-      <BitField start="5" size="1" name="PORT" description="Port number onto which nRESET is exposed" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x200+4" size="4" name="PSELRESET[1]" access="Read/Write" description="Description collection[0]:  Mapping of the nRESET function" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number of PORT onto which nRESET is exposed" />
-      <BitField start="5" size="1" name="PORT" description="Port number onto which nRESET is exposed" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x208" size="4" name="APPROTECT" access="Read/Write" description="Access port protection" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PALL" description="Enable or disable access port protection.">
-        <Enum name="Disabled" start="0xFF" description="Disable" />
-        <Enum name="Enabled" start="0x00" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x20C" size="4" name="NFCPINS" access="Read/Write" description="Setting of pins dedicated to NFC functionality: NFC antenna or GPIO" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PROTECT" description="Setting of pins dedicated to NFC functionality">
-        <Enum name="Disabled" start="0" description="Operation as GPIO pins. Same protection as normal GPIO pins" />
-        <Enum name="NFC" start="1" description="Operation as NFC antenna pins. Configures the protection for NFC operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x210" size="4" name="DEBUGCTRL" access="Read/Write" description="Processor debug control" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPUNIDEN" description="Configure CPU non-intrusive debug features">
-        <Enum name="Enabled" start="0xFF" description="Enable CPU ITM and ETM functionality (default behavior)" />
-        <Enum name="Disabled" start="0x00" description="Disable CPU ITM and ETM functionality" />
-      </BitField>
-      <BitField start="8" size="8" name="CPUFPBEN" description="Configure CPU flash patch and breakpoint (FPB) unit behavior">
-        <Enum name="Enabled" start="0xFF" description="Enable CPU FPB unit (default behavior)" />
-        <Enum name="Disabled" start="0x00" description="Disable CPU FPB unit. Writes into the FPB registers will be ignored." />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="EXTSUPPLY" access="Read/Write" description="Enable external circuitry to be supplied from VDD pin. Applicable in high voltage mode only." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTSUPPLY" description="Enable external circuitry to be supplied from VDD pin (output of REG0 stage)">
-        <Enum name="Disabled" start="0" description="No current can be drawn from the VDD pin" />
-        <Enum name="Enabled" start="1" description="It is allowed to supply external circuitry from the VDD pin" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="REGOUT0" access="Read/Write" description="GPIO reference voltage / external output supply voltage in high voltage mode" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="VOUT" description="Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.">
-        <Enum name="1V8" start="0" description="1.8 V" />
-        <Enum name="2V1" start="1" description="2.1 V" />
-        <Enum name="2V4" start="2" description="2.4 V" />
-        <Enum name="2V7" start="3" description="2.7 V" />
-        <Enum name="3V0" start="4" description="3.0 V" />
-        <Enum name="3V3" start="5" description="3.3 V" />
-        <Enum name="DEFAULT" start="7" description="Default voltage: 1.8 V" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="POWER" start="0x40000000" description="Power control">
-    <Register start="+0x078" size="4" name="TASKS_CONSTLAT" access="WriteOnly" description="Enable constant latency mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x07C" size="4" name="TASKS_LOWPWR" access="WriteOnly" description="Enable low power mode (variable latency)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_POFWARN" access="Read/Write" description="Power failure warning" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_SLEEPENTER" access="Read/Write" description="CPU entered WFI/WFE sleep" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_SLEEPEXIT" access="Read/Write" description="CPU exited WFI/WFE sleep" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_USBDETECTED" access="Read/Write" description="Voltage supply detected on VBUS" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_USBREMOVED" access="Read/Write" description="Voltage supply removed from VBUS" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_USBPWRRDY" access="Read/Write" description="USB 3.3 V supply ready" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="POFWARN" description="Write '1' to Enable interrupt for POFWARN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SLEEPENTER" description="Write '1' to Enable interrupt for SLEEPENTER event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="SLEEPEXIT" description="Write '1' to Enable interrupt for SLEEPEXIT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="USBDETECTED" description="Write '1' to Enable interrupt for USBDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="USBREMOVED" description="Write '1' to Enable interrupt for USBREMOVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="USBPWRRDY" description="Write '1' to Enable interrupt for USBPWRRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="POFWARN" description="Write '1' to Disable interrupt for POFWARN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SLEEPENTER" description="Write '1' to Disable interrupt for SLEEPENTER event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="SLEEPEXIT" description="Write '1' to Disable interrupt for SLEEPEXIT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="USBDETECTED" description="Write '1' to Disable interrupt for USBDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="USBREMOVED" description="Write '1' to Disable interrupt for USBREMOVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="USBPWRRDY" description="Write '1' to Disable interrupt for USBPWRRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RESETREAS" access="Read/Write" description="Reset reason" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESETPIN" description="Reset from pin-reset detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="1" size="1" name="DOG" description="Reset from watchdog detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="2" size="1" name="SREQ" description="Reset from soft reset detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="3" size="1" name="LOCKUP" description="Reset from CPU lock-up detected">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="16" size="1" name="OFF" description="Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="17" size="1" name="LPCOMP" description="Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="18" size="1" name="DIF" description="Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="19" size="1" name="NFC" description="Reset due to wake up from System OFF mode by NFC field detect">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-      <BitField start="20" size="1" name="VBUS" description="Reset due to wake up from System OFF mode by Vbus rising into valid range">
-        <Enum name="NotDetected" start="0" description="Not detected" />
-        <Enum name="Detected" start="1" description="Detected" />
-      </BitField>
-    </Register>
-    <Register start="+0x428" size="4" name="RAMSTATUS" access="ReadOnly" description="Deprecated register -  RAM status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAMBLOCK0" description="RAM block 0 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="RAMBLOCK1" description="RAM block 1 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="RAMBLOCK2" description="RAM block 2 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="RAMBLOCK3" description="RAM block 3 is on or off/powering up">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x438" size="4" name="USBREGSTATUS" access="ReadOnly" description="USB supply status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VBUSDETECT" description="VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)">
-        <Enum name="NoVbus" start="0" description="VBUS voltage below valid threshold" />
-        <Enum name="VbusPresent" start="1" description="VBUS voltage above valid threshold" />
-      </BitField>
-      <BitField start="1" size="1" name="OUTPUTRDY" description="USB supply output settling time elapsed">
-        <Enum name="NotReady" start="0" description="USBREG output settling time not elapsed" />
-        <Enum name="Ready" start="1" description="USBREG output settling time elapsed (same information as USBPWRRDY event)" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="SYSTEMOFF" access="WriteOnly" description="System OFF register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYSTEMOFF" description="Enable System OFF mode">
-        <Enum name="Enter" start="1" description="Enable System OFF mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="POFCON" access="Read/Write" description="Power failure comparator configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POF" description="Enable or disable power failure comparator">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="4" name="THRESHOLD" description="Power failure comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only).">
-        <Enum name="V17" start="4" description="Set threshold to 1.7 V" />
-        <Enum name="V18" start="5" description="Set threshold to 1.8 V" />
-        <Enum name="V19" start="6" description="Set threshold to 1.9 V" />
-        <Enum name="V20" start="7" description="Set threshold to 2.0 V" />
-        <Enum name="V21" start="8" description="Set threshold to 2.1 V" />
-        <Enum name="V22" start="9" description="Set threshold to 2.2 V" />
-        <Enum name="V23" start="10" description="Set threshold to 2.3 V" />
-        <Enum name="V24" start="11" description="Set threshold to 2.4 V" />
-        <Enum name="V25" start="12" description="Set threshold to 2.5 V" />
-        <Enum name="V26" start="13" description="Set threshold to 2.6 V" />
-        <Enum name="V27" start="14" description="Set threshold to 2.7 V" />
-        <Enum name="V28" start="15" description="Set threshold to 2.8 V" />
-      </BitField>
-      <BitField start="8" size="4" name="THRESHOLDVDDH" description="Power failure comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).">
-        <Enum name="V27" start="0" description="Set threshold to 2.7 V" />
-        <Enum name="V28" start="1" description="Set threshold to 2.8 V" />
-        <Enum name="V29" start="2" description="Set threshold to 2.9 V" />
-        <Enum name="V30" start="3" description="Set threshold to 3.0 V" />
-        <Enum name="V31" start="4" description="Set threshold to 3.1 V" />
-        <Enum name="V32" start="5" description="Set threshold to 3.2 V" />
-        <Enum name="V33" start="6" description="Set threshold to 3.3 V" />
-        <Enum name="V34" start="7" description="Set threshold to 3.4 V" />
-        <Enum name="V35" start="8" description="Set threshold to 3.5 V" />
-        <Enum name="V36" start="9" description="Set threshold to 3.6 V" />
-        <Enum name="V37" start="10" description="Set threshold to 3.7 V" />
-        <Enum name="V38" start="11" description="Set threshold to 3.8 V" />
-        <Enum name="V39" start="12" description="Set threshold to 3.9 V" />
-        <Enum name="V40" start="13" description="Set threshold to 4.0 V" />
-        <Enum name="V41" start="14" description="Set threshold to 4.1 V" />
-        <Enum name="V42" start="15" description="Set threshold to 4.2 V" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="GPREGRET" access="Read/Write" description="General purpose retention register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="GPREGRET" description="General purpose retention register" />
-    </Register>
-    <Register start="+0x520" size="4" name="GPREGRET2" access="Read/Write" description="General purpose retention register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="GPREGRET" description="General purpose retention register" />
-    </Register>
-    <Register start="+0x578" size="4" name="DCDCEN" access="Read/Write" description="Enable DC/DC converter for REG1 stage." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCDCEN" description="Enable DC/DC converter for REG1 stage.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x580" size="4" name="DCDCEN0" access="Read/Write" description="Enable DC/DC converter for REG0 stage." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCDCEN" description="Enable DC/DC converter for REG0 stage.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x640" size="4" name="MAINREGSTATUS" access="ReadOnly" description="Main supply status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAINREGSTATUS" description="Main supply status">
-        <Enum name="Normal" start="0" description="Normal voltage mode. Voltage supplied on VDD." />
-        <Enum name="High" start="1" description="High voltage mode. Voltage supplied on VDDH." />
-      </BitField>
-    </Register>
-    <Register start="+0x900+0*16+0x000" size="4" name="RAM[0].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+0*16+0x004" size="4" name="RAM[0].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+0*16+0x008" size="4" name="RAM[0].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+1*16+0x000" size="4" name="RAM[1].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+1*16+0x004" size="4" name="RAM[1].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+1*16+0x008" size="4" name="RAM[1].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+2*16+0x000" size="4" name="RAM[2].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+2*16+0x004" size="4" name="RAM[2].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+2*16+0x008" size="4" name="RAM[2].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+3*16+0x000" size="4" name="RAM[3].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+3*16+0x004" size="4" name="RAM[3].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+3*16+0x008" size="4" name="RAM[3].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+4*16+0x000" size="4" name="RAM[4].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+4*16+0x004" size="4" name="RAM[4].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+4*16+0x008" size="4" name="RAM[4].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+5*16+0x000" size="4" name="RAM[5].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+5*16+0x004" size="4" name="RAM[5].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+5*16+0x008" size="4" name="RAM[5].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+6*16+0x000" size="4" name="RAM[6].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+6*16+0x004" size="4" name="RAM[6].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+6*16+0x008" size="4" name="RAM[6].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+7*16+0x000" size="4" name="RAM[7].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+7*16+0x004" size="4" name="RAM[7].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+7*16+0x008" size="4" name="RAM[7].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+8*16+0x000" size="4" name="RAM[8].POWER" access="Read/Write" description="Description cluster[0]:  RAM0 power control register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 ON or OFF in System ON mode.">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is in OFF">
-        <Enum name="Off" start="0" description="Off" />
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+8*16+0x004" size="4" name="RAM[8].POWERSET" access="WriteOnly" description="Description cluster[0]:  RAM0 power control set register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="On" start="1" description="On" />
-      </BitField>
-    </Register>
-    <Register start="+0x900+8*16+0x008" size="4" name="RAM[8].POWERCLR" access="WriteOnly" description="Description cluster[0]:  RAM0 power control clear register" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="S0POWER" description="Keep RAM section S0 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="1" size="1" name="S1POWER" description="Keep RAM section S1 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="2" size="1" name="S2POWER" description="Keep RAM section S2 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="3" size="1" name="S3POWER" description="Keep RAM section S3 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="4" size="1" name="S4POWER" description="Keep RAM section S4 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="5" size="1" name="S5POWER" description="Keep RAM section S5 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="6" size="1" name="S6POWER" description="Keep RAM section S6 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="7" size="1" name="S7POWER" description="Keep RAM section S7 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="8" size="1" name="S8POWER" description="Keep RAM section S8 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="9" size="1" name="S9POWER" description="Keep RAM section S9 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="10" size="1" name="S10POWER" description="Keep RAM section S10 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="11" size="1" name="S11POWER" description="Keep RAM section S11 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="12" size="1" name="S12POWER" description="Keep RAM section S12 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="13" size="1" name="S13POWER" description="Keep RAM section S13 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="14" size="1" name="S14POWER" description="Keep RAM section S14 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="15" size="1" name="S15POWER" description="Keep RAM section S15 of RAM0 on or off in System ON mode">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="16" size="1" name="S0RETENTION" description="Keep retention on RAM section S0 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="17" size="1" name="S1RETENTION" description="Keep retention on RAM section S1 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="18" size="1" name="S2RETENTION" description="Keep retention on RAM section S2 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="19" size="1" name="S3RETENTION" description="Keep retention on RAM section S3 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="20" size="1" name="S4RETENTION" description="Keep retention on RAM section S4 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="21" size="1" name="S5RETENTION" description="Keep retention on RAM section S5 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="22" size="1" name="S6RETENTION" description="Keep retention on RAM section S6 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="23" size="1" name="S7RETENTION" description="Keep retention on RAM section S7 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="24" size="1" name="S8RETENTION" description="Keep retention on RAM section S8 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="25" size="1" name="S9RETENTION" description="Keep retention on RAM section S9 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="26" size="1" name="S10RETENTION" description="Keep retention on RAM section S10 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="27" size="1" name="S11RETENTION" description="Keep retention on RAM section S11 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="28" size="1" name="S12RETENTION" description="Keep retention on RAM section S12 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="29" size="1" name="S13RETENTION" description="Keep retention on RAM section S13 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="30" size="1" name="S14RETENTION" description="Keep retention on RAM section S14 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-      <BitField start="31" size="1" name="S15RETENTION" description="Keep retention on RAM section S15 when RAM section is switched off">
-        <Enum name="Off" start="1" description="Off" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CLOCK" start="0x40000000" description="Clock control">
-    <Register start="+0x000" size="4" name="TASKS_HFCLKSTART" access="WriteOnly" description="Start HFCLK crystal oscillator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_HFCLKSTOP" access="WriteOnly" description="Stop HFCLK crystal oscillator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_LFCLKSTART" access="WriteOnly" description="Start LFCLK source" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_LFCLKSTOP" access="WriteOnly" description="Stop LFCLK source" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_CAL" access="WriteOnly" description="Start calibration of LFRC or LFULP oscillator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_CTSTART" access="WriteOnly" description="Start calibration timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x018" size="4" name="TASKS_CTSTOP" access="WriteOnly" description="Stop calibration timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_HFCLKSTARTED" access="Read/Write" description="HFCLK oscillator started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_LFCLKSTARTED" access="Read/Write" description="LFCLK started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_DONE" access="Read/Write" description="Calibration of LFCLK RC oscillator complete event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_CTTO" access="Read/Write" description="Calibration timer timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HFCLKSTARTED" description="Write '1' to Enable interrupt for HFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="LFCLKSTARTED" description="Write '1' to Enable interrupt for LFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DONE" description="Write '1' to Enable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CTTO" description="Write '1' to Enable interrupt for CTTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HFCLKSTARTED" description="Write '1' to Disable interrupt for HFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="LFCLKSTARTED" description="Write '1' to Disable interrupt for LFCLKSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DONE" description="Write '1' to Disable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CTTO" description="Write '1' to Disable interrupt for CTTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x408" size="4" name="HFCLKRUN" access="ReadOnly" description="Status indicating that HFCLKSTART task has been triggered" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="HFCLKSTART task triggered or not">
-        <Enum name="NotTriggered" start="0" description="Task not triggered" />
-        <Enum name="Triggered" start="1" description="Task triggered" />
-      </BitField>
-    </Register>
-    <Register start="+0x40C" size="4" name="HFCLKSTAT" access="ReadOnly" description="HFCLK status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SRC" description="Source of HFCLK">
-        <Enum name="RC" start="0" description="64 MHz internal oscillator (HFINT)" />
-        <Enum name="Xtal" start="1" description="64 MHz crystal oscillator (HFXO)" />
-      </BitField>
-      <BitField start="16" size="1" name="STATE" description="HFCLK state">
-        <Enum name="NotRunning" start="0" description="HFCLK not running" />
-        <Enum name="Running" start="1" description="HFCLK running" />
-      </BitField>
-    </Register>
-    <Register start="+0x414" size="4" name="LFCLKRUN" access="ReadOnly" description="Status indicating that LFCLKSTART task has been triggered" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="LFCLKSTART task triggered or not">
-        <Enum name="NotTriggered" start="0" description="Task not triggered" />
-        <Enum name="Triggered" start="1" description="Task triggered" />
-      </BitField>
-    </Register>
-    <Register start="+0x418" size="4" name="LFCLKSTAT" access="ReadOnly" description="LFCLK status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Source of LFCLK">
-        <Enum name="RC" start="0" description="32.768 kHz RC oscillator" />
-        <Enum name="Xtal" start="1" description="32.768 kHz crystal oscillator" />
-        <Enum name="Synth" start="2" description="32.768 kHz synthesized from HFCLK" />
-      </BitField>
-      <BitField start="16" size="1" name="STATE" description="LFCLK state">
-        <Enum name="NotRunning" start="0" description="LFCLK not running" />
-        <Enum name="Running" start="1" description="LFCLK running" />
-      </BitField>
-    </Register>
-    <Register start="+0x41C" size="4" name="LFCLKSRCCOPY" access="ReadOnly" description="Copy of LFCLKSRC register, set when LFCLKSTART task was triggered" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Clock source">
-        <Enum name="RC" start="0" description="32.768 kHz RC oscillator" />
-        <Enum name="Xtal" start="1" description="32.768 kHz crystal oscillator" />
-        <Enum name="Synth" start="2" description="32.768 kHz synthesized from HFCLK" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="LFCLKSRC" access="Read/Write" description="Clock source for the LFCLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Clock source">
-        <Enum name="RC" start="0" description="32.768 kHz RC oscillator" />
-        <Enum name="Xtal" start="1" description="32.768 kHz crystal oscillator" />
-        <Enum name="Synth" start="2" description="32.768 kHz synthesized from HFCLK" />
-      </BitField>
-      <BitField start="16" size="1" name="BYPASS" description="Enable or disable bypass of LFCLK crystal oscillator with external clock source">
-        <Enum name="Disabled" start="0" description="Disable (use with Xtal or low-swing external source)" />
-        <Enum name="Enabled" start="1" description="Enable (use with rail-to-rail external source)" />
-      </BitField>
-      <BitField start="17" size="1" name="EXTERNAL" description="Enable or disable external source for LFCLK">
-        <Enum name="Disabled" start="0" description="Disable external source (use with Xtal)" />
-        <Enum name="Enabled" start="1" description="Enable use of external source instead of Xtal (SRC needs to be set to Xtal)" />
-      </BitField>
-    </Register>
-    <Register start="+0x528" size="4" name="HFXODEBOUNCE" access="Read/Write" description="HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="HFXODEBOUNCE" description="HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us." />
-    </Register>
-    <Register start="+0x538" size="4" name="CTIV" access="Read/Write" description="Calibration timer interval" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CTIV" description="Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds." />
-    </Register>
-    <Register start="+0x55C" size="4" name="TRACECONFIG" access="Read/Write" description="Clocking options for the Trace Port debug interface" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TRACEPORTSPEED" description="Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.">
-        <Enum name="32MHz" start="0" description="32 MHz Trace Port clock (TRACECLK = 16 MHz)" />
-        <Enum name="16MHz" start="1" description="16 MHz Trace Port clock (TRACECLK = 8 MHz)" />
-        <Enum name="8MHz" start="2" description="8 MHz Trace Port clock (TRACECLK = 4 MHz)" />
-        <Enum name="4MHz" start="3" description="4 MHz Trace Port clock (TRACECLK = 2 MHz)" />
-      </BitField>
-      <BitField start="16" size="2" name="TRACEMUX" description="Pin multiplexing of trace signals. See pin assignment chapter for more details.">
-        <Enum name="GPIO" start="0" description="No trace signals routed to pins. All pins can be used as regular GPIOs." />
-        <Enum name="Serial" start="1" description="SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs." />
-        <Enum name="Parallel" start="2" description="All trace signals (TRACECLK and TRACEDATA[n]) routed to pins." />
-      </BitField>
-    </Register>
-    <Register start="+0x5B4" size="4" name="LFRCMODE" access="Read/Write" description="LFRC mode configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Set LFRC mode">
-        <Enum name="Normal" start="0" description="Normal mode" />
-        <Enum name="ULP" start="1" description="Ultra-low power mode (ULP)" />
-      </BitField>
-      <BitField start="16" size="1" name="STATUS" description="Active LFRC mode. This field is read only.">
-        <Enum name="Normal" start="0" description="Normal mode" />
-        <Enum name="ULP" start="1" description="Ultra-low power mode (ULP)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RADIO" start="0x40001000" description="2.4 GHz Radio">
-    <Register start="+0x000" size="4" name="TASKS_TXEN" access="WriteOnly" description="Enable RADIO in TX mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_RXEN" access="WriteOnly" description="Enable RADIO in RX mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_START" access="WriteOnly" description="Start RADIO" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RADIO" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_DISABLE" access="WriteOnly" description="Disable RADIO" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_RSSISTART" access="WriteOnly" description="Start the RSSI and take one single sample of the receive signal strength." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x018" size="4" name="TASKS_RSSISTOP" access="WriteOnly" description="Stop the RSSI measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_BCSTART" access="WriteOnly" description="Start the bit counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_BCSTOP" access="WriteOnly" description="Stop the bit counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x024" size="4" name="TASKS_EDSTART" access="WriteOnly" description="Start the Energy Detect measurement used in IEEE 802.15.4 mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_EDSTOP" access="WriteOnly" description="Stop the Energy Detect measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x02C" size="4" name="TASKS_CCASTART" access="WriteOnly" description="Start the Clear Channel Assessment used in IEEE 802.15.4 mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030" size="4" name="TASKS_CCASTOP" access="WriteOnly" description="Stop the Clear Channel Assessment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="RADIO has ramped up and is ready to be started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_ADDRESS" access="Read/Write" description="Address sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_PAYLOAD" access="Read/Write" description="Packet payload sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_END" access="Read/Write" description="Packet sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_DISABLED" access="Read/Write" description="RADIO has been disabled" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_DEVMATCH" access="Read/Write" description="A device address match occurred on the last received packet" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_DEVMISS" access="Read/Write" description="No device address match occurred on the last received packet" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_RSSIEND" access="Read/Write" description="Sampling of receive signal strength complete." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_BCMATCH" access="Read/Write" description="Bit counter reached bit count value." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130" size="4" name="EVENTS_CRCOK" access="Read/Write" description="Packet received with CRC ok" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x134" size="4" name="EVENTS_CRCERROR" access="Read/Write" description="Packet received with CRC error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_FRAMESTART" access="Read/Write" description="IEEE 802.15.4 length field received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x13C" size="4" name="EVENTS_EDEND" access="Read/Write" description="Sampling of Energy Detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140" size="4" name="EVENTS_EDSTOPPED" access="Read/Write" description="The sampling of Energy Detection has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_CCAIDLE" access="Read/Write" description="Wireless medium in idle - clear to send" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_CCABUSY" access="Read/Write" description="Wireless medium busy - do not send" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_CCASTOPPED" access="Read/Write" description="The CCA has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_RATEBOOST" access="Read/Write" description="Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x154" size="4" name="EVENTS_TXREADY" access="Read/Write" description="RADIO has ramped up and is ready to be started TX path" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_RXREADY" access="Read/Write" description="RADIO has ramped up and is ready to be started RX path" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_MHRMATCH" access="Read/Write" description="MAC Header match found." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x16C" size="4" name="EVENTS_PHYEND" access="Read/Write" description="Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY_START" description="Shortcut between READY event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="END_DISABLE" description="Shortcut between END event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="DISABLED_TXEN" description="Shortcut between DISABLED event and TXEN task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="DISABLED_RXEN" description="Shortcut between DISABLED event and RXEN task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="ADDRESS_RSSISTART" description="Shortcut between ADDRESS event and RSSISTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="ADDRESS_BCSTART" description="Shortcut between ADDRESS event and BCSTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="DISABLED_RSSISTOP" description="Shortcut between DISABLED event and RSSISTOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="RXREADY_CCASTART" description="Shortcut between RXREADY event and CCASTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="CCAIDLE_TXEN" description="Shortcut between CCAIDLE event and TXEN task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="CCABUSY_DISABLE" description="Shortcut between CCABUSY event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="14" size="1" name="FRAMESTART_BCSTART" description="Shortcut between FRAMESTART event and BCSTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="15" size="1" name="READY_EDSTART" description="Shortcut between READY event and EDSTART task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="16" size="1" name="EDEND_DISABLE" description="Shortcut between EDEND event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="17" size="1" name="CCAIDLE_STOP" description="Shortcut between CCAIDLE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="18" size="1" name="TXREADY_START" description="Shortcut between TXREADY event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="19" size="1" name="RXREADY_START" description="Shortcut between RXREADY event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="20" size="1" name="PHYEND_DISABLE" description="Shortcut between PHYEND event and DISABLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="21" size="1" name="PHYEND_START" description="Shortcut between PHYEND event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS" description="Write '1' to Enable interrupt for ADDRESS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="PAYLOAD" description="Write '1' to Enable interrupt for PAYLOAD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DISABLED" description="Write '1' to Enable interrupt for DISABLED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DEVMATCH" description="Write '1' to Enable interrupt for DEVMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DEVMISS" description="Write '1' to Enable interrupt for DEVMISS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RSSIEND" description="Write '1' to Enable interrupt for RSSIEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="BCMATCH" description="Write '1' to Enable interrupt for BCMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CRCOK" description="Write '1' to Enable interrupt for CRCOK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CRCERROR" description="Write '1' to Enable interrupt for CRCERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="FRAMESTART" description="Write '1' to Enable interrupt for FRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="EDEND" description="Write '1' to Enable interrupt for EDEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="EDSTOPPED" description="Write '1' to Enable interrupt for EDSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CCAIDLE" description="Write '1' to Enable interrupt for CCAIDLE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CCABUSY" description="Write '1' to Enable interrupt for CCABUSY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CCASTOPPED" description="Write '1' to Enable interrupt for CCASTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="RATEBOOST" description="Write '1' to Enable interrupt for RATEBOOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="TXREADY" description="Write '1' to Enable interrupt for TXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="RXREADY" description="Write '1' to Enable interrupt for RXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="MHRMATCH" description="Write '1' to Enable interrupt for MHRMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PHYEND" description="Write '1' to Enable interrupt for PHYEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS" description="Write '1' to Disable interrupt for ADDRESS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="PAYLOAD" description="Write '1' to Disable interrupt for PAYLOAD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DISABLED" description="Write '1' to Disable interrupt for DISABLED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DEVMATCH" description="Write '1' to Disable interrupt for DEVMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DEVMISS" description="Write '1' to Disable interrupt for DEVMISS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RSSIEND" description="Write '1' to Disable interrupt for RSSIEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="BCMATCH" description="Write '1' to Disable interrupt for BCMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CRCOK" description="Write '1' to Disable interrupt for CRCOK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CRCERROR" description="Write '1' to Disable interrupt for CRCERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="FRAMESTART" description="Write '1' to Disable interrupt for FRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="EDEND" description="Write '1' to Disable interrupt for EDEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="EDSTOPPED" description="Write '1' to Disable interrupt for EDSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CCAIDLE" description="Write '1' to Disable interrupt for CCAIDLE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CCABUSY" description="Write '1' to Disable interrupt for CCABUSY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CCASTOPPED" description="Write '1' to Disable interrupt for CCASTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="RATEBOOST" description="Write '1' to Disable interrupt for RATEBOOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="TXREADY" description="Write '1' to Disable interrupt for TXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="RXREADY" description="Write '1' to Disable interrupt for RXREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="MHRMATCH" description="Write '1' to Disable interrupt for MHRMATCH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PHYEND" description="Write '1' to Disable interrupt for PHYEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="CRCSTATUS" access="ReadOnly" description="CRC status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCSTATUS" description="CRC status of packet received">
-        <Enum name="CRCError" start="0" description="Packet received with CRC error" />
-        <Enum name="CRCOk" start="1" description="Packet received with CRC ok" />
-      </BitField>
-    </Register>
-    <Register start="+0x408" size="4" name="RXMATCH" access="ReadOnly" description="Received address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXMATCH" description="Received address" />
-    </Register>
-    <Register start="+0x40C" size="4" name="RXCRC" access="ReadOnly" description="CRC field of previously received packet" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RXCRC" description="CRC field of previously received packet" />
-    </Register>
-    <Register start="+0x410" size="4" name="DAI" access="ReadOnly" description="Device address match index" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DAI" description="Device address match index" />
-    </Register>
-    <Register start="+0x414" size="4" name="PDUSTAT" access="ReadOnly" description="Payload status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDUSTAT" description="Status on payload length vs. PCNF1.MAXLEN">
-        <Enum name="LessThan" start="0" description="Payload less than PCNF1.MAXLEN" />
-        <Enum name="GreaterThan" start="1" description="Payload greater than PCNF1.MAXLEN" />
-      </BitField>
-      <BitField start="1" size="2" name="CISTAT" description="Status on what rate packet is received with in Long Range">
-        <Enum name="LR125kbit" start="0" description="Frame is received at 125kbps" />
-        <Enum name="LR500kbit" start="1" description="Frame is received at 500kbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PACKETPTR" access="Read/Write" description="Packet pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PACKETPTR" description="Packet pointer" />
-    </Register>
-    <Register start="+0x508" size="4" name="FREQUENCY" access="Read/Write" description="Frequency" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="FREQUENCY" description="Radio channel frequency" />
-      <BitField start="8" size="1" name="MAP" description="Channel map selection.">
-        <Enum name="Default" start="0" description="Channel map between 2400 MHZ .. 2500 MHz" />
-        <Enum name="Low" start="1" description="Channel map between 2360 MHZ .. 2460 MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="TXPOWER" access="Read/Write" description="Output power" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXPOWER" description="RADIO output power.">
-        <Enum name="Pos8dBm" start="0x8" description="+8 dBm" />
-        <Enum name="Pos7dBm" start="0x7" description="+7 dBm" />
-        <Enum name="Pos6dBm" start="0x6" description="+6 dBm" />
-        <Enum name="Pos5dBm" start="0x5" description="+5 dBm" />
-        <Enum name="Pos4dBm" start="0x4" description="+4 dBm" />
-        <Enum name="Pos3dBm" start="0x3" description="+3 dBm" />
-        <Enum name="Pos2dBm" start="0x2" description="+2 dBm" />
-        <Enum name="0dBm" start="0x0" description="0 dBm" />
-        <Enum name="Neg4dBm" start="0xFC" description="-4 dBm" />
-        <Enum name="Neg8dBm" start="0xF8" description="-8 dBm" />
-        <Enum name="Neg12dBm" start="0xF4" description="-12 dBm" />
-        <Enum name="Neg16dBm" start="0xF0" description="-16 dBm" />
-        <Enum name="Neg20dBm" start="0xEC" description="-20 dBm" />
-        <Enum name="Neg30dBm" start="0xD8" description="Deprecated enumerator -  -40 dBm" />
-        <Enum name="Neg40dBm" start="0xD8" description="-40 dBm" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="MODE" access="Read/Write" description="Data rate and modulation" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MODE" description="Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.">
-        <Enum name="Nrf_1Mbit" start="0" description="1 Mbit/s Nordic proprietary radio mode" />
-        <Enum name="Nrf_2Mbit" start="1" description="2 Mbit/s Nordic proprietary radio mode" />
-        <Enum name="Nrf_250Kbit" start="2" description="Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode" />
-        <Enum name="Ble_1Mbit" start="3" description="1 Mbit/s Bluetooth Low Energy" />
-        <Enum name="Ble_2Mbit" start="4" description="2 Mbit/s Bluetooth Low Energy" />
-        <Enum name="Ble_LR125Kbit" start="5" description="Long range 125 kbit/s (TX Only - RX supports both)" />
-        <Enum name="Ble_LR500Kbit" start="6" description="Long range 500 kbit/s (TX Only - RX supports both)" />
-        <Enum name="Ieee802154_250Kbit" start="15" description="IEEE 802.15.4-2006 250 kbit/s" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="PCNF0" access="Read/Write" description="Packet configuration register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="LFLEN" description="Length on air of LENGTH field in number of bits." />
-      <BitField start="8" size="1" name="S0LEN" description="Length on air of S0 field in number of bytes." />
-      <BitField start="16" size="4" name="S1LEN" description="Length on air of S1 field in number of bits." />
-      <BitField start="20" size="1" name="S1INCL" description="Include or exclude S1 field in RAM">
-        <Enum name="Automatic" start="0" description="Include S1 field in RAM only if S1LEN &amp;gt; 0" />
-        <Enum name="Include" start="1" description="Always include S1 field in RAM independent of S1LEN" />
-      </BitField>
-      <BitField start="22" size="2" name="CILEN" description="Length of Code Indicator - Long Range" />
-      <BitField start="24" size="2" name="PLEN" description="Length of preamble on air. Decision point: TASKS_START task">
-        <Enum name="8bit" start="0" description="8-bit preamble" />
-        <Enum name="16bit" start="1" description="16-bit preamble" />
-        <Enum name="32bitZero" start="2" description="32-bit zero preamble - used for IEEE 802.15.4" />
-        <Enum name="LongRange" start="3" description="Preamble - used for BTLE Long Range" />
-      </BitField>
-      <BitField start="26" size="1" name="CRCINC" description="Indicates if LENGTH field contains CRC or not">
-        <Enum name="Exclude" start="0" description="LENGTH does not contain CRC" />
-        <Enum name="Include" start="1" description="LENGTH includes CRC" />
-      </BitField>
-      <BitField start="29" size="2" name="TERMLEN" description="Length of TERM field in Long Range operation" />
-    </Register>
-    <Register start="+0x518" size="4" name="PCNF1" access="Read/Write" description="Packet configuration register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXLEN" description="Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN." />
-      <BitField start="8" size="8" name="STATLEN" description="Static length in number of bytes" />
-      <BitField start="16" size="3" name="BALEN" description="Base address length in number of bytes" />
-      <BitField start="24" size="1" name="ENDIAN" description="On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.">
-        <Enum name="Little" start="0" description="Least Significant bit on air first" />
-        <Enum name="Big" start="1" description="Most significant bit on air first" />
-      </BitField>
-      <BitField start="25" size="1" name="WHITEEN" description="Enable or disable packet whitening">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="BASE0" access="Read/Write" description="Base address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASE0" description="Base address 0" />
-    </Register>
-    <Register start="+0x520" size="4" name="BASE1" access="Read/Write" description="Base address 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASE1" description="Base address 1" />
-    </Register>
-    <Register start="+0x524" size="4" name="PREFIX0" access="Read/Write" description="Prefixes bytes for logical addresses 0-3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AP0" description="Address prefix 0." />
-      <BitField start="8" size="8" name="AP1" description="Address prefix 1." />
-      <BitField start="16" size="8" name="AP2" description="Address prefix 2." />
-      <BitField start="24" size="8" name="AP3" description="Address prefix 3." />
-    </Register>
-    <Register start="+0x528" size="4" name="PREFIX1" access="Read/Write" description="Prefixes bytes for logical addresses 4-7" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AP4" description="Address prefix 4." />
-      <BitField start="8" size="8" name="AP5" description="Address prefix 5." />
-      <BitField start="16" size="8" name="AP6" description="Address prefix 6." />
-      <BitField start="24" size="8" name="AP7" description="Address prefix 7." />
-    </Register>
-    <Register start="+0x52C" size="4" name="TXADDRESS" access="Read/Write" description="Transmit address select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="TXADDRESS" description="Transmit address select" />
-    </Register>
-    <Register start="+0x530" size="4" name="RXADDRESSES" access="Read/Write" description="Receive address select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADDR0" description="Enable or disable reception on logical address 0.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDR1" description="Enable or disable reception on logical address 1.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="ADDR2" description="Enable or disable reception on logical address 2.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="ADDR3" description="Enable or disable reception on logical address 3.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ADDR4" description="Enable or disable reception on logical address 4.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="ADDR5" description="Enable or disable reception on logical address 5.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="ADDR6" description="Enable or disable reception on logical address 6.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="ADDR7" description="Enable or disable reception on logical address 7.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x534" size="4" name="CRCCNF" access="Read/Write" description="CRC configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LEN" description="CRC length in number of bytes.">
-        <Enum name="Disabled" start="0" description="CRC length is zero and CRC calculation is disabled" />
-        <Enum name="One" start="1" description="CRC length is one byte and CRC calculation is enabled" />
-        <Enum name="Two" start="2" description="CRC length is two bytes and CRC calculation is enabled" />
-        <Enum name="Three" start="3" description="CRC length is three bytes and CRC calculation is enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="SKIPADDR" description="Include or exclude packet address field out of CRC calculation.">
-        <Enum name="Include" start="0" description="CRC calculation includes address field" />
-        <Enum name="Skip" start="1" description="CRC calculation does not include address field. The CRC calculation will start at the first byte after the address." />
-        <Enum name="Ieee802154" start="2" description="CRC calculation as per 802.15.4 standard. Starting at first byte after length field." />
-      </BitField>
-    </Register>
-    <Register start="+0x538" size="4" name="CRCPOLY" access="Read/Write" description="CRC polynomial" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CRCPOLY" description="CRC polynomial" />
-    </Register>
-    <Register start="+0x53C" size="4" name="CRCINIT" access="Read/Write" description="CRC initial value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CRCINIT" description="CRC initial value" />
-    </Register>
-    <Register start="+0x544" size="4" name="TIFS" access="Read/Write" description="Inter Frame Spacing in us" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="TIFS" description="Inter Frame Spacing in us" />
-    </Register>
-    <Register start="+0x548" size="4" name="RSSISAMPLE" access="ReadOnly" description="RSSI sample" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RSSISAMPLE" description="RSSI sample" />
-    </Register>
-    <Register start="+0x550" size="4" name="STATE" access="ReadOnly" description="Current radio state" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="STATE" description="Current radio state">
-        <Enum name="Disabled" start="0" description="RADIO is in the Disabled state" />
-        <Enum name="RxRu" start="1" description="RADIO is in the RXRU state" />
-        <Enum name="RxIdle" start="2" description="RADIO is in the RXIDLE state" />
-        <Enum name="Rx" start="3" description="RADIO is in the RX state" />
-        <Enum name="RxDisable" start="4" description="RADIO is in the RXDISABLED state" />
-        <Enum name="TxRu" start="9" description="RADIO is in the TXRU state" />
-        <Enum name="TxIdle" start="10" description="RADIO is in the TXIDLE state" />
-        <Enum name="Tx" start="11" description="RADIO is in the TX state" />
-        <Enum name="TxDisable" start="12" description="RADIO is in the TXDISABLED state" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="DATAWHITEIV" access="Read/Write" description="Data whitening initial value" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DATAWHITEIV" description="Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'." />
-    </Register>
-    <Register start="+0x560" size="4" name="BCC" access="Read/Write" description="Bit counter compare" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BCC" description="Bit counter compare" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="DAB[0]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="DAB[1]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="DAB[2]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="DAB[3]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="DAB[4]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="DAB[5]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="DAB[6]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="DAB[7]" access="Read/Write" description="Description collection[0]:  Device address base segment 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DAB" description="Device address base segment 0" />
-    </Register>
-    <Register start="+0x620+0" size="4" name="DAP[0]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+4" size="4" name="DAP[1]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+8" size="4" name="DAP[2]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+12" size="4" name="DAP[3]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+16" size="4" name="DAP[4]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+20" size="4" name="DAP[5]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+24" size="4" name="DAP[6]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x620+28" size="4" name="DAP[7]" access="Read/Write" description="Description collection[0]:  Device address prefix 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DAP" description="Device address prefix 0" />
-    </Register>
-    <Register start="+0x640" size="4" name="DACNF" access="Read/Write" description="Device address match configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA0" description="Enable or disable device address matching using device address 0">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ENA1" description="Enable or disable device address matching using device address 1">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ENA2" description="Enable or disable device address matching using device address 2">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="ENA3" description="Enable or disable device address matching using device address 3">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENA4" description="Enable or disable device address matching using device address 4">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="ENA5" description="Enable or disable device address matching using device address 5">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="ENA6" description="Enable or disable device address matching using device address 6">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ENA7" description="Enable or disable device address matching using device address 7">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TXADD0" description="TxAdd for device address 0" />
-      <BitField start="9" size="1" name="TXADD1" description="TxAdd for device address 1" />
-      <BitField start="10" size="1" name="TXADD2" description="TxAdd for device address 2" />
-      <BitField start="11" size="1" name="TXADD3" description="TxAdd for device address 3" />
-      <BitField start="12" size="1" name="TXADD4" description="TxAdd for device address 4" />
-      <BitField start="13" size="1" name="TXADD5" description="TxAdd for device address 5" />
-      <BitField start="14" size="1" name="TXADD6" description="TxAdd for device address 6" />
-      <BitField start="15" size="1" name="TXADD7" description="TxAdd for device address 7" />
-    </Register>
-    <Register start="+0x644" size="4" name="MHRMATCHCONF" access="Read/Write" description="Search Pattern Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x648" size="4" name="MHRMATCHMAS" access="Read/Write" description="Pattern mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x650" size="4" name="MODECNF0" access="Read/Write" description="Radio mode configuration register 0" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RU" description="Radio ramp-up time">
-        <Enum name="Default" start="0" description="Default ramp-up time (tRXEN), compatible with firmware written for nRF51" />
-        <Enum name="Fast" start="1" description="Fast ramp-up (tRXEN,FAST), see electrical specification for more information" />
-      </BitField>
-      <BitField start="8" size="2" name="DTX" description="Default TX value">
-        <Enum name="B1" start="0" description="Transmit '1'" />
-        <Enum name="B0" start="1" description="Transmit '0'" />
-        <Enum name="Center" start="2" description="Transmit center frequency" />
-      </BitField>
-    </Register>
-    <Register start="+0x660" size="4" name="SFD" access="Read/Write" description="IEEE 802.15.4 Start of Frame Delimiter" reset_value="0x000000A7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SFD" description="IEEE 802.15.4 Start of Frame Delimiter. Note, the least significant 4-bits of the SFD cannot all be zeros." />
-    </Register>
-    <Register start="+0x664" size="4" name="EDCNT" access="Read/Write" description="IEEE 802.15.4 Energy Detect Loop Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="21" name="EDCNT" description="IEEE 802.15.4 Energy Detect Loop Count" />
-    </Register>
-    <Register start="+0x668" size="4" name="EDSAMPLE" access="Read/Write" description="IEEE 802.15.4 Energy Detect Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EDLVL" description="IEEE 802.15.4 Energy Detect Level" />
-    </Register>
-    <Register start="+0x66C" size="4" name="CCACTRL" access="Read/Write" description="IEEE 802.15.4 Clear Channel Assessment Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CCAMODE" description="CCA Mode Of Operation">
-        <Enum name="EdMode" start="0" description="Energy Above Threshold" />
-        <Enum name="CarrierMode" start="1" description="Carrier Seen" />
-        <Enum name="CarrierAndEdMode" start="2" description="Energy Above Threshold AND Carrier Seen" />
-        <Enum name="CarrierOrEdMode" start="3" description="Energy Above Threshold OR Carrier Seen" />
-        <Enum name="EdModeTest1" start="4" description="Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging." />
-      </BitField>
-      <BitField start="8" size="8" name="CCAEDTHRES" description="CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode." />
-      <BitField start="16" size="8" name="CCACORRTHRES" description="CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode." />
-      <BitField start="24" size="8" name="CCACORRCNT" description="Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled." />
-    </Register>
-    <Register start="+0xFFC" size="4" name="POWER" access="Read/Write" description="Peripheral power control" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER" description="Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.">
-        <Enum name="Disabled" start="0" description="Peripheral is powered off" />
-        <Enum name="Enabled" start="1" description="Peripheral is powered on" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UARTE0" start="0x40002000" description="UART with EasyDMA 0">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPRX" access="WriteOnly" description="Stop UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOPTX" access="WriteOnly" description="Stop UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x02C" size="4" name="TASKS_FLUSHRX" access="WriteOnly" description="Flush RX FIFO into RX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_CTS" access="Read/Write" description="CTS is activated (set low). Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_NCTS" access="Read/Write" description="CTS is deactivated (set high). Not Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDRDY" access="Read/Write" description="Data received in RXD (but potentially not yet transferred to Data RAM)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="Receive buffer is filled up" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDRDY" access="Read/Write" description="Data sent from TXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="Last TX byte transmitted" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="Error detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_RXTO" access="Read/Write" description="Receiver timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="UART receiver has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="UART transmitter has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_TXSTOPPED" access="Read/Write" description="Transmitter stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="ENDRX_STARTRX" description="Shortcut between ENDRX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDRX_STOPRX" description="Shortcut between ENDRX event and STOPRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Enable or disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Enable or disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Enable or disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Enable or disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Enable or disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Enable or disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Enable or disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Enable or disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Enable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Enable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Enable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Enable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Enable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Enable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x480" size="4" name="ERRORSRC" access="Read/Write" description="Error source Note : this register is read / write one to clear." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="PARITY" description="Parity error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="FRAMING" description="Framing error occurred">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="3" size="1" name="BREAK" description="Break condition">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable UARTE">
-        <Enum name="Disabled" start="0" description="Disable UARTE" />
-        <Enum name="Enabled" start="8" description="Enable UARTE" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="BAUDRATE" access="Read/Write" description="Baud rate. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BAUDRATE" description="Baud rate">
-        <Enum name="Baud1200" start="0x0004F000" description="1200 baud (actual rate: 1205)" />
-        <Enum name="Baud2400" start="0x0009D000" description="2400 baud (actual rate: 2396)" />
-        <Enum name="Baud4800" start="0x0013B000" description="4800 baud (actual rate: 4808)" />
-        <Enum name="Baud9600" start="0x00275000" description="9600 baud (actual rate: 9598)" />
-        <Enum name="Baud14400" start="0x003AF000" description="14400 baud (actual rate: 14401)" />
-        <Enum name="Baud19200" start="0x004EA000" description="19200 baud (actual rate: 19208)" />
-        <Enum name="Baud28800" start="0x0075C000" description="28800 baud (actual rate: 28777)" />
-        <Enum name="Baud31250" start="0x00800000" description="31250 baud" />
-        <Enum name="Baud38400" start="0x009D0000" description="38400 baud (actual rate: 38369)" />
-        <Enum name="Baud56000" start="0x00E50000" description="56000 baud (actual rate: 55944)" />
-        <Enum name="Baud57600" start="0x00EB0000" description="57600 baud (actual rate: 57554)" />
-        <Enum name="Baud76800" start="0x013A9000" description="76800 baud (actual rate: 76923)" />
-        <Enum name="Baud115200" start="0x01D60000" description="115200 baud (actual rate: 115108)" />
-        <Enum name="Baud230400" start="0x03B00000" description="230400 baud (actual rate: 231884)" />
-        <Enum name="Baud250000" start="0x04000000" description="250000 baud" />
-        <Enum name="Baud460800" start="0x07400000" description="460800 baud (actual rate: 457143)" />
-        <Enum name="Baud921600" start="0x0F000000" description="921600 baud (actual rate: 941176)" />
-        <Enum name="Baud1M" start="0x10000000" description="1Mega baud" />
-      </BitField>
-    </Register>
-    <Register start="+0x56C" size="4" name="CONFIG" access="Read/Write" description="Configuration of parity and hardware flow control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HWFC" description="Hardware flow control">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="3" name="PARITY" description="Parity">
-        <Enum name="Excluded" start="0x0" description="Exclude parity bit" />
-        <Enum name="Included" start="0x7" description="Include even parity bit" />
-      </BitField>
-      <BitField start="4" size="1" name="STOP" description="Stop bits">
-        <Enum name="One" start="0" description="One stop bit" />
-        <Enum name="Two" start="1" description="Two stop bits" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.RTS" access="Read/Write" description="Pin select for RTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.TXD" access="Read/Write" description="Pin select for TXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.CTS" access="Read/Write" description="Pin select for CTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.RXD" access="Read/Write" description="Pin select for RXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x40002000" description="Universal Asynchronous Receiver/Transmitter">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPRX" access="WriteOnly" description="Stop UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOPTX" access="WriteOnly" description="Stop UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_CTS" access="Read/Write" description="CTS is activated (set low). Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_NCTS" access="Read/Write" description="CTS is deactivated (set high). Not Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDRDY" access="Read/Write" description="Data received in RXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDRDY" access="Read/Write" description="Data sent from TXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="Error detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_RXTO" access="Read/Write" description="Receiver timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="CTS_STARTRX" description="Shortcut between CTS event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="NCTS_STOPRX" description="Shortcut between NCTS event and STOPRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Enable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Enable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Enable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Enable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Enable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x480" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="PARITY" description="Parity error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="FRAMING" description="Framing error occurred">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="3" size="1" name="BREAK" description="Break condition">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable UART">
-        <Enum name="Disabled" start="0" description="Disable UART" />
-        <Enum name="Enabled" start="4" description="Enable UART" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received in previous transfers, double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="WriteOnly" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to be transferred" />
-    </Register>
-    <Register start="+0x524" size="4" name="BAUDRATE" access="Read/Write" description="Baud rate. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BAUDRATE" description="Baud rate">
-        <Enum name="Baud1200" start="0x0004F000" description="1200 baud (actual rate: 1205)" />
-        <Enum name="Baud2400" start="0x0009D000" description="2400 baud (actual rate: 2396)" />
-        <Enum name="Baud4800" start="0x0013B000" description="4800 baud (actual rate: 4808)" />
-        <Enum name="Baud9600" start="0x00275000" description="9600 baud (actual rate: 9598)" />
-        <Enum name="Baud14400" start="0x003B0000" description="14400 baud (actual rate: 14414)" />
-        <Enum name="Baud19200" start="0x004EA000" description="19200 baud (actual rate: 19208)" />
-        <Enum name="Baud28800" start="0x0075F000" description="28800 baud (actual rate: 28829)" />
-        <Enum name="Baud31250" start="0x00800000" description="31250 baud" />
-        <Enum name="Baud38400" start="0x009D5000" description="38400 baud (actual rate: 38462)" />
-        <Enum name="Baud56000" start="0x00E50000" description="56000 baud (actual rate: 55944)" />
-        <Enum name="Baud57600" start="0x00EBF000" description="57600 baud (actual rate: 57762)" />
-        <Enum name="Baud76800" start="0x013A9000" description="76800 baud (actual rate: 76923)" />
-        <Enum name="Baud115200" start="0x01D7E000" description="115200 baud (actual rate: 115942)" />
-        <Enum name="Baud230400" start="0x03AFB000" description="230400 baud (actual rate: 231884)" />
-        <Enum name="Baud250000" start="0x04000000" description="250000 baud" />
-        <Enum name="Baud460800" start="0x075F7000" description="460800 baud (actual rate: 470588)" />
-        <Enum name="Baud921600" start="0x0EBED000" description="921600 baud (actual rate: 941176)" />
-        <Enum name="Baud1M" start="0x10000000" description="1Mega baud" />
-      </BitField>
-    </Register>
-    <Register start="+0x56C" size="4" name="CONFIG" access="Read/Write" description="Configuration of parity and hardware flow control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HWFC" description="Hardware flow control">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="3" name="PARITY" description="Parity">
-        <Enum name="Excluded" start="0x0" description="Exclude parity bit" />
-        <Enum name="Included" start="0x7" description="Include parity bit" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.RTS" access="Read/Write" description="Pin select for RTS" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.TXD" access="Read/Write" description="Pin select for TXD" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.CTS" access="Read/Write" description="Pin select for CTS" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.RXD" access="Read/Write" description="Pin select for RXD" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM0" start="0x40003000" description="Serial Peripheral Interface Master with EasyDMA 0">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIS0" start="0x40003000" description="SPI Slave 0">
-    <Register start="+0x024" size="4" name="TASKS_ACQUIRE" access="WriteOnly" description="Acquire SPI semaphore" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_RELEASE" access="WriteOnly" description="Release SPI semaphore, enabling the SPI slave to acquire it" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="Granted transaction completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_ACQUIRED" access="Read/Write" description="Semaphore acquired" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="END_ACQUIRE" description="Shortcut between END event and ACQUIRE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Enable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Disable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="SEMSTAT" access="ReadOnly" description="Semaphore status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEMSTAT" description="Semaphore status">
-        <Enum name="Free" start="0" description="Semaphore is free" />
-        <Enum name="CPU" start="1" description="Semaphore is assigned to CPU" />
-        <Enum name="SPIS" start="2" description="Semaphore is assigned to SPI slave" />
-        <Enum name="CPUPending" start="3" description="Semaphore is assigned to SPI but a handover to the CPU is pending" />
-      </BitField>
-    </Register>
-    <Register start="+0x440" size="4" name="STATUS" access="Read/Write" description="Status from last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI slave">
-        <Enum name="Disabled" start="0" description="Disable SPI slave" />
-        <Enum name="Enabled" start="2" description="Enable SPI slave" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x55C" size="4" name="DEF" access="Read/Write" description="Default character. Character clocked out in case of an ignored transaction." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEF" description="Default character. Character clocked out in case of an ignored transaction." />
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character clocked out after an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes received in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes received in the last granted transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transmitted in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transmitted in last granted transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIM0" start="0x40003000" description="I2C compatible Two-Wire Master Interface with EasyDMA 0">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction. Must be issued while the TWI master is not suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_LASTRX" access="Read/Write" description="Byte boundary, starting to receive the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160" size="4" name="EVENTS_LASTTX" access="Read/Write" description="Byte boundary, starting to transmit the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="LASTTX_STARTRX" description="Shortcut between LASTTX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="LASTTX_SUSPEND" description="Shortcut between LASTTX event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="LASTTX_STOP" description="Shortcut between LASTTX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="LASTRX_STARTTX" description="Shortcut between LASTRX event and STARTTX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="LASTRX_STOP" description="Shortcut between LASTRX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Enable or disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Enable or disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Enable or disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Enable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Enable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIM">
-        <Enum name="Disabled" start="0" description="Disable TWIM" />
-        <Enum name="Enabled" start="6" description="Enable TWIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06400000" description="400 kbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIS0" start="0x40003000" description="I2C compatible Two-Wire Slave Interface with EasyDMA 0">
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030" size="4" name="TASKS_PREPARERX" access="WriteOnly" description="Prepare the TWI slave to respond to a write command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x034" size="4" name="TASKS_PREPARETX" access="WriteOnly" description="Prepare the TWI slave to respond to a read command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x164" size="4" name="EVENTS_WRITE" access="Read/Write" description="Write command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x168" size="4" name="EVENTS_READ" access="Read/Write" description="Read command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="1" name="WRITE_SUSPEND" description="Shortcut between WRITE event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="14" size="1" name="READ_SUSPEND" description="Shortcut between READ event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Enable or disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Enable or disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Enable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Enable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D0" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK sent after receiving a data byte">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="3" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D4" size="4" name="MATCH" access="ReadOnly" description="Status register indicating which address had a match" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH" description="Which of the addresses in {ADDRESS} matched the incoming address" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIS" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIS">
-        <Enum name="Disabled" start="0" description="Disable TWIS" />
-        <Enum name="Enabled" start="9" description="Enable TWIS" />
-      </BitField>
-    </Register>
-    <Register start="+0x588+0" size="4" name="ADDRESS[0]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x588+4" size="4" name="ADDRESS[1]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x594" size="4" name="CONFIG" access="Read/Write" description="Configuration register for the address match mechanism" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADDRESS0" description="Enable or disable address matching on ADDRESS[0]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS1" description="Enable or disable address matching on ADDRESS[1]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in RXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in RXD buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last RXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last RXD transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in TXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in TXD buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last TXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last TXD transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI0" start="0x40003000" description="Serial Peripheral Interface 0">
-    <Register start="+0x108" size="4" name="EVENTS_READY" access="Read/Write" description="TXD byte sent and RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI">
-        <Enum name="Disabled" start="0" description="Disable SPI" />
-        <Enum name="Enabled" start="1" description="Enable SPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received. Double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to send. Double buffered" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWI0" start="0x40003000" description="I2C compatible Two-Wire Interface 0">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDREADY" access="Read/Write" description="TWI RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDSENT" access="Read/Write" description="TWI TXD byte sent" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_BB" access="Read/Write" description="TWI byte boundary, generated before each byte that is sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="TWI entered the suspended state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BB_SUSPEND" description="Shortcut between BB event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="BB_STOP" description="Shortcut between BB event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Enable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Enable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Enable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Disable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Disable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Disable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: no overrun occured" />
-        <Enum name="Present" start="1" description="Read: overrun occured" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWI">
-        <Enum name="Disabled" start="0" description="Disable TWI" />
-        <Enum name="Enabled" start="5" description="Enable TWI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RXD register" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TXD register" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06680000" description="400 kbps (actual rate 410.256 kbps)" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM1" start="0x40004000" description="Serial Peripheral Interface Master with EasyDMA 1">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIS1" start="0x40004000" description="SPI Slave 1">
-    <Register start="+0x024" size="4" name="TASKS_ACQUIRE" access="WriteOnly" description="Acquire SPI semaphore" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_RELEASE" access="WriteOnly" description="Release SPI semaphore, enabling the SPI slave to acquire it" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="Granted transaction completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_ACQUIRED" access="Read/Write" description="Semaphore acquired" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="END_ACQUIRE" description="Shortcut between END event and ACQUIRE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Enable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Disable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="SEMSTAT" access="ReadOnly" description="Semaphore status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEMSTAT" description="Semaphore status">
-        <Enum name="Free" start="0" description="Semaphore is free" />
-        <Enum name="CPU" start="1" description="Semaphore is assigned to CPU" />
-        <Enum name="SPIS" start="2" description="Semaphore is assigned to SPI slave" />
-        <Enum name="CPUPending" start="3" description="Semaphore is assigned to SPI but a handover to the CPU is pending" />
-      </BitField>
-    </Register>
-    <Register start="+0x440" size="4" name="STATUS" access="Read/Write" description="Status from last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI slave">
-        <Enum name="Disabled" start="0" description="Disable SPI slave" />
-        <Enum name="Enabled" start="2" description="Enable SPI slave" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x55C" size="4" name="DEF" access="Read/Write" description="Default character. Character clocked out in case of an ignored transaction." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEF" description="Default character. Character clocked out in case of an ignored transaction." />
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character clocked out after an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes received in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes received in the last granted transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transmitted in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transmitted in last granted transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIM1" start="0x40004000" description="I2C compatible Two-Wire Master Interface with EasyDMA 1">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction. Must be issued while the TWI master is not suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_LASTRX" access="Read/Write" description="Byte boundary, starting to receive the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160" size="4" name="EVENTS_LASTTX" access="Read/Write" description="Byte boundary, starting to transmit the last byte" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="LASTTX_STARTRX" description="Shortcut between LASTTX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="LASTTX_SUSPEND" description="Shortcut between LASTTX event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="LASTTX_STOP" description="Shortcut between LASTTX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="LASTRX_STARTTX" description="Shortcut between LASTRX event and STARTTX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="LASTRX_STOP" description="Shortcut between LASTRX event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Enable or disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Enable or disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Enable or disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Enable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Enable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="LASTRX" description="Write '1' to Disable interrupt for LASTRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="LASTTX" description="Write '1' to Disable interrupt for LASTTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIM">
-        <Enum name="Disabled" start="0" description="Disable TWIM" />
-        <Enum name="Enabled" start="6" description="Enable TWIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06400000" description="400 kbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte." />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWIS1" start="0x40004000" description="I2C compatible Two-Wire Slave Interface with EasyDMA 1">
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030" size="4" name="TASKS_PREPARERX" access="WriteOnly" description="Prepare the TWI slave to respond to a write command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x034" size="4" name="TASKS_PREPARETX" access="WriteOnly" description="Prepare the TWI slave to respond to a read command" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="Receive sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="Transmit sequence started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x164" size="4" name="EVENTS_WRITE" access="Read/Write" description="Write command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x168" size="4" name="EVENTS_READ" access="Read/Write" description="Read command received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="13" size="1" name="WRITE_SUSPEND" description="Shortcut between WRITE event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="14" size="1" name="READ_SUSPEND" description="Shortcut between READ event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Enable or disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Enable or disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Enable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Enable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="WRITE" description="Write '1' to Disable interrupt for WRITE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="READ" description="Write '1' to Disable interrupt for READ event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D0" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK sent after receiving a data byte">
-        <Enum name="NotReceived" start="0" description="Error did not occur" />
-        <Enum name="Received" start="1" description="Error occurred" />
-      </BitField>
-      <BitField start="3" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotDetected" start="0" description="Error did not occur" />
-        <Enum name="Detected" start="1" description="Error occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x4D4" size="4" name="MATCH" access="ReadOnly" description="Status register indicating which address had a match" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH" description="Which of the addresses in {ADDRESS} matched the incoming address" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWIS" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWIS">
-        <Enum name="Disabled" start="0" description="Disable TWIS" />
-        <Enum name="Enabled" start="9" description="Enable TWIS" />
-      </BitField>
-    </Register>
-    <Register start="+0x588+0" size="4" name="ADDRESS[0]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x588+4" size="4" name="ADDRESS[1]" access="Read/Write" description="Description collection[0]:  TWI slave address 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="TWI slave address" />
-    </Register>
-    <Register start="+0x594" size="4" name="CONFIG" access="Read/Write" description="Configuration register for the address match mechanism" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADDRESS0" description="Enable or disable address matching on ADDRESS[0]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ADDRESS1" description="Enable or disable address matching on ADDRESS[1]">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character sent out in case of an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in RXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in RXD buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last RXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last RXD transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in TXD buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in TXD buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last TXD transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transferred in the last TXD transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI1" start="0x40004000" description="Serial Peripheral Interface 1">
-    <Register start="+0x108" size="4" name="EVENTS_READY" access="Read/Write" description="TXD byte sent and RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI">
-        <Enum name="Disabled" start="0" description="Disable SPI" />
-        <Enum name="Enabled" start="1" description="Enable SPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received. Double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to send. Double buffered" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TWI1" start="0x40004000" description="I2C compatible Two-Wire Interface 1">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start TWI receive sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start TWI transmit sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume TWI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="TWI stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDREADY" access="Read/Write" description="TWI RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDSENT" access="Read/Write" description="TWI TXD byte sent" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="TWI error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_BB" access="Read/Write" description="TWI byte boundary, generated before each byte that is sent or received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_SUSPENDED" access="Read/Write" description="TWI entered the suspended state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BB_SUSPEND" description="Shortcut between BB event and SUSPEND task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="BB_STOP" description="Shortcut between BB event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Enable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Enable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Enable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Enable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDREADY" description="Write '1' to Disable interrupt for RXDREADY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDSENT" description="Write '1' to Disable interrupt for TXDSENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BB" description="Write '1' to Disable interrupt for BB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="SUSPENDED" description="Write '1' to Disable interrupt for SUSPENDED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x4C4" size="4" name="ERRORSRC" access="Read/Write" description="Error source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: no overrun occured" />
-        <Enum name="Present" start="1" description="Read: overrun occured" />
-      </BitField>
-      <BitField start="1" size="1" name="ANACK" description="NACK received after sending the address (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="DNACK" description="NACK received after sending a data byte (write '1' to clear)">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable TWI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable TWI">
-        <Enum name="Disabled" start="0" description="Disable TWI" />
-        <Enum name="Enabled" start="5" description="Enable TWI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RXD register" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TXD register" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="TWI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="TWI master clock frequency">
-        <Enum name="K100" start="0x01980000" description="100 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K400" start="0x06680000" description="400 kbps (actual rate 410.256 kbps)" />
-      </BitField>
-    </Register>
-    <Register start="+0x588" size="4" name="ADDRESS" access="Read/Write" description="Address used in the TWI transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDRESS" description="Address used in the TWI transfer" />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCL" access="Read/Write" description="Pin select for SCL" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.SDA" access="Read/Write" description="Pin select for SDA" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NFCT" start="0x40005000" description="NFC-A compatible radio">
-    <Register start="+0x000" size="4" name="TASKS_ACTIVATE" access="WriteOnly" description="Activate NFCT peripheral for incoming and outgoing frames, change state to activated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_DISABLE" access="WriteOnly" description="Disable NFCT peripheral" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_SENSE" access="WriteOnly" description="Enable NFC sense field mode, change state to sense mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start transmission of an outgoing frame, change state to transmit" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_ENABLERXDATA" access="WriteOnly" description="Initializes the EasyDMA for receive." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x024" size="4" name="TASKS_GOIDLE" access="WriteOnly" description="Force state machine to IDLE state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_GOSLEEP" access="WriteOnly" description="Force state machine to SLEEP_A state" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="The NFCT peripheral is ready to receive and send frames" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_FIELDDETECTED" access="Read/Write" description="Remote NFC field detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_FIELDLOST" access="Read/Write" description="Remote NFC field lost" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_TXFRAMESTART" access="Read/Write" description="Marks the start of the first symbol of a transmitted frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_TXFRAMEEND" access="Read/Write" description="Marks the end of the last transmitted on-air symbol of a frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_RXFRAMESTART" access="Read/Write" description="Marks the end of the first symbol of a received frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_RXFRAMEEND" access="Read/Write" description="Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_ERROR" access="Read/Write" description="NFC error reported. The ERRORSTATUS register contains details on the source of the error." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_RXERROR" access="Read/Write" description="NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x12C" size="4" name="EVENTS_ENDRX" access="Read/Write" description="RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130" size="4" name="EVENTS_ENDTX" access="Read/Write" description="Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x138" size="4" name="EVENTS_AUTOCOLRESSTARTED" access="Read/Write" description="Auto collision resolution process has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="EVENTS_COLLISION" access="Read/Write" description="NFC auto collision resolution error reported." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_SELECTED" access="Read/Write" description="NFC auto collision resolution successfully completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_STARTED" access="Read/Write" description="EasyDMA is ready to receive or send frames." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIELDDETECTED_ACTIVATE" description="Shortcut between FIELDDETECTED event and ACTIVATE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDLOST_SENSE" description="Shortcut between FIELDLOST event and SENSE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="TXFRAMEEND_ENABLERXDATA" description="Shortcut between TXFRAMEEND event and ENABLERXDATA task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Enable or disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDDETECTED" description="Enable or disable interrupt for FIELDDETECTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="FIELDLOST" description="Enable or disable interrupt for FIELDLOST event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TXFRAMESTART" description="Enable or disable interrupt for TXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TXFRAMEEND" description="Enable or disable interrupt for TXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="RXFRAMESTART" description="Enable or disable interrupt for RXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="RXFRAMEEND" description="Enable or disable interrupt for RXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="RXERROR" description="Enable or disable interrupt for RXERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDRX" description="Enable or disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDTX" description="Enable or disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="AUTOCOLRESSTARTED" description="Enable or disable interrupt for AUTOCOLRESSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COLLISION" description="Enable or disable interrupt for COLLISION event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="SELECTED" description="Enable or disable interrupt for SELECTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDDETECTED" description="Write '1' to Enable interrupt for FIELDDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="FIELDLOST" description="Write '1' to Enable interrupt for FIELDLOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TXFRAMESTART" description="Write '1' to Enable interrupt for TXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TXFRAMEEND" description="Write '1' to Enable interrupt for TXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RXFRAMESTART" description="Write '1' to Enable interrupt for RXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXFRAMEEND" description="Write '1' to Enable interrupt for RXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="RXERROR" description="Write '1' to Enable interrupt for RXERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="AUTOCOLRESSTARTED" description="Write '1' to Enable interrupt for AUTOCOLRESSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COLLISION" description="Write '1' to Enable interrupt for COLLISION event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="SELECTED" description="Write '1' to Enable interrupt for SELECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="FIELDDETECTED" description="Write '1' to Disable interrupt for FIELDDETECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="FIELDLOST" description="Write '1' to Disable interrupt for FIELDLOST event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TXFRAMESTART" description="Write '1' to Disable interrupt for TXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TXFRAMEEND" description="Write '1' to Disable interrupt for TXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RXFRAMESTART" description="Write '1' to Disable interrupt for RXFRAMESTART event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXFRAMEEND" description="Write '1' to Disable interrupt for RXFRAMEEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="RXERROR" description="Write '1' to Disable interrupt for RXERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="AUTOCOLRESSTARTED" description="Write '1' to Disable interrupt for AUTOCOLRESSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COLLISION" description="Write '1' to Disable interrupt for COLLISION event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="SELECTED" description="Write '1' to Disable interrupt for SELECTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x404" size="4" name="ERRORSTATUS" access="Read/Write" description="NFC Error Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEDELAYTIMEOUT" description="No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX" />
-    </Register>
-    <Register start="+0x410" size="4" name="NFCTAGSTATE" access="ReadOnly" description="NfcTag state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="NFCTAGSTATE" description="NfcTag state">
-        <Enum name="Disabled" start="0" description="Disabled or sense" />
-        <Enum name="RampUp" start="2" description="RampUp" />
-        <Enum name="Idle" start="3" description="Idle" />
-        <Enum name="Receive" start="4" description="Receive" />
-        <Enum name="FrameDelay" start="5" description="FrameDelay" />
-        <Enum name="Transmit" start="6" description="Transmit" />
-      </BitField>
-    </Register>
-    <Register start="+0x43C" size="4" name="FIELDPRESENT" access="ReadOnly" description="Indicates the presence or not of a valid field" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIELDPRESENT" description="Indicates if a valid field is present. Available only in the activated state.">
-        <Enum name="NoField" start="0" description="No valid field detected" />
-        <Enum name="FieldPresent" start="1" description="Valid field detected" />
-      </BitField>
-      <BitField start="1" size="1" name="LOCKDETECT" description="Indicates if the low level has locked to the field">
-        <Enum name="NotLocked" start="0" description="Not locked to field" />
-        <Enum name="Locked" start="1" description="Locked to field" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="FRAMEDELAYMIN" access="Read/Write" description="Minimum frame delay" reset_value="0x00000480" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FRAMEDELAYMIN" description="Minimum frame delay in number of 13.56 MHz clocks" />
-    </Register>
-    <Register start="+0x508" size="4" name="FRAMEDELAYMAX" access="Read/Write" description="Maximum frame delay" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="20" name="FRAMEDELAYMAX" description="Maximum frame delay in number of 13.56 MHz clocks" />
-    </Register>
-    <Register start="+0x50C" size="4" name="FRAMEDELAYMODE" access="Read/Write" description="Configuration register for the Frame Delay Timer" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="FRAMEDELAYMODE" description="Configuration register for the Frame Delay Timer">
-        <Enum name="FreeRun" start="0" description="Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout." />
-        <Enum name="Window" start="1" description="Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX" />
-        <Enum name="ExactVal" start="2" description="Frame is transmitted exactly at FRAMEDELAYMAX" />
-        <Enum name="WindowGrid" start="3" description="Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PACKETPTR" access="Read/Write" description="Packet pointer for TXD and RXD data storage in Data RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address." />
-    </Register>
-    <Register start="+0x514" size="4" name="MAXLEN" access="Read/Write" description="Size of the RAM buffer allocated to TXD and RXD data storage each" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="MAXLEN" description="Size of the RAM buffer allocated to TXD and RXD data storage each" />
-    </Register>
-    <Register start="+0x590" size="4" name="NFCID1_LAST" access="Read/Write" description="Last NFCID1 part (4, 7 or 10 bytes ID)" reset_value="0x00006363" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="NFCID1_Z" description="NFCID1 byte Z (very last byte sent)" />
-      <BitField start="8" size="8" name="NFCID1_Y" description="NFCID1 byte Y" />
-      <BitField start="16" size="8" name="NFCID1_X" description="NFCID1 byte X" />
-      <BitField start="24" size="8" name="NFCID1_W" description="NFCID1 byte W" />
-    </Register>
-    <Register start="+0x594" size="4" name="NFCID1_2ND_LAST" access="Read/Write" description="Second last NFCID1 part (7 or 10 bytes ID)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="NFCID1_V" description="NFCID1 byte V" />
-      <BitField start="8" size="8" name="NFCID1_U" description="NFCID1 byte U" />
-      <BitField start="16" size="8" name="NFCID1_T" description="NFCID1 byte T" />
-    </Register>
-    <Register start="+0x598" size="4" name="NFCID1_3RD_LAST" access="Read/Write" description="Third last NFCID1 part (10 bytes ID)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="NFCID1_S" description="NFCID1 byte S" />
-      <BitField start="8" size="8" name="NFCID1_R" description="NFCID1 byte R" />
-      <BitField start="16" size="8" name="NFCID1_Q" description="NFCID1 byte Q" />
-    </Register>
-    <Register start="+0x59C" size="4" name="AUTOCOLRESCONFIG" access="Read/Write" description="Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled." reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Enables/disables auto collision resolution">
-        <Enum name="Enabled" start="0" description="Auto collision resolution enabled" />
-        <Enum name="Disabled" start="1" description="Auto collision resolution disabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x5A0" size="4" name="SENSRES" access="Read/Write" description="NFC-A SENS_RES auto-response settings" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="BITFRAMESDD" description="Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification">
-        <Enum name="SDD00000" start="0" description="SDD pattern 00000" />
-        <Enum name="SDD00001" start="1" description="SDD pattern 00001" />
-        <Enum name="SDD00010" start="2" description="SDD pattern 00010" />
-        <Enum name="SDD00100" start="4" description="SDD pattern 00100" />
-        <Enum name="SDD01000" start="8" description="SDD pattern 01000" />
-        <Enum name="SDD10000" start="16" description="SDD pattern 10000" />
-      </BitField>
-      <BitField start="5" size="1" name="RFU5" description="Reserved for future use. Shall be 0." />
-      <BitField start="6" size="2" name="NFCIDSIZE" description="NFCID1 size. This value is used by the auto collision resolution engine.">
-        <Enum name="NFCID1Single" start="0" description="NFCID1 size: single (4 bytes)" />
-        <Enum name="NFCID1Double" start="1" description="NFCID1 size: double (7 bytes)" />
-        <Enum name="NFCID1Triple" start="2" description="NFCID1 size: triple (10 bytes)" />
-      </BitField>
-      <BitField start="8" size="4" name="PLATFCONFIG" description="Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification" />
-      <BitField start="12" size="4" name="RFU74" description="Reserved for future use. Shall be 0." />
-    </Register>
-    <Register start="+0x5A4" size="4" name="SELRES" access="Read/Write" description="NFC-A SEL_RES auto-response settings" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RFU10" description="Reserved for future use. Shall be 0." />
-      <BitField start="2" size="1" name="CASCADE" description="Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)" />
-      <BitField start="3" size="2" name="RFU43" description="Reserved for future use. Shall be 0." />
-      <BitField start="5" size="2" name="PROTOCOL" description="Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification" />
-      <BitField start="7" size="1" name="RFU7" description="Reserved for future use. Shall be 0." />
-    </Register>
-    <Register start="+0x40C+0x000" size="4" name="FRAMESTATUS.RX" access="Read/Write" description="Result of last incoming frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERROR" description="No valid end of frame (EoF) detected">
-        <Enum name="CRCCorrect" start="0" description="Valid CRC detected" />
-        <Enum name="CRCError" start="1" description="CRC received does not match local check" />
-      </BitField>
-      <BitField start="2" size="1" name="PARITYSTATUS" description="Parity status of received frame">
-        <Enum name="ParityOK" start="0" description="Frame received with parity OK" />
-        <Enum name="ParityError" start="1" description="Frame received with parity error" />
-      </BitField>
-      <BitField start="3" size="1" name="OVERRUN" description="Overrun detected">
-        <Enum name="NoOverrun" start="0" description="No overrun detected" />
-        <Enum name="Overrun" start="1" description="Overrun error" />
-      </BitField>
-    </Register>
-    <Register start="+0x518+0x000" size="4" name="TXD.FRAMECONFIG" access="Read/Write" description="Configuration of outgoing frames" reset_value="0x00000017" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PARITY" description="Indicates if parity is added to the frame">
-        <Enum name="NoParity" start="0" description="Parity is not added to TX frames" />
-        <Enum name="Parity" start="1" description="Parity is added to TX frames" />
-      </BitField>
-      <BitField start="1" size="1" name="DISCARDMODE" description="Discarding unused bits at start or end of a frame">
-        <Enum name="DiscardEnd" start="0" description="Unused bits are discarded at end of frame (EoF)" />
-        <Enum name="DiscardStart" start="1" description="Unused bits are discarded at start of frame (SoF)" />
-      </BitField>
-      <BitField start="2" size="1" name="SOF" description="Adding SoF or not in TX frames">
-        <Enum name="NoSoF" start="0" description="SoF symbol not added" />
-        <Enum name="SoF" start="1" description="SoF symbol added" />
-      </BitField>
-      <BitField start="4" size="1" name="CRCMODETX" description="CRC mode for outgoing frames">
-        <Enum name="NoCRCTX" start="0" description="CRC is not added to the frame" />
-        <Enum name="CRC16TX" start="1" description="16 bit CRC added to the frame based on all the data read from RAM that is used in the frame" />
-      </BitField>
-    </Register>
-    <Register start="+0x518+0x004" size="4" name="TXD.AMOUNT" access="Read/Write" description="Size of outgoing frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="TXDATABITS" description="Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit)." />
-      <BitField start="3" size="9" name="TXDATABYTES" description="Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing" />
-    </Register>
-    <Register start="+0x520+0x000" size="4" name="RXD.FRAMECONFIG" access="Read/Write" description="Configuration of incoming frames" reset_value="0x00000015" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PARITY" description="Indicates if parity expected in RX frame">
-        <Enum name="NoParity" start="0" description="Parity is not expected in RX frames" />
-        <Enum name="Parity" start="1" description="Parity is expected in RX frames" />
-      </BitField>
-      <BitField start="2" size="1" name="SOF" description="SoF expected or not in RX frames">
-        <Enum name="NoSoF" start="0" description="SoF symbol is not expected in RX frames" />
-        <Enum name="SoF" start="1" description="SoF symbol is expected in RX frames" />
-      </BitField>
-      <BitField start="4" size="1" name="CRCMODERX" description="CRC mode for incoming frames">
-        <Enum name="NoCRCRX" start="0" description="CRC is not expected in RX frames" />
-        <Enum name="CRC16RX" start="1" description="Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0x004" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Size of last incoming frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDATABITS" description="Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing)." />
-      <BitField start="3" size="9" name="RXDATABYTES" description="Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOTE" start="0x40006000" description="GPIO Tasks and Events">
-    <Register start="+0x000+0" size="4" name="TASKS_OUT[0]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_OUT[1]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_OUT[2]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_OUT[3]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_OUT[4]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_OUT[5]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_OUT[6]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_OUT[7]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+0" size="4" name="TASKS_SET[0]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+4" size="4" name="TASKS_SET[1]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+8" size="4" name="TASKS_SET[2]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+12" size="4" name="TASKS_SET[3]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+16" size="4" name="TASKS_SET[4]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+20" size="4" name="TASKS_SET[5]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+24" size="4" name="TASKS_SET[6]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x030+28" size="4" name="TASKS_SET[7]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+0" size="4" name="TASKS_CLR[0]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+4" size="4" name="TASKS_CLR[1]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+8" size="4" name="TASKS_CLR[2]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+12" size="4" name="TASKS_CLR[3]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+16" size="4" name="TASKS_CLR[4]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+20" size="4" name="TASKS_CLR[5]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+24" size="4" name="TASKS_CLR[6]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x060+28" size="4" name="TASKS_CLR[7]" access="WriteOnly" description="Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_IN[0]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_IN[1]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_IN[2]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_IN[3]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_IN[4]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_IN[5]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_IN[6]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_IN[7]" access="Read/Write" description="Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x17C" size="4" name="EVENTS_PORT" access="Read/Write" description="Event generated from multiple input GPIO pins with SENSE mechanism enabled" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IN0" description="Write '1' to Enable interrupt for IN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="IN1" description="Write '1' to Enable interrupt for IN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="IN2" description="Write '1' to Enable interrupt for IN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="IN3" description="Write '1' to Enable interrupt for IN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="IN4" description="Write '1' to Enable interrupt for IN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="IN5" description="Write '1' to Enable interrupt for IN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="IN6" description="Write '1' to Enable interrupt for IN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="IN7" description="Write '1' to Enable interrupt for IN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="PORT" description="Write '1' to Enable interrupt for PORT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IN0" description="Write '1' to Disable interrupt for IN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="IN1" description="Write '1' to Disable interrupt for IN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="IN2" description="Write '1' to Disable interrupt for IN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="IN3" description="Write '1' to Disable interrupt for IN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="IN4" description="Write '1' to Disable interrupt for IN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="IN5" description="Write '1' to Disable interrupt for IN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="IN6" description="Write '1' to Disable interrupt for IN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="IN7" description="Write '1' to Disable interrupt for IN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="PORT" description="Write '1' to Disable interrupt for PORT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0" size="4" name="CONFIG[0]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4" size="4" name="CONFIG[1]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+8" size="4" name="CONFIG[2]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+12" size="4" name="CONFIG[3]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+16" size="4" name="CONFIG[4]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+20" size="4" name="CONFIG[5]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+24" size="4" name="CONFIG[6]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+28" size="4" name="CONFIG[7]" access="Read/Write" description="Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Mode">
-        <Enum name="Disabled" start="0" description="Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module." />
-        <Enum name="Event" start="1" description="Event mode" />
-        <Enum name="Task" start="3" description="Task mode" />
-      </BitField>
-      <BitField start="8" size="5" name="PSEL" description="GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event" />
-      <BitField start="13" size="1" name="PORT" description="Port number" />
-      <BitField start="16" size="2" name="POLARITY" description="When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.">
-        <Enum name="None" start="0" description="Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity." />
-        <Enum name="LoToHi" start="1" description="Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin." />
-        <Enum name="HiToLo" start="2" description="Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin." />
-        <Enum name="Toggle" start="3" description="Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin." />
-      </BitField>
-      <BitField start="20" size="1" name="OUTINIT" description="When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.">
-        <Enum name="Low" start="0" description="Task mode: Initial value of pin before task triggering is low" />
-        <Enum name="High" start="1" description="Task mode: Initial value of pin before task triggering is high" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SAADC" start="0x40007000" description="Analog to Digital Converter">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start the ADC and prepare the result buffer in RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_SAMPLE" access="WriteOnly" description="Take one ADC sample, if scan is enabled all channels are sampled" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop the ADC and terminate any on-going conversion" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CALIBRATEOFFSET" access="WriteOnly" description="Starts offset auto-calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_STARTED" access="Read/Write" description="The ADC has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="The ADC has filled up the Result buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_DONE" access="Read/Write" description="A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_RESULTDONE" access="Read/Write" description="A result is ready to get transferred to RAM." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_CALIBRATEDONE" access="Read/Write" description="Calibration is complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_STOPPED" access="Read/Write" description="The ADC has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="END" description="Enable or disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="DONE" description="Enable or disable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="RESULTDONE" description="Enable or disable interrupt for RESULTDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="CALIBRATEDONE" description="Enable or disable interrupt for CALIBRATEDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="CH0LIMITH" description="Enable or disable interrupt for CH[0].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="CH0LIMITL" description="Enable or disable interrupt for CH[0].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="CH1LIMITH" description="Enable or disable interrupt for CH[1].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="CH1LIMITL" description="Enable or disable interrupt for CH[1].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="CH2LIMITH" description="Enable or disable interrupt for CH[2].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="CH2LIMITL" description="Enable or disable interrupt for CH[2].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="CH3LIMITH" description="Enable or disable interrupt for CH[3].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="CH3LIMITL" description="Enable or disable interrupt for CH[3].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="CH4LIMITH" description="Enable or disable interrupt for CH[4].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="CH4LIMITL" description="Enable or disable interrupt for CH[4].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="CH5LIMITH" description="Enable or disable interrupt for CH[5].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="CH5LIMITL" description="Enable or disable interrupt for CH[5].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="CH6LIMITH" description="Enable or disable interrupt for CH[6].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="CH6LIMITL" description="Enable or disable interrupt for CH[6].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="CH7LIMITH" description="Enable or disable interrupt for CH[7].LIMITH event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="21" size="1" name="CH7LIMITL" description="Enable or disable interrupt for CH[7].LIMITL event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="DONE" description="Write '1' to Enable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RESULTDONE" description="Write '1' to Enable interrupt for RESULTDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CALIBRATEDONE" description="Write '1' to Enable interrupt for CALIBRATEDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH0LIMITH" description="Write '1' to Enable interrupt for CH[0].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH0LIMITL" description="Write '1' to Enable interrupt for CH[0].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH1LIMITH" description="Write '1' to Enable interrupt for CH[1].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH1LIMITL" description="Write '1' to Enable interrupt for CH[1].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH2LIMITH" description="Write '1' to Enable interrupt for CH[2].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH2LIMITL" description="Write '1' to Enable interrupt for CH[2].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH3LIMITH" description="Write '1' to Enable interrupt for CH[3].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH3LIMITL" description="Write '1' to Enable interrupt for CH[3].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH4LIMITH" description="Write '1' to Enable interrupt for CH[4].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH4LIMITL" description="Write '1' to Enable interrupt for CH[4].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH5LIMITH" description="Write '1' to Enable interrupt for CH[5].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH5LIMITL" description="Write '1' to Enable interrupt for CH[5].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH6LIMITH" description="Write '1' to Enable interrupt for CH[6].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH6LIMITL" description="Write '1' to Enable interrupt for CH[6].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH7LIMITH" description="Write '1' to Enable interrupt for CH[7].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH7LIMITL" description="Write '1' to Enable interrupt for CH[7].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="DONE" description="Write '1' to Disable interrupt for DONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RESULTDONE" description="Write '1' to Disable interrupt for RESULTDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CALIBRATEDONE" description="Write '1' to Disable interrupt for CALIBRATEDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH0LIMITH" description="Write '1' to Disable interrupt for CH[0].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH0LIMITL" description="Write '1' to Disable interrupt for CH[0].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH1LIMITH" description="Write '1' to Disable interrupt for CH[1].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH1LIMITL" description="Write '1' to Disable interrupt for CH[1].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH2LIMITH" description="Write '1' to Disable interrupt for CH[2].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH2LIMITL" description="Write '1' to Disable interrupt for CH[2].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH3LIMITH" description="Write '1' to Disable interrupt for CH[3].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH3LIMITL" description="Write '1' to Disable interrupt for CH[3].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH4LIMITH" description="Write '1' to Disable interrupt for CH[4].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH4LIMITL" description="Write '1' to Disable interrupt for CH[4].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH5LIMITH" description="Write '1' to Disable interrupt for CH[5].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH5LIMITL" description="Write '1' to Disable interrupt for CH[5].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH6LIMITH" description="Write '1' to Disable interrupt for CH[6].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH6LIMITL" description="Write '1' to Disable interrupt for CH[6].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH7LIMITH" description="Write '1' to Disable interrupt for CH[7].LIMITH event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH7LIMITL" description="Write '1' to Disable interrupt for CH[7].LIMITL event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Status">
-        <Enum name="Ready" start="0" description="ADC is ready. No on-going conversion." />
-        <Enum name="Busy" start="1" description="ADC is busy. Conversion in progress." />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable or disable ADC" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable ADC">
-        <Enum name="Disabled" start="0" description="Disable ADC" />
-        <Enum name="Enabled" start="1" description="Enable ADC" />
-      </BitField>
-    </Register>
-    <Register start="+0x5F0" size="4" name="RESOLUTION" access="Read/Write" description="Resolution configuration" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="VAL" description="Set the resolution">
-        <Enum name="8bit" start="0" description="8 bit" />
-        <Enum name="10bit" start="1" description="10 bit" />
-        <Enum name="12bit" start="2" description="12 bit" />
-        <Enum name="14bit" start="3" description="14 bit" />
-      </BitField>
-    </Register>
-    <Register start="+0x5F4" size="4" name="OVERSAMPLE" access="Read/Write" description="Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="OVERSAMPLE" description="Oversample control">
-        <Enum name="Bypass" start="0" description="Bypass oversampling" />
-        <Enum name="Over2x" start="1" description="Oversample 2x" />
-        <Enum name="Over4x" start="2" description="Oversample 4x" />
-        <Enum name="Over8x" start="3" description="Oversample 8x" />
-        <Enum name="Over16x" start="4" description="Oversample 16x" />
-        <Enum name="Over32x" start="5" description="Oversample 32x" />
-        <Enum name="Over64x" start="6" description="Oversample 64x" />
-        <Enum name="Over128x" start="7" description="Oversample 128x" />
-        <Enum name="Over256x" start="8" description="Oversample 256x" />
-      </BitField>
-    </Register>
-    <Register start="+0x5F8" size="4" name="SAMPLERATE" access="Read/Write" description="Controls normal or continuous sample rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="CC" description="Capture and compare value. Sample rate is 16 MHz/CC" />
-      <BitField start="12" size="1" name="MODE" description="Select mode for sample rate control">
-        <Enum name="Task" start="0" description="Rate is controlled from SAMPLE task" />
-        <Enum name="Timers" start="1" description="Rate is controlled from local timer (use CC to control the rate)" />
-      </BitField>
-    </Register>
-    <Register start="+0x118+0*8+0x000" size="4" name="EVENTS_CH[0].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+0*8+0x004" size="4" name="EVENTS_CH[0].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+1*8+0x000" size="4" name="EVENTS_CH[1].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+1*8+0x004" size="4" name="EVENTS_CH[1].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+2*8+0x000" size="4" name="EVENTS_CH[2].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+2*8+0x004" size="4" name="EVENTS_CH[2].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+3*8+0x000" size="4" name="EVENTS_CH[3].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+3*8+0x004" size="4" name="EVENTS_CH[3].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+4*8+0x000" size="4" name="EVENTS_CH[4].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+4*8+0x004" size="4" name="EVENTS_CH[4].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+5*8+0x000" size="4" name="EVENTS_CH[5].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+5*8+0x004" size="4" name="EVENTS_CH[5].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+6*8+0x000" size="4" name="EVENTS_CH[6].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+6*8+0x004" size="4" name="EVENTS_CH[6].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+7*8+0x000" size="4" name="EVENTS_CH[7].LIMITH" access="Read/Write" description="Description cluster[0]:  Last results is equal or above CH[0].LIMIT.HIGH" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118+7*8+0x004" size="4" name="EVENTS_CH[7].LIMITL" access="Read/Write" description="Description cluster[0]:  Last results is equal or below CH[0].LIMIT.LOW" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x510+0*16+0x000" size="4" name="CH[0].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0*16+0x004" size="4" name="CH[0].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0*16+0x008" size="4" name="CH[0].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+0*16+0x00C" size="4" name="CH[0].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+1*16+0x000" size="4" name="CH[1].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+1*16+0x004" size="4" name="CH[1].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+1*16+0x008" size="4" name="CH[1].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+1*16+0x00C" size="4" name="CH[1].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+2*16+0x000" size="4" name="CH[2].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+2*16+0x004" size="4" name="CH[2].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+2*16+0x008" size="4" name="CH[2].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+2*16+0x00C" size="4" name="CH[2].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+3*16+0x000" size="4" name="CH[3].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+3*16+0x004" size="4" name="CH[3].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+3*16+0x008" size="4" name="CH[3].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+3*16+0x00C" size="4" name="CH[3].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+4*16+0x000" size="4" name="CH[4].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4*16+0x004" size="4" name="CH[4].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4*16+0x008" size="4" name="CH[4].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+4*16+0x00C" size="4" name="CH[4].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+5*16+0x000" size="4" name="CH[5].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+5*16+0x004" size="4" name="CH[5].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+5*16+0x008" size="4" name="CH[5].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+5*16+0x00C" size="4" name="CH[5].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+6*16+0x000" size="4" name="CH[6].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+6*16+0x004" size="4" name="CH[6].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+6*16+0x008" size="4" name="CH[6].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+6*16+0x00C" size="4" name="CH[6].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x510+7*16+0x000" size="4" name="CH[7].PSELP" access="Read/Write" description="Description cluster[0]:  Input positive pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELP" description="Analog positive input channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+7*16+0x004" size="4" name="CH[7].PSELN" access="Read/Write" description="Description cluster[0]:  Input negative pin selection for CH[0]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PSELN" description="Analog negative input, enables differential channel">
-        <Enum name="NC" start="0" description="Not connected" />
-        <Enum name="AnalogInput0" start="1" description="AIN0" />
-        <Enum name="AnalogInput1" start="2" description="AIN1" />
-        <Enum name="AnalogInput2" start="3" description="AIN2" />
-        <Enum name="AnalogInput3" start="4" description="AIN3" />
-        <Enum name="AnalogInput4" start="5" description="AIN4" />
-        <Enum name="AnalogInput5" start="6" description="AIN5" />
-        <Enum name="AnalogInput6" start="7" description="AIN6" />
-        <Enum name="AnalogInput7" start="8" description="AIN7" />
-        <Enum name="VDD" start="9" description="VDD" />
-        <Enum name="VDDHDIV5" start="0x0D" description="VDDH/5" />
-      </BitField>
-    </Register>
-    <Register start="+0x510+7*16+0x008" size="4" name="CH[7].CONFIG" access="Read/Write" description="Description cluster[0]:  Input configuration for CH[0]" reset_value="0x00020000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESP" description="Positive channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="4" size="2" name="RESN" description="Negative channel resistor control">
-        <Enum name="Bypass" start="0" description="Bypass resistor ladder" />
-        <Enum name="Pulldown" start="1" description="Pull-down to GND" />
-        <Enum name="Pullup" start="2" description="Pull-up to VDD" />
-        <Enum name="VDD1_2" start="3" description="Set input at VDD/2" />
-      </BitField>
-      <BitField start="8" size="3" name="GAIN" description="Gain control">
-        <Enum name="Gain1_6" start="0" description="1/6" />
-        <Enum name="Gain1_5" start="1" description="1/5" />
-        <Enum name="Gain1_4" start="2" description="1/4" />
-        <Enum name="Gain1_3" start="3" description="1/3" />
-        <Enum name="Gain1_2" start="4" description="1/2" />
-        <Enum name="Gain1" start="5" description="1" />
-        <Enum name="Gain2" start="6" description="2" />
-        <Enum name="Gain4" start="7" description="4" />
-      </BitField>
-      <BitField start="12" size="1" name="REFSEL" description="Reference control">
-        <Enum name="Internal" start="0" description="Internal reference (0.6 V)" />
-        <Enum name="VDD1_4" start="1" description="VDD/4 as reference" />
-      </BitField>
-      <BitField start="16" size="3" name="TACQ" description="Acquisition time, the time the ADC uses to sample the input voltage">
-        <Enum name="3us" start="0" description="3 us" />
-        <Enum name="5us" start="1" description="5 us" />
-        <Enum name="10us" start="2" description="10 us" />
-        <Enum name="15us" start="3" description="15 us" />
-        <Enum name="20us" start="4" description="20 us" />
-        <Enum name="40us" start="5" description="40 us" />
-      </BitField>
-      <BitField start="20" size="1" name="MODE" description="Enable differential mode">
-        <Enum name="SE" start="0" description="Single ended, PSELN will be ignored, negative input to ADC shorted to GND" />
-        <Enum name="Diff" start="1" description="Differential" />
-      </BitField>
-      <BitField start="24" size="1" name="BURST" description="Enable burst mode">
-        <Enum name="Disabled" start="0" description="Burst mode is disabled (normal operation)" />
-        <Enum name="Enabled" start="1" description="Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM." />
-      </BitField>
-    </Register>
-    <Register start="+0x510+7*16+0x00C" size="4" name="CH[7].LIMIT" access="Read/Write" description="Description cluster[0]:  High/low limits for event monitoring a channel" reset_value="0x7FFF8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOW" description="Low level limit" />
-      <BitField start="16" size="16" name="HIGH" description="High level limit" />
-    </Register>
-    <Register start="+0x62C+0x000" size="4" name="RESULT.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x62C+0x004" size="4" name="RESULT.MAXCNT" access="Read/Write" description="Maximum number of buffer words to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MAXCNT" description="Maximum number of buffer words to transfer" />
-    </Register>
-    <Register start="+0x62C+0x008" size="4" name="RESULT.AMOUNT" access="ReadOnly" description="Number of buffer words transferred since last START" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="AMOUNT" description="Number of buffer words transferred since last START. This register can be read after an END or STOPPED event." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40008000" description="Timer/Counter 0">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40009000" description="Timer/Counter 1">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x4000A000" description="Timer/Counter 2">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC0" start="0x4000B000" description="Real time counter 0">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_TRIGOVRFLW" access="WriteOnly" description="Set COUNTER to 0xFFFFF0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TICK" access="Read/Write" description="Event on COUNTER increment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_OVRFLW" access="Read/Write" description="Event on COUNTER overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x340" size="4" name="EVTEN" access="Read/Write" description="Enable or disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Enable or disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Enable or disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Enable or disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Enable or disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Enable or disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Enable or disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x344" size="4" name="EVTENSET" access="Read/Write" description="Enable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x348" size="4" name="EVTENCLR" access="Read/Write" description="Disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="COUNTER" access="ReadOnly" description="Current COUNTER value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNTER" description="Counter value" />
-    </Register>
-    <Register start="+0x508" size="4" name="PRESCALER" access="Read/Write" description="12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TEMP" start="0x4000C000" description="Temperature Sensor">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start temperature measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop temperature measurement" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_DATARDY" access="Read/Write" description="Temperature measurement complete, data ready" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Write '1' to Enable interrupt for DATARDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Write '1' to Disable interrupt for DATARDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="TEMP" access="ReadOnly" description="Temperature in degC (0.25deg steps)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEMP" description="Temperature in degC (0.25deg steps)" />
-    </Register>
-    <Register start="+0x520" size="4" name="A0" access="Read/Write" description="Slope of 1st piece wise linear function" reset_value="0x00000326" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A0" description="Slope of 1st piece wise linear function" />
-    </Register>
-    <Register start="+0x524" size="4" name="A1" access="Read/Write" description="Slope of 2nd piece wise linear function" reset_value="0x00000348" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A1" description="Slope of 2nd piece wise linear function" />
-    </Register>
-    <Register start="+0x528" size="4" name="A2" access="Read/Write" description="Slope of 3rd piece wise linear function" reset_value="0x000003AA" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A2" description="Slope of 3rd piece wise linear function" />
-    </Register>
-    <Register start="+0x52C" size="4" name="A3" access="Read/Write" description="Slope of 4th piece wise linear function" reset_value="0x0000040E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A3" description="Slope of 4th piece wise linear function" />
-    </Register>
-    <Register start="+0x530" size="4" name="A4" access="Read/Write" description="Slope of 5th piece wise linear function" reset_value="0x000004BD" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A4" description="Slope of 5th piece wise linear function" />
-    </Register>
-    <Register start="+0x534" size="4" name="A5" access="Read/Write" description="Slope of 6th piece wise linear function" reset_value="0x000005A3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="A5" description="Slope of 6th piece wise linear function" />
-    </Register>
-    <Register start="+0x540" size="4" name="B0" access="Read/Write" description="y-intercept of 1st piece wise linear function" reset_value="0x00003FEF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B0" description="y-intercept of 1st piece wise linear function" />
-    </Register>
-    <Register start="+0x544" size="4" name="B1" access="Read/Write" description="y-intercept of 2nd piece wise linear function" reset_value="0x00003FBE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B1" description="y-intercept of 2nd piece wise linear function" />
-    </Register>
-    <Register start="+0x548" size="4" name="B2" access="Read/Write" description="y-intercept of 3rd piece wise linear function" reset_value="0x00003FBE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B2" description="y-intercept of 3rd piece wise linear function" />
-    </Register>
-    <Register start="+0x54C" size="4" name="B3" access="Read/Write" description="y-intercept of 4th piece wise linear function" reset_value="0x00000012" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B3" description="y-intercept of 4th piece wise linear function" />
-    </Register>
-    <Register start="+0x550" size="4" name="B4" access="Read/Write" description="y-intercept of 5th piece wise linear function" reset_value="0x00000124" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B4" description="y-intercept of 5th piece wise linear function" />
-    </Register>
-    <Register start="+0x554" size="4" name="B5" access="Read/Write" description="y-intercept of 6th piece wise linear function" reset_value="0x0000027C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="B5" description="y-intercept of 6th piece wise linear function" />
-    </Register>
-    <Register start="+0x560" size="4" name="T0" access="Read/Write" description="End point of 1st piece wise linear function" reset_value="0x000000E2" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T0" description="End point of 1st piece wise linear function" />
-    </Register>
-    <Register start="+0x564" size="4" name="T1" access="Read/Write" description="End point of 2nd piece wise linear function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T1" description="End point of 2nd piece wise linear function" />
-    </Register>
-    <Register start="+0x568" size="4" name="T2" access="Read/Write" description="End point of 3rd piece wise linear function" reset_value="0x00000019" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T2" description="End point of 3rd piece wise linear function" />
-    </Register>
-    <Register start="+0x56C" size="4" name="T3" access="Read/Write" description="End point of 4th piece wise linear function" reset_value="0x0000003C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T3" description="End point of 4th piece wise linear function" />
-    </Register>
-    <Register start="+0x570" size="4" name="T4" access="Read/Write" description="End point of 5th piece wise linear function" reset_value="0x00000050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="T4" description="End point of 5th piece wise linear function" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RNG" start="0x4000D000" description="Random Number Generator">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Task starting the random number generator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Task stopping the random number generator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_VALRDY" access="Read/Write" description="Event being generated for every new random number written to the VALUE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VALRDY_STOP" description="Shortcut between VALRDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VALRDY" description="Write '1' to Enable interrupt for VALRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VALRDY" description="Write '1' to Disable interrupt for VALRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DERCEN" description="Bias correction">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="VALUE" access="ReadOnly" description="Output random number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="VALUE" description="Generated random number" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ECB" start="0x4000E000" description="AES ECB Mode Encryption">
-    <Register start="+0x000" size="4" name="TASKS_STARTECB" access="WriteOnly" description="Start ECB block encrypt" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPECB" access="WriteOnly" description="Abort a possible executing ECB operation" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_ENDECB" access="Read/Write" description="ECB block encrypt complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_ERRORECB" access="Read/Write" description="ECB block encrypt aborted because of a STOPECB task or due to an error" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDECB" description="Write '1' to Enable interrupt for ENDECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ERRORECB" description="Write '1' to Enable interrupt for ERRORECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDECB" description="Write '1' to Disable interrupt for ENDECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ERRORECB" description="Write '1' to Disable interrupt for ERRORECB event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="ECBDATAPTR" access="Read/Write" description="ECB block encrypt memory pointers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ECBDATAPTR" description="Pointer to the ECB data structure (see Table 1 ECB data structure overview)" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCM" start="0x4000F000" description="AES CCM Mode Encryption">
-    <Register start="+0x000" size="4" name="TASKS_KSGEN" access="WriteOnly" description="Start generation of key-stream. This operation will stop by itself when completed." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_CRYPT" access="WriteOnly" description="Start encryption/decryption. This operation will stop by itself when completed." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop encryption/decryption" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_RATEOVERRIDE" access="WriteOnly" description="Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_ENDKSGEN" access="Read/Write" description="Key-stream generation complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_ENDCRYPT" access="Read/Write" description="Encrypt/decrypt complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_ERROR" access="Read/Write" description="Deprecated register -  CCM error event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDKSGEN_CRYPT" description="Shortcut between ENDKSGEN event and CRYPT task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDKSGEN" description="Write '1' to Enable interrupt for ENDKSGEN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ENDCRYPT" description="Write '1' to Enable interrupt for ENDCRYPT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDKSGEN" description="Write '1' to Disable interrupt for ENDKSGEN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="ENDCRYPT" description="Write '1' to Disable interrupt for ENDCRYPT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="MICSTATUS" access="ReadOnly" description="MIC check result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MICSTATUS" description="The result of the MIC check performed during the previous decryption operation">
-        <Enum name="CheckFailed" start="0" description="MIC check failed" />
-        <Enum name="CheckPassed" start="1" description="MIC check passed" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable CCM">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="2" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Operation mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.">
-        <Enum name="Encryption" start="0" description="AES CCM packet encryption mode" />
-        <Enum name="Decryption" start="1" description="AES CCM packet decryption mode" />
-      </BitField>
-      <BitField start="16" size="2" name="DATARATE" description="Radio data rate that the CCM shall run synchronous with">
-        <Enum name="1Mbit" start="0" description="1 Mbps" />
-        <Enum name="2Mbit" start="1" description="2 Mbps" />
-        <Enum name="125Kbps" start="2" description="125 Kbps" />
-        <Enum name="500Kbps" start="3" description="500 Kbps" />
-      </BitField>
-      <BitField start="24" size="1" name="LENGTH" description="Packet length configuration">
-        <Enum name="Default" start="0" description="Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated." />
-        <Enum name="Extended" start="1" description="Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated." />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="CNFPTR" access="Read/Write" description="Pointer to data structure holding AES key and NONCE vector" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CNFPTR" description="Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)" />
-    </Register>
-    <Register start="+0x50C" size="4" name="INPTR" access="Read/Write" description="Input pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INPTR" description="Input pointer" />
-    </Register>
-    <Register start="+0x510" size="4" name="OUTPTR" access="Read/Write" description="Output pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTPTR" description="Output pointer" />
-    </Register>
-    <Register start="+0x514" size="4" name="SCRATCHPTR" access="Read/Write" description="Pointer to data area used for temporary storage" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SCRATCHPTR" description="Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption." />
-    </Register>
-    <Register start="+0x518" size="4" name="MAXPACKETSIZE" access="Read/Write" description="Length of key-stream generated when MODE.LENGTH = Extended." reset_value="0x000000FB" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXPACKETSIZE" description="Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted." />
-    </Register>
-    <Register start="+0x51C" size="4" name="RATEOVERRIDE" access="Read/Write" description="Data rate override setting." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RATEOVERRIDE" description="Data rate override setting.">
-        <Enum name="1Mbit" start="0" description="1 Mbps" />
-        <Enum name="2Mbit" start="1" description="2 Mbps" />
-        <Enum name="125Kbps" start="2" description="125 Kbps" />
-        <Enum name="500Kbps" start="3" description="500 Kbps" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="AAR" start="0x4000F000" description="Accelerated Address Resolver">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start resolving addresses based on IRKs specified in the IRK data structure" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop resolving addresses" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_END" access="Read/Write" description="Address resolution procedure complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_RESOLVED" access="Read/Write" description="Address resolved" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_NOTRESOLVED" access="Read/Write" description="Address not resolved" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RESOLVED" description="Write '1' to Enable interrupt for RESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="NOTRESOLVED" description="Write '1' to Enable interrupt for NOTRESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RESOLVED" description="Write '1' to Disable interrupt for RESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="NOTRESOLVED" description="Write '1' to Disable interrupt for NOTRESOLVED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Resolution status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="STATUS" description="The IRK that was used last time an address was resolved" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable AAR" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable AAR">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="3" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="NIRK" access="Read/Write" description="Number of IRKs" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="NIRK" description="Number of Identity root keys available in the IRK data structure" />
-    </Register>
-    <Register start="+0x508" size="4" name="IRKPTR" access="Read/Write" description="Pointer to IRK data structure" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IRKPTR" description="Pointer to the IRK data structure" />
-    </Register>
-    <Register start="+0x510" size="4" name="ADDRPTR" access="Read/Write" description="Pointer to the resolvable address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRPTR" description="Pointer to the resolvable address (6-bytes)" />
-    </Register>
-    <Register start="+0x514" size="4" name="SCRATCHPTR" access="Read/Write" description="Pointer to data area used for temporary storage" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SCRATCHPTR" description="Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WDT" start="0x40010000" description="Watchdog Timer">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start the watchdog" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TIMEOUT" access="Read/Write" description="Watchdog timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMEOUT" description="Write '1' to Enable interrupt for TIMEOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMEOUT" description="Write '1' to Disable interrupt for TIMEOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RUNSTATUS" access="ReadOnly" description="Run status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUNSTATUS" description="Indicates whether or not the watchdog is running">
-        <Enum name="NotRunning" start="0" description="Watchdog not running" />
-        <Enum name="Running" start="1" description="Watchdog is running" />
-      </BitField>
-    </Register>
-    <Register start="+0x404" size="4" name="REQSTATUS" access="ReadOnly" description="Request status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RR0" description="Request status for RR[0] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[0] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[0] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="1" size="1" name="RR1" description="Request status for RR[1] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[1] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[1] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="2" size="1" name="RR2" description="Request status for RR[2] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[2] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[2] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="3" size="1" name="RR3" description="Request status for RR[3] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[3] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[3] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="4" size="1" name="RR4" description="Request status for RR[4] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[4] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[4] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="5" size="1" name="RR5" description="Request status for RR[5] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[5] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[5] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="6" size="1" name="RR6" description="Request status for RR[6] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[6] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[6] register is enabled, and are not yet requesting reload" />
-      </BitField>
-      <BitField start="7" size="1" name="RR7" description="Request status for RR[7] register">
-        <Enum name="DisabledOrRequested" start="0" description="RR[7] register is not enabled, or are already requesting reload" />
-        <Enum name="EnabledAndUnrequested" start="1" description="RR[7] register is enabled, and are not yet requesting reload" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CRV" access="Read/Write" description="Counter reload value" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRV" description="Counter reload value in number of cycles of the 32.768 kHz clock" />
-    </Register>
-    <Register start="+0x508" size="4" name="RREN" access="Read/Write" description="Enable register for reload request registers" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RR0" description="Enable or disable RR[0] register">
-        <Enum name="Disabled" start="0" description="Disable RR[0] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[0] register" />
-      </BitField>
-      <BitField start="1" size="1" name="RR1" description="Enable or disable RR[1] register">
-        <Enum name="Disabled" start="0" description="Disable RR[1] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[1] register" />
-      </BitField>
-      <BitField start="2" size="1" name="RR2" description="Enable or disable RR[2] register">
-        <Enum name="Disabled" start="0" description="Disable RR[2] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[2] register" />
-      </BitField>
-      <BitField start="3" size="1" name="RR3" description="Enable or disable RR[3] register">
-        <Enum name="Disabled" start="0" description="Disable RR[3] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[3] register" />
-      </BitField>
-      <BitField start="4" size="1" name="RR4" description="Enable or disable RR[4] register">
-        <Enum name="Disabled" start="0" description="Disable RR[4] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[4] register" />
-      </BitField>
-      <BitField start="5" size="1" name="RR5" description="Enable or disable RR[5] register">
-        <Enum name="Disabled" start="0" description="Disable RR[5] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[5] register" />
-      </BitField>
-      <BitField start="6" size="1" name="RR6" description="Enable or disable RR[6] register">
-        <Enum name="Disabled" start="0" description="Disable RR[6] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[6] register" />
-      </BitField>
-      <BitField start="7" size="1" name="RR7" description="Enable or disable RR[7] register">
-        <Enum name="Disabled" start="0" description="Disable RR[7] register" />
-        <Enum name="Enabled" start="1" description="Enable RR[7] register" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEP" description="Configure the watchdog to either be paused, or kept running, while the CPU is sleeping">
-        <Enum name="Pause" start="0" description="Pause watchdog while the CPU is sleeping" />
-        <Enum name="Run" start="1" description="Keep the watchdog running while the CPU is sleeping" />
-      </BitField>
-      <BitField start="3" size="1" name="HALT" description="Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger">
-        <Enum name="Pause" start="0" description="Pause watchdog while the CPU is halted by the debugger" />
-        <Enum name="Run" start="1" description="Keep the watchdog running while the CPU is halted by the debugger" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+0" size="4" name="RR[0]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+4" size="4" name="RR[1]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+8" size="4" name="RR[2]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+12" size="4" name="RR[3]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+16" size="4" name="RR[4]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+20" size="4" name="RR[5]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+24" size="4" name="RR[6]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+28" size="4" name="RR[7]" access="WriteOnly" description="Description collection[0]:  Reload request 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RR" description="Reload request register">
-        <Enum name="Reload" start="0x6E524635" description="Value to request a reload of the watchdog timer" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC1" start="0x40011000" description="Real time counter 1">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_TRIGOVRFLW" access="WriteOnly" description="Set COUNTER to 0xFFFFF0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TICK" access="Read/Write" description="Event on COUNTER increment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_OVRFLW" access="Read/Write" description="Event on COUNTER overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x340" size="4" name="EVTEN" access="Read/Write" description="Enable or disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Enable or disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Enable or disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Enable or disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Enable or disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Enable or disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Enable or disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x344" size="4" name="EVTENSET" access="Read/Write" description="Enable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x348" size="4" name="EVTENCLR" access="Read/Write" description="Disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="COUNTER" access="ReadOnly" description="Current COUNTER value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNTER" description="Counter value" />
-    </Register>
-    <Register start="+0x508" size="4" name="PRESCALER" access="Read/Write" description="12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QDEC" start="0x40012000" description="Quadrature Decoder">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Task starting the quadrature decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Task stopping the quadrature decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_READCLRACC" access="WriteOnly" description="Read and clear ACC and ACCDBL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_RDCLRACC" access="WriteOnly" description="Read and clear ACC" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_RDCLRDBL" access="WriteOnly" description="Read and clear ACCDBL" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_SAMPLERDY" access="Read/Write" description="Event being generated for every new sample value written to the SAMPLE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_REPORTRDY" access="Read/Write" description="Non-null report ready" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_ACCOF" access="Read/Write" description="ACC or ACCDBL register overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_DBLRDY" access="Read/Write" description="Double displacement(s) detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_STOPPED" access="Read/Write" description="QDEC has been stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REPORTRDY_READCLRACC" description="Shortcut between REPORTRDY event and READCLRACC task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SAMPLERDY_STOP" description="Shortcut between SAMPLERDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="REPORTRDY_RDCLRACC" description="Shortcut between REPORTRDY event and RDCLRACC task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="REPORTRDY_STOP" description="Shortcut between REPORTRDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="DBLRDY_RDCLRDBL" description="Shortcut between DBLRDY event and RDCLRDBL task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="DBLRDY_STOP" description="Shortcut between DBLRDY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="SAMPLERDY_READCLRACC" description="Shortcut between SAMPLERDY event and READCLRACC task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SAMPLERDY" description="Write '1' to Enable interrupt for SAMPLERDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REPORTRDY" description="Write '1' to Enable interrupt for REPORTRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ACCOF" description="Write '1' to Enable interrupt for ACCOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DBLRDY" description="Write '1' to Enable interrupt for DBLRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SAMPLERDY" description="Write '1' to Disable interrupt for SAMPLERDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REPORTRDY" description="Write '1' to Disable interrupt for REPORTRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ACCOF" description="Write '1' to Disable interrupt for ACCOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DBLRDY" description="Write '1' to Disable interrupt for DBLRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable the quadrature decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable the quadrature decoder">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="LEDPOL" access="Read/Write" description="LED output pin polarity" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEDPOL" description="LED output pin polarity">
-        <Enum name="ActiveLow" start="0" description="Led active on output pin low" />
-        <Enum name="ActiveHigh" start="1" description="Led active on output pin high" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="SAMPLEPER" access="Read/Write" description="Sample period" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLEPER" description="Sample period. The SAMPLE register will be updated for every new sample">
-        <Enum name="128us" start="0" description="128 us" />
-        <Enum name="256us" start="1" description="256 us" />
-        <Enum name="512us" start="2" description="512 us" />
-        <Enum name="1024us" start="3" description="1024 us" />
-        <Enum name="2048us" start="4" description="2048 us" />
-        <Enum name="4096us" start="5" description="4096 us" />
-        <Enum name="8192us" start="6" description="8192 us" />
-        <Enum name="16384us" start="7" description="16384 us" />
-        <Enum name="32ms" start="8" description="32768 us" />
-        <Enum name="65ms" start="9" description="65536 us" />
-        <Enum name="131ms" start="10" description="131072 us" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="SAMPLE" access="ReadOnly" description="Motion sample value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLE" description="Last motion sample" />
-    </Register>
-    <Register start="+0x510" size="4" name="REPORTPER" access="Read/Write" description="Number of samples to be taken before REPORTRDY and DBLRDY events can be generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REPORTPER" description="Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated">
-        <Enum name="10Smpl" start="0" description="10 samples / report" />
-        <Enum name="40Smpl" start="1" description="40 samples / report" />
-        <Enum name="80Smpl" start="2" description="80 samples / report" />
-        <Enum name="120Smpl" start="3" description="120 samples / report" />
-        <Enum name="160Smpl" start="4" description="160 samples / report" />
-        <Enum name="200Smpl" start="5" description="200 samples / report" />
-        <Enum name="240Smpl" start="6" description="240 samples / report" />
-        <Enum name="280Smpl" start="7" description="280 samples / report" />
-        <Enum name="1Smpl" start="8" description="1 sample / report" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="ACC" access="ReadOnly" description="Register accumulating the valid transitions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACC" description="Register accumulating all valid samples (not double transition) read from the SAMPLE register" />
-    </Register>
-    <Register start="+0x518" size="4" name="ACCREAD" access="ReadOnly" description="Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ACCREAD" description="Snapshot of the ACC register." />
-    </Register>
-    <Register start="+0x528" size="4" name="DBFEN" access="Read/Write" description="Enable input debounce filters" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBFEN" description="Enable input debounce filters">
-        <Enum name="Disabled" start="0" description="Debounce input filters disabled" />
-        <Enum name="Enabled" start="1" description="Debounce input filters enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x540" size="4" name="LEDPRE" access="Read/Write" description="Time period the LED is switched ON prior to sampling" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="LEDPRE" description="Period in us the LED is switched on prior to sampling" />
-    </Register>
-    <Register start="+0x544" size="4" name="ACCDBL" access="ReadOnly" description="Register accumulating the number of detected double transitions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ACCDBL" description="Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 )." />
-    </Register>
-    <Register start="+0x548" size="4" name="ACCDBLREAD" access="ReadOnly" description="Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ACCDBLREAD" description="Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered." />
-    </Register>
-    <Register start="+0x51C+0x000" size="4" name="PSEL.LED" access="Read/Write" description="Pin select for LED signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C+0x004" size="4" name="PSEL.A" access="Read/Write" description="Pin select for A signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C+0x008" size="4" name="PSEL.B" access="Read/Write" description="Pin select for B signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="COMP" start="0x40013000" description="Comparator">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_SAMPLE" access="WriteOnly" description="Sample comparator value" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="COMP is ready and output is valid" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_DOWN" access="Read/Write" description="Downward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_UP" access="Read/Write" description="Upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_CROSS" access="Read/Write" description="Downward or upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY_SAMPLE" description="Shortcut between READY event and SAMPLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="READY_STOP" description="Shortcut between READY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="DOWN_STOP" description="Shortcut between DOWN event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="UP_STOP" description="Shortcut between UP event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="CROSS_STOP" description="Shortcut between CROSS event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Enable or disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Enable or disable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Enable or disable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Enable or disable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Enable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Enable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Enable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Disable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Disable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Disable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RESULT" access="ReadOnly" description="Compare result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESULT" description="Result of last compare. Decision point SAMPLE task.">
-        <Enum name="Below" start="0" description="Input voltage is below the threshold (VIN+ &amp;lt; VIN-)" />
-        <Enum name="Above" start="1" description="Input voltage is above the threshold (VIN+ &amp;gt; VIN-)" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="COMP enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable COMP">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="2" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PSEL" access="Read/Write" description="Pin select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PSEL" description="Analog pin select">
-        <Enum name="AnalogInput0" start="0" description="AIN0 selected as analog input" />
-        <Enum name="AnalogInput1" start="1" description="AIN1 selected as analog input" />
-        <Enum name="AnalogInput2" start="2" description="AIN2 selected as analog input" />
-        <Enum name="AnalogInput3" start="3" description="AIN3 selected as analog input" />
-        <Enum name="AnalogInput4" start="4" description="AIN4 selected as analog input" />
-        <Enum name="AnalogInput5" start="5" description="AIN5 selected as analog input" />
-        <Enum name="AnalogInput6" start="6" description="AIN6 selected as analog input" />
-        <Enum name="AnalogInput7" start="7" description="AIN7 selected as analog input" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="REFSEL" access="Read/Write" description="Reference source select" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="REFSEL" description="Reference select">
-        <Enum name="Int1V2" start="0" description="VREF = internal 1.2 V reference (VDD &amp;gt;= 1.7 V)" />
-        <Enum name="Int1V8" start="1" description="VREF = internal 1.8 V reference (VDD &amp;gt;= VREF + 0.2 V)" />
-        <Enum name="Int2V4" start="2" description="VREF = internal 2.4 V reference (VDD &amp;gt;= VREF + 0.2 V)" />
-        <Enum name="VDD" start="4" description="VREF = VDD" />
-        <Enum name="ARef" start="5" description="VREF = AREF (VDD &amp;gt;= VREF &amp;gt;= AREFMIN)" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="EXTREFSEL" access="Read/Write" description="External reference select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTREFSEL" description="External analog reference select">
-        <Enum name="AnalogReference0" start="0" description="Use AIN0 as external analog reference" />
-        <Enum name="AnalogReference1" start="1" description="Use AIN1 as external analog reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x530" size="4" name="TH" access="Read/Write" description="Threshold configuration for hysteresis unit" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="THDOWN" description="VDOWN = (THDOWN+1)/64*VREF" />
-      <BitField start="8" size="6" name="THUP" description="VUP = (THUP+1)/64*VREF" />
-    </Register>
-    <Register start="+0x534" size="4" name="MODE" access="Read/Write" description="Mode configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SP" description="Speed and power mode">
-        <Enum name="Low" start="0" description="Low power mode" />
-        <Enum name="Normal" start="1" description="Normal mode" />
-        <Enum name="High" start="2" description="High speed mode" />
-      </BitField>
-      <BitField start="8" size="1" name="MAIN" description="Main operation mode">
-        <Enum name="SE" start="0" description="Single ended mode" />
-        <Enum name="Diff" start="1" description="Differential mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x538" size="4" name="HYST" access="Read/Write" description="Comparator hysteresis enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HYST" description="Comparator hysteresis">
-        <Enum name="NoHyst" start="0" description="Comparator hysteresis disabled" />
-        <Enum name="Hyst50mV" start="1" description="Comparator hysteresis enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x53C" size="4" name="ISOURCE" access="Read/Write" description="Current source select on analog input" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ISOURCE" description="Comparator hysteresis">
-        <Enum name="Off" start="0" description="Current source disabled" />
-        <Enum name="Ien2mA5" start="1" description="Current source enabled (+/- 2.5 uA)" />
-        <Enum name="Ien5mA" start="2" description="Current source enabled (+/- 5 uA)" />
-        <Enum name="Ien10mA" start="3" description="Current source enabled (+/- 10 uA)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LPCOMP" start="0x40013000" description="Low Power Comparator">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop comparator" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_SAMPLE" access="WriteOnly" description="Sample comparator value" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="LPCOMP is ready and output is valid" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_DOWN" access="Read/Write" description="Downward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_UP" access="Read/Write" description="Upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x10C" size="4" name="EVENTS_CROSS" access="Read/Write" description="Downward or upward crossing" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY_SAMPLE" description="Shortcut between READY event and SAMPLE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="READY_STOP" description="Shortcut between READY event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="DOWN_STOP" description="Shortcut between DOWN event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="UP_STOP" description="Shortcut between UP event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="CROSS_STOP" description="Shortcut between CROSS event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Enable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Enable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Enable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="DOWN" description="Write '1' to Disable interrupt for DOWN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="UP" description="Write '1' to Disable interrupt for UP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CROSS" description="Write '1' to Disable interrupt for CROSS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="RESULT" access="ReadOnly" description="Compare result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESULT" description="Result of last compare. Decision point SAMPLE task.">
-        <Enum name="Below" start="0" description="Input voltage is below the reference threshold (VIN+ &amp;lt; VIN-)." />
-        <Enum name="Above" start="1" description="Input voltage is above the reference threshold (VIN+ &amp;gt; VIN-)." />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable LPCOMP" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ENABLE" description="Enable or disable LPCOMP">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PSEL" access="Read/Write" description="Input pin select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PSEL" description="Analog pin select">
-        <Enum name="AnalogInput0" start="0" description="AIN0 selected as analog input" />
-        <Enum name="AnalogInput1" start="1" description="AIN1 selected as analog input" />
-        <Enum name="AnalogInput2" start="2" description="AIN2 selected as analog input" />
-        <Enum name="AnalogInput3" start="3" description="AIN3 selected as analog input" />
-        <Enum name="AnalogInput4" start="4" description="AIN4 selected as analog input" />
-        <Enum name="AnalogInput5" start="5" description="AIN5 selected as analog input" />
-        <Enum name="AnalogInput6" start="6" description="AIN6 selected as analog input" />
-        <Enum name="AnalogInput7" start="7" description="AIN7 selected as analog input" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="REFSEL" access="Read/Write" description="Reference select" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference select">
-        <Enum name="Ref1_8Vdd" start="0" description="VDD * 1/8 selected as reference" />
-        <Enum name="Ref2_8Vdd" start="1" description="VDD * 2/8 selected as reference" />
-        <Enum name="Ref3_8Vdd" start="2" description="VDD * 3/8 selected as reference" />
-        <Enum name="Ref4_8Vdd" start="3" description="VDD * 4/8 selected as reference" />
-        <Enum name="Ref5_8Vdd" start="4" description="VDD * 5/8 selected as reference" />
-        <Enum name="Ref6_8Vdd" start="5" description="VDD * 6/8 selected as reference" />
-        <Enum name="Ref7_8Vdd" start="6" description="VDD * 7/8 selected as reference" />
-        <Enum name="ARef" start="7" description="External analog reference selected" />
-        <Enum name="Ref1_16Vdd" start="8" description="VDD * 1/16 selected as reference" />
-        <Enum name="Ref3_16Vdd" start="9" description="VDD * 3/16 selected as reference" />
-        <Enum name="Ref5_16Vdd" start="10" description="VDD * 5/16 selected as reference" />
-        <Enum name="Ref7_16Vdd" start="11" description="VDD * 7/16 selected as reference" />
-        <Enum name="Ref9_16Vdd" start="12" description="VDD * 9/16 selected as reference" />
-        <Enum name="Ref11_16Vdd" start="13" description="VDD * 11/16 selected as reference" />
-        <Enum name="Ref13_16Vdd" start="14" description="VDD * 13/16 selected as reference" />
-        <Enum name="Ref15_16Vdd" start="15" description="VDD * 15/16 selected as reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="EXTREFSEL" access="Read/Write" description="External reference select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTREFSEL" description="External analog reference select">
-        <Enum name="AnalogReference0" start="0" description="Use AIN0 as external analog reference" />
-        <Enum name="AnalogReference1" start="1" description="Use AIN1 as external analog reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="ANADETECT" access="Read/Write" description="Analog detect configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ANADETECT" description="Analog detect configuration">
-        <Enum name="Cross" start="0" description="Generate ANADETECT on crossing, both upward crossing and downward crossing" />
-        <Enum name="Up" start="1" description="Generate ANADETECT on upward crossing only" />
-        <Enum name="Down" start="2" description="Generate ANADETECT on downward crossing only" />
-      </BitField>
-    </Register>
-    <Register start="+0x538" size="4" name="HYST" access="Read/Write" description="Comparator hysteresis enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HYST" description="Comparator hysteresis enable">
-        <Enum name="NoHyst" start="0" description="Comparator hysteresis disabled" />
-        <Enum name="Hyst50mV" start="1" description="Comparator hysteresis disabled (typ. 50 mV)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI0" start="0x40014000" description="Software interrupt 0">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU0" start="0x40014000" description="Event Generator Unit 0">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI1" start="0x40015000" description="Software interrupt 1">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU1" start="0x40015000" description="Event Generator Unit 1">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI2" start="0x40016000" description="Software interrupt 2">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU2" start="0x40016000" description="Event Generator Unit 2">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI3" start="0x40017000" description="Software interrupt 3">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU3" start="0x40017000" description="Event Generator Unit 3">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI4" start="0x40018000" description="Software interrupt 4">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU4" start="0x40018000" description="Event Generator Unit 4">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SWI5" start="0x40019000" description="Software interrupt 5">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="EGU5" start="0x40019000" description="Event Generator Unit 5">
-    <Register start="+0x000+0" size="4" name="TASKS_TRIGGER[0]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4" size="4" name="TASKS_TRIGGER[1]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+8" size="4" name="TASKS_TRIGGER[2]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+12" size="4" name="TASKS_TRIGGER[3]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+16" size="4" name="TASKS_TRIGGER[4]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+20" size="4" name="TASKS_TRIGGER[5]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+24" size="4" name="TASKS_TRIGGER[6]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+28" size="4" name="TASKS_TRIGGER[7]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+32" size="4" name="TASKS_TRIGGER[8]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+36" size="4" name="TASKS_TRIGGER[9]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+40" size="4" name="TASKS_TRIGGER[10]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+44" size="4" name="TASKS_TRIGGER[11]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+48" size="4" name="TASKS_TRIGGER[12]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+52" size="4" name="TASKS_TRIGGER[13]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+56" size="4" name="TASKS_TRIGGER[14]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+60" size="4" name="TASKS_TRIGGER[15]" access="WriteOnly" description="Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0" size="4" name="EVENTS_TRIGGERED[0]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+4" size="4" name="EVENTS_TRIGGERED[1]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+8" size="4" name="EVENTS_TRIGGERED[2]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+12" size="4" name="EVENTS_TRIGGERED[3]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+16" size="4" name="EVENTS_TRIGGERED[4]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+20" size="4" name="EVENTS_TRIGGERED[5]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+24" size="4" name="EVENTS_TRIGGERED[6]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+28" size="4" name="EVENTS_TRIGGERED[7]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+32" size="4" name="EVENTS_TRIGGERED[8]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+36" size="4" name="EVENTS_TRIGGERED[9]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+40" size="4" name="EVENTS_TRIGGERED[10]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+44" size="4" name="EVENTS_TRIGGERED[11]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+48" size="4" name="EVENTS_TRIGGERED[12]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+52" size="4" name="EVENTS_TRIGGERED[13]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+56" size="4" name="EVENTS_TRIGGERED[14]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+60" size="4" name="EVENTS_TRIGGERED[15]" access="Read/Write" description="Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Enable or disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Enable or disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Enable or disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Enable or disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Enable or disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Enable or disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Enable or disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Enable or disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Enable or disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Enable or disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Enable or disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Enable or disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Enable or disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Enable or disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Enable or disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Enable or disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Enable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Enable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Enable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Enable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Enable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Enable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Enable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Enable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Enable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Enable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Enable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Enable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Enable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Enable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Enable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Enable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRIGGERED0" description="Write '1' to Disable interrupt for TRIGGERED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRIGGERED1" description="Write '1' to Disable interrupt for TRIGGERED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="TRIGGERED2" description="Write '1' to Disable interrupt for TRIGGERED[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="TRIGGERED3" description="Write '1' to Disable interrupt for TRIGGERED[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="TRIGGERED4" description="Write '1' to Disable interrupt for TRIGGERED[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TRIGGERED5" description="Write '1' to Disable interrupt for TRIGGERED[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="TRIGGERED6" description="Write '1' to Disable interrupt for TRIGGERED[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TRIGGERED7" description="Write '1' to Disable interrupt for TRIGGERED[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="TRIGGERED8" description="Write '1' to Disable interrupt for TRIGGERED[8] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="TRIGGERED9" description="Write '1' to Disable interrupt for TRIGGERED[9] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="TRIGGERED10" description="Write '1' to Disable interrupt for TRIGGERED[10] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="TRIGGERED11" description="Write '1' to Disable interrupt for TRIGGERED[11] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="TRIGGERED12" description="Write '1' to Disable interrupt for TRIGGERED[12] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="TRIGGERED13" description="Write '1' to Disable interrupt for TRIGGERED[13] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="TRIGGERED14" description="Write '1' to Disable interrupt for TRIGGERED[14] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="TRIGGERED15" description="Write '1' to Disable interrupt for TRIGGERED[15] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x4001A000" description="Timer/Counter 3">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER4" start="0x4001B000" description="Timer/Counter 4">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop Timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_COUNT" access="WriteOnly" description="Increment Timer (Counter mode only)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear time" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_SHUTDOWN" access="WriteOnly" description="Deprecated register -  Shut down timer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+0" size="4" name="TASKS_CAPTURE[0]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+4" size="4" name="TASKS_CAPTURE[1]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+8" size="4" name="TASKS_CAPTURE[2]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+12" size="4" name="TASKS_CAPTURE[3]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+16" size="4" name="TASKS_CAPTURE[4]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x040+20" size="4" name="TASKS_CAPTURE[5]" access="WriteOnly" description="Description collection[0]:  Capture Timer value to CC[0] register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+16" size="4" name="EVENTS_COMPARE[4]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+20" size="4" name="EVENTS_COMPARE[5]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPARE0_CLEAR" description="Shortcut between COMPARE[0] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="COMPARE1_CLEAR" description="Shortcut between COMPARE[1] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="COMPARE2_CLEAR" description="Shortcut between COMPARE[2] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="COMPARE3_CLEAR" description="Shortcut between COMPARE[3] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="COMPARE4_CLEAR" description="Shortcut between COMPARE[4] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="5" size="1" name="COMPARE5_CLEAR" description="Shortcut between COMPARE[5] event and CLEAR task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="8" size="1" name="COMPARE0_STOP" description="Shortcut between COMPARE[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="9" size="1" name="COMPARE1_STOP" description="Shortcut between COMPARE[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="10" size="1" name="COMPARE2_STOP" description="Shortcut between COMPARE[2] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="11" size="1" name="COMPARE3_STOP" description="Shortcut between COMPARE[3] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="12" size="1" name="COMPARE4_STOP" description="Shortcut between COMPARE[4] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="13" size="1" name="COMPARE5_STOP" description="Shortcut between COMPARE[5] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Enable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Enable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="COMPARE4" description="Write '1' to Disable interrupt for COMPARE[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="COMPARE5" description="Write '1' to Disable interrupt for COMPARE[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STATUS" access="ReadOnly" description="Timer status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS" description="Timer status">
-        <Enum name="Stopped" start="0" description="Timer is stopped" />
-        <Enum name="Started" start="1" description="Timer is started" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Timer mode selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Timer mode">
-        <Enum name="Timer" start="0" description="Select Timer mode" />
-        <Enum name="Counter" start="1" description="Deprecated enumerator -  Select Counter mode" />
-        <Enum name="LowPowerCounter" start="2" description="Select Low Power Counter mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="BITMODE" access="Read/Write" description="Configure the number of bits used by the TIMER" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BITMODE" description="Timer bit width">
-        <Enum name="16Bit" start="0" description="16 bit timer bit width" />
-        <Enum name="08Bit" start="1" description="8 bit timer bit width" />
-        <Enum name="24Bit" start="2" description="24 bit timer bit width" />
-        <Enum name="32Bit" start="3" description="32 bit timer bit width" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="PRESCALER" access="Read/Write" description="Timer prescaler register" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+16" size="4" name="CC[4]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-    <Register start="+0x540+20" size="4" name="CC[5]" access="Read/Write" description="Description collection[0]:  Capture/Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Capture/Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM0" start="0x4001C000" description="Pulse Width Modulation Unit 0">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PDM" start="0x4001D000" description="Pulse Density Modulation (Digital Microphone) Interface">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Starts continuous PDM transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PDM transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_STARTED" access="Read/Write" description="PDM transfer has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="PDM transfer has finished" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_END" access="Read/Write" description="The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="END" description="Enable or disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PDM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PDM module">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="PDMCLKCTRL" access="Read/Write" description="PDM clock generator control" reset_value="0x08400000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQ" description="PDM_CLK frequency">
-        <Enum name="1000K" start="0x08000000" description="PDM_CLK = 32 MHz / 32 = 1.000 MHz" />
-        <Enum name="Default" start="0x08400000" description="PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64." />
-        <Enum name="1067K" start="0x08800000" description="PDM_CLK = 32 MHz / 30 = 1.067 MHz" />
-        <Enum name="1231K" start="0x09800000" description="PDM_CLK = 32 MHz / 26 = 1.231 MHz" />
-        <Enum name="1280K" start="0x0A000000" description="PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80." />
-        <Enum name="1333K" start="0x0A800000" description="PDM_CLK = 32 MHz / 24 = 1.333 MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="MODE" access="Read/Write" description="Defines the routing of the connected PDM microphones' signals" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OPERATION" description="Mono or stereo operation">
-        <Enum name="Stereo" start="0" description="Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]" />
-        <Enum name="Mono" start="1" description="Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]" />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Defines on which PDM_CLK edge Left (or mono) is sampled">
-        <Enum name="LeftFalling" start="0" description="Left (or mono) is sampled on falling edge of PDM_CLK" />
-        <Enum name="LeftRising" start="1" description="Left (or mono) is sampled on rising edge of PDM_CLK" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="GAINL" access="Read/Write" description="Left output gain adjustment" reset_value="0x00000028" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="GAINL" description="Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust">
-        <Enum name="MinGain" start="0x00" description="-20dB gain adjustment (minimum)" />
-        <Enum name="DefaultGain" start="0x28" description="0dB gain adjustment ('2500 RMS' requirement)" />
-        <Enum name="MaxGain" start="0x50" description="+20dB gain adjustment (maximum)" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="GAINR" access="Read/Write" description="Right output gain adjustment" reset_value="0x00000028" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="GAINR" description="Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)">
-        <Enum name="MinGain" start="0x00" description="-20dB gain adjustment (minimum)" />
-        <Enum name="DefaultGain" start="0x28" description="0dB gain adjustment ('2500 RMS' requirement)" />
-        <Enum name="MaxGain" start="0x50" description="+20dB gain adjustment (maximum)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="RATIO" access="Read/Write" description="Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RATIO" description="Selects the ratio between PDM_CLK and output sample rate">
-        <Enum name="Ratio64" start="0" description="Ratio of 64" />
-        <Enum name="Ratio80" start="1" description="Ratio of 80" />
-      </BitField>
-    </Register>
-    <Register start="+0x540+0x000" size="4" name="PSEL.CLK" access="Read/Write" description="Pin number configuration for PDM CLK signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x540+0x004" size="4" name="PSEL.DIN" access="Read/Write" description="Pin number configuration for PDM DIN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="SAMPLE.PTR" access="Read/Write" description="RAM address pointer to write samples to with EasyDMA" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLEPTR" description="Address to write PDM samples to over DMA" />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="SAMPLE.MAXCNT" access="Read/Write" description="Number of samples to allocate memory for in EasyDMA mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="BUFFSIZE" description="Length of DMA RAM allocation in number of samples" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVMC" start="0x4001E000" description="Non Volatile Memory Controller">
-    <Register start="+0x400" size="4" name="READY" access="ReadOnly" description="Ready flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVMC is ready or busy">
-        <Enum name="Busy" start="0" description="NVMC is busy (on-going write or erase operation)" />
-        <Enum name="Ready" start="1" description="NVMC is ready" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WEN" description="Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.">
-        <Enum name="Ren" start="0" description="Read only access" />
-        <Enum name="Wen" start="1" description="Write enabled" />
-        <Enum name="Een" start="2" description="Erase enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="ERASEPAGE" access="Read/Write" description="Register for erasing a page in code area" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ERASEPAGE" description="Register for starting erase of a page in code area" />
-    </Register>
-    <Register start="+0x508" size="4" name="ERASEPCR1" access="Read/Write" description="Deprecated register -  Register for erasing a page in code area. Equivalent to ERASEPAGE." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ERASEPCR1" description="Register for erasing a page in code area. Equivalent to ERASEPAGE." />
-    </Register>
-    <Register start="+0x50C" size="4" name="ERASEALL" access="Read/Write" description="Register for erasing all non-volatile user memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERASEALL" description="Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.">
-        <Enum name="NoOperation" start="0" description="No operation" />
-        <Enum name="Erase" start="1" description="Start chip erase" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="ERASEPCR0" access="Read/Write" description="Deprecated register -  Register for erasing a page in code area. Equivalent to ERASEPAGE." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ERASEPCR0" description="Register for starting erase of a page in code area. Equivalent to ERASEPAGE." />
-    </Register>
-    <Register start="+0x514" size="4" name="ERASEUICR" access="Read/Write" description="Register for erasing user information configuration registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERASEUICR" description="Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.">
-        <Enum name="NoOperation" start="0" description="No operation" />
-        <Enum name="Erase" start="1" description="Start erase of UICR" />
-      </BitField>
-    </Register>
-    <Register start="+0x540" size="4" name="ICACHECNF" access="Read/Write" description="I-code cache configuration register." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CACHEEN" description="Cache enable">
-        <Enum name="Disabled" start="0" description="Disable cache. Invalidates all cache entries." />
-        <Enum name="Enabled" start="1" description="Enable cache" />
-      </BitField>
-      <BitField start="8" size="1" name="CACHEPROFEN" description="Cache profiling enable">
-        <Enum name="Disabled" start="0" description="Disable cache profiling" />
-        <Enum name="Enabled" start="1" description="Enable cache profiling" />
-      </BitField>
-    </Register>
-    <Register start="+0x548" size="4" name="IHIT" access="Read/Write" description="I-code cache hit counter." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HITS" description="Number of cache hits" />
-    </Register>
-    <Register start="+0x54C" size="4" name="IMISS" access="Read/Write" description="I-code cache miss counter." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MISSES" description="Number of cache misses" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ACL (ACL[%s])" start="0x4001E000" description="Access control lists">
-    <Register start="+0x000" size="4" name="ADDR" access="Read/Write" description="Description cluster[0]:  Configure the word-aligned start address of region 0 to protect" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary." />
-    </Register>
-    <Register start="+0x004" size="4" name="SIZE" access="Read/Write" description="Description cluster[0]:  Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SIZE" description="Size of flash region 0 in bytes. Must be a multiple of the flash page size." />
-    </Register>
-    <Register start="+0x008" size="4" name="PERM" access="Read/Write" description="Description cluster[0]:  Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="WRITE" description="Configure write and erase permissions for region 0. Write '0' has no effect.">
-        <Enum name="Enable" start="0" description="Allow write and erase instructions to region 0" />
-        <Enum name="Disable" start="1" description="Block write and erase instructions to region 0" />
-      </BitField>
-      <BitField start="2" size="1" name="READ" description="Configure read permissions for region 0. Write '0' has no effect.">
-        <Enum name="Enable" start="0" description="Allow read instructions to region 0" />
-        <Enum name="Disable" start="1" description="Block read instructions to region 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="4" name="UNUSED0" access="Read/Write" description="Unspecified" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="PPI" start="0x4001F000" description="Programmable Peripheral Interconnect">
-    <Register start="+0x500" size="4" name="CHEN" access="Read/Write" description="Channel enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Enable or disable channel 0">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Enable or disable channel 1">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Enable or disable channel 2">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Enable or disable channel 3">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Enable or disable channel 4">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Enable or disable channel 5">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Enable or disable channel 6">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Enable or disable channel 7">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Enable or disable channel 8">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Enable or disable channel 9">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Enable or disable channel 10">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Enable or disable channel 11">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Enable or disable channel 12">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Enable or disable channel 13">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Enable or disable channel 14">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Enable or disable channel 15">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Enable or disable channel 16">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Enable or disable channel 17">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Enable or disable channel 18">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Enable or disable channel 19">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Enable or disable channel 20">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Enable or disable channel 21">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Enable or disable channel 22">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Enable or disable channel 23">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Enable or disable channel 24">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Enable or disable channel 25">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Enable or disable channel 26">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Enable or disable channel 27">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Enable or disable channel 28">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Enable or disable channel 29">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Enable or disable channel 30">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Enable or disable channel 31">
-        <Enum name="Disabled" start="0" description="Disable channel" />
-        <Enum name="Enabled" start="1" description="Enable channel" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="CHENSET" access="Read/Write" description="Channel enable set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Channel 0 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Channel 1 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Channel 2 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Channel 3 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Channel 4 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Channel 5 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Channel 6 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Channel 7 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Channel 8 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Channel 9 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Channel 10 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Channel 11 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Channel 12 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Channel 13 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Channel 14 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Channel 15 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Channel 16 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Channel 17 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Channel 18 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Channel 19 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Channel 20 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Channel 21 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Channel 22 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Channel 23 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Channel 24 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Channel 25 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Channel 26 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Channel 27 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Channel 28 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Channel 29 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Channel 30 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Channel 31 enable set register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="CHENCLR" access="Read/Write" description="Channel enable clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Channel 0 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Channel 1 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Channel 2 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Channel 3 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Channel 4 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Channel 5 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Channel 6 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Channel 7 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Channel 8 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Channel 9 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Channel 10 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Channel 11 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Channel 12 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Channel 13 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Channel 14 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Channel 15 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Channel 16 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Channel 17 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Channel 18 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Channel 19 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Channel 20 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Channel 21 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Channel 22 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Channel 23 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Channel 24 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Channel 25 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Channel 26 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Channel 27 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Channel 28 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Channel 29 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Channel 30 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Channel 31 enable clear register.  Writing '0' has no effect">
-        <Enum name="Disabled" start="0" description="Read: channel disabled" />
-        <Enum name="Enabled" start="1" description="Read: channel enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+0" size="4" name="CHG[0]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+4" size="4" name="CHG[1]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+8" size="4" name="CHG[2]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+12" size="4" name="CHG[3]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+16" size="4" name="CHG[4]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x800+20" size="4" name="CHG[5]" access="Read/Write" description="Description collection[0]:  Channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Include or exclude channel 0">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="CH1" description="Include or exclude channel 1">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="CH2" description="Include or exclude channel 2">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="CH3" description="Include or exclude channel 3">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="CH4" description="Include or exclude channel 4">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="CH5" description="Include or exclude channel 5">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="CH6" description="Include or exclude channel 6">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="CH7" description="Include or exclude channel 7">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="CH8" description="Include or exclude channel 8">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="CH9" description="Include or exclude channel 9">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="CH10" description="Include or exclude channel 10">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="CH11" description="Include or exclude channel 11">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="CH12" description="Include or exclude channel 12">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="CH13" description="Include or exclude channel 13">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="CH14" description="Include or exclude channel 14">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="CH15" description="Include or exclude channel 15">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="CH16" description="Include or exclude channel 16">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="CH17" description="Include or exclude channel 17">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="CH18" description="Include or exclude channel 18">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="CH19" description="Include or exclude channel 19">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="CH20" description="Include or exclude channel 20">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="CH21" description="Include or exclude channel 21">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="CH22" description="Include or exclude channel 22">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="CH23" description="Include or exclude channel 23">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="CH24" description="Include or exclude channel 24">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="CH25" description="Include or exclude channel 25">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="CH26" description="Include or exclude channel 26">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="CH27" description="Include or exclude channel 27">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="CH28" description="Include or exclude channel 28">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="CH29" description="Include or exclude channel 29">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="CH30" description="Include or exclude channel 30">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="CH31" description="Include or exclude channel 31">
-        <Enum name="Excluded" start="0" description="Exclude" />
-        <Enum name="Included" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x000+0*8+0x000" size="4" name="TASKS_CHG[0].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+0*8+0x004" size="4" name="TASKS_CHG[0].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+1*8+0x000" size="4" name="TASKS_CHG[1].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+1*8+0x004" size="4" name="TASKS_CHG[1].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+2*8+0x000" size="4" name="TASKS_CHG[2].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+2*8+0x004" size="4" name="TASKS_CHG[2].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+3*8+0x000" size="4" name="TASKS_CHG[3].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+3*8+0x004" size="4" name="TASKS_CHG[3].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4*8+0x000" size="4" name="TASKS_CHG[4].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+4*8+0x004" size="4" name="TASKS_CHG[4].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+5*8+0x000" size="4" name="TASKS_CHG[5].EN" access="WriteOnly" description="Description cluster[0]:  Enable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000+5*8+0x004" size="4" name="TASKS_CHG[5].DIS" access="WriteOnly" description="Description cluster[0]:  Disable channel group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x510+0*8+0x000" size="4" name="CH[0].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+0*8+0x004" size="4" name="CH[0].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+1*8+0x000" size="4" name="CH[1].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+1*8+0x004" size="4" name="CH[1].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+2*8+0x000" size="4" name="CH[2].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+2*8+0x004" size="4" name="CH[2].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+3*8+0x000" size="4" name="CH[3].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+3*8+0x004" size="4" name="CH[3].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+4*8+0x000" size="4" name="CH[4].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+4*8+0x004" size="4" name="CH[4].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+5*8+0x000" size="4" name="CH[5].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+5*8+0x004" size="4" name="CH[5].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+6*8+0x000" size="4" name="CH[6].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+6*8+0x004" size="4" name="CH[6].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+7*8+0x000" size="4" name="CH[7].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+7*8+0x004" size="4" name="CH[7].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+8*8+0x000" size="4" name="CH[8].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+8*8+0x004" size="4" name="CH[8].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+9*8+0x000" size="4" name="CH[9].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+9*8+0x004" size="4" name="CH[9].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+10*8+0x000" size="4" name="CH[10].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+10*8+0x004" size="4" name="CH[10].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+11*8+0x000" size="4" name="CH[11].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+11*8+0x004" size="4" name="CH[11].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+12*8+0x000" size="4" name="CH[12].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+12*8+0x004" size="4" name="CH[12].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+13*8+0x000" size="4" name="CH[13].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+13*8+0x004" size="4" name="CH[13].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+14*8+0x000" size="4" name="CH[14].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+14*8+0x004" size="4" name="CH[14].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+15*8+0x000" size="4" name="CH[15].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+15*8+0x004" size="4" name="CH[15].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+16*8+0x000" size="4" name="CH[16].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+16*8+0x004" size="4" name="CH[16].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+17*8+0x000" size="4" name="CH[17].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+17*8+0x004" size="4" name="CH[17].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+18*8+0x000" size="4" name="CH[18].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+18*8+0x004" size="4" name="CH[18].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x510+19*8+0x000" size="4" name="CH[19].EEP" access="Read/Write" description="Description cluster[0]:  Channel 0 event end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EEP" description="Pointer to event register. Accepts only addresses to registers from the Event group." />
-    </Register>
-    <Register start="+0x510+19*8+0x004" size="4" name="CH[19].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register. Accepts only addresses to registers from the Task group." />
-    </Register>
-    <Register start="+0x910+0*4+0x000" size="4" name="FORK[0].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+1*4+0x000" size="4" name="FORK[1].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+2*4+0x000" size="4" name="FORK[2].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+3*4+0x000" size="4" name="FORK[3].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+4*4+0x000" size="4" name="FORK[4].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+5*4+0x000" size="4" name="FORK[5].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+6*4+0x000" size="4" name="FORK[6].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+7*4+0x000" size="4" name="FORK[7].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+8*4+0x000" size="4" name="FORK[8].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+9*4+0x000" size="4" name="FORK[9].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+10*4+0x000" size="4" name="FORK[10].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+11*4+0x000" size="4" name="FORK[11].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+12*4+0x000" size="4" name="FORK[12].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+13*4+0x000" size="4" name="FORK[13].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+14*4+0x000" size="4" name="FORK[14].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+15*4+0x000" size="4" name="FORK[15].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+16*4+0x000" size="4" name="FORK[16].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+17*4+0x000" size="4" name="FORK[17].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+18*4+0x000" size="4" name="FORK[18].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+19*4+0x000" size="4" name="FORK[19].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+20*4+0x000" size="4" name="FORK[20].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+21*4+0x000" size="4" name="FORK[21].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+22*4+0x000" size="4" name="FORK[22].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+23*4+0x000" size="4" name="FORK[23].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+24*4+0x000" size="4" name="FORK[24].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+25*4+0x000" size="4" name="FORK[25].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+26*4+0x000" size="4" name="FORK[26].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+27*4+0x000" size="4" name="FORK[27].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+28*4+0x000" size="4" name="FORK[28].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+29*4+0x000" size="4" name="FORK[29].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+30*4+0x000" size="4" name="FORK[30].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-    <Register start="+0x910+31*4+0x000" size="4" name="FORK[31].TEP" access="Read/Write" description="Description cluster[0]:  Channel 0 task end-point" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TEP" description="Pointer to task register" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MWU" start="0x40020000" description="Memory Watch Unit">
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Enable or disable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Enable or disable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Enable or disable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Enable or disable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Enable or disable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Enable or disable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Enable or disable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Enable or disable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Enable or disable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Enable or disable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Enable or disable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Enable or disable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Enable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Enable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Enable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Enable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Enable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Enable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Enable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Enable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Enable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Enable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Enable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Enable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Disable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Disable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Disable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Disable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Disable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Disable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Disable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Disable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Disable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Disable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Disable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Disable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x320" size="4" name="NMIEN" access="Read/Write" description="Enable or disable non-maskable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Enable or disable non-maskable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Enable or disable non-maskable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Enable or disable non-maskable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Enable or disable non-maskable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Enable or disable non-maskable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Enable or disable non-maskable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Enable or disable non-maskable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Enable or disable non-maskable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Enable or disable non-maskable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Enable or disable non-maskable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Enable or disable non-maskable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Enable or disable non-maskable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x324" size="4" name="NMIENSET" access="Read/Write" description="Enable non-maskable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Enable non-maskable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Enable non-maskable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Enable non-maskable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Enable non-maskable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Enable non-maskable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Enable non-maskable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Enable non-maskable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Enable non-maskable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Enable non-maskable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Enable non-maskable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Enable non-maskable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Enable non-maskable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x328" size="4" name="NMIENCLR" access="Read/Write" description="Disable non-maskable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="REGION0WA" description="Write '1' to Disable non-maskable interrupt for REGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="REGION0RA" description="Write '1' to Disable non-maskable interrupt for REGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="REGION1WA" description="Write '1' to Disable non-maskable interrupt for REGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="REGION1RA" description="Write '1' to Disable non-maskable interrupt for REGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="REGION2WA" description="Write '1' to Disable non-maskable interrupt for REGION[2].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="REGION2RA" description="Write '1' to Disable non-maskable interrupt for REGION[2].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="REGION3WA" description="Write '1' to Disable non-maskable interrupt for REGION[3].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="REGION3RA" description="Write '1' to Disable non-maskable interrupt for REGION[3].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PREGION0WA" description="Write '1' to Disable non-maskable interrupt for PREGION[0].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PREGION0RA" description="Write '1' to Disable non-maskable interrupt for PREGION[0].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PREGION1WA" description="Write '1' to Disable non-maskable interrupt for PREGION[1].WA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PREGION1RA" description="Write '1' to Disable non-maskable interrupt for PREGION[1].RA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="REGIONEN" access="Read/Write" description="Enable/disable regions watch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RGN0WA" description="Enable/disable write access watch in region[0]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="1" size="1" name="RGN0RA" description="Enable/disable read access watch in region[0]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="2" size="1" name="RGN1WA" description="Enable/disable write access watch in region[1]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="3" size="1" name="RGN1RA" description="Enable/disable read access watch in region[1]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="4" size="1" name="RGN2WA" description="Enable/disable write access watch in region[2]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="5" size="1" name="RGN2RA" description="Enable/disable read access watch in region[2]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="6" size="1" name="RGN3WA" description="Enable/disable write access watch in region[3]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this region" />
-      </BitField>
-      <BitField start="7" size="1" name="RGN3RA" description="Enable/disable read access watch in region[3]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this region" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this region" />
-      </BitField>
-      <BitField start="24" size="1" name="PRGN0WA" description="Enable/disable write access watch in PREGION[0]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this PREGION" />
-      </BitField>
-      <BitField start="25" size="1" name="PRGN0RA" description="Enable/disable read access watch in PREGION[0]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this PREGION" />
-      </BitField>
-      <BitField start="26" size="1" name="PRGN1WA" description="Enable/disable write access watch in PREGION[1]">
-        <Enum name="Disable" start="0" description="Disable write access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable write access watch in this PREGION" />
-      </BitField>
-      <BitField start="27" size="1" name="PRGN1RA" description="Enable/disable read access watch in PREGION[1]">
-        <Enum name="Disable" start="0" description="Disable read access watch in this PREGION" />
-        <Enum name="Enable" start="1" description="Enable read access watch in this PREGION" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="REGIONENSET" access="Read/Write" description="Enable regions watch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RGN0WA" description="Enable write access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RGN0RA" description="Enable read access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RGN1WA" description="Enable write access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RGN1RA" description="Enable read access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="RGN2WA" description="Enable write access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RGN2RA" description="Enable read access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RGN3WA" description="Enable write access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RGN3RA" description="Enable read access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PRGN0WA" description="Enable write access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PRGN0RA" description="Enable read access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PRGN1WA" description="Enable write access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PRGN1RA" description="Enable read access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="REGIONENCLR" access="Read/Write" description="Disable regions watch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RGN0WA" description="Disable write access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="RGN0RA" description="Disable read access watch in region[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RGN1WA" description="Disable write access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="RGN1RA" description="Disable read access watch in region[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="RGN2WA" description="Disable write access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="RGN2RA" description="Disable read access watch in region[2]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RGN3WA" description="Disable write access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Write access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this region is enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="RGN3RA" description="Disable read access watch in region[3]">
-        <Enum name="Disabled" start="0" description="Read access watch in this region is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this region is enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="PRGN0WA" description="Disable write access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="PRGN0RA" description="Disable read access watch in PREGION[0]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="26" size="1" name="PRGN1WA" description="Disable write access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Write access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Write access watch in this PREGION is enabled" />
-      </BitField>
-      <BitField start="27" size="1" name="PRGN1RA" description="Disable read access watch in PREGION[1]">
-        <Enum name="Disabled" start="0" description="Read access watch in this PREGION is disabled" />
-        <Enum name="Enabled" start="1" description="Read access watch in this PREGION is enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x100+0*8+0x000" size="4" name="EVENTS_REGION[0].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+0*8+0x004" size="4" name="EVENTS_REGION[0].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+1*8+0x000" size="4" name="EVENTS_REGION[1].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+1*8+0x004" size="4" name="EVENTS_REGION[1].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+2*8+0x000" size="4" name="EVENTS_REGION[2].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+2*8+0x004" size="4" name="EVENTS_REGION[2].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+3*8+0x000" size="4" name="EVENTS_REGION[3].WA" access="Read/Write" description="Description cluster[0]:  Write access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100+3*8+0x004" size="4" name="EVENTS_REGION[3].RA" access="Read/Write" description="Description cluster[0]:  Read access to region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+0*8+0x000" size="4" name="EVENTS_PREGION[0].WA" access="Read/Write" description="Description cluster[0]:  Write access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+0*8+0x004" size="4" name="EVENTS_PREGION[0].RA" access="Read/Write" description="Description cluster[0]:  Read access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+1*8+0x000" size="4" name="EVENTS_PREGION[1].WA" access="Read/Write" description="Description cluster[0]:  Write access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160+1*8+0x004" size="4" name="EVENTS_PREGION[1].RA" access="Read/Write" description="Description cluster[0]:  Read access to peripheral region 0 detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x400+0*8+0x000" size="4" name="PERREGION[0].SUBSTATWA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x400+0*8+0x004" size="4" name="PERREGION[0].SUBSTATRA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x400+1*8+0x000" size="4" name="PERREGION[1].SUBSTATWA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No write access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Write access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x400+1*8+0x004" size="4" name="PERREGION[1].SUBSTATRA" access="Read/Write" description="Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Subregion 0 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Subregion 1 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Subregion 2 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Subregion 3 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Subregion 4 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Subregion 5 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Subregion 6 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Subregion 7 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Subregion 8 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Subregion 9 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Subregion 10 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Subregion 11 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Subregion 12 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Subregion 13 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Subregion 14 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Subregion 15 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Subregion 16 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Subregion 17 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Subregion 18 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Subregion 19 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Subregion 20 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Subregion 21 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Subregion 22 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Subregion 23 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Subregion 24 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Subregion 25 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Subregion 26 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Subregion 27 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Subregion 28 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Subregion 29 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Subregion 30 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Subregion 31 in region 0 (write '1' to clear)">
-        <Enum name="NoAccess" start="0" description="No read access occurred in this subregion" />
-        <Enum name="Access" start="1" description="Read access(es) occurred in this subregion" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+0*16+0x000" size="4" name="REGION[0].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+0*16+0x004" size="4" name="REGION[0].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x600+1*16+0x000" size="4" name="REGION[1].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+1*16+0x004" size="4" name="REGION[1].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x600+2*16+0x000" size="4" name="REGION[2].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+2*16+0x004" size="4" name="REGION[2].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x600+3*16+0x000" size="4" name="REGION[3].START" access="Read/Write" description="Description cluster[0]:  Start address for region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Start address for region" />
-    </Register>
-    <Register start="+0x600+3*16+0x004" size="4" name="REGION[3].END" access="Read/Write" description="Description cluster[0]:  End address of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End address of region." />
-    </Register>
-    <Register start="+0x6C0+0*16+0x000" size="4" name="PREGION[0].START" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+0*16+0x004" size="4" name="PREGION[0].END" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+0*16+0x008" size="4" name="PREGION[0].SUBS" access="Read/Write" description="Description cluster[0]:  Subregions of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Include or exclude subregion 0 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Include or exclude subregion 1 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Include or exclude subregion 2 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Include or exclude subregion 3 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Include or exclude subregion 4 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Include or exclude subregion 5 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Include or exclude subregion 6 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Include or exclude subregion 7 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Include or exclude subregion 8 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Include or exclude subregion 9 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Include or exclude subregion 10 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Include or exclude subregion 11 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Include or exclude subregion 12 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Include or exclude subregion 13 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Include or exclude subregion 14 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Include or exclude subregion 15 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Include or exclude subregion 16 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Include or exclude subregion 17 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Include or exclude subregion 18 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Include or exclude subregion 19 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Include or exclude subregion 20 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Include or exclude subregion 21 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Include or exclude subregion 22 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Include or exclude subregion 23 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Include or exclude subregion 24 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Include or exclude subregion 25 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Include or exclude subregion 26 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Include or exclude subregion 27 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Include or exclude subregion 28 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Include or exclude subregion 29 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Include or exclude subregion 30 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Include or exclude subregion 31 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-    </Register>
-    <Register start="+0x6C0+1*16+0x000" size="4" name="PREGION[1].START" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="START" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+1*16+0x004" size="4" name="PREGION[1].END" access="ReadOnly" description="Description cluster[0]:  Reserved for future use" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="Reserved for future use" />
-    </Register>
-    <Register start="+0x6C0+1*16+0x008" size="4" name="PREGION[1].SUBS" access="Read/Write" description="Description cluster[0]:  Subregions of region 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SR0" description="Include or exclude subregion 0 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="1" size="1" name="SR1" description="Include or exclude subregion 1 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="2" size="1" name="SR2" description="Include or exclude subregion 2 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="3" size="1" name="SR3" description="Include or exclude subregion 3 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="4" size="1" name="SR4" description="Include or exclude subregion 4 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="5" size="1" name="SR5" description="Include or exclude subregion 5 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="6" size="1" name="SR6" description="Include or exclude subregion 6 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="7" size="1" name="SR7" description="Include or exclude subregion 7 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="8" size="1" name="SR8" description="Include or exclude subregion 8 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="9" size="1" name="SR9" description="Include or exclude subregion 9 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="10" size="1" name="SR10" description="Include or exclude subregion 10 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="11" size="1" name="SR11" description="Include or exclude subregion 11 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="12" size="1" name="SR12" description="Include or exclude subregion 12 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="13" size="1" name="SR13" description="Include or exclude subregion 13 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="14" size="1" name="SR14" description="Include or exclude subregion 14 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="15" size="1" name="SR15" description="Include or exclude subregion 15 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="16" size="1" name="SR16" description="Include or exclude subregion 16 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="17" size="1" name="SR17" description="Include or exclude subregion 17 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="18" size="1" name="SR18" description="Include or exclude subregion 18 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="19" size="1" name="SR19" description="Include or exclude subregion 19 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="20" size="1" name="SR20" description="Include or exclude subregion 20 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="21" size="1" name="SR21" description="Include or exclude subregion 21 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="22" size="1" name="SR22" description="Include or exclude subregion 22 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="23" size="1" name="SR23" description="Include or exclude subregion 23 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="24" size="1" name="SR24" description="Include or exclude subregion 24 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="25" size="1" name="SR25" description="Include or exclude subregion 25 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="26" size="1" name="SR26" description="Include or exclude subregion 26 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="27" size="1" name="SR27" description="Include or exclude subregion 27 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="28" size="1" name="SR28" description="Include or exclude subregion 28 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="29" size="1" name="SR29" description="Include or exclude subregion 29 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="30" size="1" name="SR30" description="Include or exclude subregion 30 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-      <BitField start="31" size="1" name="SR31" description="Include or exclude subregion 31 in region">
-        <Enum name="Exclude" start="0" description="Exclude" />
-        <Enum name="Include" start="1" description="Include" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40021000" description="Pulse Width Modulation Unit 1">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM2" start="0x40022000" description="Pulse Width Modulation Unit 2">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM2" start="0x40023000" description="Serial Peripheral Interface Master with EasyDMA 2">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIS2" start="0x40023000" description="SPI Slave 2">
-    <Register start="+0x024" size="4" name="TASKS_ACQUIRE" access="WriteOnly" description="Acquire SPI semaphore" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028" size="4" name="TASKS_RELEASE" access="WriteOnly" description="Release SPI semaphore, enabling the SPI slave to acquire it" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_END" access="Read/Write" description="Granted transaction completed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_ACQUIRED" access="Read/Write" description="Semaphore acquired" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="END_ACQUIRE" description="Shortcut between END event and ACQUIRE task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Enable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="ACQUIRED" description="Write '1' to Disable interrupt for ACQUIRED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="SEMSTAT" access="ReadOnly" description="Semaphore status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SEMSTAT" description="Semaphore status">
-        <Enum name="Free" start="0" description="Semaphore is free" />
-        <Enum name="CPU" start="1" description="Semaphore is assigned to CPU" />
-        <Enum name="SPIS" start="2" description="Semaphore is assigned to SPI slave" />
-        <Enum name="CPUPending" start="3" description="Semaphore is assigned to SPI but a handover to the CPU is pending" />
-      </BitField>
-    </Register>
-    <Register start="+0x440" size="4" name="STATUS" access="Read/Write" description="Status from last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERREAD" description="TX buffer over-read detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="OVERFLOW" description="RX buffer overflow detected, and prevented">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI slave">
-        <Enum name="Disabled" start="0" description="Disable SPI slave" />
-        <Enum name="Enabled" start="2" description="Enable SPI slave" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x55C" size="4" name="DEF" access="Read/Write" description="Default character. Character clocked out in case of an ignored transaction." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEF" description="Default character. Character clocked out in case of an ignored transaction." />
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Over-read character" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Over-read character. Character clocked out after an over-read of the transmit buffer." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="RXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="RXD data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes received in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes received in the last granted transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="TXD data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="TXD data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transmitted in last granted transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="AMOUNT" description="Number of bytes transmitted in last granted transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI2" start="0x40023000" description="Serial Peripheral Interface 2">
-    <Register start="+0x108" size="4" name="EVENTS_READY" access="Read/Write" description="TXD byte sent and RXD byte received" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPI" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPI">
-        <Enum name="Disabled" start="0" description="Disable SPI" />
-        <Enum name="Enabled" start="1" description="Enable SPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="RXD" access="None" description="RXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXD" description="RX data received. Double buffered" />
-    </Register>
-    <Register start="+0x51C" size="4" name="TXD" access="Read/Write" description="TXD register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXD" description="TX data to send. Double buffered" />
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC2" start="0x40024000" description="Real time counter 2">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Start RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_CLEAR" access="WriteOnly" description="Clear RTC COUNTER" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_TRIGOVRFLW" access="WriteOnly" description="Set COUNTER to 0xFFFFF0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_TICK" access="Read/Write" description="Event on COUNTER increment" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_OVRFLW" access="Read/Write" description="Event on COUNTER overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+0" size="4" name="EVENTS_COMPARE[0]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+4" size="4" name="EVENTS_COMPARE[1]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+8" size="4" name="EVENTS_COMPARE[2]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140+12" size="4" name="EVENTS_COMPARE[3]" access="Read/Write" description="Description collection[0]:  Compare event on CC[0] match" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable interrupt for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable interrupt for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable interrupt for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable interrupt for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable interrupt for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable interrupt for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x340" size="4" name="EVTEN" access="Read/Write" description="Enable or disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Enable or disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Enable or disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Enable or disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Enable or disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Enable or disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Enable or disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x344" size="4" name="EVTENSET" access="Read/Write" description="Enable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Enable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Enable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Enable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Enable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Enable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Enable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x348" size="4" name="EVTENCLR" access="Read/Write" description="Disable event routing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TICK" description="Write '1' to Disable event routing for TICK event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="OVRFLW" description="Write '1' to Disable event routing for OVRFLW event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="COMPARE0" description="Write '1' to Disable event routing for COMPARE[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="COMPARE1" description="Write '1' to Disable event routing for COMPARE[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="COMPARE2" description="Write '1' to Disable event routing for COMPARE[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="COMPARE3" description="Write '1' to Disable event routing for COMPARE[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="COUNTER" access="ReadOnly" description="Current COUNTER value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNTER" description="Counter value" />
-    </Register>
-    <Register start="+0x508" size="4" name="PRESCALER" access="Read/Write" description="12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESCALER" description="Prescaler value" />
-    </Register>
-    <Register start="+0x540+0" size="4" name="CC[0]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+4" size="4" name="CC[1]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+8" size="4" name="CC[2]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-    <Register start="+0x540+12" size="4" name="CC[3]" access="Read/Write" description="Description collection[0]:  Compare register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COMPARE" description="Compare value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x40025000" description="Inter-IC Sound">
-    <Register start="+0x000" size="4" name="TASKS_START" access="WriteOnly" description="Starts continuous I2S transfer. Also starts MCK generator when this is enabled." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_RXPTRUPD" access="Read/Write" description="The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_STOPPED" access="Read/Write" description="I2S transfer stopped." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x114" size="4" name="EVENTS_TXPTRUPD" access="Read/Write" description="The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RXPTRUPD" description="Enable or disable interrupt for RXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="TXPTRUPD" description="Enable or disable interrupt for TXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RXPTRUPD" description="Write '1' to Enable interrupt for RXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TXPTRUPD" description="Write '1' to Enable interrupt for TXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RXPTRUPD" description="Write '1' to Disable interrupt for RXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="TXPTRUPD" description="Write '1' to Disable interrupt for TXPTRUPD event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable I2S module." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable I2S module.">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x000" size="4" name="CONFIG.MODE" access="Read/Write" description="I2S mode." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="I2S mode.">
-        <Enum name="Master" start="0" description="Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx." />
-        <Enum name="Slave" start="1" description="Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x004" size="4" name="CONFIG.RXEN" access="Read/Write" description="Reception (RX) enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXEN" description="Reception (RX) enable.">
-        <Enum name="Disabled" start="0" description="Reception disabled and now data will be written to the RXD.PTR address." />
-        <Enum name="Enabled" start="1" description="Reception enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x008" size="4" name="CONFIG.TXEN" access="Read/Write" description="Transmission (TX) enable." reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmission (TX) enable.">
-        <Enum name="Disabled" start="0" description="Transmission disabled and now data will be read from the RXD.TXD address." />
-        <Enum name="Enabled" start="1" description="Transmission enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x00C" size="4" name="CONFIG.MCKEN" access="Read/Write" description="Master clock generator enable." reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCKEN" description="Master clock generator enable.">
-        <Enum name="Disabled" start="0" description="Master clock generator disabled and PSEL.MCK not connected(available as GPIO)." />
-        <Enum name="Enabled" start="1" description="Master clock generator running and MCK output on PSEL.MCK." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x010" size="4" name="CONFIG.MCKFREQ" access="Read/Write" description="Master clock generator frequency." reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCKFREQ" description="Master clock generator frequency.">
-        <Enum name="32MDIV2" start="0x80000000" description="32 MHz / 2 = 16.0 MHz" />
-        <Enum name="32MDIV3" start="0x50000000" description="32 MHz / 3 = 10.6666667 MHz" />
-        <Enum name="32MDIV4" start="0x40000000" description="32 MHz / 4 = 8.0 MHz" />
-        <Enum name="32MDIV5" start="0x30000000" description="32 MHz / 5 = 6.4 MHz" />
-        <Enum name="32MDIV6" start="0x28000000" description="32 MHz / 6 = 5.3333333 MHz" />
-        <Enum name="32MDIV8" start="0x20000000" description="32 MHz / 8 = 4.0 MHz" />
-        <Enum name="32MDIV10" start="0x18000000" description="32 MHz / 10 = 3.2 MHz" />
-        <Enum name="32MDIV11" start="0x16000000" description="32 MHz / 11 = 2.9090909 MHz" />
-        <Enum name="32MDIV15" start="0x11000000" description="32 MHz / 15 = 2.1333333 MHz" />
-        <Enum name="32MDIV16" start="0x10000000" description="32 MHz / 16 = 2.0 MHz" />
-        <Enum name="32MDIV21" start="0x0C000000" description="32 MHz / 21 = 1.5238095" />
-        <Enum name="32MDIV23" start="0x0B000000" description="32 MHz / 23 = 1.3913043 MHz" />
-        <Enum name="32MDIV30" start="0x08800000" description="32 MHz / 30 = 1.0666667 MHz" />
-        <Enum name="32MDIV31" start="0x08400000" description="32 MHz / 31 = 1.0322581 MHz" />
-        <Enum name="32MDIV32" start="0x08000000" description="32 MHz / 32 = 1.0 MHz" />
-        <Enum name="32MDIV42" start="0x06000000" description="32 MHz / 42 = 0.7619048 MHz" />
-        <Enum name="32MDIV63" start="0x04100000" description="32 MHz / 63 = 0.5079365 MHz" />
-        <Enum name="32MDIV125" start="0x020C0000" description="32 MHz / 125 = 0.256 MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x014" size="4" name="CONFIG.RATIO" access="Read/Write" description="MCK / LRCK ratio." reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RATIO" description="MCK / LRCK ratio.">
-        <Enum name="32X" start="0" description="LRCK = MCK / 32" />
-        <Enum name="48X" start="1" description="LRCK = MCK / 48" />
-        <Enum name="64X" start="2" description="LRCK = MCK / 64" />
-        <Enum name="96X" start="3" description="LRCK = MCK / 96" />
-        <Enum name="128X" start="4" description="LRCK = MCK / 128" />
-        <Enum name="192X" start="5" description="LRCK = MCK / 192" />
-        <Enum name="256X" start="6" description="LRCK = MCK / 256" />
-        <Enum name="384X" start="7" description="LRCK = MCK / 384" />
-        <Enum name="512X" start="8" description="LRCK = MCK / 512" />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x018" size="4" name="CONFIG.SWIDTH" access="Read/Write" description="Sample width." reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SWIDTH" description="Sample width.">
-        <Enum name="8Bit" start="0" description="8 bit." />
-        <Enum name="16Bit" start="1" description="16 bit." />
-        <Enum name="24Bit" start="2" description="24 bit." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x01C" size="4" name="CONFIG.ALIGN" access="Read/Write" description="Alignment of sample within a frame." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALIGN" description="Alignment of sample within a frame.">
-        <Enum name="Left" start="0" description="Left-aligned." />
-        <Enum name="Right" start="1" description="Right-aligned." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x020" size="4" name="CONFIG.FORMAT" access="Read/Write" description="Frame format." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FORMAT" description="Frame format.">
-        <Enum name="I2S" start="0" description="Original I2S format." />
-        <Enum name="Aligned" start="1" description="Alternate (left- or right-aligned) format." />
-      </BitField>
-    </Register>
-    <Register start="+0x504+0x024" size="4" name="CONFIG.CHANNELS" access="Read/Write" description="Enable channels." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CHANNELS" description="Enable channels.">
-        <Enum name="Stereo" start="0" description="Stereo." />
-        <Enum name="Left" start="1" description="Left only." />
-        <Enum name="Right" start="2" description="Right only." />
-      </BitField>
-    </Register>
-    <Register start="+0x538+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Receive buffer RAM start address." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address." />
-    </Register>
-    <Register start="+0x540+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Transmit buffer RAM start address." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address." />
-    </Register>
-    <Register start="+0x550+0x000" size="4" name="RXTXD.MAXCNT" access="Read/Write" description="Size of RXD and TXD buffers." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="MAXCNT" description="Size of RXD and TXD buffers in number of 32 bit words." />
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="PSEL.MCK" access="Read/Write" description="Pin select for MCK signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x008" size="4" name="PSEL.LRCK" access="Read/Write" description="Pin select for LRCK signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x00C" size="4" name="PSEL.SDIN" access="Read/Write" description="Pin select for SDIN signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x010" size="4" name="PSEL.SDOUT" access="Read/Write" description="Pin select for SDOUT signal." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="8" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FPU" start="0x40026000" description="FPU">
-    <Register start="+0x000" size="4" name="UNUSED" access="ReadOnly" description="Unused." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="USBD" start="0x40027000" description="Universal Serial Bus device">
-    <Register start="+0x004+0" size="4" name="TASKS_STARTEPIN[0]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+4" size="4" name="TASKS_STARTEPIN[1]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+8" size="4" name="TASKS_STARTEPIN[2]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+12" size="4" name="TASKS_STARTEPIN[3]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+16" size="4" name="TASKS_STARTEPIN[4]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+20" size="4" name="TASKS_STARTEPIN[5]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+24" size="4" name="TASKS_STARTEPIN[6]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004+28" size="4" name="TASKS_STARTEPIN[7]" access="WriteOnly" description="Description collection[0]:  Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x024" size="4" name="TASKS_STARTISOIN" access="WriteOnly" description="Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers values, and enables sending data on iso endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+0" size="4" name="TASKS_STARTEPOUT[0]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+4" size="4" name="TASKS_STARTEPOUT[1]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+8" size="4" name="TASKS_STARTEPOUT[2]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+12" size="4" name="TASKS_STARTEPOUT[3]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+16" size="4" name="TASKS_STARTEPOUT[4]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+20" size="4" name="TASKS_STARTEPOUT[5]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+24" size="4" name="TASKS_STARTEPOUT[6]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x028+28" size="4" name="TASKS_STARTEPOUT[7]" access="WriteOnly" description="Description collection[0]:  Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x048" size="4" name="TASKS_STARTISOOUT" access="WriteOnly" description="Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers values, and enables receiving of data on iso endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x04C" size="4" name="TASKS_EP0RCVOUT" access="WriteOnly" description="Allows OUT data stage on control endpoint 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x050" size="4" name="TASKS_EP0STATUS" access="WriteOnly" description="Allows status stage on control endpoint 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x054" size="4" name="TASKS_EP0STALL" access="WriteOnly" description="STALLs data and status stage on control endpoint 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x058" size="4" name="TASKS_DPDMDRIVE" access="WriteOnly" description="Forces D+ and D-lines to the state defined in the DPDMVALUE register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x05C" size="4" name="TASKS_DPDMNODRIVE" access="WriteOnly" description="Stops forcing D+ and D- lines to any state (USB engine takes control)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_USBRESET" access="Read/Write" description="Signals that a USB reset condition has been detected on the USB lines" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STARTED" access="Read/Write" description="Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_ENDEPIN[0]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_ENDEPIN[1]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+8" size="4" name="EVENTS_ENDEPIN[2]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+12" size="4" name="EVENTS_ENDEPIN[3]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+16" size="4" name="EVENTS_ENDEPIN[4]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+20" size="4" name="EVENTS_ENDEPIN[5]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+24" size="4" name="EVENTS_ENDEPIN[6]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+28" size="4" name="EVENTS_ENDEPIN[7]" access="Read/Write" description="Description collection[0]:  The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x128" size="4" name="EVENTS_EP0DATADONE" access="Read/Write" description="An acknowledged data transfer has taken place on the control endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x12C" size="4" name="EVENTS_ENDISOIN" access="Read/Write" description="The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+0" size="4" name="EVENTS_ENDEPOUT[0]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+4" size="4" name="EVENTS_ENDEPOUT[1]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+8" size="4" name="EVENTS_ENDEPOUT[2]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+12" size="4" name="EVENTS_ENDEPOUT[3]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+16" size="4" name="EVENTS_ENDEPOUT[4]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+20" size="4" name="EVENTS_ENDEPOUT[5]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+24" size="4" name="EVENTS_ENDEPOUT[6]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130+28" size="4" name="EVENTS_ENDEPOUT[7]" access="Read/Write" description="Description collection[0]:  The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_ENDISOOUT" access="Read/Write" description="The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x154" size="4" name="EVENTS_SOF" access="Read/Write" description="Signals that a SOF (start of frame) condition has been detected on the USB lines" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_USBEVENT" access="Read/Write" description="An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x15C" size="4" name="EVENTS_EP0SETUP" access="Read/Write" description="A valid SETUP token has been received (and acknowledged) on the control endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x160" size="4" name="EVENTS_EPDATA" access="Read/Write" description="A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x164" size="4" name="EVENTS_ACCESSFAULT" access="Read/Write" description="Access to an unavailable USB register has been attempted (software or EasyDMA). This event can  get fired even when USBD is not ENABLEd." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP0DATADONE_STARTEPIN0" description="Shortcut between EP0DATADONE event and STARTEPIN[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="EP0DATADONE_STARTEPOUT0" description="Shortcut between EP0DATADONE event and STARTEPOUT[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="EP0DATADONE_EP0STATUS" description="Shortcut between EP0DATADONE event and EP0STATUS task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPOUT0_EP0STATUS" description="Shortcut between ENDEPOUT[0] event and EP0STATUS task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPOUT0_EP0RCVOUT" description="Shortcut between ENDEPOUT[0] event and EP0RCVOUT task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USBRESET" description="Enable or disable interrupt for USBRESET event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="STARTED" description="Enable or disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="ENDEPIN0" description="Enable or disable interrupt for ENDEPIN[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPIN1" description="Enable or disable interrupt for ENDEPIN[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPIN2" description="Enable or disable interrupt for ENDEPIN[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="ENDEPIN3" description="Enable or disable interrupt for ENDEPIN[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDEPIN4" description="Enable or disable interrupt for ENDEPIN[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="ENDEPIN5" description="Enable or disable interrupt for ENDEPIN[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDEPIN6" description="Enable or disable interrupt for ENDEPIN[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ENDEPIN7" description="Enable or disable interrupt for ENDEPIN[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="10" size="1" name="EP0DATADONE" description="Enable or disable interrupt for EP0DATADONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDISOIN" description="Enable or disable interrupt for ENDISOIN event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDEPOUT0" description="Enable or disable interrupt for ENDEPOUT[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="13" size="1" name="ENDEPOUT1" description="Enable or disable interrupt for ENDEPOUT[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="14" size="1" name="ENDEPOUT2" description="Enable or disable interrupt for ENDEPOUT[2] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="15" size="1" name="ENDEPOUT3" description="Enable or disable interrupt for ENDEPOUT[3] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="16" size="1" name="ENDEPOUT4" description="Enable or disable interrupt for ENDEPOUT[4] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="ENDEPOUT5" description="Enable or disable interrupt for ENDEPOUT[5] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="18" size="1" name="ENDEPOUT6" description="Enable or disable interrupt for ENDEPOUT[6] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="ENDEPOUT7" description="Enable or disable interrupt for ENDEPOUT[7] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="ENDISOOUT" description="Enable or disable interrupt for ENDISOOUT event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="21" size="1" name="SOF" description="Enable or disable interrupt for SOF event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="USBEVENT" description="Enable or disable interrupt for USBEVENT event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="23" size="1" name="EP0SETUP" description="Enable or disable interrupt for EP0SETUP event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="24" size="1" name="EPDATA" description="Enable or disable interrupt for EPDATA event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="25" size="1" name="ACCESSFAULT" description="Enable or disable interrupt for ACCESSFAULT event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USBRESET" description="Write '1' to Enable interrupt for USBRESET event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ENDEPIN0" description="Write '1' to Enable interrupt for ENDEPIN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPIN1" description="Write '1' to Enable interrupt for ENDEPIN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPIN2" description="Write '1' to Enable interrupt for ENDEPIN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="ENDEPIN3" description="Write '1' to Enable interrupt for ENDEPIN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDEPIN4" description="Write '1' to Enable interrupt for ENDEPIN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ENDEPIN5" description="Write '1' to Enable interrupt for ENDEPIN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDEPIN6" description="Write '1' to Enable interrupt for ENDEPIN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ENDEPIN7" description="Write '1' to Enable interrupt for ENDEPIN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="EP0DATADONE" description="Write '1' to Enable interrupt for EP0DATADONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDISOIN" description="Write '1' to Enable interrupt for ENDISOIN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDEPOUT0" description="Write '1' to Enable interrupt for ENDEPOUT[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="ENDEPOUT1" description="Write '1' to Enable interrupt for ENDEPOUT[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="ENDEPOUT2" description="Write '1' to Enable interrupt for ENDEPOUT[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="ENDEPOUT3" description="Write '1' to Enable interrupt for ENDEPOUT[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="ENDEPOUT4" description="Write '1' to Enable interrupt for ENDEPOUT[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="ENDEPOUT5" description="Write '1' to Enable interrupt for ENDEPOUT[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="ENDEPOUT6" description="Write '1' to Enable interrupt for ENDEPOUT[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="ENDEPOUT7" description="Write '1' to Enable interrupt for ENDEPOUT[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="ENDISOOUT" description="Write '1' to Enable interrupt for ENDISOOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="SOF" description="Write '1' to Enable interrupt for SOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="USBEVENT" description="Write '1' to Enable interrupt for USBEVENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="EP0SETUP" description="Write '1' to Enable interrupt for EP0SETUP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="EPDATA" description="Write '1' to Enable interrupt for EPDATA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="ACCESSFAULT" description="Write '1' to Enable interrupt for ACCESSFAULT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USBRESET" description="Write '1' to Disable interrupt for USBRESET event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="ENDEPIN0" description="Write '1' to Disable interrupt for ENDEPIN[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="ENDEPIN1" description="Write '1' to Disable interrupt for ENDEPIN[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDEPIN2" description="Write '1' to Disable interrupt for ENDEPIN[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="ENDEPIN3" description="Write '1' to Disable interrupt for ENDEPIN[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDEPIN4" description="Write '1' to Disable interrupt for ENDEPIN[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="ENDEPIN5" description="Write '1' to Disable interrupt for ENDEPIN[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDEPIN6" description="Write '1' to Disable interrupt for ENDEPIN[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ENDEPIN7" description="Write '1' to Disable interrupt for ENDEPIN[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="10" size="1" name="EP0DATADONE" description="Write '1' to Disable interrupt for EP0DATADONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="11" size="1" name="ENDISOIN" description="Write '1' to Disable interrupt for ENDISOIN event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="ENDEPOUT0" description="Write '1' to Disable interrupt for ENDEPOUT[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="13" size="1" name="ENDEPOUT1" description="Write '1' to Disable interrupt for ENDEPOUT[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="ENDEPOUT2" description="Write '1' to Disable interrupt for ENDEPOUT[2] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="ENDEPOUT3" description="Write '1' to Disable interrupt for ENDEPOUT[3] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="16" size="1" name="ENDEPOUT4" description="Write '1' to Disable interrupt for ENDEPOUT[4] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="ENDEPOUT5" description="Write '1' to Disable interrupt for ENDEPOUT[5] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="18" size="1" name="ENDEPOUT6" description="Write '1' to Disable interrupt for ENDEPOUT[6] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="ENDEPOUT7" description="Write '1' to Disable interrupt for ENDEPOUT[7] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="ENDISOOUT" description="Write '1' to Disable interrupt for ENDISOOUT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="21" size="1" name="SOF" description="Write '1' to Disable interrupt for SOF event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="USBEVENT" description="Write '1' to Disable interrupt for USBEVENT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="23" size="1" name="EP0SETUP" description="Write '1' to Disable interrupt for EP0SETUP event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="24" size="1" name="EPDATA" description="Write '1' to Disable interrupt for EPDATA event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="25" size="1" name="ACCESSFAULT" description="Write '1' to Disable interrupt for ACCESSFAULT event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="EVENTCAUSE" access="Read/Write" description="Details on event that caused the USBEVENT event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ISOOUTCRC" description="CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="No error detected" />
-        <Enum name="Detected" start="1" description="Error detected" />
-      </BitField>
-      <BitField start="8" size="1" name="SUSPEND" description="Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="Suspend not detected" />
-        <Enum name="Detected" start="1" description="Suspend detected" />
-      </BitField>
-      <BitField start="9" size="1" name="RESUME" description="Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="Resume not detected" />
-        <Enum name="Detected" start="1" description="Resume detected" />
-      </BitField>
-      <BitField start="11" size="1" name="READY" description="Wrapper has re-initialized SFRs to the proper values. MAC is ready for normal operation. Write '1' to clear.">
-        <Enum name="NotDetected" start="0" description="USBEVENT was not issued due to USBD peripheral ready" />
-        <Enum name="Ready" start="1" description="USBD peripheral is ready" />
-      </BitField>
-    </Register>
-    <Register start="+0x404" size="4" name="BUSSTATE" access="ReadOnly" description="Provides the logic state of the D+ and D- lines" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DM" description="State of the D- line">
-        <Enum name="Low" start="0" description="Low" />
-        <Enum name="High" start="1" description="High" />
-      </BitField>
-      <BitField start="1" size="1" name="DP" description="State of the D+ line">
-        <Enum name="Low" start="0" description="Low" />
-        <Enum name="High" start="1" description="High" />
-      </BitField>
-    </Register>
-    <Register start="+0x468" size="4" name="EPSTATUS" access="Read/Write" description="Provides information on which endpoint's EasyDMA registers have been captured" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPIN0" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="1" size="1" name="EPIN1" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="2" size="1" name="EPIN2" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="3" size="1" name="EPIN3" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="4" size="1" name="EPIN4" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="5" size="1" name="EPIN5" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="6" size="1" name="EPIN6" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="7" size="1" name="EPIN7" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="8" size="1" name="EPIN8" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="16" size="1" name="EPOUT0" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="17" size="1" name="EPOUT1" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="18" size="1" name="EPOUT2" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="19" size="1" name="EPOUT3" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="20" size="1" name="EPOUT4" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="21" size="1" name="EPOUT5" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="22" size="1" name="EPOUT6" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="23" size="1" name="EPOUT7" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-      <BitField start="24" size="1" name="EPOUT8" description="Endpoint's EasyDMA registers captured state. Write '1' to clear.">
-        <Enum name="NoData" start="0" description="EasyDMA registers have not been captured for this endpoint" />
-        <Enum name="DataDone" start="1" description="EasyDMA registers have been captured for this endpoint" />
-      </BitField>
-    </Register>
-    <Register start="+0x46C" size="4" name="EPDATASTATUS" access="Read/Write" description="Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="EPIN1" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="2" size="1" name="EPIN2" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="3" size="1" name="EPIN3" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="4" size="1" name="EPIN4" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="5" size="1" name="EPIN5" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="6" size="1" name="EPIN6" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="7" size="1" name="EPIN7" description="Acknowledged data transfer on this IN endpoint. Write '1' to clear.">
-        <Enum name="NotDone" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="DataDone" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="17" size="1" name="EPOUT1" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="18" size="1" name="EPOUT2" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="19" size="1" name="EPOUT3" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="20" size="1" name="EPOUT4" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="21" size="1" name="EPOUT5" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="22" size="1" name="EPOUT6" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-      <BitField start="23" size="1" name="EPOUT7" description="Acknowledged data transfer on this OUT endpoint. Write '1' to clear.">
-        <Enum name="NotStarted" start="0" description="No acknowledged data transfer on this endpoint" />
-        <Enum name="Started" start="1" description="Acknowledged data transfer on this endpoint has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x470" size="4" name="USBADDR" access="ReadOnly" description="Device USB address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="ADDR" description="Device USB address" />
-    </Register>
-    <Register start="+0x480" size="4" name="BMREQUESTTYPE" access="ReadOnly" description="SETUP data, byte 0, bmRequestType" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RECIPIENT" description="Data transfer type">
-        <Enum name="Device" start="0" description="Device" />
-        <Enum name="Interface" start="1" description="Interface" />
-        <Enum name="Endpoint" start="2" description="Endpoint" />
-        <Enum name="Other" start="3" description="Other" />
-      </BitField>
-      <BitField start="5" size="2" name="TYPE" description="Data transfer type">
-        <Enum name="Standard" start="0" description="Standard" />
-        <Enum name="Class" start="1" description="Class" />
-        <Enum name="Vendor" start="2" description="Vendor" />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECTION" description="Data transfer direction">
-        <Enum name="HostToDevice" start="0" description="Host-to-device" />
-        <Enum name="DeviceToHost" start="1" description="Device-to-host" />
-      </BitField>
-    </Register>
-    <Register start="+0x484" size="4" name="BREQUEST" access="ReadOnly" description="SETUP data, byte 1, bRequest" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BREQUEST" description="SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values.">
-        <Enum name="STD_GET_STATUS" start="0" description="Standard request GET_STATUS" />
-        <Enum name="STD_CLEAR_FEATURE" start="1" description="Standard request CLEAR_FEATURE" />
-        <Enum name="STD_SET_FEATURE" start="3" description="Standard request SET_FEATURE" />
-        <Enum name="STD_SET_ADDRESS" start="5" description="Standard request SET_ADDRESS" />
-        <Enum name="STD_GET_DESCRIPTOR" start="6" description="Standard request GET_DESCRIPTOR" />
-        <Enum name="STD_SET_DESCRIPTOR" start="7" description="Standard request SET_DESCRIPTOR" />
-        <Enum name="STD_GET_CONFIGURATION" start="8" description="Standard request GET_CONFIGURATION" />
-        <Enum name="STD_SET_CONFIGURATION" start="9" description="Standard request SET_CONFIGURATION" />
-        <Enum name="STD_GET_INTERFACE" start="10" description="Standard request GET_INTERFACE" />
-        <Enum name="STD_SET_INTERFACE" start="11" description="Standard request SET_INTERFACE" />
-        <Enum name="STD_SYNCH_FRAME" start="12" description="Standard request SYNCH_FRAME" />
-      </BitField>
-    </Register>
-    <Register start="+0x488" size="4" name="WVALUEL" access="ReadOnly" description="SETUP data, byte 2, LSB of wValue" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WVALUEL" description="SETUP data, byte 2, LSB of wValue" />
-    </Register>
-    <Register start="+0x48C" size="4" name="WVALUEH" access="ReadOnly" description="SETUP data, byte 3, MSB of wValue" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WVALUEH" description="SETUP data, byte 3, MSB of wValue" />
-    </Register>
-    <Register start="+0x490" size="4" name="WINDEXL" access="ReadOnly" description="SETUP data, byte 4, LSB of wIndex" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WINDEXL" description="SETUP data, byte 4, LSB of wIndex" />
-    </Register>
-    <Register start="+0x494" size="4" name="WINDEXH" access="ReadOnly" description="SETUP data, byte 5, MSB of wIndex" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WINDEXH" description="SETUP data, byte 5, MSB of wIndex" />
-    </Register>
-    <Register start="+0x498" size="4" name="WLENGTHL" access="ReadOnly" description="SETUP data, byte 6, LSB of wLength" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WLENGTHL" description="SETUP data, byte 6, LSB of wLength" />
-    </Register>
-    <Register start="+0x49C" size="4" name="WLENGTHH" access="ReadOnly" description="SETUP data, byte 7, MSB of wLength" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="WLENGTHH" description="SETUP data, byte 7, MSB of wLength" />
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable USB" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable USB">
-        <Enum name="Disabled" start="0" description="USB peripheral is disabled" />
-        <Enum name="Enabled" start="1" description="USB peripheral is enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="USBPULLUP" access="Read/Write" description="Control of the USB pull-up" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONNECT" description="Control of the USB pull-up on the D+ line">
-        <Enum name="Disabled" start="0" description="Pull-up is disconnected" />
-        <Enum name="Enabled" start="1" description="Pull-up is connected to D+" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="DPDMVALUE" access="Read/Write" description="State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing)." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE" description="State at which the DPDMDRIVE task will force D+ and D-">
-        <Enum name="Resume" start="1" description="D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state)" />
-        <Enum name="J" start="2" description="D+ forced high, D- forced low (J state)" />
-        <Enum name="K" start="4" description="D+ forced low, D- forced high (K state)" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="DTOGGLE" access="Read/Write" description="Data toggle control and status." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EP" description="Select bulk endpoint number" />
-      <BitField start="7" size="1" name="IO" description="Selects IN or OUT endpoint">
-        <Enum name="Out" start="0" description="Selects OUT endpoint" />
-        <Enum name="In" start="1" description="Selects IN endpoint" />
-      </BitField>
-      <BitField start="8" size="2" name="VALUE" description="Data toggle value">
-        <Enum name="Nop" start="0" description="No action on data toggle when writing the register with this value" />
-        <Enum name="Data0" start="1" description="Data toggle is DATA0 on endpoint set by EP and IO" />
-        <Enum name="Data1" start="2" description="Data toggle is DATA1 on endpoint set by EP and IO" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="EPINEN" access="Read/Write" description="Endpoint IN enable" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IN0" description="Enable IN endpoint 0">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 0 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 0 (response to IN tokens)" />
-      </BitField>
-      <BitField start="1" size="1" name="IN1" description="Enable IN endpoint 1">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 1 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 1 (response to IN tokens)" />
-      </BitField>
-      <BitField start="2" size="1" name="IN2" description="Enable IN endpoint 2">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 2 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 2 (response to IN tokens)" />
-      </BitField>
-      <BitField start="3" size="1" name="IN3" description="Enable IN endpoint 3">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 3 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 3 (response to IN tokens)" />
-      </BitField>
-      <BitField start="4" size="1" name="IN4" description="Enable IN endpoint 4">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 4 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 4 (response to IN tokens)" />
-      </BitField>
-      <BitField start="5" size="1" name="IN5" description="Enable IN endpoint 5">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 5 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 5 (response to IN tokens)" />
-      </BitField>
-      <BitField start="6" size="1" name="IN6" description="Enable IN endpoint 6">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 6 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 6 (response to IN tokens)" />
-      </BitField>
-      <BitField start="7" size="1" name="IN7" description="Enable IN endpoint 7">
-        <Enum name="Disable" start="0" description="Disable endpoint IN 7 (no response to IN tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint IN 7 (response to IN tokens)" />
-      </BitField>
-      <BitField start="8" size="1" name="ISOIN" description="Enable iso IN endpoint">
-        <Enum name="Disable" start="0" description="Disable iso IN endpoint 8" />
-        <Enum name="Enable" start="1" description="Enable iso IN endpoint 8" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="EPOUTEN" access="Read/Write" description="Endpoint OUT enable" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OUT0" description="Enable OUT endpoint 0">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 0 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 0 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="1" size="1" name="OUT1" description="Enable OUT endpoint 1">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 1 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 1 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="2" size="1" name="OUT2" description="Enable OUT endpoint 2">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 2 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 2 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="3" size="1" name="OUT3" description="Enable OUT endpoint 3">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 3 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 3 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="4" size="1" name="OUT4" description="Enable OUT endpoint 4">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 4 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 4 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="5" size="1" name="OUT5" description="Enable OUT endpoint 5">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 5 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 5 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="6" size="1" name="OUT6" description="Enable OUT endpoint 6">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 6 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 6 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="7" size="1" name="OUT7" description="Enable OUT endpoint 7">
-        <Enum name="Disable" start="0" description="Disable endpoint OUT 7 (no response to OUT tokens)" />
-        <Enum name="Enable" start="1" description="Enable endpoint OUT 7 (response to OUT tokens)" />
-      </BitField>
-      <BitField start="8" size="1" name="ISOOUT" description="Enable iso OUT endpoint 8">
-        <Enum name="Disable" start="0" description="Disable iso OUT endpoint 8" />
-        <Enum name="Enable" start="1" description="Enable iso OUT endpoint 8" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="EPSTALL" access="None" description="STALL endpoints" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EP" description="Select endpoint number" />
-      <BitField start="7" size="1" name="IO" description="Selects IN or OUT endpoint">
-        <Enum name="Out" start="0" description="Selects OUT endpoint" />
-        <Enum name="In" start="1" description="Selects IN endpoint" />
-      </BitField>
-      <BitField start="8" size="1" name="STALL" description="Stall selected endpoint">
-        <Enum name="UnStall" start="0" description="Don't stall selected endpoint" />
-        <Enum name="Stall" start="1" description="Stall selected endpoint" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="ISOSPLIT" access="Read/Write" description="Controls the split of ISO buffers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SPLIT" description="Controls the split of ISO buffers">
-        <Enum name="OneDir" start="0x0000" description="Full buffer dedicated to either iso IN or OUT" />
-        <Enum name="HalfIN" start="0x0080" description="Lower half for IN, upper half for OUT" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="FRAMECNTR" access="ReadOnly" description="Returns the current value of the start of frame counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="FRAMECNTR" description="Returns the current value of the start of frame counter" />
-    </Register>
-    <Register start="+0x52C" size="4" name="LOWPOWER" access="Read/Write" description="First silicon only: Controls USBD peripheral low-power mode during USB suspend" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOWPOWER" description="Controls USBD peripheral low-power mode during USB suspend">
-        <Enum name="ForceNormal" start="0" description="Software must write this value to exit low power mode and before performing a remote wake-up" />
-        <Enum name="LowPower" start="1" description="Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral" />
-      </BitField>
-    </Register>
-    <Register start="+0x530" size="4" name="ISOINCONFIG" access="Read/Write" description="Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESPONSE" description="Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent">
-        <Enum name="NoResp" start="0" description="Endpoint does not respond in that case" />
-        <Enum name="ZeroData" start="1" description="Endpoint responds with a zero-length data packet in that case" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+0" size="4" name="HALTED.EPIN[0]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+4" size="4" name="HALTED.EPIN[1]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+8" size="4" name="HALTED.EPIN[2]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+12" size="4" name="HALTED.EPIN[3]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+16" size="4" name="HALTED.EPIN[4]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+20" size="4" name="HALTED.EPIN[5]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+24" size="4" name="HALTED.EPIN[6]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x000+28" size="4" name="HALTED.EPIN[7]" access="ReadOnly" description="Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+0" size="4" name="HALTED.EPOUT[0]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+4" size="4" name="HALTED.EPOUT[1]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+8" size="4" name="HALTED.EPOUT[2]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+12" size="4" name="HALTED.EPOUT[3]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+16" size="4" name="HALTED.EPOUT[4]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+20" size="4" name="HALTED.EPOUT[5]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+24" size="4" name="HALTED.EPOUT[6]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x420+0x024+28" size="4" name="HALTED.EPOUT[7]" access="ReadOnly" description="Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GETSTATUS" description="OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.">
-        <Enum name="NotHalted" start="0" description="Endpoint is not halted" />
-        <Enum name="Halted" start="1" description="Endpoint is halted" />
-      </BitField>
-    </Register>
-    <Register start="+0x4A0+0x000+0" size="4" name="SIZE.EPOUT[0]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+4" size="4" name="SIZE.EPOUT[1]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+8" size="4" name="SIZE.EPOUT[2]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+12" size="4" name="SIZE.EPOUT[3]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+16" size="4" name="SIZE.EPOUT[4]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+20" size="4" name="SIZE.EPOUT[5]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+24" size="4" name="SIZE.EPOUT[6]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x000+28" size="4" name="SIZE.EPOUT[7]" access="Read/Write" description="Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SIZE" description="Amount of bytes received last in the data stage of this OUT endpoint" />
-    </Register>
-    <Register start="+0x4A0+0x020" size="4" name="SIZE.ISOOUT" access="ReadOnly" description="Amount of bytes received last on this iso OUT data endpoint" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SIZE" description="Amount of bytes received last on this iso OUT data endpoint" />
-      <BitField start="16" size="1" name="ZERO" description="Zero-length data packet received">
-        <Enum name="Normal" start="0" description="No zero-length data received, use value in SIZE" />
-        <Enum name="ZeroData" start="1" description="Zero-length data received, ignore value in SIZE" />
-      </BitField>
-    </Register>
-    <Register start="+0x600+0*20+0x000" size="4" name="EPIN[0].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+0*20+0x004" size="4" name="EPIN[0].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+0*20+0x008" size="4" name="EPIN[0].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+1*20+0x000" size="4" name="EPIN[1].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+1*20+0x004" size="4" name="EPIN[1].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+1*20+0x008" size="4" name="EPIN[1].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+2*20+0x000" size="4" name="EPIN[2].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+2*20+0x004" size="4" name="EPIN[2].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+2*20+0x008" size="4" name="EPIN[2].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+3*20+0x000" size="4" name="EPIN[3].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+3*20+0x004" size="4" name="EPIN[3].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+3*20+0x008" size="4" name="EPIN[3].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+4*20+0x000" size="4" name="EPIN[4].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+4*20+0x004" size="4" name="EPIN[4].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+4*20+0x008" size="4" name="EPIN[4].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+5*20+0x000" size="4" name="EPIN[5].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+5*20+0x004" size="4" name="EPIN[5].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+5*20+0x008" size="4" name="EPIN[5].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+6*20+0x000" size="4" name="EPIN[6].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+6*20+0x004" size="4" name="EPIN[6].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+6*20+0x008" size="4" name="EPIN[6].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x600+7*20+0x000" size="4" name="EPIN[7].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x600+7*20+0x004" size="4" name="EPIN[7].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x600+7*20+0x008" size="4" name="EPIN[7].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x6A0+0x000" size="4" name="ISOIN.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x6A0+0x004" size="4" name="ISOIN.MAXCNT" access="Read/Write" description="Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x6A0+0x008" size="4" name="ISOIN.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+0*20+0x000" size="4" name="EPOUT[0].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+0*20+0x004" size="4" name="EPOUT[0].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+0*20+0x008" size="4" name="EPOUT[0].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+1*20+0x000" size="4" name="EPOUT[1].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+1*20+0x004" size="4" name="EPOUT[1].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+1*20+0x008" size="4" name="EPOUT[1].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+2*20+0x000" size="4" name="EPOUT[2].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+2*20+0x004" size="4" name="EPOUT[2].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+2*20+0x008" size="4" name="EPOUT[2].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+3*20+0x000" size="4" name="EPOUT[3].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+3*20+0x004" size="4" name="EPOUT[3].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+3*20+0x008" size="4" name="EPOUT[3].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+4*20+0x000" size="4" name="EPOUT[4].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+4*20+0x004" size="4" name="EPOUT[4].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+4*20+0x008" size="4" name="EPOUT[4].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+5*20+0x000" size="4" name="EPOUT[5].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+5*20+0x004" size="4" name="EPOUT[5].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+5*20+0x008" size="4" name="EPOUT[5].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+6*20+0x000" size="4" name="EPOUT[6].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+6*20+0x004" size="4" name="EPOUT[6].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+6*20+0x008" size="4" name="EPOUT[6].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x700+7*20+0x000" size="4" name="EPOUT[7].PTR" access="Read/Write" description="Description cluster[0]:  Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x700+7*20+0x004" size="4" name="EPOUT[7].MAXCNT" access="Read/Write" description="Description cluster[0]:  Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x700+7*20+0x008" size="4" name="EPOUT[7].AMOUNT" access="ReadOnly" description="Description cluster[0]:  Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x7A0+0x000" size="4" name="ISOOUT.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer. Accepts any address in Data RAM." />
-    </Register>
-    <Register start="+0x7A0+0x004" size="4" name="ISOOUT.MAXCNT" access="Read/Write" description="Maximum number of bytes to transfer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes to transfer" />
-    </Register>
-    <Register start="+0x7A0+0x008" size="4" name="ISOOUT.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UARTE1" start="0x40028000" description="UART with EasyDMA 1">
-    <Register start="+0x000" size="4" name="TASKS_STARTRX" access="WriteOnly" description="Start UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_STOPRX" access="WriteOnly" description="Stop UART receiver" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_STARTTX" access="WriteOnly" description="Start UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_STOPTX" access="WriteOnly" description="Stop UART transmitter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x02C" size="4" name="TASKS_FLUSHRX" access="WriteOnly" description="Flush RX FIFO into RX buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_CTS" access="Read/Write" description="CTS is activated (set low). Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_NCTS" access="Read/Write" description="CTS is deactivated (set high). Not Clear To Send." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108" size="4" name="EVENTS_RXDRDY" access="Read/Write" description="Data received in RXD (but potentially not yet transferred to Data RAM)" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="Receive buffer is filled up" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_TXDRDY" access="Read/Write" description="Data sent from TXD" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="Last TX byte transmitted" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x124" size="4" name="EVENTS_ERROR" access="Read/Write" description="Error detected" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x144" size="4" name="EVENTS_RXTO" access="Read/Write" description="Receiver timeout" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_RXSTARTED" access="Read/Write" description="UART receiver has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x150" size="4" name="EVENTS_TXSTARTED" access="Read/Write" description="UART transmitter has started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x158" size="4" name="EVENTS_TXSTOPPED" access="Read/Write" description="Transmitter stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="1" name="ENDRX_STARTRX" description="Shortcut between ENDRX event and STARTRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="6" size="1" name="ENDRX_STOPRX" description="Shortcut between ENDRX event and STOPRX task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Enable or disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Enable or disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Enable or disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Enable or disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Enable or disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Enable or disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Enable or disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Enable or disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Enable or disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Enable or disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Enable or disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Enable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Enable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Enable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Enable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Enable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Enable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Enable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Enable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Enable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CTS" description="Write '1' to Disable interrupt for CTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="NCTS" description="Write '1' to Disable interrupt for NCTS event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="RXDRDY" description="Write '1' to Disable interrupt for RXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="TXDRDY" description="Write '1' to Disable interrupt for TXDRDY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ERROR" description="Write '1' to Disable interrupt for ERROR event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="RXTO" description="Write '1' to Disable interrupt for RXTO event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="RXSTARTED" description="Write '1' to Disable interrupt for RXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="20" size="1" name="TXSTARTED" description="Write '1' to Disable interrupt for TXSTARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXSTOPPED" description="Write '1' to Disable interrupt for TXSTOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x480" size="4" name="ERRORSRC" access="Read/Write" description="Error source Note : this register is read / write one to clear." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVERRUN" description="Overrun error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="1" size="1" name="PARITY" description="Parity error">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="2" size="1" name="FRAMING" description="Framing error occurred">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-      <BitField start="3" size="1" name="BREAK" description="Break condition">
-        <Enum name="NotPresent" start="0" description="Read: error not present" />
-        <Enum name="Present" start="1" description="Read: error present" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable UART" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable UARTE">
-        <Enum name="Disabled" start="0" description="Disable UARTE" />
-        <Enum name="Enabled" start="8" description="Enable UARTE" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="BAUDRATE" access="Read/Write" description="Baud rate. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BAUDRATE" description="Baud rate">
-        <Enum name="Baud1200" start="0x0004F000" description="1200 baud (actual rate: 1205)" />
-        <Enum name="Baud2400" start="0x0009D000" description="2400 baud (actual rate: 2396)" />
-        <Enum name="Baud4800" start="0x0013B000" description="4800 baud (actual rate: 4808)" />
-        <Enum name="Baud9600" start="0x00275000" description="9600 baud (actual rate: 9598)" />
-        <Enum name="Baud14400" start="0x003AF000" description="14400 baud (actual rate: 14401)" />
-        <Enum name="Baud19200" start="0x004EA000" description="19200 baud (actual rate: 19208)" />
-        <Enum name="Baud28800" start="0x0075C000" description="28800 baud (actual rate: 28777)" />
-        <Enum name="Baud31250" start="0x00800000" description="31250 baud" />
-        <Enum name="Baud38400" start="0x009D0000" description="38400 baud (actual rate: 38369)" />
-        <Enum name="Baud56000" start="0x00E50000" description="56000 baud (actual rate: 55944)" />
-        <Enum name="Baud57600" start="0x00EB0000" description="57600 baud (actual rate: 57554)" />
-        <Enum name="Baud76800" start="0x013A9000" description="76800 baud (actual rate: 76923)" />
-        <Enum name="Baud115200" start="0x01D60000" description="115200 baud (actual rate: 115108)" />
-        <Enum name="Baud230400" start="0x03B00000" description="230400 baud (actual rate: 231884)" />
-        <Enum name="Baud250000" start="0x04000000" description="250000 baud" />
-        <Enum name="Baud460800" start="0x07400000" description="460800 baud (actual rate: 457143)" />
-        <Enum name="Baud921600" start="0x0F000000" description="921600 baud (actual rate: 941176)" />
-        <Enum name="Baud1M" start="0x10000000" description="1Mega baud" />
-      </BitField>
-    </Register>
-    <Register start="+0x56C" size="4" name="CONFIG" access="Read/Write" description="Configuration of parity and hardware flow control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HWFC" description="Hardware flow control">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="3" name="PARITY" description="Parity">
-        <Enum name="Excluded" start="0x0" description="Exclude parity bit" />
-        <Enum name="Included" start="0x7" description="Include even parity bit" />
-      </BitField>
-      <BitField start="4" size="1" name="STOP" description="Stop bits">
-        <Enum name="One" start="0" description="One stop bit" />
-        <Enum name="Two" start="1" description="Two stop bits" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.RTS" access="Read/Write" description="Pin select for RTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.TXD" access="Read/Write" description="Pin select for TXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.CTS" access="Read/Write" description="Pin select for CTS signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.RXD" access="Read/Write" description="Pin select for RXD signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QSPI" start="0x40029000" description="External flash interface">
-    <Register start="+0x000" size="4" name="TASKS_ACTIVATE" access="WriteOnly" description="Activate QSPI interface" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="TASKS_READSTART" access="WriteOnly" description="Start transfer from external flash memory to internal RAM" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="TASKS_WRITESTART" access="WriteOnly" description="Start transfer from internal RAM to external flash memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="TASKS_ERASESTART" access="WriteOnly" description="Start external flash memory erase operation" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_DEACTIVATE" access="WriteOnly" description="Deactivate QSPI interface" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x100" size="4" name="EVENTS_READY" access="Read/Write" description="QSPI peripheral is ready. This event will be generated as a response to any QSPI task." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Enable or disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Enable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Write '1' to Disable interrupt for READY event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable QSPI peripheral and acquire the pins selected in PSELn registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable QSPI">
-        <Enum name="Disabled" start="0" description="Disable QSPI" />
-        <Enum name="Enabled" start="1" description="Enable QSPI" />
-      </BitField>
-    </Register>
-    <Register start="+0x540" size="4" name="XIPOFFSET" access="Read/Write" description="Address offset into the external memory for Execute in Place operation." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="XIPOFFSET" description="Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4." />
-    </Register>
-    <Register start="+0x544" size="4" name="IFCONFIG0" access="Read/Write" description="Interface configuration." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="READOC" description="Configure number of data lines and opcode used for reading.">
-        <Enum name="FASTREAD" start="0" description="Single data line SPI. FAST_READ (opcode 0x0B)." />
-        <Enum name="READ2O" start="1" description="Dual data line SPI. READ2O (opcode 0x3B)." />
-        <Enum name="READ2IO" start="2" description="Dual data line SPI. READ2IO (opcode 0xBB)." />
-        <Enum name="READ4O" start="3" description="Quad data line SPI. READ4O (opcode 0x6B)." />
-        <Enum name="READ4IO" start="4" description="Quad data line SPI. READ4IO (opcode 0xEB)." />
-      </BitField>
-      <BitField start="3" size="3" name="WRITEOC" description="Configure number of data lines and opcode used for writing.">
-        <Enum name="PP" start="0" description="Single data line SPI. PP (opcode 0x02)." />
-        <Enum name="PP2O" start="1" description="Dual data line SPI. PP2O (opcode 0xA2)." />
-        <Enum name="PP4O" start="2" description="Quad data line SPI. PP4O (opcode 0x32)." />
-        <Enum name="PP4IO" start="3" description="Quad data line SPI. PP4IO (opcode 0x38)." />
-      </BitField>
-      <BitField start="6" size="1" name="ADDRMODE" description="Addressing mode.">
-        <Enum name="24BIT" start="0" description="24-bit addressing." />
-        <Enum name="32BIT" start="1" description="32-bit addressing." />
-      </BitField>
-      <BitField start="7" size="1" name="DPMENABLE" description="Enable deep power-down mode (DPM) feature.">
-        <Enum name="Disable" start="0" description="Disable DPM feature." />
-        <Enum name="Enable" start="1" description="Enable DPM feature." />
-      </BitField>
-      <BitField start="12" size="1" name="PPSIZE" description="Page size for commands PP, PP2O, PP4O and PP4IO.">
-        <Enum name="256Bytes" start="0" description="256 bytes." />
-        <Enum name="512Bytes" start="1" description="512 bytes." />
-      </BitField>
-    </Register>
-    <Register start="+0x600" size="4" name="IFCONFIG1" access="Read/Write" description="Interface configuration." reset_value="0x00040480" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SCKDELAY" description="Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)." />
-      <BitField start="24" size="1" name="DPMEN" description="Enter/exit deep power-down mode (DPM) for external flash memory.">
-        <Enum name="Exit" start="0" description="Exit DPM." />
-        <Enum name="Enter" start="1" description="Enter DPM." />
-      </BitField>
-      <BitField start="25" size="1" name="SPIMODE" description="Select SPI mode.">
-        <Enum name="MODE0" start="0" description="Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0)." />
-        <Enum name="MODE3" start="1" description="Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1)." />
-      </BitField>
-      <BitField start="28" size="4" name="SCKFREQ" description="SCK frequency is given as 32 MHz / (SCKFREQ + 1)." />
-    </Register>
-    <Register start="+0x604" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="DPM" description="Deep power-down mode (DPM) status of external flash.">
-        <Enum name="Disabled" start="0" description="External flash is not in DPM." />
-        <Enum name="Enabled" start="1" description="External flash is in DPM." />
-      </BitField>
-      <BitField start="3" size="1" name="READY" description="Ready status.">
-        <Enum name="READY" start="1" description="QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM." />
-        <Enum name="BUSY" start="0" description="QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM." />
-      </BitField>
-      <BitField start="24" size="8" name="SREG" description="Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte." />
-    </Register>
-    <Register start="+0x614" size="4" name="DPMDUR" access="Read/Write" description="Set the duration required to enter/exit deep power-down mode (DPM)." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENTER" description="Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns." />
-      <BitField start="16" size="16" name="EXIT" description="Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns." />
-    </Register>
-    <Register start="+0x624" size="4" name="ADDRCONF" access="Read/Write" description="Extended address configuration." reset_value="0x000000B7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="OPCODE" description="Opcode that enters the 32-bit addressing mode." />
-      <BitField start="8" size="8" name="BYTE0" description="Byte 0 following opcode." />
-      <BitField start="16" size="8" name="BYTE1" description="Byte 1 following byte 0." />
-      <BitField start="24" size="2" name="MODE" description="Extended addressing mode.">
-        <Enum name="NoInstr" start="0" description="Do not send any instruction." />
-        <Enum name="Opcode" start="1" description="Send opcode." />
-        <Enum name="OpByte0" start="2" description="Send opcode, byte0." />
-        <Enum name="All" start="3" description="Send opcode, byte0, byte1." />
-      </BitField>
-      <BitField start="26" size="1" name="WIPWAIT" description="Wait for write complete before sending command.">
-        <Enum name="Disable" start="0" description="No wait." />
-        <Enum name="Enable" start="1" description="Wait." />
-      </BitField>
-      <BitField start="27" size="1" name="WREN" description="Send WREN (write enable opcode 0x06) before instruction.">
-        <Enum name="Disable" start="0" description="Do not send WREN." />
-        <Enum name="Enable" start="1" description="Send WREN." />
-      </BitField>
-    </Register>
-    <Register start="+0x634" size="4" name="CINSTRCONF" access="Read/Write" description="Custom instruction configuration register." reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="OPCODE" description="Opcode of Custom instruction." />
-      <BitField start="8" size="4" name="LENGTH" description="Length of custom instruction in number of bytes.">
-        <Enum name="1B" start="1" description="Send opcode only." />
-        <Enum name="2B" start="2" description="Send opcode, CINSTRDAT0.BYTE0." />
-        <Enum name="3B" start="3" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT0.BYTE1." />
-        <Enum name="4B" start="4" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT0.BYTE2." />
-        <Enum name="5B" start="5" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT0.BYTE3." />
-        <Enum name="6B" start="6" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE4." />
-        <Enum name="7B" start="7" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE5." />
-        <Enum name="8B" start="8" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE6." />
-        <Enum name="9B" start="9" description="Send opcode, CINSTRDAT0.BYTE0 -&amp;gt; CINSTRDAT1.BYTE7." />
-      </BitField>
-      <BitField start="12" size="1" name="LIO2" description="Level of the IO2 pin (if connected) during transmission of custom instruction." />
-      <BitField start="13" size="1" name="LIO3" description="Level of the IO3 pin (if connected) during transmission of custom instruction." />
-      <BitField start="14" size="1" name="WIPWAIT" description="Wait for write complete before sending command.">
-        <Enum name="Disable" start="0" description="No wait." />
-        <Enum name="Enable" start="1" description="Wait." />
-      </BitField>
-      <BitField start="15" size="1" name="WREN" description="Send WREN (write enable opcode 0x06) before instruction.">
-        <Enum name="Disable" start="0" description="Do not send WREN." />
-        <Enum name="Enable" start="1" description="Send WREN." />
-      </BitField>
-      <BitField start="16" size="1" name="LFEN" description="Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.">
-        <Enum name="Disable" start="0" description="Long frame mode disabled" />
-        <Enum name="Enable" start="1" description="Long frame mode enabled" />
-      </BitField>
-      <BitField start="17" size="1" name="LFSTOP" description="Stop (finalize) long frame transaction">
-        <Enum name="Stop" start="1" description="Stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x638" size="4" name="CINSTRDAT0" access="Read/Write" description="Custom instruction data register 0." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BYTE0" description="Data byte 0" />
-      <BitField start="8" size="8" name="BYTE1" description="Data byte 1" />
-      <BitField start="16" size="8" name="BYTE2" description="Data byte 2" />
-      <BitField start="24" size="8" name="BYTE3" description="Data byte 3" />
-    </Register>
-    <Register start="+0x63C" size="4" name="CINSTRDAT1" access="Read/Write" description="Custom instruction data register 1." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BYTE4" description="Data byte 4" />
-      <BitField start="8" size="8" name="BYTE5" description="Data byte 5" />
-      <BitField start="16" size="8" name="BYTE6" description="Data byte 6" />
-      <BitField start="24" size="8" name="BYTE7" description="Data byte 7" />
-    </Register>
-    <Register start="+0x640" size="4" name="IFTIMING" access="Read/Write" description="SPI interface timing." reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="3" name="RXDELAY" description="Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x504+0x000" size="4" name="READ.SRC" access="Read/Write" description="Flash memory source address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRC" description="Word-aligned flash memory source address." />
-    </Register>
-    <Register start="+0x504+0x004" size="4" name="READ.DST" access="Read/Write" description="RAM destination address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DST" description="Word-aligned RAM destination address." />
-    </Register>
-    <Register start="+0x504+0x008" size="4" name="READ.CNT" access="Read/Write" description="Read transfer length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="21" name="CNT" description="Read transfer length in number of bytes. The length must be a multiple of 4 bytes." />
-    </Register>
-    <Register start="+0x510+0x000" size="4" name="WRITE.DST" access="Read/Write" description="Flash destination address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DST" description="Word-aligned flash destination address." />
-    </Register>
-    <Register start="+0x510+0x004" size="4" name="WRITE.SRC" access="Read/Write" description="RAM source address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRC" description="Word-aligned RAM source address." />
-    </Register>
-    <Register start="+0x510+0x008" size="4" name="WRITE.CNT" access="Read/Write" description="Write transfer length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="21" name="CNT" description="Write transfer length in number of bytes. The length must be a multiple of 4 bytes." />
-    </Register>
-    <Register start="+0x51C+0x000" size="4" name="ERASE.PTR" access="Read/Write" description="Start address of flash block to be erased" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Word-aligned start address of block to be erased." />
-    </Register>
-    <Register start="+0x51C+0x004" size="4" name="ERASE.LEN" access="Read/Write" description="Size of block to be erased." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LEN" description="LEN">
-        <Enum name="4KB" start="0" description="Erase 4 kB block (flash command 0x20)" />
-        <Enum name="64KB" start="1" description="Erase 64 kB block (flash command 0xD8)" />
-        <Enum name="All" start="2" description="Erase all (flash command 0xC7)" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for serial clock SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x004" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for chip select signal CSN." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x00C" size="4" name="PSEL.IO0" access="Read/Write" description="Pin select for serial data MOSI/IO0." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x010" size="4" name="PSEL.IO1" access="Read/Write" description="Pin select for serial data MISO/IO1." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x014" size="4" name="PSEL.IO2" access="Read/Write" description="Pin select for serial data IO2." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x524+0x018" size="4" name="PSEL.IO3" access="Read/Write" description="Pin select for serial data IO3." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM3" start="0x4002D000" description="Pulse Width Modulation Unit 3">
-    <Register start="+0x004" size="4" name="TASKS_STOP" access="WriteOnly" description="Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+0" size="4" name="TASKS_SEQSTART[0]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008+4" size="4" name="TASKS_SEQSTART[1]" access="WriteOnly" description="Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x010" size="4" name="TASKS_NEXTSTEP" access="WriteOnly" description="Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running." reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="Response to STOP task, emitted when PWM pulses are no longer generated" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+0" size="4" name="EVENTS_SEQSTARTED[0]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x108+4" size="4" name="EVENTS_SEQSTARTED[1]" access="Read/Write" description="Description collection[0]:  First PWM period started on sequence 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="EVENTS_SEQEND[0]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+4" size="4" name="EVENTS_SEQEND[1]" access="Read/Write" description="Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_PWMPERIODEND" access="Read/Write" description="Emitted at the end of each PWM period" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x11C" size="4" name="EVENTS_LOOPSDONE" access="Read/Write" description="Concatenated sequences have been played the amount of times defined in LOOP.CNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SEQEND0_STOP" description="Shortcut between SEQEND[0] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="1" size="1" name="SEQEND1_STOP" description="Shortcut between SEQEND[1] event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="2" size="1" name="LOOPSDONE_SEQSTART0" description="Shortcut between LOOPSDONE event and SEQSTART[0] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="3" size="1" name="LOOPSDONE_SEQSTART1" description="Shortcut between LOOPSDONE event and SEQSTART[1] task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-      <BitField start="4" size="1" name="LOOPSDONE_STOP" description="Shortcut between LOOPSDONE event and STOP task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x300" size="4" name="INTEN" access="Read/Write" description="Enable or disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Enable or disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Enable or disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Enable or disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Enable or disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Enable or disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Enable or disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Enable or disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Disable" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Enable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Enable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Enable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Enable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Enable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Enable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="SEQSTARTED0" description="Write '1' to Disable interrupt for SEQSTARTED[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="SEQSTARTED1" description="Write '1' to Disable interrupt for SEQSTARTED[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="SEQEND0" description="Write '1' to Disable interrupt for SEQEND[0] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="SEQEND1" description="Write '1' to Disable interrupt for SEQEND[1] event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="PWMPERIODEND" description="Write '1' to Disable interrupt for PWMPERIODEND event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="LOOPSDONE" description="Write '1' to Disable interrupt for LOOPSDONE event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="PWM module enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable PWM module">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="Enabled" start="1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x504" size="4" name="MODE" access="Read/Write" description="Selects operating mode of the wave counter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UPDOWN" description="Selects up or up and down as wave counter mode">
-        <Enum name="Up" start="0" description="Up counter - edge aligned PWM duty-cycle" />
-        <Enum name="UpAndDown" start="1" description="Up and down counter - center aligned PWM duty cycle" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="COUNTERTOP" access="Read/Write" description="Value up to which the pulse generator counter counts" reset_value="0x000003FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="COUNTERTOP" description="Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used." />
-    </Register>
-    <Register start="+0x50C" size="4" name="PRESCALER" access="Read/Write" description="Configuration for PWM_CLK" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER" description="Pre-scaler of PWM_CLK">
-        <Enum name="DIV_1" start="0" description="Divide by   1 (16MHz)" />
-        <Enum name="DIV_2" start="1" description="Divide by   2 ( 8MHz)" />
-        <Enum name="DIV_4" start="2" description="Divide by   4 ( 4MHz)" />
-        <Enum name="DIV_8" start="3" description="Divide by   8 ( 2MHz)" />
-        <Enum name="DIV_16" start="4" description="Divide by  16 ( 1MHz)" />
-        <Enum name="DIV_32" start="5" description="Divide by  32 ( 500kHz)" />
-        <Enum name="DIV_64" start="6" description="Divide by  64 ( 250kHz)" />
-        <Enum name="DIV_128" start="7" description="Divide by 128 ( 125kHz)" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="DECODER" access="Read/Write" description="Configuration of the decoder" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LOAD" description="How a sequence is read from RAM and spread to the compare register">
-        <Enum name="Common" start="0" description="1st half word (16-bit) used in all PWM channels 0..3" />
-        <Enum name="Grouped" start="1" description="1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3" />
-        <Enum name="Individual" start="2" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3" />
-        <Enum name="WaveForm" start="3" description="1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP" />
-      </BitField>
-      <BitField start="8" size="1" name="MODE" description="Selects source for advancing the active sequence">
-        <Enum name="RefreshCount" start="0" description="SEQ[n].REFRESH is used to determine loading internal compare registers" />
-        <Enum name="NextStep" start="1" description="NEXTSTEP task causes a new value to be loaded to internal compare registers" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="LOOP" access="Read/Write" description="Amount of playback of a loop" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CNT" description="Amount of playback of pattern cycles">
-        <Enum name="Disabled" start="0" description="Looping disabled (stop at the end of the sequence)" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x000" size="4" name="SEQ[0].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+0*32+0x004" size="4" name="SEQ[0].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x008" size="4" name="SEQ[0].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+0*32+0x00C" size="4" name="SEQ[0].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x520+1*32+0x000" size="4" name="SEQ[1].PTR" access="Read/Write" description="Description cluster[0]:  Beginning address in Data RAM of this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Beginning address in Data RAM of this sequence" />
-    </Register>
-    <Register start="+0x520+1*32+0x004" size="4" name="SEQ[1].CNT" access="Read/Write" description="Description cluster[0]:  Amount of values (duty cycles) in this sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="CNT" description="Amount of values (duty cycles) in this sequence">
-        <Enum name="Disabled" start="0" description="Sequence is disabled, and shall not be started as it is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x008" size="4" name="SEQ[1].REFRESH" access="Read/Write" description="Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)">
-        <Enum name="Continuous" start="0" description="Update every PWM period" />
-      </BitField>
-    </Register>
-    <Register start="+0x520+1*32+0x00C" size="4" name="SEQ[1].ENDDELAY" access="Read/Write" description="Description cluster[0]:  Time added after the sequence" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CNT" description="Time added after the sequence in PWM periods" />
-    </Register>
-    <Register start="+0x560+0x000+0" size="4" name="PSEL.OUT[0]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+4" size="4" name="PSEL.OUT[1]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+8" size="4" name="PSEL.OUT[2]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000+12" size="4" name="PSEL.OUT[3]" access="Read/Write" description="Description collection[0]:  Output pin select for PWM channel 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIM3" start="0x4002F000" description="Serial Peripheral Interface Master with EasyDMA 3">
-    <Register start="+0x010" size="4" name="TASKS_START" access="WriteOnly" description="Start SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x014" size="4" name="TASKS_STOP" access="WriteOnly" description="Stop SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x01C" size="4" name="TASKS_SUSPEND" access="WriteOnly" description="Suspend SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x020" size="4" name="TASKS_RESUME" access="WriteOnly" description="Resume SPI transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x104" size="4" name="EVENTS_STOPPED" access="Read/Write" description="SPI transaction has stopped" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110" size="4" name="EVENTS_ENDRX" access="Read/Write" description="End of RXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x118" size="4" name="EVENTS_END" access="Read/Write" description="End of RXD buffer and TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x120" size="4" name="EVENTS_ENDTX" access="Read/Write" description="End of TXD buffer reached" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x14C" size="4" name="EVENTS_STARTED" access="Read/Write" description="Transaction started" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x200" size="4" name="SHORTS" access="Read/Write" description="Shortcut register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="17" size="1" name="END_START" description="Shortcut between END event and START task">
-        <Enum name="Disabled" start="0" description="Disable shortcut" />
-        <Enum name="Enabled" start="1" description="Enable shortcut" />
-      </BitField>
-    </Register>
-    <Register start="+0x304" size="4" name="INTENSET" access="Read/Write" description="Enable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Enable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Enable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Enable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Enable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Enable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x308" size="4" name="INTENCLR" access="Read/Write" description="Disable interrupt" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="STOPPED" description="Write '1' to Disable interrupt for STOPPED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="ENDRX" description="Write '1' to Disable interrupt for ENDRX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="END" description="Write '1' to Disable interrupt for END event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ENDTX" description="Write '1' to Disable interrupt for ENDTX event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-      <BitField start="19" size="1" name="STARTED" description="Write '1' to Disable interrupt for STARTED event">
-        <Enum name="Disabled" start="0" description="Read: Disabled" />
-        <Enum name="Enabled" start="1" description="Read: Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x400" size="4" name="STALLSTAT" access="Read/Write" description="Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TX" description="Stall status for EasyDMA RAM reads">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-      <BitField start="1" size="1" name="RX" description="Stall status for EasyDMA RAM writes">
-        <Enum name="NOSTALL" start="0" description="No stall" />
-        <Enum name="STALL" start="1" description="A stall has occurred" />
-      </BitField>
-    </Register>
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Enable SPIM" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ENABLE" description="Enable or disable SPIM">
-        <Enum name="Disabled" start="0" description="Disable SPIM" />
-        <Enum name="Enabled" start="7" description="Enable SPIM" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="FREQUENCY" access="Read/Write" description="SPI frequency. Accuracy depends on the HFCLK source selected." reset_value="0x04000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FREQUENCY" description="SPI master data rate">
-        <Enum name="K125" start="0x02000000" description="125 kbps" />
-        <Enum name="K250" start="0x04000000" description="250 kbps" />
-        <Enum name="K500" start="0x08000000" description="500 kbps" />
-        <Enum name="M1" start="0x10000000" description="1 Mbps" />
-        <Enum name="M2" start="0x20000000" description="2 Mbps" />
-        <Enum name="M4" start="0x40000000" description="4 Mbps" />
-        <Enum name="M8" start="0x80000000" description="8 Mbps" />
-        <Enum name="M16" start="0x0A000000" description="16 Mbps" />
-        <Enum name="M32" start="0x14000000" description="32 Mbps" />
-      </BitField>
-    </Register>
-    <Register start="+0x554" size="4" name="CONFIG" access="Read/Write" description="Configuration register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ORDER" description="Bit order">
-        <Enum name="MsbFirst" start="0" description="Most significant bit shifted out first" />
-        <Enum name="LsbFirst" start="1" description="Least significant bit shifted out first" />
-      </BitField>
-      <BitField start="1" size="1" name="CPHA" description="Serial clock (SCK) phase">
-        <Enum name="Leading" start="0" description="Sample on leading edge of clock, shift serial data on trailing edge" />
-        <Enum name="Trailing" start="1" description="Sample on trailing edge of clock, shift serial data on leading edge" />
-      </BitField>
-      <BitField start="2" size="1" name="CPOL" description="Serial clock (SCK) polarity">
-        <Enum name="ActiveHigh" start="0" description="Active high" />
-        <Enum name="ActiveLow" start="1" description="Active low" />
-      </BitField>
-    </Register>
-    <Register start="+0x5C0" size="4" name="ORC" access="Read/Write" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ORC" description="Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT." />
-    </Register>
-    <Register start="+0x508+0x000" size="4" name="PSEL.SCK" access="Read/Write" description="Pin select for SCK" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x004" size="4" name="PSEL.MOSI" access="Read/Write" description="Pin select for MOSI signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x008" size="4" name="PSEL.MISO" access="Read/Write" description="Pin select for MISO signal" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x508+0x00C" size="4" name="PSEL.CSN" access="Read/Write" description="Pin select for CSN" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PIN" description="Pin number" />
-      <BitField start="5" size="1" name="PORT" description="Port number" />
-      <BitField start="31" size="1" name="CONNECT" description="Connection">
-        <Enum name="Disconnected" start="1" description="Disconnect" />
-        <Enum name="Connected" start="0" description="Connect" />
-      </BitField>
-    </Register>
-    <Register start="+0x534+0x000" size="4" name="RXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x534+0x004" size="4" name="RXD.MAXCNT" access="Read/Write" description="Maximum number of bytes in receive buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in receive buffer" />
-    </Register>
-    <Register start="+0x534+0x008" size="4" name="RXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x534+0x00C" size="4" name="RXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x544+0x000" size="4" name="TXD.PTR" access="Read/Write" description="Data pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PTR" description="Data pointer" />
-    </Register>
-    <Register start="+0x544+0x004" size="4" name="TXD.MAXCNT" access="Read/Write" description="Number of bytes in transmit buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXCNT" description="Maximum number of bytes in transmit buffer" />
-    </Register>
-    <Register start="+0x544+0x008" size="4" name="TXD.AMOUNT" access="ReadOnly" description="Number of bytes transferred in the last transaction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="AMOUNT" description="Number of bytes transferred in the last transaction" />
-    </Register>
-    <Register start="+0x544+0x00C" size="4" name="TXD.LIST" access="Read/Write" description="EasyDMA list type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LIST" description="List type">
-        <Enum name="Disabled" start="0" description="Disable EasyDMA list" />
-        <Enum name="ArrayList" start="1" description="Use array list" />
-      </BitField>
-    </Register>
-    <Register start="+0x560+0x000" size="4" name="IFTIMING.RXDELAY" access="Read/Write" description="Sample delay for input serial data on MISO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RXDELAY" description="Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK." />
-    </Register>
-    <Register start="+0x560+0x004" size="4" name="IFTIMING.CSNDUR" access="Read/Write" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CSNDUR" description="Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="P0" start="0x50000000" description="GPIO Port 1">
-    <Register start="+0x504" size="4" name="OUT" access="Read/Write" description="Write GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="OUTSET" access="Read/Write" description="Set individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="OUTCLR" access="Read/Write" description="Clear individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="IN" access="ReadOnly" description="Read GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="DIR" access="Read/Write" description="Direction of GPIO pins" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="DIRSET" access="Read/Write" description="DIR set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as output pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as output pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as output pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as output pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as output pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as output pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as output pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as output pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as output pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as output pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as output pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as output pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as output pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as output pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as output pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as output pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as output pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as output pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as output pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as output pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as output pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as output pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as output pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as output pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as output pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as output pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as output pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as output pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as output pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as output pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as output pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as output pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="DIRCLR" access="Read/Write" description="DIR clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as input pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as input pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as input pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as input pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as input pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as input pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as input pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as input pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as input pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as input pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as input pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as input pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as input pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as input pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as input pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as input pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as input pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as input pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as input pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as input pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as input pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as input pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as input pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as input pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as input pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as input pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as input pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as input pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as input pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as input pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as input pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as input pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="LATCH" access="Read/Write" description="Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="DETECTMODE" access="Read/Write" description="Select between default DETECT signal behaviour and LDETECT mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETECTMODE" description="Select between default DETECT signal behaviour and LDETECT mode">
-        <Enum name="Default" start="0" description="DETECT directly connected to PIN DETECT signals" />
-        <Enum name="LDETECT" start="1" description="Use the latched LDETECT behaviour" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+0" size="4" name="PIN_CNF[0]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+4" size="4" name="PIN_CNF[1]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+8" size="4" name="PIN_CNF[2]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+12" size="4" name="PIN_CNF[3]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+16" size="4" name="PIN_CNF[4]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+20" size="4" name="PIN_CNF[5]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+24" size="4" name="PIN_CNF[6]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+28" size="4" name="PIN_CNF[7]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+32" size="4" name="PIN_CNF[8]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+36" size="4" name="PIN_CNF[9]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+40" size="4" name="PIN_CNF[10]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+44" size="4" name="PIN_CNF[11]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+48" size="4" name="PIN_CNF[12]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+52" size="4" name="PIN_CNF[13]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+56" size="4" name="PIN_CNF[14]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+60" size="4" name="PIN_CNF[15]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+64" size="4" name="PIN_CNF[16]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+68" size="4" name="PIN_CNF[17]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+72" size="4" name="PIN_CNF[18]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+76" size="4" name="PIN_CNF[19]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+80" size="4" name="PIN_CNF[20]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+84" size="4" name="PIN_CNF[21]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+88" size="4" name="PIN_CNF[22]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+92" size="4" name="PIN_CNF[23]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+96" size="4" name="PIN_CNF[24]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+100" size="4" name="PIN_CNF[25]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+104" size="4" name="PIN_CNF[26]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+108" size="4" name="PIN_CNF[27]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+112" size="4" name="PIN_CNF[28]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+116" size="4" name="PIN_CNF[29]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+120" size="4" name="PIN_CNF[30]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+124" size="4" name="PIN_CNF[31]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="P1" start="0x50000300" description="GPIO Port 2">
-    <Register start="+0x504" size="4" name="OUT" access="Read/Write" description="Write GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin driver is low" />
-        <Enum name="High" start="1" description="Pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x508" size="4" name="OUTSET" access="Read/Write" description="Set individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x50C" size="4" name="OUTCLR" access="Read/Write" description="Clear individual bits in GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Read: pin driver is low" />
-        <Enum name="High" start="1" description="Read: pin driver is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x510" size="4" name="IN" access="ReadOnly" description="Read GPIO port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Low" start="0" description="Pin input is low" />
-        <Enum name="High" start="1" description="Pin input is high" />
-      </BitField>
-    </Register>
-    <Register start="+0x514" size="4" name="DIR" access="Read/Write" description="Direction of GPIO pins" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Pin 0">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Pin 1">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Pin 2">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Pin 3">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Pin 4">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Pin 5">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Pin 6">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Pin 7">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Pin 8">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Pin 9">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Pin 10">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Pin 11">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Pin 12">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Pin 13">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Pin 14">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Pin 15">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Pin 16">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Pin 17">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Pin 18">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Pin 19">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Pin 20">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Pin 21">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Pin 22">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Pin 23">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Pin 24">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Pin 25">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Pin 26">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Pin 27">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Pin 28">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Pin 29">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Pin 30">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Pin 31">
-        <Enum name="Input" start="0" description="Pin set as input" />
-        <Enum name="Output" start="1" description="Pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x518" size="4" name="DIRSET" access="Read/Write" description="DIR set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as output pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as output pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as output pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as output pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as output pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as output pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as output pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as output pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as output pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as output pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as output pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as output pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as output pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as output pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as output pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as output pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as output pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as output pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as output pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as output pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as output pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as output pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as output pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as output pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as output pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as output pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as output pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as output pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as output pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as output pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as output pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as output pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x51C" size="4" name="DIRCLR" access="Read/Write" description="DIR clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Set as input pin 0">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Set as input pin 1">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Set as input pin 2">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Set as input pin 3">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Set as input pin 4">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Set as input pin 5">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Set as input pin 6">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Set as input pin 7">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Set as input pin 8">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Set as input pin 9">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Set as input pin 10">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Set as input pin 11">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Set as input pin 12">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Set as input pin 13">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Set as input pin 14">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Set as input pin 15">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Set as input pin 16">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Set as input pin 17">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Set as input pin 18">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Set as input pin 19">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Set as input pin 20">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Set as input pin 21">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Set as input pin 22">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Set as input pin 23">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Set as input pin 24">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Set as input pin 25">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Set as input pin 26">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Set as input pin 27">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Set as input pin 28">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Set as input pin 29">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Set as input pin 30">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Set as input pin 31">
-        <Enum name="Input" start="0" description="Read: pin set as input" />
-        <Enum name="Output" start="1" description="Read: pin set as output" />
-      </BitField>
-    </Register>
-    <Register start="+0x520" size="4" name="LATCH" access="Read/Write" description="Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PIN0" description="Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="1" size="1" name="PIN1" description="Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="2" size="1" name="PIN2" description="Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="3" size="1" name="PIN3" description="Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="4" size="1" name="PIN4" description="Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="5" size="1" name="PIN5" description="Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="6" size="1" name="PIN6" description="Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="7" size="1" name="PIN7" description="Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="8" size="1" name="PIN8" description="Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="9" size="1" name="PIN9" description="Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="10" size="1" name="PIN10" description="Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="11" size="1" name="PIN11" description="Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="12" size="1" name="PIN12" description="Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="13" size="1" name="PIN13" description="Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="14" size="1" name="PIN14" description="Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="15" size="1" name="PIN15" description="Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="16" size="1" name="PIN16" description="Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="17" size="1" name="PIN17" description="Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="18" size="1" name="PIN18" description="Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="19" size="1" name="PIN19" description="Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="20" size="1" name="PIN20" description="Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="21" size="1" name="PIN21" description="Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="22" size="1" name="PIN22" description="Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="23" size="1" name="PIN23" description="Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="24" size="1" name="PIN24" description="Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="25" size="1" name="PIN25" description="Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="26" size="1" name="PIN26" description="Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="27" size="1" name="PIN27" description="Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="28" size="1" name="PIN28" description="Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="29" size="1" name="PIN29" description="Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="30" size="1" name="PIN30" description="Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-      <BitField start="31" size="1" name="PIN31" description="Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.">
-        <Enum name="NotLatched" start="0" description="Criteria has not been met" />
-        <Enum name="Latched" start="1" description="Criteria has been met" />
-      </BitField>
-    </Register>
-    <Register start="+0x524" size="4" name="DETECTMODE" access="Read/Write" description="Select between default DETECT signal behaviour and LDETECT mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETECTMODE" description="Select between default DETECT signal behaviour and LDETECT mode">
-        <Enum name="Default" start="0" description="DETECT directly connected to PIN DETECT signals" />
-        <Enum name="LDETECT" start="1" description="Use the latched LDETECT behaviour" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+0" size="4" name="PIN_CNF[0]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+4" size="4" name="PIN_CNF[1]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+8" size="4" name="PIN_CNF[2]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+12" size="4" name="PIN_CNF[3]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+16" size="4" name="PIN_CNF[4]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+20" size="4" name="PIN_CNF[5]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+24" size="4" name="PIN_CNF[6]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+28" size="4" name="PIN_CNF[7]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+32" size="4" name="PIN_CNF[8]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+36" size="4" name="PIN_CNF[9]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+40" size="4" name="PIN_CNF[10]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+44" size="4" name="PIN_CNF[11]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+48" size="4" name="PIN_CNF[12]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+52" size="4" name="PIN_CNF[13]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+56" size="4" name="PIN_CNF[14]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+60" size="4" name="PIN_CNF[15]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+64" size="4" name="PIN_CNF[16]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+68" size="4" name="PIN_CNF[17]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+72" size="4" name="PIN_CNF[18]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+76" size="4" name="PIN_CNF[19]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+80" size="4" name="PIN_CNF[20]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+84" size="4" name="PIN_CNF[21]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+88" size="4" name="PIN_CNF[22]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+92" size="4" name="PIN_CNF[23]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+96" size="4" name="PIN_CNF[24]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+100" size="4" name="PIN_CNF[25]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+104" size="4" name="PIN_CNF[26]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+108" size="4" name="PIN_CNF[27]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+112" size="4" name="PIN_CNF[28]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+116" size="4" name="PIN_CNF[29]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+120" size="4" name="PIN_CNF[30]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-    <Register start="+0x700+124" size="4" name="PIN_CNF[31]" access="Read/Write" description="Description collection[0]:  Configuration of GPIO pins" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Pin direction. Same physical register as DIR register">
-        <Enum name="Input" start="0" description="Configure pin as an input pin" />
-        <Enum name="Output" start="1" description="Configure pin as an output pin" />
-      </BitField>
-      <BitField start="1" size="1" name="INPUT" description="Connect or disconnect input buffer">
-        <Enum name="Connect" start="0" description="Connect input buffer" />
-        <Enum name="Disconnect" start="1" description="Disconnect input buffer" />
-      </BitField>
-      <BitField start="2" size="2" name="PULL" description="Pull configuration">
-        <Enum name="Disabled" start="0" description="No pull" />
-        <Enum name="Pulldown" start="1" description="Pull down on pin" />
-        <Enum name="Pullup" start="3" description="Pull up on pin" />
-      </BitField>
-      <BitField start="8" size="3" name="DRIVE" description="Drive configuration">
-        <Enum name="S0S1" start="0" description="Standard '0', standard '1'" />
-        <Enum name="H0S1" start="1" description="High drive '0', standard '1'" />
-        <Enum name="S0H1" start="2" description="Standard '0', high drive '1'" />
-        <Enum name="H0H1" start="3" description="High drive '0', high 'drive '1''" />
-        <Enum name="D0S1" start="4" description="Disconnect '0' standard '1' (normally used for wired-or connections)" />
-        <Enum name="D0H1" start="5" description="Disconnect '0', high drive '1' (normally used for wired-or connections)" />
-        <Enum name="S0D1" start="6" description="Standard '0'. disconnect '1' (normally used for wired-and connections)" />
-        <Enum name="H0D1" start="7" description="High drive '0', disconnect '1' (normally used for wired-and connections)" />
-      </BitField>
-      <BitField start="16" size="2" name="SENSE" description="Pin sensing mechanism">
-        <Enum name="Disabled" start="0" description="Disabled" />
-        <Enum name="High" start="2" description="Sense for high level" />
-        <Enum name="Low" start="3" description="Sense for low level" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CRYPTOCELL" start="0x5002A000" description="ARM CryptoCell register interface">
-    <Register start="+0x500" size="4" name="ENABLE" access="Read/Write" description="Control power and clock for ARM CryptoCell subsystem" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable or disable the CryptoCell subsystem">
-        <Enum name="Disabled" start="0" description="CryptoCell subsystem disabled" />
-        <Enum name="Enabled" start="1" description="CryptoCell subsystem enabled" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="POWER_CLOCK" start="0" size="1" />
-      <BitField name="RADIO" start="1" size="1" />
-      <BitField name="UARTE0_UART0" start="2" size="1" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="3" size="1" />
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="4" size="1" />
-      <BitField name="NFCT" start="5" size="1" />
-      <BitField name="GPIOTE" start="6" size="1" />
-      <BitField name="SAADC" start="7" size="1" />
-      <BitField name="TIMER0" start="8" size="1" />
-      <BitField name="TIMER1" start="9" size="1" />
-      <BitField name="TIMER2" start="10" size="1" />
-      <BitField name="RTC0" start="11" size="1" />
-      <BitField name="TEMP" start="12" size="1" />
-      <BitField name="RNG" start="13" size="1" />
-      <BitField name="ECB" start="14" size="1" />
-      <BitField name="CCM_AAR" start="15" size="1" />
-      <BitField name="WDT" start="16" size="1" />
-      <BitField name="RTC1" start="17" size="1" />
-      <BitField name="QDEC" start="18" size="1" />
-      <BitField name="COMP_LPCOMP" start="19" size="1" />
-      <BitField name="SWI0_EGU0" start="20" size="1" />
-      <BitField name="SWI1_EGU1" start="21" size="1" />
-      <BitField name="SWI2_EGU2" start="22" size="1" />
-      <BitField name="SWI3_EGU3" start="23" size="1" />
-      <BitField name="SWI4_EGU4" start="24" size="1" />
-      <BitField name="SWI5_EGU5" start="25" size="1" />
-      <BitField name="TIMER3" start="26" size="1" />
-      <BitField name="TIMER4" start="27" size="1" />
-      <BitField name="PWM0" start="28" size="1" />
-      <BitField name="PDM" start="29" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="MWU" start="0" size="1" />
-      <BitField name="PWM1" start="1" size="1" />
-      <BitField name="PWM2" start="2" size="1" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="3" size="1" />
-      <BitField name="RTC2" start="4" size="1" />
-      <BitField name="I2S" start="5" size="1" />
-      <BitField name="FPU" start="6" size="1" />
-      <BitField name="USBD" start="7" size="1" />
-      <BitField name="UARTE1" start="8" size="1" />
-      <BitField name="QSPI" start="9" size="1" />
-      <BitField name="CRYPTOCELL" start="10" size="1" />
-      <BitField name="PWM3" start="13" size="1" />
-      <BitField name="SPIM3" start="15" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="POWER_CLOCK" start="5" size="3" />
-      <BitField name="RADIO" start="13" size="3" />
-      <BitField name="UARTE0_UART0" start="21" size="3" />
-      <BitField name="SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1" start="5" size="3" />
-      <BitField name="NFCT" start="13" size="3" />
-      <BitField name="GPIOTE" start="21" size="3" />
-      <BitField name="SAADC" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="TIMER0" start="5" size="3" />
-      <BitField name="TIMER1" start="13" size="3" />
-      <BitField name="TIMER2" start="21" size="3" />
-      <BitField name="RTC0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TEMP" start="5" size="3" />
-      <BitField name="RNG" start="13" size="3" />
-      <BitField name="ECB" start="21" size="3" />
-      <BitField name="CCM_AAR" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="WDT" start="5" size="3" />
-      <BitField name="RTC1" start="13" size="3" />
-      <BitField name="QDEC" start="21" size="3" />
-      <BitField name="COMP_LPCOMP" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SWI0_EGU0" start="5" size="3" />
-      <BitField name="SWI1_EGU1" start="13" size="3" />
-      <BitField name="SWI2_EGU2" start="21" size="3" />
-      <BitField name="SWI3_EGU3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="SWI4_EGU4" start="5" size="3" />
-      <BitField name="SWI5_EGU5" start="13" size="3" />
-      <BitField name="TIMER3" start="21" size="3" />
-      <BitField name="TIMER4" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="PWM0" start="5" size="3" />
-      <BitField name="PDM" start="13" size="3" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="MWU" start="5" size="3" />
-      <BitField name="PWM1" start="13" size="3" />
-      <BitField name="PWM2" start="21" size="3" />
-      <BitField name="SPIM2_SPIS2_SPI2" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="RTC2" start="5" size="3" />
-      <BitField name="I2S" start="13" size="3" />
-      <BitField name="FPU" start="21" size="3" />
-      <BitField name="USBD" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="UARTE1" start="5" size="3" />
-      <BitField name="QSPI" start="13" size="3" />
-      <BitField name="CRYPTOCELL" start="21" size="3" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="PWM3" start="13" size="3" />
-      <BitField name="SPIM3" start="29" size="3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc_freertos/ses/nrf5x/nrf5x.emProject b/examples/device/cdc_msc_freertos/ses/nrf5x/nrf5x.emProject
deleted file mode 100644
index e964d6fb..00000000
--- a/examples/device/cdc_msc_freertos/ses/nrf5x/nrf5x.emProject
+++ /dev/null
@@ -1,151 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="nrf5x" target="8" version="2">
-  <project Name="nrf5x">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="nRF52840_xxAA"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00100000;RAM;0x20000000;0x00040000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="nRF52840_xxAA"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="No"
-      c_preprocessor_definitions="NRF52840_XXAA;__nRF_FAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_NRF5X"
-      c_user_include_directories="./;../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(nrfxDir)/..;$(nrfxDir);$(nrfxDir)/mdk;$(nrfxDir)/hal;$(nrfxDir)/drivers/include;$(nrfxDir)/drivers/src;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM4F"
-      debug_register_definition_file="nrf52840_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="nRF52840_xxAA_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      macros="DeviceFamily=nRF;Target=nRF52840_xxAA;Placement=Flash;rootDir=../../../../..;nrfxDir=../../../../../hw/mcu/nordic/nrfx;freertosDir=../../../../../lib/FreeRTOS"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/nRF_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <folder Name="pca10056">
-          <file file_name="../../../../../hw/bsp/pca10056/board_pca10056.c" />
-        </folder>
-        <file file_name="../../../../../hw/bsp/board.h" />
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nordic">
-          <folder Name="nrfx">
-            <folder Name="drivers">
-              <folder Name="include">
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/include/nrfx_power_clock.h" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/include/nrfx_power.h" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/include/nrfx_qspi.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c" />
-                <file file_name="../../../../../hw/mcu/nordic/nrfx/drivers/src/nrfx_qspi.c" />
-              </folder>
-            </folder>
-            <folder Name="hal">
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/hal/nrf_power.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/hal/nrf_qspi.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/hal/nrf_usbd.h" />
-            </folder>
-            <folder Name="mdk">
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf51_to_nrf52840.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52840_bitfields.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52840.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52840_peripherals.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/nrf52_to_nrf52840.h" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/ses_startup_nrf52840.s" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/ses_startup_nrf_common.s" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/system_nrf52840.c" />
-              <file file_name="../../../../../hw/mcu/nordic/nrfx/mdk/system_nrf52840.h" />
-            </folder>
-          </folder>
-          <file file_name="../../../../../hw/mcu/nordic/nrfx_config.h" />
-          <file file_name="../../../../../hw/mcu/nordic/nrfx_glue.h" />
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="nrf52840_Registers.xml" />
-      <file file_name="nRF52840_xxAA_MemoryMap.xml" />
-      <file file_name="nRF_Target.js" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder Name="lib">
-      <folder Name="FreeRTOS">
-        <folder Name="Source">
-          <folder Name="include">
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/croutine.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/deprecated_definitions.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/event_groups.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/FreeRTOS.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/list.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/message_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_prototypes.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_wrappers.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/portable.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/projdefs.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/queue.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/semphr.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stack_macros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/StackMacros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stream_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/task.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/timers.h" />
-          </folder>
-          <folder Name="portable">
-            <folder Name="GCC">
-              <folder Name="ARM_CM4F">
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c" />
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM4F/portmacro.h" />
-              </folder>
-            </folder>
-            <folder Name="MemMang">
-              <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/MemMang/heap_4.c" />
-            </folder>
-          </folder>
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/list.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/queue.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/tasks.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/timers.c" />
-        </folder>
-      </folder>
-    </folder>
-    <configuration
-      Name="pca10056"
-      c_preprocessor_definitions="BOARD_PCA10056" />
-  </project>
-  <configuration Name="pca10056" />
-</solution>
diff --git a/examples/device/cdc_msc_freertos/ses/nrf5x/thumb_crt0.s b/examples/device/cdc_msc_freertos/ses/nrf5x/thumb_crt0.s
deleted file mode 100644
index 71820cb5..00000000
--- a/examples/device/cdc_msc_freertos/ses/nrf5x/thumb_crt0.s
+++ /dev/null
@@ -1,420 +0,0 @@
-// SEGGER Embedded Studio, runtime support.
-//
-// Copyright (c) 2014-2017 SEGGER Microcontroller GmbH & Co KG
-// Copyright (c) 2001-2017 Rowley Associates Limited.
-//
-// This file may be distributed under the terms of the License Agreement
-// provided with this software.
-//
-// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
-// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .align 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER __heap_lock
-  bx lr
-HELPER __heap_unlock
-  bx lr
-HELPER __printf_lock
-  bx lr
-HELPER __printf_unlock
-  bx lr
-HELPER __scanf_lock
-  bx lr
-HELPER __scanf_unlock
-  bx lr
-HELPER __debug_io_lock
-  bx lr
-HELPER __debug_io_unlock
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __cxa_pure_virtual
-  b .
-HELPER __cxa_guard_acquire
-  ldr r3, [r0]
-#if defined(__thumb__) && !defined(__thumb2__)
-  movs r0, #1
-  tst r3, r0
-#else
-  tst r3, #1
-#endif
-  beq 1f
-  movs r0, #0
-  bx lr
-1:
-  movs r0, #1
-  bx lr
-HELPER __cxa_guard_release
-  movs r3, #1
-  str r3, [r0]
-  bx lr
-HELPER __cxa_guard_abort
-  bx lr
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_MemoryMap.xml b/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_MemoryMap.xml
deleted file mode 100644
index 2143d305..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_MemoryMap.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="ATSAMD21G18A">
-  <MemorySegment name="FLASH" start="0x00002000" size="0x0003E000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20000000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_Registers.xml b/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_Registers.xml
deleted file mode 100644
index 2e0fa061..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_Registers.xml
+++ /dev/null
@@ -1,9587 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="ATSAMD21G18A" description="Atmel ATSAMD21G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G18A.aspx for more)">
-  <RegisterGroup name="AC" start="0x42004400" description="Analog Comparators">
-    <Register start="+0x10+0" size="4" name="AC_COMPCTRL0" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable" />
-      <BitField start="1" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="2" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="LOW" start="0x0" description="Low speed" />
-        <Enum name="HIGH" start="0x1" description="High speed" />
-      </BitField>
-      <BitField start="5" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="2" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-      <BitField start="19" size="1" name="HYST" description="Hysteresis Enable" />
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-    </Register>
-    <Register start="+0x10+4" size="4" name="AC_COMPCTRL1" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable" />
-      <BitField start="1" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="2" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="LOW" start="0x0" description="Low speed" />
-        <Enum name="HIGH" start="0x1" description="High speed" />
-      </BitField>
-      <BitField start="5" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="2" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-      <BitField start="19" size="1" name="HYST" description="Hysteresis Enable" />
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-    </Register>
-    <Register start="+0x00" size="1" name="AC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="LPMUX" description="Low-Power Mux" />
-    </Register>
-    <Register start="+0x01" size="1" name="AC_CTRLB" access="WriteOnly" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START0" description="Comparator 0 Start Comparison" />
-      <BitField start="1" size="1" name="START1" description="Comparator 1 Start Comparison" />
-    </Register>
-    <Register start="+0x02" size="2" name="AC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPEO0" description="Comparator 0 Event Output Enable" />
-      <BitField start="1" size="1" name="COMPEO1" description="Comparator 1 Event Output Enable" />
-      <BitField start="4" size="1" name="WINEO0" description="Window 0 Event Output Enable" />
-      <BitField start="8" size="1" name="COMPEI0" description="Comparator 0 Event Input" />
-      <BitField start="9" size="1" name="COMPEI1" description="Comparator 1 Event Input" />
-    </Register>
-    <Register start="+0x04" size="1" name="AC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="AC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="AC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0" />
-    </Register>
-    <Register start="+0x20+0" size="1" name="AC_SCALER0" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x20+1" size="1" name="AC_SCALER1" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x08" size="1" name="AC_STATUSA" access="ReadOnly" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATE0" description="Comparator 0 Current State" />
-      <BitField start="1" size="1" name="STATE1" description="Comparator 1 Current State" />
-      <BitField start="4" size="2" name="WSTATE0" description="Window 0 Current State">
-        <Enum name="ABOVE" start="0x0" description="Signal is above window" />
-        <Enum name="INSIDE" start="0x1" description="Signal is inside window" />
-        <Enum name="BELOW" start="0x2" description="Signal is below window" />
-      </BitField>
-    </Register>
-    <Register start="+0x09" size="1" name="AC_STATUSB" access="ReadOnly" description="Status B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY0" description="Comparator 0 Ready" />
-      <BitField start="1" size="1" name="READY1" description="Comparator 1 Ready" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-    <Register start="+0x0A" size="1" name="AC_STATUSC" access="ReadOnly" description="Status C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATE0" description="Comparator 0 Current State" />
-      <BitField start="1" size="1" name="STATE1" description="Comparator 1 Current State" />
-      <BitField start="4" size="2" name="WSTATE0" description="Window 0 Current State">
-        <Enum name="ABOVE" start="0x0" description="Signal is above window" />
-        <Enum name="INSIDE" start="0x1" description="Signal is inside window" />
-        <Enum name="BELOW" start="0x2" description="Signal is below window" />
-      </BitField>
-    </Register>
-    <Register start="+0x0C" size="1" name="AC_WINCTRL" access="Read/Write" description="Window Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WEN0" description="Window 0 Mode Enable" />
-      <BitField start="1" size="2" name="WINTSEL0" description="Window 0 Interrupt Selection">
-        <Enum name="ABOVE" start="0x0" description="Interrupt on signal above window" />
-        <Enum name="INSIDE" start="0x1" description="Interrupt on signal inside window" />
-        <Enum name="BELOW" start="0x2" description="Interrupt on signal below window" />
-        <Enum name="OUTSIDE" start="0x3" description="Interrupt on signal outside window" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x42004000" description="Analog Digital Converter">
-    <Register start="+0x02" size="1" name="ADC_AVGCTRL" access="Read/Write" description="Average Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLENUM" description="Number of Samples to be Collected">
-        <Enum name="1" start="0x0" description="1 sample" />
-        <Enum name="2" start="0x1" description="2 samples" />
-        <Enum name="4" start="0x2" description="4 samples" />
-        <Enum name="8" start="0x3" description="8 samples" />
-        <Enum name="16" start="0x4" description="16 samples" />
-        <Enum name="32" start="0x5" description="32 samples" />
-        <Enum name="64" start="0x6" description="64 samples" />
-        <Enum name="128" start="0x7" description="128 samples" />
-        <Enum name="256" start="0x8" description="256 samples" />
-        <Enum name="512" start="0x9" description="512 samples" />
-        <Enum name="1024" start="0xa" description="1024 samples" />
-      </BitField>
-      <BitField start="4" size="3" name="ADJRES" description="Adjusting Result / Division Coefficient" />
-    </Register>
-    <Register start="+0x28" size="2" name="ADC_CALIB" access="Read/Write" description="Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LINEARITY_CAL" description="Linearity Calibration Value" />
-      <BitField start="8" size="3" name="BIAS_CAL" description="Bias Calibration Value" />
-    </Register>
-    <Register start="+0x00" size="1" name="ADC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x04" size="2" name="ADC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIFFMODE" description="Differential Mode" />
-      <BitField start="1" size="1" name="LEFTADJ" description="Left-Adjusted Result" />
-      <BitField start="2" size="1" name="FREERUN" description="Free Running Mode" />
-      <BitField start="3" size="1" name="CORREN" description="Digital Correction Logic Enabled" />
-      <BitField start="4" size="2" name="RESSEL" description="Conversion Result Resolution">
-        <Enum name="12BIT" start="0x0" description="12-bit result" />
-        <Enum name="16BIT" start="0x1" description="For averaging mode output" />
-        <Enum name="10BIT" start="0x2" description="10-bit result" />
-        <Enum name="8BIT" start="0x3" description="8-bit result" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler Configuration">
-        <Enum name="DIV4" start="0x0" description="Peripheral clock divided by 4" />
-        <Enum name="DIV8" start="0x1" description="Peripheral clock divided by 8" />
-        <Enum name="DIV16" start="0x2" description="Peripheral clock divided by 16" />
-        <Enum name="DIV32" start="0x3" description="Peripheral clock divided by 32" />
-        <Enum name="DIV64" start="0x4" description="Peripheral clock divided by 64" />
-        <Enum name="DIV128" start="0x5" description="Peripheral clock divided by 128" />
-        <Enum name="DIV256" start="0x6" description="Peripheral clock divided by 256" />
-        <Enum name="DIV512" start="0x7" description="Peripheral clock divided by 512" />
-      </BitField>
-    </Register>
-    <Register start="+0x2A" size="1" name="ADC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x14" size="1" name="ADC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTEI" description="Start Conversion Event In" />
-      <BitField start="1" size="1" name="SYNCEI" description="Synchronization Event In" />
-      <BitField start="4" size="1" name="RESRDYEO" description="Result Ready Event Out" />
-      <BitField start="5" size="1" name="WINMONEO" description="Window Monitor Event Out" />
-    </Register>
-    <Register start="+0x24" size="2" name="ADC_GAINCORR" access="Read/Write" description="Gain Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="GAINCORR" description="Gain Correction Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="ADC_INPUTCTRL" access="Read/Write" description="Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MUXPOS" description="Positive Mux Input Selection">
-        <Enum name="PIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="PIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="PIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="PIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="PIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="PIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="PIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="PIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="PIN8" start="0x8" description="ADC AIN8 Pin" />
-        <Enum name="PIN9" start="0x9" description="ADC AIN9 Pin" />
-        <Enum name="PIN10" start="0xa" description="ADC AIN10 Pin" />
-        <Enum name="PIN11" start="0xb" description="ADC AIN11 Pin" />
-        <Enum name="PIN12" start="0xc" description="ADC AIN12 Pin" />
-        <Enum name="PIN13" start="0xd" description="ADC AIN13 Pin" />
-        <Enum name="PIN14" start="0xe" description="ADC AIN14 Pin" />
-        <Enum name="PIN15" start="0xf" description="ADC AIN15 Pin" />
-        <Enum name="PIN16" start="0x10" description="ADC AIN16 Pin" />
-        <Enum name="PIN17" start="0x11" description="ADC AIN17 Pin" />
-        <Enum name="PIN18" start="0x12" description="ADC AIN18 Pin" />
-        <Enum name="PIN19" start="0x13" description="ADC AIN19 Pin" />
-        <Enum name="TEMP" start="0x18" description="Temperature Reference" />
-        <Enum name="BANDGAP" start="0x19" description="Bandgap Voltage" />
-        <Enum name="SCALEDCOREVCC" start="0x1a" description="1/4  Scaled Core Supply" />
-        <Enum name="SCALEDIOVCC" start="0x1b" description="1/4  Scaled I/O Supply" />
-        <Enum name="DAC" start="0x1c" description="DAC Output" />
-      </BitField>
-      <BitField start="8" size="5" name="MUXNEG" description="Negative Mux Input Selection">
-        <Enum name="PIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="PIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="PIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="PIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="PIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="PIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="PIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="PIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="GND" start="0x18" description="Internal Ground" />
-        <Enum name="IOGND" start="0x19" description="I/O Ground" />
-      </BitField>
-      <BitField start="16" size="4" name="INPUTSCAN" description="Number of Input Channels Included in Scan" />
-      <BitField start="20" size="4" name="INPUTOFFSET" description="Positive Mux Setting Offset" />
-      <BitField start="24" size="4" name="GAIN" description="Gain Factor Selection">
-        <Enum name="1X" start="0x0" description="1x" />
-        <Enum name="2X" start="0x1" description="2x" />
-        <Enum name="4X" start="0x2" description="4x" />
-        <Enum name="8X" start="0x3" description="8x" />
-        <Enum name="16X" start="0x4" description="16x" />
-        <Enum name="DIV2" start="0xf" description="1/2x" />
-      </BitField>
-    </Register>
-    <Register start="+0x16" size="1" name="ADC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x17" size="1" name="ADC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="ADC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-    </Register>
-    <Register start="+0x26" size="2" name="ADC_OFFSETCORR" access="Read/Write" description="Offset Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="OFFSETCORR" description="Offset Correction Value" />
-    </Register>
-    <Register start="+0x01" size="1" name="ADC_REFCTRL" access="Read/Write" description="Reference Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference Selection">
-        <Enum name="INT1V" start="0x0" description="1.0V voltage reference" />
-        <Enum name="INTVCC0" start="0x1" description="1/1.48 VDDANA" />
-        <Enum name="INTVCC1" start="0x2" description="1/2 VDDANA (only for VDDANA &gt; 2.0V)" />
-        <Enum name="AREFA" start="0x3" description="External reference" />
-        <Enum name="AREFB" start="0x4" description="External reference" />
-      </BitField>
-      <BitField start="7" size="1" name="REFCOMP" description="Reference Buffer Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x1A" size="2" name="ADC_RESULT" access="ReadOnly" description="Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Result Conversion Value" />
-    </Register>
-    <Register start="+0x03" size="1" name="ADC_SAMPCTRL" access="Read/Write" description="Sampling Time Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SAMPLEN" description="Sampling Time Length" />
-    </Register>
-    <Register start="+0x19" size="1" name="ADC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-    <Register start="+0x0C" size="1" name="ADC_SWTRIG" access="Read/Write" description="Software Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSH" description="ADC Conversion Flush" />
-      <BitField start="1" size="1" name="START" description="ADC Start Conversion" />
-    </Register>
-    <Register start="+0x08" size="1" name="ADC_WINCTRL" access="Read/Write" description="Window Monitor Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WINMODE" description="Window Monitor Mode">
-        <Enum name="DISABLE" start="0x0" description="No window mode (default)" />
-        <Enum name="MODE1" start="0x1" description="Mode 1: RESULT &gt; WINLT" />
-        <Enum name="MODE2" start="0x2" description="Mode 2: RESULT &lt; WINUT" />
-        <Enum name="MODE3" start="0x3" description="Mode 3: WINLT &lt; RESULT &lt; WINUT" />
-        <Enum name="MODE4" start="0x4" description="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C" size="2" name="ADC_WINLT" access="Read/Write" description="Window Monitor Lower Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINLT" description="Window Lower Threshold" />
-    </Register>
-    <Register start="+0x20" size="2" name="ADC_WINUT" access="Read/Write" description="Window Monitor Upper Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINUT" description="Window Upper Threshold" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x42004800" description="Digital Analog Converter">
-    <Register start="+0x0" size="1" name="DAC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x1" size="1" name="DAC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOEN" description="External Output Enable" />
-      <BitField start="1" size="1" name="IOEN" description="Internal Output Enable" />
-      <BitField start="2" size="1" name="LEFTADJ" description="Left Adjusted Data" />
-      <BitField start="3" size="1" name="VPD" description="Voltage Pump Disable" />
-      <BitField start="4" size="1" name="BDWP" description="Bypass DATABUF Write Protection" />
-      <BitField start="6" size="2" name="REFSEL" description="Reference Selection">
-        <Enum name="INT1V" start="0x0" description="Internal 1.0V reference" />
-        <Enum name="AVCC" start="0x1" description="AVCC" />
-        <Enum name="VREFP" start="0x2" description="External reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x8" size="2" name="DAC_DATA" access="Read/Write" description="Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Data value to be converted" />
-    </Register>
-    <Register start="+0xC" size="2" name="DAC_DATABUF" access="Read/Write" description="Data Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATABUF" description="Data Buffer" />
-    </Register>
-    <Register start="+0x2" size="1" name="DAC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTEI" description="Start Conversion Event Input" />
-      <BitField start="1" size="1" name="EMPTYEO" description="Data Buffer Empty Event Output" />
-    </Register>
-    <Register start="+0x4" size="1" name="DAC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN" description="Underrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EMPTY" description="Data Buffer Empty Interrupt Enable" />
-      <BitField start="2" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x5" size="1" name="DAC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN" description="Underrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EMPTY" description="Data Buffer Empty Interrupt Enable" />
-      <BitField start="2" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x6" size="1" name="DAC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN" description="Underrun" />
-      <BitField start="1" size="1" name="EMPTY" description="Data Buffer Empty" />
-      <BitField start="2" size="1" name="SYNCRDY" description="Synchronization Ready" />
-    </Register>
-    <Register start="+0x7" size="1" name="DAC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMAC" start="0x41004800" description="Direct Memory Access Controller">
-    <Register start="+0x30" size="4" name="DMAC_ACTIVE" access="ReadOnly" description="Active Channel and Levels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LVLEX0" description="Level 0 Channel Trigger Request Executing" />
-      <BitField start="1" size="1" name="LVLEX1" description="Level 1 Channel Trigger Request Executing" />
-      <BitField start="2" size="1" name="LVLEX2" description="Level 2 Channel Trigger Request Executing" />
-      <BitField start="3" size="1" name="LVLEX3" description="Level 3 Channel Trigger Request Executing" />
-      <BitField start="8" size="5" name="ID" description="Active Channel ID" />
-      <BitField start="15" size="1" name="ABUSY" description="Active Channel Busy" />
-      <BitField start="16" size="16" name="BTCNT" description="Active Channel Block Transfer Count" />
-    </Register>
-    <Register start="+0x34" size="4" name="DMAC_BASEADDR" access="Read/Write" description="Descriptor Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASEADDR" description="Descriptor Memory Base Address" />
-    </Register>
-    <Register start="+0x28" size="4" name="DMAC_BUSYCH" access="ReadOnly" description="Busy Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSYCH0" description="Busy Channel 0" />
-      <BitField start="1" size="1" name="BUSYCH1" description="Busy Channel 1" />
-      <BitField start="2" size="1" name="BUSYCH2" description="Busy Channel 2" />
-      <BitField start="3" size="1" name="BUSYCH3" description="Busy Channel 3" />
-      <BitField start="4" size="1" name="BUSYCH4" description="Busy Channel 4" />
-      <BitField start="5" size="1" name="BUSYCH5" description="Busy Channel 5" />
-      <BitField start="6" size="1" name="BUSYCH6" description="Busy Channel 6" />
-      <BitField start="7" size="1" name="BUSYCH7" description="Busy Channel 7" />
-      <BitField start="8" size="1" name="BUSYCH8" description="Busy Channel 8" />
-      <BitField start="9" size="1" name="BUSYCH9" description="Busy Channel 9" />
-      <BitField start="10" size="1" name="BUSYCH10" description="Busy Channel 10" />
-      <BitField start="11" size="1" name="BUSYCH11" description="Busy Channel 11" />
-    </Register>
-    <Register start="+0x40" size="1" name="DMAC_CHCTRLA" access="Read/Write" description="Channel Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-    </Register>
-    <Register start="+0x44" size="4" name="DMAC_CHCTRLB" access="Read/Write" description="Channel Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-      </BitField>
-      <BitField start="3" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="4" size="1" name="EVOE" description="Channel Event Output Enable" />
-      <BitField start="5" size="2" name="LVL" description="Channel Arbitration Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-      </BitField>
-      <BitField start="8" size="6" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="22" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BEAT" start="0x2" description="One trigger required for each beat transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x3F" size="1" name="DMAC_CHID" access="Read/Write" description="Channel ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Channel ID" />
-    </Register>
-    <Register start="+0x4C" size="1" name="DMAC_CHINTENCLR" access="Read/Write" description="Channel Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D" size="1" name="DMAC_CHINTENSET" access="Read/Write" description="Channel Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4E" size="1" name="DMAC_CHINTFLAG" access="Read/Write" description="Channel Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4F" size="1" name="DMAC_CHSTATUS" access="ReadOnly" description="Channel Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-    </Register>
-    <Register start="+0x08" size="4" name="DMAC_CRCCHKSUM" access="Read/Write" description="CRC Checksum" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCCHKSUM" description="CRC Checksum" />
-    </Register>
-    <Register start="+0x02" size="2" name="DMAC_CRCCTRL" access="Read/Write" description="CRC Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRCBEATSIZE" description="CRC Beat Size">
-        <Enum name="BYTE" start="0x0" description="8-bit bus transfer" />
-        <Enum name="HWORD" start="0x1" description="16-bit bus transfer" />
-        <Enum name="WORD" start="0x2" description="32-bit bus transfer" />
-      </BitField>
-      <BitField start="2" size="2" name="CRCPOLY" description="CRC Polynomial Type">
-        <Enum name="CRC16" start="0x0" description="CRC-16 (CRC-CCITT)" />
-        <Enum name="CRC32" start="0x1" description="CRC32 (IEEE 802.3)" />
-      </BitField>
-      <BitField start="8" size="6" name="CRCSRC" description="CRC Input Source">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="IO" start="0x1" description="I/O interface" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="DMAC_CRCDATAIN" access="Read/Write" description="CRC Data Input" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCDATAIN" description="CRC Data Input" />
-    </Register>
-    <Register start="+0x0C" size="1" name="DMAC_CRCSTATUS" access="Read/Write" description="CRC Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCBUSY" description="CRC Module Busy" />
-      <BitField start="1" size="1" name="CRCZERO" description="CRC Zero" />
-    </Register>
-    <Register start="+0x00" size="2" name="DMAC_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="DMAENABLE" description="DMA Enable" />
-      <BitField start="2" size="1" name="CRCENABLE" description="CRC Enable" />
-      <BitField start="8" size="1" name="LVLEN0" description="Priority Level 0 Enable" />
-      <BitField start="9" size="1" name="LVLEN1" description="Priority Level 1 Enable" />
-      <BitField start="10" size="1" name="LVLEN2" description="Priority Level 2 Enable" />
-      <BitField start="11" size="1" name="LVLEN3" description="Priority Level 3 Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="DMAC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x20" size="2" name="DMAC_INTPEND" access="Read/Write" description="Interrupt Pending" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Channel ID" />
-      <BitField start="8" size="1" name="TERR" description="Transfer Error" />
-      <BitField start="9" size="1" name="TCMPL" description="Transfer Complete" />
-      <BitField start="10" size="1" name="SUSP" description="Channel Suspend" />
-      <BitField start="13" size="1" name="FERR" description="Fetch Error" />
-      <BitField start="14" size="1" name="BUSY" description="Busy" />
-      <BitField start="15" size="1" name="PEND" description="Pending" />
-    </Register>
-    <Register start="+0x24" size="4" name="DMAC_INTSTATUS" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHINT0" description="Channel 0 Pending Interrupt" />
-      <BitField start="1" size="1" name="CHINT1" description="Channel 1 Pending Interrupt" />
-      <BitField start="2" size="1" name="CHINT2" description="Channel 2 Pending Interrupt" />
-      <BitField start="3" size="1" name="CHINT3" description="Channel 3 Pending Interrupt" />
-      <BitField start="4" size="1" name="CHINT4" description="Channel 4 Pending Interrupt" />
-      <BitField start="5" size="1" name="CHINT5" description="Channel 5 Pending Interrupt" />
-      <BitField start="6" size="1" name="CHINT6" description="Channel 6 Pending Interrupt" />
-      <BitField start="7" size="1" name="CHINT7" description="Channel 7 Pending Interrupt" />
-      <BitField start="8" size="1" name="CHINT8" description="Channel 8 Pending Interrupt" />
-      <BitField start="9" size="1" name="CHINT9" description="Channel 9 Pending Interrupt" />
-      <BitField start="10" size="1" name="CHINT10" description="Channel 10 Pending Interrupt" />
-      <BitField start="11" size="1" name="CHINT11" description="Channel 11 Pending Interrupt" />
-    </Register>
-    <Register start="+0x2C" size="4" name="DMAC_PENDCH" access="ReadOnly" description="Pending Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PENDCH0" description="Pending Channel 0" />
-      <BitField start="1" size="1" name="PENDCH1" description="Pending Channel 1" />
-      <BitField start="2" size="1" name="PENDCH2" description="Pending Channel 2" />
-      <BitField start="3" size="1" name="PENDCH3" description="Pending Channel 3" />
-      <BitField start="4" size="1" name="PENDCH4" description="Pending Channel 4" />
-      <BitField start="5" size="1" name="PENDCH5" description="Pending Channel 5" />
-      <BitField start="6" size="1" name="PENDCH6" description="Pending Channel 6" />
-      <BitField start="7" size="1" name="PENDCH7" description="Pending Channel 7" />
-      <BitField start="8" size="1" name="PENDCH8" description="Pending Channel 8" />
-      <BitField start="9" size="1" name="PENDCH9" description="Pending Channel 9" />
-      <BitField start="10" size="1" name="PENDCH10" description="Pending Channel 10" />
-      <BitField start="11" size="1" name="PENDCH11" description="Pending Channel 11" />
-    </Register>
-    <Register start="+0x14" size="4" name="DMAC_PRICTRL0" access="Read/Write" description="Priority Control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="LVLPRI0" description="Level 0 Channel Priority Number" />
-      <BitField start="7" size="1" name="RRLVLEN0" description="Level 0 Round-Robin Scheduling Enable" />
-      <BitField start="8" size="4" name="LVLPRI1" description="Level 1 Channel Priority Number" />
-      <BitField start="15" size="1" name="RRLVLEN1" description="Level 1 Round-Robin Scheduling Enable" />
-      <BitField start="16" size="4" name="LVLPRI2" description="Level 2 Channel Priority Number" />
-      <BitField start="23" size="1" name="RRLVLEN2" description="Level 2 Round-Robin Scheduling Enable" />
-      <BitField start="24" size="4" name="LVLPRI3" description="Level 3 Channel Priority Number" />
-      <BitField start="31" size="1" name="RRLVLEN3" description="Level 3 Round-Robin Scheduling Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="DMAC_QOSCTRL" access="Read/Write" description="QOS Control" reset_value="0x15" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WRBQOS" description="Write-Back Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="2" size="2" name="FQOS" description="Fetch Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="4" size="2" name="DQOS" description="Data Transfer Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-    </Register>
-    <Register start="+0x10" size="4" name="DMAC_SWTRIGCTRL" access="Read/Write" description="Software Trigger Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWTRIG0" description="Channel 0 Software Trigger" />
-      <BitField start="1" size="1" name="SWTRIG1" description="Channel 1 Software Trigger" />
-      <BitField start="2" size="1" name="SWTRIG2" description="Channel 2 Software Trigger" />
-      <BitField start="3" size="1" name="SWTRIG3" description="Channel 3 Software Trigger" />
-      <BitField start="4" size="1" name="SWTRIG4" description="Channel 4 Software Trigger" />
-      <BitField start="5" size="1" name="SWTRIG5" description="Channel 5 Software Trigger" />
-      <BitField start="6" size="1" name="SWTRIG6" description="Channel 6 Software Trigger" />
-      <BitField start="7" size="1" name="SWTRIG7" description="Channel 7 Software Trigger" />
-      <BitField start="8" size="1" name="SWTRIG8" description="Channel 8 Software Trigger" />
-      <BitField start="9" size="1" name="SWTRIG9" description="Channel 9 Software Trigger" />
-      <BitField start="10" size="1" name="SWTRIG10" description="Channel 10 Software Trigger" />
-      <BitField start="11" size="1" name="SWTRIG11" description="Channel 11 Software Trigger" />
-    </Register>
-    <Register start="+0x38" size="4" name="DMAC_WRBADDR" access="Read/Write" description="Write-Back Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WRBADDR" description="Write-Back Memory Base Address" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DSU" start="0x41002000" description="Device Service Unit">
-    <Register start="+0x0004" size="4" name="DSU_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="30" name="ADDR" description="Address" />
-    </Register>
-    <Register start="+0x1FF0" size="4" name="DSU_CID0" access="ReadOnly" description="Component Identification 0" reset_value="0x0000000D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB0" description="Preamble Byte 0" />
-    </Register>
-    <Register start="+0x1FF4" size="4" name="DSU_CID1" access="ReadOnly" description="Component Identification 1" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PREAMBLE" description="Preamble" />
-      <BitField start="4" size="4" name="CCLASS" description="Component Class" />
-    </Register>
-    <Register start="+0x1FF8" size="4" name="DSU_CID2" access="ReadOnly" description="Component Identification 2" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB2" description="Preamble Byte 2" />
-    </Register>
-    <Register start="+0x1FFC" size="4" name="DSU_CID3" access="ReadOnly" description="Component Identification 3" reset_value="0x000000B1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB3" description="Preamble Byte 3" />
-    </Register>
-    <Register start="+0x0000" size="1" name="DSU_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="2" size="1" name="CRC" description="32-bit Cyclic Redundancy Check" />
-      <BitField start="3" size="1" name="MBIST" description="Memory Built-In Self-Test" />
-      <BitField start="4" size="1" name="CE" description="Chip Erase" />
-    </Register>
-    <Register start="+0x000C" size="4" name="DSU_DATA" access="Read/Write" description="Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+0" size="4" name="DSU_DCC0" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+4" size="4" name="DSU_DCC1" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0018" size="4" name="DSU_DID" access="ReadOnly" description="Device Identification" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEVSEL" description="Device Select" />
-      <BitField start="8" size="4" name="REVISION" description="Revision" />
-      <BitField start="12" size="4" name="DIE" description="Die Identification" />
-      <BitField start="16" size="6" name="SERIES" description="Product Series" />
-      <BitField start="23" size="5" name="FAMILY" description="Product Family" />
-      <BitField start="28" size="4" name="PROCESSOR" description="Processor" />
-    </Register>
-    <Register start="+0x1008" size="4" name="DSU_END" access="ReadOnly" description="Coresight ROM Table End" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End Marker" />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="DSU_ENTRY0" access="ReadOnly" description="Coresight ROM Table Entry n" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRES" description="Entry Present" />
-      <BitField start="1" size="1" name="FMT" description="Format" />
-      <BitField start="12" size="20" name="ADDOFF" description="Address Offset" />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="DSU_ENTRY1" access="ReadOnly" description="Coresight ROM Table Entry n" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRES" description="Entry Present" />
-      <BitField start="1" size="1" name="FMT" description="Format" />
-      <BitField start="12" size="20" name="ADDOFF" description="Address Offset" />
-    </Register>
-    <Register start="+0x0008" size="4" name="DSU_LENGTH" access="Read/Write" description="Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="30" name="LENGTH" description="Length" />
-    </Register>
-    <Register start="+0x1FCC" size="4" name="DSU_MEMTYPE" access="ReadOnly" description="Coresight ROM Table Memory Type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SMEMP" description="System Memory Present" />
-    </Register>
-    <Register start="+0x1FE0" size="4" name="DSU_PID0" access="ReadOnly" description="Peripheral Identification 0" reset_value="0x000000D0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PARTNBL" description="Part Number Low" />
-    </Register>
-    <Register start="+0x1FE4" size="4" name="DSU_PID1" access="ReadOnly" description="Peripheral Identification 1" reset_value="0x000000FC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PARTNBH" description="Part Number High" />
-      <BitField start="4" size="4" name="JEPIDCL" description="Low part of the JEP-106 Identity Code" />
-    </Register>
-    <Register start="+0x1FE8" size="4" name="DSU_PID2" access="ReadOnly" description="Peripheral Identification 2" reset_value="0x00000009" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="JEPIDCH" description="JEP-106 Identity Code High" />
-      <BitField start="3" size="1" name="JEPU" description="JEP-106 Identity Code is used" />
-      <BitField start="4" size="4" name="REVISION" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FEC" size="4" name="DSU_PID3" access="ReadOnly" description="Peripheral Identification 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CUSMOD" description="ARM CUSMOD" />
-      <BitField start="4" size="4" name="REVAND" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FD0" size="4" name="DSU_PID4" access="ReadOnly" description="Peripheral Identification 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="JEPCC" description="JEP-106 Continuation Code" />
-      <BitField start="4" size="4" name="FKBC" description="4KB Count" />
-    </Register>
-    <Register start="+0x0001" size="1" name="DSU_STATUSA" access="Read/Write" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Done" />
-      <BitField start="1" size="1" name="CRSTEXT" description="CPU Reset Phase Extension" />
-      <BitField start="2" size="1" name="BERR" description="Bus Error" />
-      <BitField start="3" size="1" name="FAIL" description="Failure" />
-      <BitField start="4" size="1" name="PERR" description="Protection Error" />
-    </Register>
-    <Register start="+0x0002" size="1" name="DSU_STATUSB" access="ReadOnly" description="Status B" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PROT" description="Protected" />
-      <BitField start="1" size="1" name="DBGPRES" description="Debugger Present" />
-      <BitField start="2" size="1" name="DCCD0" description="Debug Communication Channel 0 Dirty" />
-      <BitField start="3" size="1" name="DCCD1" description="Debug Communication Channel 1 Dirty" />
-      <BitField start="4" size="1" name="HPE" description="Hot-Plugging Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EIC" start="0x40001800" description="External Interrupt Controller">
-    <Register start="+0x18+0" size="4" name="EIC_CONFIG0" access="Read/Write" description="Configuration n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense 0 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter 0 Enable" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense 1 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter 1 Enable" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense 2 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter 2 Enable" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense 3 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter 3 Enable" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense 4 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter 4 Enable" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense 5 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter 5 Enable" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense 6 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter 6 Enable" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense 7 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter 7 Enable" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="EIC_CONFIG1" access="Read/Write" description="Configuration n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense 0 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter 0 Enable" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense 1 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter 1 Enable" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense 2 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter 2 Enable" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense 3 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter 3 Enable" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense 4 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter 4 Enable" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense 5 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter 5 Enable" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense 6 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter 6 Enable" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense 7 Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter 7 Enable" />
-    </Register>
-    <Register start="+0x00" size="1" name="EIC_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="EIC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINTEO0" description="External Interrupt 0 Event Output Enable" />
-      <BitField start="1" size="1" name="EXTINTEO1" description="External Interrupt 1 Event Output Enable" />
-      <BitField start="2" size="1" name="EXTINTEO2" description="External Interrupt 2 Event Output Enable" />
-      <BitField start="3" size="1" name="EXTINTEO3" description="External Interrupt 3 Event Output Enable" />
-      <BitField start="4" size="1" name="EXTINTEO4" description="External Interrupt 4 Event Output Enable" />
-      <BitField start="5" size="1" name="EXTINTEO5" description="External Interrupt 5 Event Output Enable" />
-      <BitField start="6" size="1" name="EXTINTEO6" description="External Interrupt 6 Event Output Enable" />
-      <BitField start="7" size="1" name="EXTINTEO7" description="External Interrupt 7 Event Output Enable" />
-      <BitField start="8" size="1" name="EXTINTEO8" description="External Interrupt 8 Event Output Enable" />
-      <BitField start="9" size="1" name="EXTINTEO9" description="External Interrupt 9 Event Output Enable" />
-      <BitField start="10" size="1" name="EXTINTEO10" description="External Interrupt 10 Event Output Enable" />
-      <BitField start="11" size="1" name="EXTINTEO11" description="External Interrupt 11 Event Output Enable" />
-      <BitField start="12" size="1" name="EXTINTEO12" description="External Interrupt 12 Event Output Enable" />
-      <BitField start="13" size="1" name="EXTINTEO13" description="External Interrupt 13 Event Output Enable" />
-      <BitField start="14" size="1" name="EXTINTEO14" description="External Interrupt 14 Event Output Enable" />
-      <BitField start="15" size="1" name="EXTINTEO15" description="External Interrupt 15 Event Output Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="EIC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0 Enable" />
-      <BitField start="1" size="1" name="EXTINT1" description="External Interrupt 1 Enable" />
-      <BitField start="2" size="1" name="EXTINT2" description="External Interrupt 2 Enable" />
-      <BitField start="3" size="1" name="EXTINT3" description="External Interrupt 3 Enable" />
-      <BitField start="4" size="1" name="EXTINT4" description="External Interrupt 4 Enable" />
-      <BitField start="5" size="1" name="EXTINT5" description="External Interrupt 5 Enable" />
-      <BitField start="6" size="1" name="EXTINT6" description="External Interrupt 6 Enable" />
-      <BitField start="7" size="1" name="EXTINT7" description="External Interrupt 7 Enable" />
-      <BitField start="8" size="1" name="EXTINT8" description="External Interrupt 8 Enable" />
-      <BitField start="9" size="1" name="EXTINT9" description="External Interrupt 9 Enable" />
-      <BitField start="10" size="1" name="EXTINT10" description="External Interrupt 10 Enable" />
-      <BitField start="11" size="1" name="EXTINT11" description="External Interrupt 11 Enable" />
-      <BitField start="12" size="1" name="EXTINT12" description="External Interrupt 12 Enable" />
-      <BitField start="13" size="1" name="EXTINT13" description="External Interrupt 13 Enable" />
-      <BitField start="14" size="1" name="EXTINT14" description="External Interrupt 14 Enable" />
-      <BitField start="15" size="1" name="EXTINT15" description="External Interrupt 15 Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="EIC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0 Enable" />
-      <BitField start="1" size="1" name="EXTINT1" description="External Interrupt 1 Enable" />
-      <BitField start="2" size="1" name="EXTINT2" description="External Interrupt 2 Enable" />
-      <BitField start="3" size="1" name="EXTINT3" description="External Interrupt 3 Enable" />
-      <BitField start="4" size="1" name="EXTINT4" description="External Interrupt 4 Enable" />
-      <BitField start="5" size="1" name="EXTINT5" description="External Interrupt 5 Enable" />
-      <BitField start="6" size="1" name="EXTINT6" description="External Interrupt 6 Enable" />
-      <BitField start="7" size="1" name="EXTINT7" description="External Interrupt 7 Enable" />
-      <BitField start="8" size="1" name="EXTINT8" description="External Interrupt 8 Enable" />
-      <BitField start="9" size="1" name="EXTINT9" description="External Interrupt 9 Enable" />
-      <BitField start="10" size="1" name="EXTINT10" description="External Interrupt 10 Enable" />
-      <BitField start="11" size="1" name="EXTINT11" description="External Interrupt 11 Enable" />
-      <BitField start="12" size="1" name="EXTINT12" description="External Interrupt 12 Enable" />
-      <BitField start="13" size="1" name="EXTINT13" description="External Interrupt 13 Enable" />
-      <BitField start="14" size="1" name="EXTINT14" description="External Interrupt 14 Enable" />
-      <BitField start="15" size="1" name="EXTINT15" description="External Interrupt 15 Enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="EIC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0" />
-      <BitField start="1" size="1" name="EXTINT1" description="External Interrupt 1" />
-      <BitField start="2" size="1" name="EXTINT2" description="External Interrupt 2" />
-      <BitField start="3" size="1" name="EXTINT3" description="External Interrupt 3" />
-      <BitField start="4" size="1" name="EXTINT4" description="External Interrupt 4" />
-      <BitField start="5" size="1" name="EXTINT5" description="External Interrupt 5" />
-      <BitField start="6" size="1" name="EXTINT6" description="External Interrupt 6" />
-      <BitField start="7" size="1" name="EXTINT7" description="External Interrupt 7" />
-      <BitField start="8" size="1" name="EXTINT8" description="External Interrupt 8" />
-      <BitField start="9" size="1" name="EXTINT9" description="External Interrupt 9" />
-      <BitField start="10" size="1" name="EXTINT10" description="External Interrupt 10" />
-      <BitField start="11" size="1" name="EXTINT11" description="External Interrupt 11" />
-      <BitField start="12" size="1" name="EXTINT12" description="External Interrupt 12" />
-      <BitField start="13" size="1" name="EXTINT13" description="External Interrupt 13" />
-      <BitField start="14" size="1" name="EXTINT14" description="External Interrupt 14" />
-      <BitField start="15" size="1" name="EXTINT15" description="External Interrupt 15" />
-    </Register>
-    <Register start="+0x02" size="1" name="EIC_NMICTRL" access="Read/Write" description="Non-Maskable Interrupt Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="NMISENSE" description="Non-Maskable Interrupt Sense">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="NMIFILTEN" description="Non-Maskable Interrupt Filter Enable" />
-    </Register>
-    <Register start="+0x03" size="1" name="EIC_NMIFLAG" access="Read/Write" description="Non-Maskable Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMI" description="Non-Maskable Interrupt" />
-    </Register>
-    <Register start="+0x01" size="1" name="EIC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-    <Register start="+0x14" size="4" name="EIC_WAKEUP" access="Read/Write" description="Wake-Up Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUPEN0" description="External Interrupt 0 Wake-up Enable" />
-      <BitField start="1" size="1" name="WAKEUPEN1" description="External Interrupt 1 Wake-up Enable" />
-      <BitField start="2" size="1" name="WAKEUPEN2" description="External Interrupt 2 Wake-up Enable" />
-      <BitField start="3" size="1" name="WAKEUPEN3" description="External Interrupt 3 Wake-up Enable" />
-      <BitField start="4" size="1" name="WAKEUPEN4" description="External Interrupt 4 Wake-up Enable" />
-      <BitField start="5" size="1" name="WAKEUPEN5" description="External Interrupt 5 Wake-up Enable" />
-      <BitField start="6" size="1" name="WAKEUPEN6" description="External Interrupt 6 Wake-up Enable" />
-      <BitField start="7" size="1" name="WAKEUPEN7" description="External Interrupt 7 Wake-up Enable" />
-      <BitField start="8" size="1" name="WAKEUPEN8" description="External Interrupt 8 Wake-up Enable" />
-      <BitField start="9" size="1" name="WAKEUPEN9" description="External Interrupt 9 Wake-up Enable" />
-      <BitField start="10" size="1" name="WAKEUPEN10" description="External Interrupt 10 Wake-up Enable" />
-      <BitField start="11" size="1" name="WAKEUPEN11" description="External Interrupt 11 Wake-up Enable" />
-      <BitField start="12" size="1" name="WAKEUPEN12" description="External Interrupt 12 Wake-up Enable" />
-      <BitField start="13" size="1" name="WAKEUPEN13" description="External Interrupt 13 Wake-up Enable" />
-      <BitField start="14" size="1" name="WAKEUPEN14" description="External Interrupt 14 Wake-up Enable" />
-      <BitField start="15" size="1" name="WAKEUPEN15" description="External Interrupt 15 Wake-up Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVSYS" start="0x42000400" description="Event System Interface">
-    <Register start="+0x04" size="4" name="EVSYS_CHANNEL" access="Read/Write" description="Channel" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CHANNEL" description="Channel Selection" />
-      <BitField start="8" size="1" name="SWEVT" description="Software Event" />
-      <BitField start="16" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="24" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="26" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-    </Register>
-    <Register start="+0x0C" size="4" name="EVSYS_CHSTATUS" access="ReadOnly" description="Channel Status" reset_value="0x000F00FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USRRDY0" description="Channel 0 User Ready" />
-      <BitField start="1" size="1" name="USRRDY1" description="Channel 1 User Ready" />
-      <BitField start="2" size="1" name="USRRDY2" description="Channel 2 User Ready" />
-      <BitField start="3" size="1" name="USRRDY3" description="Channel 3 User Ready" />
-      <BitField start="4" size="1" name="USRRDY4" description="Channel 4 User Ready" />
-      <BitField start="5" size="1" name="USRRDY5" description="Channel 5 User Ready" />
-      <BitField start="6" size="1" name="USRRDY6" description="Channel 6 User Ready" />
-      <BitField start="7" size="1" name="USRRDY7" description="Channel 7 User Ready" />
-      <BitField start="8" size="1" name="CHBUSY0" description="Channel 0 Busy" />
-      <BitField start="9" size="1" name="CHBUSY1" description="Channel 1 Busy" />
-      <BitField start="10" size="1" name="CHBUSY2" description="Channel 2 Busy" />
-      <BitField start="11" size="1" name="CHBUSY3" description="Channel 3 Busy" />
-      <BitField start="12" size="1" name="CHBUSY4" description="Channel 4 Busy" />
-      <BitField start="13" size="1" name="CHBUSY5" description="Channel 5 Busy" />
-      <BitField start="14" size="1" name="CHBUSY6" description="Channel 6 Busy" />
-      <BitField start="15" size="1" name="CHBUSY7" description="Channel 7 Busy" />
-      <BitField start="16" size="1" name="USRRDY8" description="Channel 8 User Ready" />
-      <BitField start="17" size="1" name="USRRDY9" description="Channel 9 User Ready" />
-      <BitField start="18" size="1" name="USRRDY10" description="Channel 10 User Ready" />
-      <BitField start="19" size="1" name="USRRDY11" description="Channel 11 User Ready" />
-      <BitField start="24" size="1" name="CHBUSY8" description="Channel 8 Busy" />
-      <BitField start="25" size="1" name="CHBUSY9" description="Channel 9 Busy" />
-      <BitField start="26" size="1" name="CHBUSY10" description="Channel 10 Busy" />
-      <BitField start="27" size="1" name="CHBUSY11" description="Channel 11 Busy" />
-    </Register>
-    <Register start="+0x00" size="1" name="EVSYS_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="4" size="1" name="GCLKREQ" description="Generic Clock Requests" />
-    </Register>
-    <Register start="+0x10" size="4" name="EVSYS_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR0" description="Channel 0 Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="OVR1" description="Channel 1 Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="OVR2" description="Channel 2 Overrun Interrupt Enable" />
-      <BitField start="3" size="1" name="OVR3" description="Channel 3 Overrun Interrupt Enable" />
-      <BitField start="4" size="1" name="OVR4" description="Channel 4 Overrun Interrupt Enable" />
-      <BitField start="5" size="1" name="OVR5" description="Channel 5 Overrun Interrupt Enable" />
-      <BitField start="6" size="1" name="OVR6" description="Channel 6 Overrun Interrupt Enable" />
-      <BitField start="7" size="1" name="OVR7" description="Channel 7 Overrun Interrupt Enable" />
-      <BitField start="8" size="1" name="EVD0" description="Channel 0 Event Detection Interrupt Enable" />
-      <BitField start="9" size="1" name="EVD1" description="Channel 1 Event Detection Interrupt Enable" />
-      <BitField start="10" size="1" name="EVD2" description="Channel 2 Event Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="EVD3" description="Channel 3 Event Detection Interrupt Enable" />
-      <BitField start="12" size="1" name="EVD4" description="Channel 4 Event Detection Interrupt Enable" />
-      <BitField start="13" size="1" name="EVD5" description="Channel 5 Event Detection Interrupt Enable" />
-      <BitField start="14" size="1" name="EVD6" description="Channel 6 Event Detection Interrupt Enable" />
-      <BitField start="15" size="1" name="EVD7" description="Channel 7 Event Detection Interrupt Enable" />
-      <BitField start="16" size="1" name="OVR8" description="Channel 8 Overrun Interrupt Enable" />
-      <BitField start="17" size="1" name="OVR9" description="Channel 9 Overrun Interrupt Enable" />
-      <BitField start="18" size="1" name="OVR10" description="Channel 10 Overrun Interrupt Enable" />
-      <BitField start="19" size="1" name="OVR11" description="Channel 11 Overrun Interrupt Enable" />
-      <BitField start="24" size="1" name="EVD8" description="Channel 8 Event Detection Interrupt Enable" />
-      <BitField start="25" size="1" name="EVD9" description="Channel 9 Event Detection Interrupt Enable" />
-      <BitField start="26" size="1" name="EVD10" description="Channel 10 Event Detection Interrupt Enable" />
-      <BitField start="27" size="1" name="EVD11" description="Channel 11 Event Detection Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="4" name="EVSYS_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR0" description="Channel 0 Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="OVR1" description="Channel 1 Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="OVR2" description="Channel 2 Overrun Interrupt Enable" />
-      <BitField start="3" size="1" name="OVR3" description="Channel 3 Overrun Interrupt Enable" />
-      <BitField start="4" size="1" name="OVR4" description="Channel 4 Overrun Interrupt Enable" />
-      <BitField start="5" size="1" name="OVR5" description="Channel 5 Overrun Interrupt Enable" />
-      <BitField start="6" size="1" name="OVR6" description="Channel 6 Overrun Interrupt Enable" />
-      <BitField start="7" size="1" name="OVR7" description="Channel 7 Overrun Interrupt Enable" />
-      <BitField start="8" size="1" name="EVD0" description="Channel 0 Event Detection Interrupt Enable" />
-      <BitField start="9" size="1" name="EVD1" description="Channel 1 Event Detection Interrupt Enable" />
-      <BitField start="10" size="1" name="EVD2" description="Channel 2 Event Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="EVD3" description="Channel 3 Event Detection Interrupt Enable" />
-      <BitField start="12" size="1" name="EVD4" description="Channel 4 Event Detection Interrupt Enable" />
-      <BitField start="13" size="1" name="EVD5" description="Channel 5 Event Detection Interrupt Enable" />
-      <BitField start="14" size="1" name="EVD6" description="Channel 6 Event Detection Interrupt Enable" />
-      <BitField start="15" size="1" name="EVD7" description="Channel 7 Event Detection Interrupt Enable" />
-      <BitField start="16" size="1" name="OVR8" description="Channel 8 Overrun Interrupt Enable" />
-      <BitField start="17" size="1" name="OVR9" description="Channel 9 Overrun Interrupt Enable" />
-      <BitField start="18" size="1" name="OVR10" description="Channel 10 Overrun Interrupt Enable" />
-      <BitField start="19" size="1" name="OVR11" description="Channel 11 Overrun Interrupt Enable" />
-      <BitField start="24" size="1" name="EVD8" description="Channel 8 Event Detection Interrupt Enable" />
-      <BitField start="25" size="1" name="EVD9" description="Channel 9 Event Detection Interrupt Enable" />
-      <BitField start="26" size="1" name="EVD10" description="Channel 10 Event Detection Interrupt Enable" />
-      <BitField start="27" size="1" name="EVD11" description="Channel 11 Event Detection Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="4" name="EVSYS_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR0" description="Channel 0 Overrun" />
-      <BitField start="1" size="1" name="OVR1" description="Channel 1 Overrun" />
-      <BitField start="2" size="1" name="OVR2" description="Channel 2 Overrun" />
-      <BitField start="3" size="1" name="OVR3" description="Channel 3 Overrun" />
-      <BitField start="4" size="1" name="OVR4" description="Channel 4 Overrun" />
-      <BitField start="5" size="1" name="OVR5" description="Channel 5 Overrun" />
-      <BitField start="6" size="1" name="OVR6" description="Channel 6 Overrun" />
-      <BitField start="7" size="1" name="OVR7" description="Channel 7 Overrun" />
-      <BitField start="8" size="1" name="EVD0" description="Channel 0 Event Detection" />
-      <BitField start="9" size="1" name="EVD1" description="Channel 1 Event Detection" />
-      <BitField start="10" size="1" name="EVD2" description="Channel 2 Event Detection" />
-      <BitField start="11" size="1" name="EVD3" description="Channel 3 Event Detection" />
-      <BitField start="12" size="1" name="EVD4" description="Channel 4 Event Detection" />
-      <BitField start="13" size="1" name="EVD5" description="Channel 5 Event Detection" />
-      <BitField start="14" size="1" name="EVD6" description="Channel 6 Event Detection" />
-      <BitField start="15" size="1" name="EVD7" description="Channel 7 Event Detection" />
-      <BitField start="16" size="1" name="OVR8" description="Channel 8 Overrun" />
-      <BitField start="17" size="1" name="OVR9" description="Channel 9 Overrun" />
-      <BitField start="18" size="1" name="OVR10" description="Channel 10 Overrun" />
-      <BitField start="19" size="1" name="OVR11" description="Channel 11 Overrun" />
-      <BitField start="24" size="1" name="EVD8" description="Channel 8 Event Detection" />
-      <BitField start="25" size="1" name="EVD9" description="Channel 9 Event Detection" />
-      <BitField start="26" size="1" name="EVD10" description="Channel 10 Event Detection" />
-      <BitField start="27" size="1" name="EVD11" description="Channel 11 Event Detection" />
-    </Register>
-    <Register start="+0x08" size="2" name="EVSYS_USER" access="Read/Write" description="User Multiplexer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="USER" description="User Multiplexer Selection" />
-      <BitField start="8" size="5" name="CHANNEL" description="Channel Event Selection">
-        <Enum name="0" start="0x0" description="No Channel Output Selected" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GCLK" start="0x40000C00" description="Generic Clock Generator">
-    <Register start="+0x2" size="2" name="GCLK_CLKCTRL" access="Read/Write" description="Generic Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ID" description="Generic Clock Selection ID">
-        <Enum name="DFLL48" start="0x0" description="DFLL48" />
-        <Enum name="FDPLL" start="0x1" description="FDPLL" />
-        <Enum name="FDPLL32K" start="0x2" description="FDPLL32K" />
-        <Enum name="WDT" start="0x3" description="WDT" />
-        <Enum name="RTC" start="0x4" description="RTC" />
-        <Enum name="EIC" start="0x5" description="EIC" />
-        <Enum name="USB" start="0x6" description="USB" />
-        <Enum name="EVSYS_0" start="0x7" description="EVSYS_0" />
-        <Enum name="EVSYS_1" start="0x8" description="EVSYS_1" />
-        <Enum name="EVSYS_2" start="0x9" description="EVSYS_2" />
-        <Enum name="EVSYS_3" start="0xa" description="EVSYS_3" />
-        <Enum name="EVSYS_4" start="0xb" description="EVSYS_4" />
-        <Enum name="EVSYS_5" start="0xc" description="EVSYS_5" />
-        <Enum name="EVSYS_6" start="0xd" description="EVSYS_6" />
-        <Enum name="EVSYS_7" start="0xe" description="EVSYS_7" />
-        <Enum name="EVSYS_8" start="0xf" description="EVSYS_8" />
-        <Enum name="EVSYS_9" start="0x10" description="EVSYS_9" />
-        <Enum name="EVSYS_10" start="0x11" description="EVSYS_10" />
-        <Enum name="EVSYS_11" start="0x12" description="EVSYS_11" />
-        <Enum name="SERCOMX_SLOW" start="0x13" description="SERCOMX_SLOW" />
-        <Enum name="SERCOM0_CORE" start="0x14" description="SERCOM0_CORE" />
-        <Enum name="SERCOM1_CORE" start="0x15" description="SERCOM1_CORE" />
-        <Enum name="SERCOM2_CORE" start="0x16" description="SERCOM2_CORE" />
-        <Enum name="SERCOM3_CORE" start="0x17" description="SERCOM3_CORE" />
-        <Enum name="SERCOM4_CORE" start="0x18" description="SERCOM4_CORE" />
-        <Enum name="SERCOM5_CORE" start="0x19" description="SERCOM5_CORE" />
-        <Enum name="TCC0_TCC1" start="0x1a" description="TCC0_TCC1" />
-        <Enum name="TCC2_TC3" start="0x1b" description="TCC2_TC3" />
-        <Enum name="TC4_TC5" start="0x1c" description="TC4_TC5" />
-        <Enum name="TC6_TC7" start="0x1d" description="TC6_TC7" />
-        <Enum name="ADC" start="0x1e" description="ADC" />
-        <Enum name="AC_DIG" start="0x1f" description="AC_DIG" />
-        <Enum name="AC_ANA" start="0x20" description="AC_ANA" />
-        <Enum name="DAC" start="0x21" description="DAC" />
-        <Enum name="PTC" start="0x22" description="PTC" />
-        <Enum name="I2S_0" start="0x23" description="I2S_0" />
-        <Enum name="I2S_1" start="0x24" description="I2S_1" />
-      </BitField>
-      <BitField start="8" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-      </BitField>
-      <BitField start="14" size="1" name="CLKEN" description="Clock Enable" />
-      <BitField start="15" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x0" size="1" name="GCLK_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-    </Register>
-    <Register start="+0x4" size="4" name="GCLK_GENCTRL" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Generic Clock Generator Selection" />
-      <BitField start="8" size="5" name="SRC" description="Source Select">
-        <Enum name="XOSC" start="0x0" description="XOSC oscillator output" />
-        <Enum name="GCLKIN" start="0x1" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x2" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x3" description="OSCULP32K oscillator output" />
-        <Enum name="OSC32K" start="0x4" description="OSC32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="OSC8M" start="0x6" description="OSC8M oscillator output" />
-        <Enum name="DFLL48M" start="0x7" description="DFLL48M output" />
-        <Enum name="FDPLL" start="0x8" description="FDPLL output" />
-      </BitField>
-      <BitField start="16" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="17" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="18" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="19" size="1" name="OE" description="Output Enable" />
-      <BitField start="20" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="21" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x8" size="4" name="GCLK_GENDIV" access="Read/Write" description="Generic Clock Generator Division" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Generic Clock Generator Selection" />
-      <BitField start="8" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x1" size="1" name="GCLK_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="HMATRIX" start="0x41007000" description="HSB Matrix">
-    <Register start="+0x080+0" size="4" name="HMATRIXB_PRAS0" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+8" size="4" name="HMATRIXB_PRAS1" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+16" size="4" name="HMATRIXB_PRAS2" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+24" size="4" name="HMATRIXB_PRAS3" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+32" size="4" name="HMATRIXB_PRAS4" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+40" size="4" name="HMATRIXB_PRAS5" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+48" size="4" name="HMATRIXB_PRAS6" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+56" size="4" name="HMATRIXB_PRAS7" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+64" size="4" name="HMATRIXB_PRAS8" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+72" size="4" name="HMATRIXB_PRAS9" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+80" size="4" name="HMATRIXB_PRAS10" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+88" size="4" name="HMATRIXB_PRAS11" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+96" size="4" name="HMATRIXB_PRAS12" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+104" size="4" name="HMATRIXB_PRAS13" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+112" size="4" name="HMATRIXB_PRAS14" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+120" size="4" name="HMATRIXB_PRAS15" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+0" size="4" name="HMATRIXB_PRBS0" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+8" size="4" name="HMATRIXB_PRBS1" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+16" size="4" name="HMATRIXB_PRBS2" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+24" size="4" name="HMATRIXB_PRBS3" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+32" size="4" name="HMATRIXB_PRBS4" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+40" size="4" name="HMATRIXB_PRBS5" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+48" size="4" name="HMATRIXB_PRBS6" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+56" size="4" name="HMATRIXB_PRBS7" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+64" size="4" name="HMATRIXB_PRBS8" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+72" size="4" name="HMATRIXB_PRBS9" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+80" size="4" name="HMATRIXB_PRBS10" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+88" size="4" name="HMATRIXB_PRBS11" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+96" size="4" name="HMATRIXB_PRBS12" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+104" size="4" name="HMATRIXB_PRBS13" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+112" size="4" name="HMATRIXB_PRBS14" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+120" size="4" name="HMATRIXB_PRBS15" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x110+0" size="4" name="HMATRIXB_SFR0" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+4" size="4" name="HMATRIXB_SFR1" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+8" size="4" name="HMATRIXB_SFR2" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+12" size="4" name="HMATRIXB_SFR3" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+16" size="4" name="HMATRIXB_SFR4" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+20" size="4" name="HMATRIXB_SFR5" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+24" size="4" name="HMATRIXB_SFR6" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+28" size="4" name="HMATRIXB_SFR7" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+32" size="4" name="HMATRIXB_SFR8" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+36" size="4" name="HMATRIXB_SFR9" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+40" size="4" name="HMATRIXB_SFR10" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+44" size="4" name="HMATRIXB_SFR11" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+48" size="4" name="HMATRIXB_SFR12" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+52" size="4" name="HMATRIXB_SFR13" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+56" size="4" name="HMATRIXB_SFR14" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-    <Register start="+0x110+60" size="4" name="HMATRIXB_SFR15" access="Read/Write" description="Special Function" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SFR" description="Special Function Register" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x42005000" description="Inter-IC Sound Interface">
-    <Register start="+0x04+0" size="4" name="I2S_CLKCTRL0" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="11" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="12" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="16" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="18" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="19" size="5" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="5" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-      <BitField start="29" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="30" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="31" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-    </Register>
-    <Register start="+0x04+4" size="4" name="I2S_CLKCTRL1" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="11" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="12" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="16" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="18" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="19" size="5" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="5" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-      <BitField start="29" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="30" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="31" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-    </Register>
-    <Register start="+0x00" size="1" name="I2S_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable" />
-      <BitField start="4" size="1" name="SEREN0" description="Serializer 0 Enable" />
-      <BitField start="5" size="1" name="SEREN1" description="Serializer 1 Enable" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="I2S_DATA0" access="Read/Write" description="Data n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="I2S_DATA1" access="Read/Write" description="Data n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-    <Register start="+0x0C" size="2" name="I2S_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="2" name="I2S_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="2" name="I2S_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="I2S_SERCTRL0" access="Read/Write" description="Serializer n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SERMODE" description="Serializer Mode">
-        <Enum name="RX" start="0x0" description="Receive" />
-        <Enum name="TX" start="0x1" description="Transmit" />
-        <Enum name="PDM2" start="0x2" description="Receive one PDM data on each serial clock edge" />
-      </BitField>
-      <BitField start="2" size="2" name="TXDEFAULT" description="Line Default Line when Slot Disabled">
-        <Enum name="ZERO" start="0x0" description="Output Default Value is 0" />
-        <Enum name="ONE" start="0x1" description="Output Default Value is 1" />
-        <Enum name="HIZ" start="0x3" description="Output Default Value is high impedance" />
-      </BitField>
-      <BitField start="4" size="1" name="TXSAME" description="Transmit Data when Underrun">
-        <Enum name="ZERO" start="0x0" description="Zero data transmitted in case of underrun" />
-        <Enum name="SAME" start="0x1" description="Last data transmitted in case of underrun" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Unit Selection">
-        <Enum name="CLK0" start="0x0" description="Use Clock Unit 0" />
-        <Enum name="CLK1" start="0x1" description="Use Clock Unit 1" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-      <BitField start="26" size="1" name="RXLOOP" description="Loop-back Test Mode" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="I2S_SERCTRL1" access="Read/Write" description="Serializer n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SERMODE" description="Serializer Mode">
-        <Enum name="RX" start="0x0" description="Receive" />
-        <Enum name="TX" start="0x1" description="Transmit" />
-        <Enum name="PDM2" start="0x2" description="Receive one PDM data on each serial clock edge" />
-      </BitField>
-      <BitField start="2" size="2" name="TXDEFAULT" description="Line Default Line when Slot Disabled">
-        <Enum name="ZERO" start="0x0" description="Output Default Value is 0" />
-        <Enum name="ONE" start="0x1" description="Output Default Value is 1" />
-        <Enum name="HIZ" start="0x3" description="Output Default Value is high impedance" />
-      </BitField>
-      <BitField start="4" size="1" name="TXSAME" description="Transmit Data when Underrun">
-        <Enum name="ZERO" start="0x0" description="Zero data transmitted in case of underrun" />
-        <Enum name="SAME" start="0x1" description="Last data transmitted in case of underrun" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Unit Selection">
-        <Enum name="CLK0" start="0x0" description="Use Clock Unit 0" />
-        <Enum name="CLK1" start="0x1" description="Use Clock Unit 1" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-      <BitField start="26" size="1" name="RXLOOP" description="Loop-back Test Mode" />
-    </Register>
-    <Register start="+0x18" size="2" name="I2S_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Status" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Status" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable Synchronization Status" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable Synchronization Status" />
-      <BitField start="4" size="1" name="SEREN0" description="Serializer 0 Enable Synchronization Status" />
-      <BitField start="5" size="1" name="SEREN1" description="Serializer 1 Enable Synchronization Status" />
-      <BitField start="8" size="1" name="DATA0" description="Data 0 Synchronization Status" />
-      <BitField start="9" size="1" name="DATA1" description="Data 1 Synchronization Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MTB" start="0x41006000" description="Cortex-M0+ Micro-Trace Buffer">
-    <Register start="+0xFB8" size="4" name="MTB_AUTHSTATUS" access="ReadOnly" description="MTB Authentication Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x00C" size="4" name="MTB_BASE" access="ReadOnly" description="MTB Base" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFF0" size="4" name="MTB_CID0" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFF4" size="4" name="MTB_CID1" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFF8" size="4" name="MTB_CID2" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFFC" size="4" name="MTB_CID3" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFA4" size="4" name="MTB_CLAIMCLR" access="Read/Write" description="MTB Claim Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFA0" size="4" name="MTB_CLAIMSET" access="Read/Write" description="MTB Claim Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFBC" size="4" name="MTB_DEVARCH" access="ReadOnly" description="MTB Device Architecture" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFC8" size="4" name="MTB_DEVID" access="ReadOnly" description="MTB Device Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFCC" size="4" name="MTB_DEVTYPE" access="ReadOnly" description="MTB Device Type" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x008" size="4" name="MTB_FLOW" access="Read/Write" description="MTB Flow" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUTOSTOP" description="Auto Stop Tracing" />
-      <BitField start="1" size="1" name="AUTOHALT" description="Auto Halt Request" />
-      <BitField start="3" size="29" name="WATERMARK" description="Watermark value" />
-    </Register>
-    <Register start="+0xF00" size="4" name="MTB_ITCTRL" access="Read/Write" description="MTB Integration Mode Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFB0" size="4" name="MTB_LOCKACCESS" access="Read/Write" description="MTB Lock Access" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFB4" size="4" name="MTB_LOCKSTATUS" access="ReadOnly" description="MTB Lock Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x004" size="4" name="MTB_MASTER" access="Read/Write" description="MTB Master" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MASK" description="Maximum Value of the Trace Buffer in SRAM" />
-      <BitField start="5" size="1" name="TSTARTEN" description="Trace Start Input Enable" />
-      <BitField start="6" size="1" name="TSTOPEN" description="Trace Stop Input Enable" />
-      <BitField start="7" size="1" name="SFRWPRIV" description="Special Function Register Write Privilege" />
-      <BitField start="8" size="1" name="RAMPRIV" description="SRAM Privilege" />
-      <BitField start="9" size="1" name="HALTREQ" description="Halt Request" />
-      <BitField start="31" size="1" name="EN" description="Main Trace Enable" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="MTB_PID0" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFE4" size="4" name="MTB_PID1" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFE8" size="4" name="MTB_PID2" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFEC" size="4" name="MTB_PID3" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFD0" size="4" name="MTB_PID4" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFD4" size="4" name="MTB_PID5" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFD8" size="4" name="MTB_PID6" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0xFDC" size="4" name="MTB_PID7" access="ReadOnly" description="CoreSight" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x000" size="4" name="MTB_POSITION" access="Read/Write" description="MTB Position" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="WRAP" description="Pointer Value Wraps" />
-      <BitField start="3" size="29" name="POINTER" description="Trace Packet Location Pointer" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVMCTRL" start="0x41004000" description="Non-Volatile Memory Controller">
-    <Register start="+0x1C" size="4" name="NVMCTRL_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="ADDR" description="NVM Address" />
-    </Register>
-    <Register start="+0x00" size="2" name="NVMCTRL_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CMD" description="Command">
-        <Enum name="ER" start="0x2" description="Erase Row - Erases the row addressed by the ADDR register." />
-        <Enum name="WP" start="0x4" description="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." />
-        <Enum name="EAR" start="0x5" description="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." />
-        <Enum name="WAP" start="0x6" description="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." />
-        <Enum name="SF" start="0xa" description="Security Flow Command" />
-        <Enum name="WL" start="0xf" description="Write lockbits" />
-        <Enum name="LR" start="0x40" description="Lock Region - Locks the region containing the address location in the ADDR register." />
-        <Enum name="UR" start="0x41" description="Unlock Region - Unlocks the region containing the address location in the ADDR register." />
-        <Enum name="SPRM" start="0x42" description="Sets the power reduction mode." />
-        <Enum name="CPRM" start="0x43" description="Clears the power reduction mode." />
-        <Enum name="PBC" start="0x44" description="Page Buffer Clear - Clears the page buffer." />
-        <Enum name="SSB" start="0x45" description="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." />
-        <Enum name="INVALL" start="0x46" description="Invalidates all cache lines." />
-      </BitField>
-      <BitField start="8" size="8" name="CMDEX" description="Command Execution">
-        <Enum name="KEY" start="0xa5" description="Execution Key" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="NVMCTRL_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="4" name="RWS" description="NVM Read Wait States">
-        <Enum name="SINGLE" start="0x0" description="Single Auto Wait State" />
-        <Enum name="HALF" start="0x1" description="Half Auto Wait State" />
-        <Enum name="DUAL" start="0x2" description="Dual Auto Wait State" />
-      </BitField>
-      <BitField start="7" size="1" name="MANW" description="Manual Write" />
-      <BitField start="8" size="2" name="SLEEPPRM" description="Power Reduction Mode during Sleep">
-        <Enum name="WAKEONACCESS" start="0x0" description="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." />
-        <Enum name="WAKEUPINSTANT" start="0x1" description="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." />
-        <Enum name="DISABLED" start="0x3" description="Auto power reduction disabled." />
-      </BitField>
-      <BitField start="16" size="2" name="READMODE" description="NVMCTRL Read Mode">
-        <Enum name="NO_MISS_PENALTY" start="0x0" description="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." />
-        <Enum name="LOW_POWER" start="0x1" description="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." />
-        <Enum name="DETERMINISTIC" start="0x2" description="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." />
-      </BitField>
-      <BitField start="18" size="1" name="CACHEDIS" description="Cache Disable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="NVMCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVM Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="ERROR" description="Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="1" name="NVMCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVM Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="ERROR" description="Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="1" name="NVMCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="NVM Ready" />
-      <BitField start="1" size="1" name="ERROR" description="Error" />
-    </Register>
-    <Register start="+0x20" size="2" name="NVMCTRL_LOCK" access="Read/Write" description="Lock Section" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LOCK" description="Region Lock Bits" />
-    </Register>
-    <Register start="+0x08" size="4" name="NVMCTRL_PARAM" access="Read/Write" description="NVM Parameter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NVMP" description="NVM Pages" />
-      <BitField start="16" size="3" name="PSZ" description="Page Size">
-        <Enum name="8" start="0x0" description="8 bytes" />
-        <Enum name="16" start="0x1" description="16 bytes" />
-        <Enum name="32" start="0x2" description="32 bytes" />
-        <Enum name="64" start="0x3" description="64 bytes" />
-        <Enum name="128" start="0x4" description="128 bytes" />
-        <Enum name="256" start="0x5" description="256 bytes" />
-        <Enum name="512" start="0x6" description="512 bytes" />
-        <Enum name="1024" start="0x7" description="1024 bytes" />
-      </BitField>
-    </Register>
-    <Register start="+0x18" size="2" name="NVMCTRL_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PRM" description="Power Reduction Mode" />
-      <BitField start="1" size="1" name="LOAD" description="NVM Page Buffer Active Loading" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error Status" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error Status" />
-      <BitField start="4" size="1" name="NVME" description="NVM Error" />
-      <BitField start="8" size="1" name="SB" description="Security Bit Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC0" start="0x40000000" description="Peripheral Access Controller 0">
-    <Register start="+0x0" size="4" name="PAC_WPCLR" access="Read/Write" description="Write Protection Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Clear" />
-    </Register>
-    <Register start="+0x4" size="4" name="PAC_WPSET" access="Read/Write" description="Write Protection Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Set" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC1" start="0x41000000" description="Peripheral Access Controller 1">
-    <Register start="+0x0" size="4" name="PAC_WPCLR" access="Read/Write" description="Write Protection Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Clear" />
-    </Register>
-    <Register start="+0x4" size="4" name="PAC_WPSET" access="Read/Write" description="Write Protection Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Set" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC2" start="0x42000000" description="Peripheral Access Controller 2">
-    <Register start="+0x0" size="4" name="PAC_WPCLR" access="Read/Write" description="Write Protection Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Clear" />
-    </Register>
-    <Register start="+0x4" size="4" name="PAC_WPSET" access="Read/Write" description="Write Protection Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="31" name="WP" description="Write Protection Set" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PM" start="0x40000400" description="Power Manager">
-    <Register start="+0x14" size="4" name="PM_AHBMASK" access="Read/Write" description="AHB Mask" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HPB0_" description="HPB0 AHB Clock Mask" />
-      <BitField start="1" size="1" name="HPB1_" description="HPB1 AHB Clock Mask" />
-      <BitField start="2" size="1" name="HPB2_" description="HPB2 AHB Clock Mask" />
-      <BitField start="3" size="1" name="DSU_" description="DSU AHB Clock Mask" />
-      <BitField start="4" size="1" name="NVMCTRL_" description="NVMCTRL AHB Clock Mask" />
-      <BitField start="5" size="1" name="DMAC_" description="DMAC AHB Clock Mask" />
-      <BitField start="6" size="1" name="USB_" description="USB AHB Clock Mask" />
-    </Register>
-    <Register start="+0x18" size="4" name="PM_APBAMASK" access="Read/Write" description="APBA Mask" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC0_" description="PAC0 APB Clock Enable" />
-      <BitField start="1" size="1" name="PM_" description="PM APB Clock Enable" />
-      <BitField start="2" size="1" name="SYSCTRL_" description="SYSCTRL APB Clock Enable" />
-      <BitField start="3" size="1" name="GCLK_" description="GCLK APB Clock Enable" />
-      <BitField start="4" size="1" name="WDT_" description="WDT APB Clock Enable" />
-      <BitField start="5" size="1" name="RTC_" description="RTC APB Clock Enable" />
-      <BitField start="6" size="1" name="EIC_" description="EIC APB Clock Enable" />
-    </Register>
-    <Register start="+0x09" size="1" name="PM_APBASEL" access="Read/Write" description="APBA Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="APBADIV" description="APBA Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C" size="4" name="PM_APBBMASK" access="Read/Write" description="APBB Mask" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC1_" description="PAC1 APB Clock Enable" />
-      <BitField start="1" size="1" name="DSU_" description="DSU APB Clock Enable" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL APB Clock Enable" />
-      <BitField start="3" size="1" name="PORT_" description="PORT APB Clock Enable" />
-      <BitField start="4" size="1" name="DMAC_" description="DMAC APB Clock Enable" />
-      <BitField start="5" size="1" name="USB_" description="USB APB Clock Enable" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX APB Clock Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="PM_APBBSEL" access="Read/Write" description="APBB Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="APBBDIV" description="APBB Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x20" size="4" name="PM_APBCMASK" access="Read/Write" description="APBC Mask" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC2_" description="PAC2 APB Clock Enable" />
-      <BitField start="1" size="1" name="EVSYS_" description="EVSYS APB Clock Enable" />
-      <BitField start="2" size="1" name="SERCOM0_" description="SERCOM0 APB Clock Enable" />
-      <BitField start="3" size="1" name="SERCOM1_" description="SERCOM1 APB Clock Enable" />
-      <BitField start="4" size="1" name="SERCOM2_" description="SERCOM2 APB Clock Enable" />
-      <BitField start="5" size="1" name="SERCOM3_" description="SERCOM3 APB Clock Enable" />
-      <BitField start="6" size="1" name="SERCOM4_" description="SERCOM4 APB Clock Enable" />
-      <BitField start="7" size="1" name="SERCOM5_" description="SERCOM5 APB Clock Enable" />
-      <BitField start="8" size="1" name="TCC0_" description="TCC0 APB Clock Enable" />
-      <BitField start="9" size="1" name="TCC1_" description="TCC1 APB Clock Enable" />
-      <BitField start="10" size="1" name="TCC2_" description="TCC2 APB Clock Enable" />
-      <BitField start="11" size="1" name="TC3_" description="TC3 APB Clock Enable" />
-      <BitField start="12" size="1" name="TC4_" description="TC4 APB Clock Enable" />
-      <BitField start="13" size="1" name="TC5_" description="TC5 APB Clock Enable" />
-      <BitField start="16" size="1" name="ADC_" description="ADC APB Clock Enable" />
-      <BitField start="17" size="1" name="AC_" description="AC APB Clock Enable" />
-      <BitField start="18" size="1" name="DAC_" description="DAC APB Clock Enable" />
-      <BitField start="19" size="1" name="PTC_" description="PTC APB Clock Enable" />
-      <BitField start="20" size="1" name="I2S_" description="I2S APB Clock Enable" />
-    </Register>
-    <Register start="+0x0B" size="1" name="PM_APBCSEL" access="Read/Write" description="APBC Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="APBCDIV" description="APBC Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="1" name="PM_CPUSEL" access="Read/Write" description="CPU Clock Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CPUDIV" description="CPU Prescaler Selection">
-        <Enum name="DIV1" start="0x0" description="Divide by 1" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x00" size="1" name="PM_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x34" size="1" name="PM_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x35" size="1" name="PM_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x36" size="1" name="PM_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready" />
-    </Register>
-    <Register start="+0x38" size="1" name="PM_RCAUSE" access="ReadOnly" description="Reset Cause" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POR" description="Power On Reset" />
-      <BitField start="1" size="1" name="BOD12" description="Brown Out 12 Detector Reset" />
-      <BitField start="2" size="1" name="BOD33" description="Brown Out 33 Detector Reset" />
-      <BitField start="4" size="1" name="EXT" description="External Reset" />
-      <BitField start="5" size="1" name="WDT" description="Watchdog Reset" />
-      <BitField start="6" size="1" name="SYST" description="System Reset Request" />
-    </Register>
-    <Register start="+0x01" size="1" name="PM_SLEEP" access="Read/Write" description="Sleep Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IDLE" description="Idle Mode Configuration">
-        <Enum name="CPU" start="0x0" description="The CPU clock domain is stopped" />
-        <Enum name="AHB" start="0x1" description="The CPU and AHB clock domains are stopped" />
-        <Enum name="APB" start="0x2" description="The CPU, AHB and APB clock domains are stopped" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PORT" start="0x41004400" description="Port Module">
-    <Register start="+0x24+0" size="4" name="PORT_CTRL0" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x24+128" size="4" name="PORT_CTRL1" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x00+0" size="4" name="PORT_DIR0" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x00+128" size="4" name="PORT_DIR1" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x04+0" size="4" name="PORT_DIRCLR0" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x04+128" size="4" name="PORT_DIRCLR1" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x08+0" size="4" name="PORT_DIRSET0" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x08+128" size="4" name="PORT_DIRSET1" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x0C+0" size="4" name="PORT_DIRTGL0" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x0C+128" size="4" name="PORT_DIRTGL1" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="PORT_IN0" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="Port Data Input Value" />
-    </Register>
-    <Register start="+0x20+128" size="4" name="PORT_IN1" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="Port Data Input Value" />
-    </Register>
-    <Register start="+0x10+0" size="4" name="PORT_OUT0" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="Port Data Output Value" />
-    </Register>
-    <Register start="+0x10+128" size="4" name="PORT_OUT1" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="Port Data Output Value" />
-    </Register>
-    <Register start="+0x14+0" size="4" name="PORT_OUTCLR0" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="Port Data Output Value Clear" />
-    </Register>
-    <Register start="+0x14+128" size="4" name="PORT_OUTCLR1" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="Port Data Output Value Clear" />
-    </Register>
-    <Register start="+0x18+0" size="4" name="PORT_OUTSET0" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="Port Data Output Value Set" />
-    </Register>
-    <Register start="+0x18+128" size="4" name="PORT_OUTSET1" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="Port Data Output Value Set" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="PORT_OUTTGL0" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="Port Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x1C+128" size="4" name="PORT_OUTTGL1" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="Port Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x40+0" size="1" name="PORT_PINCFG0_0" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+1" size="1" name="PORT_PINCFG0_1" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+2" size="1" name="PORT_PINCFG0_2" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+3" size="1" name="PORT_PINCFG0_3" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+4" size="1" name="PORT_PINCFG0_4" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+5" size="1" name="PORT_PINCFG0_5" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+6" size="1" name="PORT_PINCFG0_6" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+7" size="1" name="PORT_PINCFG0_7" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+8" size="1" name="PORT_PINCFG0_8" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+9" size="1" name="PORT_PINCFG0_9" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+10" size="1" name="PORT_PINCFG0_10" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+11" size="1" name="PORT_PINCFG0_11" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+12" size="1" name="PORT_PINCFG0_12" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+13" size="1" name="PORT_PINCFG0_13" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+14" size="1" name="PORT_PINCFG0_14" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+15" size="1" name="PORT_PINCFG0_15" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+16" size="1" name="PORT_PINCFG0_16" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+17" size="1" name="PORT_PINCFG0_17" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+18" size="1" name="PORT_PINCFG0_18" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+19" size="1" name="PORT_PINCFG0_19" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+20" size="1" name="PORT_PINCFG0_20" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+21" size="1" name="PORT_PINCFG0_21" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+22" size="1" name="PORT_PINCFG0_22" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+23" size="1" name="PORT_PINCFG0_23" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+24" size="1" name="PORT_PINCFG0_24" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+25" size="1" name="PORT_PINCFG0_25" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+26" size="1" name="PORT_PINCFG0_26" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+27" size="1" name="PORT_PINCFG0_27" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+28" size="1" name="PORT_PINCFG0_28" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+29" size="1" name="PORT_PINCFG0_29" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+30" size="1" name="PORT_PINCFG0_30" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+31" size="1" name="PORT_PINCFG0_31" access="Read/Write" description="Pin Configuration n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+0" size="1" name="PORT_PINCFG1_0" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+1" size="1" name="PORT_PINCFG1_1" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+2" size="1" name="PORT_PINCFG1_2" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+3" size="1" name="PORT_PINCFG1_3" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+4" size="1" name="PORT_PINCFG1_4" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+5" size="1" name="PORT_PINCFG1_5" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+6" size="1" name="PORT_PINCFG1_6" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+7" size="1" name="PORT_PINCFG1_7" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+8" size="1" name="PORT_PINCFG1_8" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+9" size="1" name="PORT_PINCFG1_9" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+10" size="1" name="PORT_PINCFG1_10" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+11" size="1" name="PORT_PINCFG1_11" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+12" size="1" name="PORT_PINCFG1_12" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+13" size="1" name="PORT_PINCFG1_13" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+14" size="1" name="PORT_PINCFG1_14" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+15" size="1" name="PORT_PINCFG1_15" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+16" size="1" name="PORT_PINCFG1_16" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+17" size="1" name="PORT_PINCFG1_17" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+18" size="1" name="PORT_PINCFG1_18" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+19" size="1" name="PORT_PINCFG1_19" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+20" size="1" name="PORT_PINCFG1_20" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+21" size="1" name="PORT_PINCFG1_21" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+22" size="1" name="PORT_PINCFG1_22" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+23" size="1" name="PORT_PINCFG1_23" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+24" size="1" name="PORT_PINCFG1_24" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+25" size="1" name="PORT_PINCFG1_25" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+26" size="1" name="PORT_PINCFG1_26" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+27" size="1" name="PORT_PINCFG1_27" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+28" size="1" name="PORT_PINCFG1_28" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+29" size="1" name="PORT_PINCFG1_29" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+30" size="1" name="PORT_PINCFG1_30" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+31" size="1" name="PORT_PINCFG1_31" access="Read/Write" description="Pin Configuration n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="PORT_PMUX0_0" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+1" size="1" name="PORT_PMUX0_1" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+2" size="1" name="PORT_PMUX0_2" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+3" size="1" name="PORT_PMUX0_3" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+4" size="1" name="PORT_PMUX0_4" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+5" size="1" name="PORT_PMUX0_5" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+6" size="1" name="PORT_PMUX0_6" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+7" size="1" name="PORT_PMUX0_7" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+8" size="1" name="PORT_PMUX0_8" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+9" size="1" name="PORT_PMUX0_9" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+10" size="1" name="PORT_PMUX0_10" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+11" size="1" name="PORT_PMUX0_11" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+12" size="1" name="PORT_PMUX0_12" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+13" size="1" name="PORT_PMUX0_13" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+14" size="1" name="PORT_PMUX0_14" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x30+15" size="1" name="PORT_PMUX0_15" access="Read/Write" description="Peripheral Multiplexing n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+0" size="1" name="PORT_PMUX1_0" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+1" size="1" name="PORT_PMUX1_1" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+2" size="1" name="PORT_PMUX1_2" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+3" size="1" name="PORT_PMUX1_3" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+4" size="1" name="PORT_PMUX1_4" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+5" size="1" name="PORT_PMUX1_5" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+6" size="1" name="PORT_PMUX1_6" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+7" size="1" name="PORT_PMUX1_7" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+8" size="1" name="PORT_PMUX1_8" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+9" size="1" name="PORT_PMUX1_9" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+10" size="1" name="PORT_PMUX1_10" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+11" size="1" name="PORT_PMUX1_11" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+12" size="1" name="PORT_PMUX1_12" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+13" size="1" name="PORT_PMUX1_13" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+14" size="1" name="PORT_PMUX1_14" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0xb0+15" size="1" name="PORT_PMUX1_15" access="Read/Write" description="Peripheral Multiplexing n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing Even">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing Odd">
-        <Enum name="A" start="0x0" description="Peripheral function A selected" />
-        <Enum name="B" start="0x1" description="Peripheral function B selected" />
-        <Enum name="C" start="0x2" description="Peripheral function C selected" />
-        <Enum name="D" start="0x3" description="Peripheral function D selected" />
-        <Enum name="E" start="0x4" description="Peripheral function E selected" />
-        <Enum name="F" start="0x5" description="Peripheral function F selected" />
-        <Enum name="G" start="0x6" description="Peripheral function G selected" />
-        <Enum name="H" start="0x7" description="Peripheral function H selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x28+0" size="4" name="PORT_WRCONFIG0" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-    <Register start="+0x28+128" size="4" name="PORT_WRCONFIG1" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE0)" start="0x40001400" description="Real-Time Counter">
-    <Register start="+0x18+0" size="4" name="RTC_COMP0" access="Read/Write" description="MODE0 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_COUNT" access="Read/Write" description="MODE0 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="RTC_CTRL" access="Read/Write" description="MODE0 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x0B" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x04" size="2" name="RTC_EVCTRL" access="Read/Write" description="MODE0 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x06" size="1" name="RTC_INTENCLR" access="Read/Write" description="MODE0 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="RTC_INTENSET" access="Read/Write" description="MODE0 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="RTC_INTFLAG" access="Read/Write" description="MODE0 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="7" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_READREQ" access="Read/Write" description="Read Request" reset_value="0x0010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0A" size="1" name="RTC_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE1)" start="0x40001400" description="Real-Time Counter">
-    <Register start="+0x18+0" size="2" name="RTC_COMP0" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="RTC_COMP1" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="RTC_COUNT" access="Read/Write" description="MODE1 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="RTC_CTRL" access="Read/Write" description="MODE1 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x0B" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x04" size="2" name="RTC_EVCTRL" access="Read/Write" description="MODE1 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="9" size="1" name="CMPEO1" description="Compare 1 Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x06" size="1" name="RTC_INTENCLR" access="Read/Write" description="MODE1 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="RTC_INTENSET" access="Read/Write" description="MODE1 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="RTC_INTFLAG" access="Read/Write" description="MODE1 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="1" size="1" name="CMP1" description="Compare 1" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="7" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x14" size="2" name="RTC_PER" access="Read/Write" description="MODE1 Counter Period" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PER" description="Counter Period" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_READREQ" access="Read/Write" description="Read Request" reset_value="0x0010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0A" size="1" name="RTC_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE2)" start="0x40001400" description="Real-Time Counter">
-    <Register start="+0x18+0" size="4" name="RTC_ALARM0" access="Read/Write" description="MODE2 Alarm n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour" />
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_CLOCK" access="Read/Write" description="MODE2 Clock Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="PM" start="0x10" description="Afternoon Hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x00" size="2" name="RTC_CTRL" access="Read/Write" description="MODE2 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="6" size="1" name="CLKREP" description="Clock Representation" />
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x0B" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x04" size="2" name="RTC_EVCTRL" access="Read/Write" description="MODE2 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="ALARMEO0" description="Alarm 0 Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x06" size="1" name="RTC_INTENCLR" access="Read/Write" description="MODE2 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="RTC_INTENSET" access="Read/Write" description="MODE2 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="7" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="RTC_INTFLAG" access="Read/Write" description="MODE2 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALARM0" description="Alarm 0" />
-      <BitField start="6" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="7" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="RTC_MASK0" access="Read/Write" description="MODE2 Alarm n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SEL" description="Alarm Mask Selection">
-        <Enum name="OFF" start="0x0" description="Alarm Disabled" />
-        <Enum name="SS" start="0x1" description="Match seconds only" />
-        <Enum name="MMSS" start="0x2" description="Match seconds and minutes only" />
-        <Enum name="HHMMSS" start="0x3" description="Match seconds, minutes, and hours only" />
-        <Enum name="DDHHMMSS" start="0x4" description="Match seconds, minutes, hours, and days only" />
-        <Enum name="MMDDHHMMSS" start="0x5" description="Match seconds, minutes, hours, days, and months only" />
-        <Enum name="YYMMDDHHMMSS" start="0x6" description="Match seconds, minutes, hours, days, months, and years" />
-      </BitField>
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_READREQ" access="Read/Write" description="Read Request" reset_value="0x0010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0A" size="1" name="RTC_STATUS" access="Read/Write" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CM)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CS)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (SPI)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (USART)" start="0x42000800" description="Serial Communication Interface 0">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CM)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CS)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (SPI)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (USART)" start="0x42000C00" description="Serial Communication Interface 1">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CM)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CS)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (SPI)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (USART)" start="0x42001000" description="Serial Communication Interface 2">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CM)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CS)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (SPI)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (USART)" start="0x42001400" description="Serial Communication Interface 3">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CM)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CS)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (SPI)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (USART)" start="0x42001800" description="Serial Communication Interface 4">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CM)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CS)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x28" size="1" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (SPI)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (USART)" start="0x42001C00" description="Serial Communication Interface 5">
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode">
-        <Enum name="USART_EXT_CLK" start="0x0" description="USART mode with external clock" />
-        <Enum name="USART_INT_CLK" start="0x1" description="USART mode with internal clock" />
-        <Enum name="SPI_SLAVE" start="0x2" description="SPI mode with external clock" />
-        <Enum name="SPI_MASTER" start="0x3" description="SPI mode with internal clock" />
-        <Enum name="I2C_SLAVE" start="0x4" description="I2C mode with external clock" />
-        <Enum name="I2C_MASTER" start="0x5" description="I2C mode with internal clock" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x28" size="2" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Syncbusy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCTRL" start="0x40000800" description="System Control">
-    <Register start="+0x34" size="4" name="SYSCTRL_BOD33" access="Read/Write" description="3.3V Brown-Out Detector (BOD33) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="HYST" description="Hysteresis" />
-      <BitField start="3" size="2" name="ACTION" description="BOD33 Action">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RESET" start="0x1" description="The BOD33 generates a reset" />
-        <Enum name="INTERRUPT" start="0x2" description="The BOD33 generates an interrupt" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="1" name="MODE" description="Operation Mode" />
-      <BitField start="9" size="1" name="CEN" description="Clock Enable" />
-      <BitField start="12" size="4" name="PSEL" description="Prescaler Select">
-        <Enum name="DIV2" start="0x0" description="Divide clock by 2" />
-        <Enum name="DIV4" start="0x1" description="Divide clock by 4" />
-        <Enum name="DIV8" start="0x2" description="Divide clock by 8" />
-        <Enum name="DIV16" start="0x3" description="Divide clock by 16" />
-        <Enum name="DIV32" start="0x4" description="Divide clock by 32" />
-        <Enum name="DIV64" start="0x5" description="Divide clock by 64" />
-        <Enum name="DIV128" start="0x6" description="Divide clock by 128" />
-        <Enum name="DIV256" start="0x7" description="Divide clock by 256" />
-        <Enum name="DIV512" start="0x8" description="Divide clock by 512" />
-        <Enum name="DIV1K" start="0x9" description="Divide clock by 1024" />
-        <Enum name="DIV2K" start="0xa" description="Divide clock by 2048" />
-        <Enum name="DIV4K" start="0xb" description="Divide clock by 4096" />
-        <Enum name="DIV8K" start="0xc" description="Divide clock by 8192" />
-        <Enum name="DIV16K" start="0xd" description="Divide clock by 16384" />
-        <Enum name="DIV32K" start="0xe" description="Divide clock by 32768" />
-        <Enum name="DIV64K" start="0xf" description="Divide clock by 65536" />
-      </BitField>
-      <BitField start="16" size="6" name="LEVEL" description="BOD33 Threshold Level" />
-    </Register>
-    <Register start="+0x24" size="2" name="SYSCTRL_DFLLCTRL" access="Read/Write" description="DFLL48M Control" reset_value="0x0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DFLL Enable" />
-      <BitField start="2" size="1" name="MODE" description="Operating Mode Selection" />
-      <BitField start="3" size="1" name="STABLE" description="Stable DFLL Frequency" />
-      <BitField start="4" size="1" name="LLAW" description="Lose Lock After Wake" />
-      <BitField start="5" size="1" name="USBCRM" description="USB Clock Recovery Mode" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="1" name="CCDIS" description="Chill Cycle Disable" />
-      <BitField start="9" size="1" name="QLDIS" description="Quick Lock Disable" />
-      <BitField start="10" size="1" name="BPLCKC" description="Bypass Coarse Lock" />
-      <BitField start="11" size="1" name="WAITLOCK" description="Wait Lock" />
-    </Register>
-    <Register start="+0x2C" size="4" name="SYSCTRL_DFLLMUL" access="Read/Write" description="DFLL48M Multiplier" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MUL" description="DFLL Multiply Factor" />
-      <BitField start="16" size="10" name="FSTEP" description="Fine Maximum Step" />
-      <BitField start="26" size="6" name="CSTEP" description="Coarse Maximum Step" />
-    </Register>
-    <Register start="+0x30" size="1" name="SYSCTRL_DFLLSYNC" access="Read/Write" description="DFLL48M Synchronization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="READREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x28" size="4" name="SYSCTRL_DFLLVAL" access="Read/Write" description="DFLL48M Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="FINE" description="Fine Value" />
-      <BitField start="10" size="6" name="COARSE" description="Coarse Value" />
-      <BitField start="16" size="16" name="DIFF" description="Multiplication Ratio Difference" />
-    </Register>
-    <Register start="+0x44" size="1" name="SYSCTRL_DPLLCTRLA" access="Read/Write" description="DPLL Control A" reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Clock Activation" />
-    </Register>
-    <Register start="+0x4C" size="4" name="SYSCTRL_DPLLCTRLB" access="Read/Write" description="DPLL Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="FILTER" description="Proportional Integral Filter Selection">
-        <Enum name="DEFAULT" start="0x0" description="Default filter mode" />
-        <Enum name="LBFILT" start="0x1" description="Low bandwidth filter" />
-        <Enum name="HBFILT" start="0x2" description="High bandwidth filter" />
-        <Enum name="HDFILT" start="0x3" description="High damping filter" />
-      </BitField>
-      <BitField start="2" size="1" name="LPEN" description="Low-Power Enable" />
-      <BitField start="3" size="1" name="WUF" description="Wake Up Fast" />
-      <BitField start="4" size="2" name="REFCLK" description="Reference Clock Selection">
-        <Enum name="REF0" start="0x0" description="CLK_DPLL_REF0 clock reference" />
-        <Enum name="REF1" start="0x1" description="CLK_DPLL_REF1 clock reference" />
-        <Enum name="GCLK" start="0x2" description="GCLK_DPLL clock reference" />
-      </BitField>
-      <BitField start="8" size="3" name="LTIME" description="Lock Time">
-        <Enum name="DEFAULT" start="0x0" description="No time-out" />
-        <Enum name="8MS" start="0x4" description="Time-out if no lock within 8 ms" />
-        <Enum name="9MS" start="0x5" description="Time-out if no lock within 9 ms" />
-        <Enum name="10MS" start="0x6" description="Time-out if no lock within 10 ms" />
-        <Enum name="11MS" start="0x7" description="Time-out if no lock within 11 ms" />
-      </BitField>
-      <BitField start="12" size="1" name="LBYPASS" description="Lock Bypass" />
-      <BitField start="16" size="11" name="DIV" description="Clock Divider" />
-    </Register>
-    <Register start="+0x48" size="4" name="SYSCTRL_DPLLRATIO" access="Read/Write" description="DPLL Ratio Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="LDR" description="Loop Divider Ratio" />
-      <BitField start="16" size="4" name="LDRFRAC" description="Loop Divider Ratio Fractional Part" />
-    </Register>
-    <Register start="+0x50" size="1" name="SYSCTRL_DPLLSTATUS" access="ReadOnly" description="DPLL Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="DPLL Lock Status" />
-      <BitField start="1" size="1" name="CLKRDY" description="Output Clock Ready" />
-      <BitField start="2" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="3" size="1" name="DIV" description="Divider Enable" />
-    </Register>
-    <Register start="+0x00" size="4" name="SYSCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready Interrupt Enable" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready Interrupt Enable" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready Interrupt Enable" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout Interrupt Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SYSCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready Interrupt Enable" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready Interrupt Enable" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection Interrupt Enable" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready Interrupt Enable" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SYSCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout" />
-    </Register>
-    <Register start="+0x18" size="4" name="SYSCTRL_OSC32K" access="Read/Write" description="32kHz Internal Oscillator (OSC32K) Control" reset_value="0x003F0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="EN32K" description="32kHz Output Enable" />
-      <BitField start="3" size="1" name="EN1K" description="1kHz Output Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="STARTUP" description="Oscillator Start-Up Time" />
-      <BitField start="12" size="1" name="WRTLOCK" description="Write Lock" />
-      <BitField start="16" size="7" name="CALIB" description="Oscillator Calibration" />
-    </Register>
-    <Register start="+0x20" size="4" name="SYSCTRL_OSC8M" access="Read/Write" description="8MHz Internal Oscillator (OSC8M) Control" reset_value="0x87070382" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="2" name="PRESC" description="Oscillator Prescaler">
-        <Enum name="0" start="0x0" description="1" />
-        <Enum name="1" start="0x1" description="2" />
-        <Enum name="2" start="0x2" description="4" />
-        <Enum name="3" start="0x3" description="8" />
-      </BitField>
-      <BitField start="16" size="12" name="CALIB" description="Oscillator Calibration" />
-      <BitField start="30" size="2" name="FRANGE" description="Oscillator Frequency Range">
-        <Enum name="0" start="0x0" description="4 to 6MHz" />
-        <Enum name="1" start="0x1" description="6 to 8MHz" />
-        <Enum name="2" start="0x2" description="8 to 11MHz" />
-        <Enum name="3" start="0x3" description="11 to 15MHz" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C" size="1" name="SYSCTRL_OSCULP32K" access="Read/Write" description="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control" reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="CALIB" description="Oscillator Calibration" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SYSCTRL_PCLKSR" access="ReadOnly" description="Power and Clocks Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY" description="XOSC Ready" />
-      <BitField start="1" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="OSC32KRDY" description="OSC32K Ready" />
-      <BitField start="3" size="1" name="OSC8MRDY" description="OSC8M Ready" />
-      <BitField start="4" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="5" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="6" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="7" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="8" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="9" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="10" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="11" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="15" size="1" name="DPLLLCKR" description="DPLL Lock Rise" />
-      <BitField start="16" size="1" name="DPLLLCKF" description="DPLL Lock Fall" />
-      <BitField start="17" size="1" name="DPLLLTO" description="DPLL Lock Timeout" />
-    </Register>
-    <Register start="+0x40" size="4" name="SYSCTRL_VREF" access="Read/Write" description="Voltage References System (VREF) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="TSEN" description="Temperature Sensor Enable" />
-      <BitField start="2" size="1" name="BGOUTEN" description="Bandgap Output Enable" />
-      <BitField start="16" size="11" name="CALIB" description="Bandgap Voltage Generator Calibration" />
-    </Register>
-    <Register start="+0x3C" size="2" name="SYSCTRL_VREG" access="Read/Write" description="Voltage Regulator System (VREG) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="13" size="1" name="FORCELDO" description="Force LDO Voltage Regulator" />
-    </Register>
-    <Register start="+0x10" size="2" name="SYSCTRL_XOSC" access="Read/Write" description="External Multipurpose Crystal Oscillator (XOSC) Control" reset_value="0x0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="GAIN" description="Oscillator Gain">
-        <Enum name="0" start="0x0" description="2MHz" />
-        <Enum name="1" start="0x1" description="4MHz" />
-        <Enum name="2" start="0x2" description="8MHz" />
-        <Enum name="3" start="0x3" description="16MHz" />
-        <Enum name="4" start="0x4" description="30MHz" />
-      </BitField>
-      <BitField start="11" size="1" name="AMPGC" description="Automatic Amplitude Gain Control" />
-      <BitField start="12" size="4" name="STARTUP" description="Start-Up Time" />
-    </Register>
-    <Register start="+0x14" size="2" name="SYSCTRL_XOSC32K" access="Read/Write" description="32kHz External Crystal Oscillator (XOSC32K) Control" reset_value="0x0080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="3" size="1" name="EN32K" description="32kHz Output Enable" />
-      <BitField start="4" size="1" name="EN1K" description="1kHz Output Enable" />
-      <BitField start="5" size="1" name="AAMPEN" description="Automatic Amplitude Control Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="STARTUP" description="Oscillator Start-Up Time" />
-      <BitField start="12" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT8)" start="0x42002C00" description="Basic Timer Counter 3">
-    <Register start="+0x18+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period Value" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT16)" start="0x42002C00" description="Basic Timer Counter 3">
-    <Register start="+0x18+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT32)" start="0x42002C00" description="Basic Timer Counter 3">
-    <Register start="+0x18+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT8)" start="0x42003000" description="Basic Timer Counter 4">
-    <Register start="+0x18+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period Value" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT16)" start="0x42003000" description="Basic Timer Counter 4">
-    <Register start="+0x18+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT32)" start="0x42003000" description="Basic Timer Counter 4">
-    <Register start="+0x18+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT8)" start="0x42003400" description="Basic Timer Counter 5">
-    <Register start="+0x18+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period Value" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT16)" start="0x42003400" description="Basic Timer Counter 5">
-    <Register start="+0x18+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT32)" start="0x42003400" description="Basic Timer Counter 5">
-    <Register start="+0x18+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x18+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare/Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Compare/Capture Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Value" />
-    </Register>
-    <Register start="+0x00" size="2" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="TC Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="5" size="2" name="WAVEGEN" description="Waveform Generation Operation">
-        <Enum name="NFRQ" start="0x0" />
-        <Enum name="MFRQ" start="0x1" />
-        <Enum name="NPWM" start="0x2" />
-        <Enum name="MPWM" start="0x3" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock. Reset the prescaler counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="6" size="2" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="1" name="TC_CTRLC" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform 0 Invert Enable" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform 1 Invert Enable" />
-      <BitField start="4" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="5" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x0A" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="PPW" start="0x5" description="Period captured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period captured in CC1, pulse width in CC0" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Inverted Event Input" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Input" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x0E" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="3" size="1" name="SYNCRDY" description="Synchronization Ready" />
-      <BitField start="4" size="1" name="MC0" description="Match or Capture Channel 0" />
-      <BitField start="5" size="1" name="MC1" description="Match or Capture Channel 1" />
-    </Register>
-    <Register start="+0x02" size="2" name="TC_READREQ" access="Read/Write" description="Read Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ADDR" description="Address" />
-      <BitField start="14" size="1" name="RCONT" description="Read Continuously" />
-      <BitField start="15" size="1" name="RREQ" description="Read Request" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_STATUS" access="ReadOnly" description="Status" reset_value="0x08" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="STOP" description="Stop" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC0" start="0x42002000" description="Timer Counter Control 0">
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTB" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBV" description="Pattern Buffer Valid" />
-      <BitField start="6" size="1" name="WAVEBV" description="Wave Buffer Valid" />
-      <BitField start="7" size="1" name="PERBV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="16" size="1" name="PATTB" description="Pattern Buffer Busy" />
-      <BitField start="17" size="1" name="WAVEB" description="Wave Buffer Busy" />
-      <BitField start="18" size="1" name="PERB" description="Period Buffer Busy" />
-      <BitField start="19" size="1" name="CCB0" description="Compare Channel Buffer 0 Busy" />
-      <BitField start="20" size="1" name="CCB1" description="Compare Channel Buffer 1 Busy" />
-      <BitField start="21" size="1" name="CCB2" description="Compare Channel Buffer 2 Busy" />
-      <BitField start="22" size="1" name="CCB3" description="Compare Channel Buffer 3 Busy" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x68" size="4" name="TCC_WAVEB" access="Read/Write" description="Waveform Control Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGENB" description="Waveform Generation Buffer">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMPB" description="Ramp Mode Buffer">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPERENB" description="Circular Period Enable Buffer" />
-      <BitField start="8" size="1" name="CICCENB0" description="Circular Channel 0 Enable Buffer" />
-      <BitField start="9" size="1" name="CICCENB1" description="Circular Channel 1 Enable Buffer" />
-      <BitField start="10" size="1" name="CICCENB2" description="Circular Channel 2 Enable Buffer" />
-      <BitField start="11" size="1" name="CICCENB3" description="Circular Channel 3 Enable Buffer" />
-      <BitField start="16" size="1" name="POLB0" description="Channel 0 Polarity Buffer" />
-      <BitField start="17" size="1" name="POLB1" description="Channel 1 Polarity Buffer" />
-      <BitField start="18" size="1" name="POLB2" description="Channel 2 Polarity Buffer" />
-      <BitField start="19" size="1" name="POLB3" description="Channel 3 Polarity Buffer" />
-      <BitField start="24" size="1" name="SWAPB0" description="Swap DTI Output Pair 0 Buffer" />
-      <BitField start="25" size="1" name="SWAPB1" description="Swap DTI Output Pair 1 Buffer" />
-      <BitField start="26" size="1" name="SWAPB2" description="Swap DTI Output Pair 2 Buffer" />
-      <BitField start="27" size="1" name="SWAPB3" description="Swap DTI Output Pair 3 Buffer" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC1" start="0x42002400" description="Timer Counter Control 1">
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTB" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBV" description="Pattern Buffer Valid" />
-      <BitField start="6" size="1" name="WAVEBV" description="Wave Buffer Valid" />
-      <BitField start="7" size="1" name="PERBV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="16" size="1" name="PATTB" description="Pattern Buffer Busy" />
-      <BitField start="17" size="1" name="WAVEB" description="Wave Buffer Busy" />
-      <BitField start="18" size="1" name="PERB" description="Period Buffer Busy" />
-      <BitField start="19" size="1" name="CCB0" description="Compare Channel Buffer 0 Busy" />
-      <BitField start="20" size="1" name="CCB1" description="Compare Channel Buffer 1 Busy" />
-      <BitField start="21" size="1" name="CCB2" description="Compare Channel Buffer 2 Busy" />
-      <BitField start="22" size="1" name="CCB3" description="Compare Channel Buffer 3 Busy" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x68" size="4" name="TCC_WAVEB" access="Read/Write" description="Waveform Control Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGENB" description="Waveform Generation Buffer">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMPB" description="Ramp Mode Buffer">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPERENB" description="Circular Period Enable Buffer" />
-      <BitField start="8" size="1" name="CICCENB0" description="Circular Channel 0 Enable Buffer" />
-      <BitField start="9" size="1" name="CICCENB1" description="Circular Channel 1 Enable Buffer" />
-      <BitField start="10" size="1" name="CICCENB2" description="Circular Channel 2 Enable Buffer" />
-      <BitField start="11" size="1" name="CICCENB3" description="Circular Channel 3 Enable Buffer" />
-      <BitField start="16" size="1" name="POLB0" description="Channel 0 Polarity Buffer" />
-      <BitField start="17" size="1" name="POLB1" description="Channel 1 Polarity Buffer" />
-      <BitField start="18" size="1" name="POLB2" description="Channel 2 Polarity Buffer" />
-      <BitField start="19" size="1" name="POLB3" description="Channel 3 Polarity Buffer" />
-      <BitField start="24" size="1" name="SWAPB0" description="Swap DTI Output Pair 0 Buffer" />
-      <BitField start="25" size="1" name="SWAPB1" description="Swap DTI Output Pair 1 Buffer" />
-      <BitField start="26" size="1" name="SWAPB2" description="Swap DTI Output Pair 2 Buffer" />
-      <BitField start="27" size="1" name="SWAPB3" description="Swap DTI Output Pair 3 Buffer" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC2" start="0x42002800" description="Timer Counter Control 2">
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCB0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCB1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCB2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCB3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCB" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-      </BitField>
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="NONE" start="0x0" description="No blanking applied" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-      </BitField>
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTB" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCY" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERB_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERCYB" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERB" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBV" description="Pattern Buffer Valid" />
-      <BitField start="6" size="1" name="WAVEBV" description="Wave Buffer Valid" />
-      <BitField start="7" size="1" name="PERBV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="16" size="1" name="PATTB" description="Pattern Buffer Busy" />
-      <BitField start="17" size="1" name="WAVEB" description="Wave Buffer Busy" />
-      <BitField start="18" size="1" name="PERB" description="Period Buffer Busy" />
-      <BitField start="19" size="1" name="CCB0" description="Compare Channel Buffer 0 Busy" />
-      <BitField start="20" size="1" name="CCB1" description="Compare Channel Buffer 1 Busy" />
-      <BitField start="21" size="1" name="CCB2" description="Compare Channel Buffer 2 Busy" />
-      <BitField start="22" size="1" name="CCB3" description="Compare Channel Buffer 3 Busy" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x68" size="4" name="TCC_WAVEB" access="Read/Write" description="Waveform Control Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGENB" description="Waveform Generation Buffer">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMPB" description="Ramp Mode Buffer">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPERENB" description="Circular Period Enable Buffer" />
-      <BitField start="8" size="1" name="CICCENB0" description="Circular Channel 0 Enable Buffer" />
-      <BitField start="9" size="1" name="CICCENB1" description="Circular Channel 1 Enable Buffer" />
-      <BitField start="10" size="1" name="CICCENB2" description="Circular Channel 2 Enable Buffer" />
-      <BitField start="11" size="1" name="CICCENB3" description="Circular Channel 3 Enable Buffer" />
-      <BitField start="16" size="1" name="POLB0" description="Channel 0 Polarity Buffer" />
-      <BitField start="17" size="1" name="POLB1" description="Channel 1 Polarity Buffer" />
-      <BitField start="18" size="1" name="POLB2" description="Channel 2 Polarity Buffer" />
-      <BitField start="19" size="1" name="POLB3" description="Channel 3 Polarity Buffer" />
-      <BitField start="24" size="1" name="SWAPB0" description="Swap DTI Output Pair 0 Buffer" />
-      <BitField start="25" size="1" name="SWAPB1" description="Swap DTI Output Pair 1 Buffer" />
-      <BitField start="26" size="1" name="SWAPB2" description="Swap DTI Output Pair 2 Buffer" />
-      <BitField start="27" size="1" name="SWAPB3" description="Swap DTI Output Pair 3 Buffer" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (DEVICE)" start="0x41005000" description="Universal Serial Bus">
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="DEVICE Control B" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETACH" description="Detach" />
-      <BitField start="1" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration">
-        <Enum name="FS" start="0x0" description="FS : Full Speed" />
-        <Enum name="LS" start="0x1" description="LS : Low Speed" />
-        <Enum name="HS" start="0x2" description="HS : High Speed capable" />
-        <Enum name="HSTM" start="0x3" description="HSTM: High Speed Test Mode (force high-speed mode for test mode)" />
-      </BitField>
-      <BitField start="4" size="1" name="NREPLY" description="No Reply" />
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="7" size="1" name="TSTPCKT" description="Test packet mode" />
-      <BitField start="8" size="1" name="OPMODE2" description="Specific Operational Mode" />
-      <BitField start="9" size="1" name="GNAK" description="Global NAK" />
-      <BitField start="10" size="2" name="LPMHDSK" description="Link Power Management Handshake">
-        <Enum name="NO" start="0x0" description="No handshake. LPM is not supported" />
-        <Enum name="ACK" start="0x1" description="ACK" />
-        <Enum name="NYET" start="0x2" description="NYET" />
-        <Enum name="STALL" start="0x3" description="STALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_DADD" access="Read/Write" description="DEVICE Device Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DADD" description="Device Address" />
-      <BitField start="7" size="1" name="ADDEN" description="Device Address Enable" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_EPCFG0" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_EPCFG1" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_EPCFG2" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_EPCFG3" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_EPCFG4" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_EPCFG5" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_EPCFG6" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_EPCFG7" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_EPINTENCLR0" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_EPINTENCLR1" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_EPINTENCLR2" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_EPINTENCLR3" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_EPINTENCLR4" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_EPINTENCLR5" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_EPINTENCLR6" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_EPINTENCLR7" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_EPINTENSET0" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_EPINTENSET1" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_EPINTENSET2" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_EPINTENSET3" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_EPINTENSET4" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_EPINTENSET5" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_EPINTENSET6" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_EPINTENSET7" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_EPINTFLAG0" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_EPINTFLAG1" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_EPINTFLAG2" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_EPINTFLAG3" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_EPINTFLAG4" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_EPINTFLAG5" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_EPINTFLAG6" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_EPINTFLAG7" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_EPINTSMRY" access="ReadOnly" description="DEVICE End Point Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="End Point 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="End Point 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="End Point 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="End Point 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="End Point 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="End Point 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="End Point 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="End Point 7 Interrupt" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_EPSTATUS0" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_EPSTATUS1" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_EPSTATUS2" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_EPSTATUS3" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_EPSTATUS4" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_EPSTATUS5" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_EPSTATUS6" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_EPSTATUS7" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_EPSTATUSCLR0" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_EPSTATUSCLR1" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_EPSTATUSCLR2" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_EPSTATUSCLR3" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_EPSTATUSCLR4" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_EPSTATUSCLR5" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_EPSTATUSCLR6" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_EPSTATUSCLR7" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_EPSTATUSSET0" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_EPSTATUSSET1" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_EPSTATUSSET2" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_EPSTATUSSET3" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_EPSTATUSSET4" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_EPSTATUSSET5" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_EPSTATUSSET6" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_EPSTATUSSET7" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="ReadOnly" description="DEVICE Device Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-      <BitField start="15" size="1" name="FNCERR" description="Frame Number CRC Error" />
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="DEVICE Device Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="DEVICE Device Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="DEVICE Device Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x05" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="ReadOnly" description="DEVICE Status" reset_value="0x40" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status">
-        <Enum name="FS" start="0x0" description="Full-speed mode" />
-        <Enum name="HS" start="0x1" description="High-speed mode" />
-        <Enum name="LS" start="0x2" description="Low-speed mode" />
-      </BitField>
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status">
-        <Enum name="0" start="0x0" description="SE0/RESET" />
-        <Enum name="1" start="0x1" description="FS-J or LS-K State" />
-        <Enum name="2" start="0x2" description="FS-K or LS-J State" />
-      </BitField>
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (HOST)" start="0x41005000" description="Universal Serial Bus">
-    <Register start="+0x103+0" size="1" name="USB_BINTERVAL0" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+32" size="1" name="USB_BINTERVAL1" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+64" size="1" name="USB_BINTERVAL2" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+96" size="1" name="USB_BINTERVAL3" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+128" size="1" name="USB_BINTERVAL4" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+160" size="1" name="USB_BINTERVAL5" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+192" size="1" name="USB_BINTERVAL6" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+224" size="1" name="USB_BINTERVAL7" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="HOST Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RESUME" description="Send USB Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration for Host">
-        <Enum name="NORMAL" start="0x0" description="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." />
-        <Enum name="FS" start="0x3" description="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." />
-      </BitField>
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="8" size="1" name="SOFE" description="Start of Frame Generation Enable" />
-      <BitField start="9" size="1" name="BUSRESET" description="Send USB Reset" />
-      <BitField start="10" size="1" name="VBUSOK" description="VBUS is OK" />
-      <BitField start="11" size="1" name="L1RESUME" description="Send L1 Resume" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x012" size="1" name="USB_FLENHIGH" access="ReadOnly" description="HOST Host Frame Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FLENHIGH" description="Frame Length" />
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="Read/Write" description="HOST Host Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_HSOFC" access="Read/Write" description="HOST Host Start Of Frame Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FLENC" description="Frame Length Control" />
-      <BitField start="7" size="1" name="FLENCE" description="Frame Length Control Enable" />
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="HOST Host Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Disable" />
-      <BitField start="3" size="1" name="RST" description="BUS Reset Interrupt Disable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Disable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to Device Interrupt Disable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from Device Interrupt Disable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Disable" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection Interrupt Disable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Disable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="HOST Host Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to the Device Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume fromthe device Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="DCONN" description="Link Power Management Interrupt Enable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="HOST Host Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="DNRSM" description="Downstream" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from the Device" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_PCFG0" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_PCFG1" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_PCFG2" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_PCFG3" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_PCFG4" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_PCFG5" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_PCFG6" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_PCFG7" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_PINTENCLR0" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_PINTENCLR1" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_PINTENCLR2" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_PINTENCLR3" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_PINTENCLR4" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_PINTENCLR5" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_PINTENCLR6" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_PINTENCLR7" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_PINTENSET0" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_PINTENSET1" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_PINTENSET2" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_PINTENSET3" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_PINTENSET4" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_PINTENSET5" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_PINTENSET6" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_PINTENSET7" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_PINTFLAG0" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_PINTFLAG1" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_PINTFLAG2" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_PINTFLAG3" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_PINTFLAG4" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_PINTFLAG5" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_PINTFLAG6" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_PINTFLAG7" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_PINTSMRY" access="ReadOnly" description="HOST Pipe Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="Pipe 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="Pipe 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="Pipe 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="Pipe 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="Pipe 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="Pipe 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="Pipe 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="Pipe 7 Interrupt" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_PSTATUS0" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_PSTATUS1" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_PSTATUS2" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_PSTATUS3" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_PSTATUS4" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_PSTATUS5" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_PSTATUS6" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_PSTATUS7" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_PSTATUSCLR0" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_PSTATUSCLR1" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_PSTATUSCLR2" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_PSTATUSCLR3" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_PSTATUSCLR4" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_PSTATUSCLR5" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_PSTATUSCLR6" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_PSTATUSCLR7" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_PSTATUSSET0" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_PSTATUSSET1" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_PSTATUSSET2" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_PSTATUSSET3" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_PSTATUSSET4" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_PSTATUSSET5" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_PSTATUSSET6" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_PSTATUSSET7" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x05" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service">
-        <Enum name="DISABLE" start="0x0" description="Background (no sensitive operation)" />
-        <Enum name="LOW" start="0x1" description="Sensitive Bandwidth" />
-        <Enum name="MEDIUM" start="0x2" description="Sensitive Latency" />
-        <Enum name="HIGH" start="0x3" description="Critical Latency" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="Read/Write" description="HOST Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status" />
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status" />
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WDT" start="0x40001000" description="Watchdog Timer">
-    <Register start="+0x8" size="1" name="WDT_CLEAR" access="WriteOnly" description="Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLEAR" description="Watchdog Clear">
-        <Enum name="KEY" start="0xa5" description="Clear Key" />
-      </BitField>
-    </Register>
-    <Register start="+0x1" size="1" name="WDT_CONFIG" access="Read/Write" description="Configuration" reset_value="0xBB" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PER" description="Time-Out Period">
-        <Enum name="8" start="0x0" description="8 clock cycles" />
-        <Enum name="16" start="0x1" description="16 clock cycles" />
-        <Enum name="32" start="0x2" description="32 clock cycles" />
-        <Enum name="64" start="0x3" description="64 clock cycles" />
-        <Enum name="128" start="0x4" description="128 clock cycles" />
-        <Enum name="256" start="0x5" description="256 clock cycles" />
-        <Enum name="512" start="0x6" description="512 clock cycles" />
-        <Enum name="1K" start="0x7" description="1024 clock cycles" />
-        <Enum name="2K" start="0x8" description="2048 clock cycles" />
-        <Enum name="4K" start="0x9" description="4096 clock cycles" />
-        <Enum name="8K" start="0xa" description="8192 clock cycles" />
-        <Enum name="16K" start="0xb" description="16384 clock cycles" />
-      </BitField>
-      <BitField start="4" size="4" name="WINDOW" description="Window Mode Time-Out Period">
-        <Enum name="8" start="0x0" description="8 clock cycles" />
-        <Enum name="16" start="0x1" description="16 clock cycles" />
-        <Enum name="32" start="0x2" description="32 clock cycles" />
-        <Enum name="64" start="0x3" description="64 clock cycles" />
-        <Enum name="128" start="0x4" description="128 clock cycles" />
-        <Enum name="256" start="0x5" description="256 clock cycles" />
-        <Enum name="512" start="0x6" description="512 clock cycles" />
-        <Enum name="1K" start="0x7" description="1024 clock cycles" />
-        <Enum name="2K" start="0x8" description="2048 clock cycles" />
-        <Enum name="4K" start="0x9" description="4096 clock cycles" />
-        <Enum name="8K" start="0xa" description="8192 clock cycles" />
-        <Enum name="16K" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x0" size="1" name="WDT_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="WEN" description="Watchdog Timer Window Mode Enable" />
-      <BitField start="7" size="1" name="ALWAYSON" description="Always-On" />
-    </Register>
-    <Register start="+0x2" size="1" name="WDT_EWCTRL" access="Read/Write" description="Early Warning Interrupt Control" reset_value="0x0B" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EWOFFSET" description="Early Warning Interrupt Time Offset">
-        <Enum name="8" start="0x0" description="8 clock cycles" />
-        <Enum name="16" start="0x1" description="16 clock cycles" />
-        <Enum name="32" start="0x2" description="32 clock cycles" />
-        <Enum name="64" start="0x3" description="64 clock cycles" />
-        <Enum name="128" start="0x4" description="128 clock cycles" />
-        <Enum name="256" start="0x5" description="256 clock cycles" />
-        <Enum name="512" start="0x6" description="512 clock cycles" />
-        <Enum name="1K" start="0x7" description="1024 clock cycles" />
-        <Enum name="2K" start="0x8" description="2048 clock cycles" />
-        <Enum name="4K" start="0x9" description="4096 clock cycles" />
-        <Enum name="8K" start="0xa" description="8192 clock cycles" />
-        <Enum name="16K" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x4" size="1" name="WDT_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x5" size="1" name="WDT_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x6" size="1" name="WDT_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning" />
-    </Register>
-    <Register start="+0x7" size="1" name="WDT_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="1" name="SYNCBUSY" description="Synchronization Busy" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="PM" start="0" size="1" />
-      <BitField name="SYSCTRL" start="1" size="1" />
-      <BitField name="WDT" start="2" size="1" />
-      <BitField name="RTC" start="3" size="1" />
-      <BitField name="EIC" start="4" size="1" />
-      <BitField name="NVMCTRL" start="5" size="1" />
-      <BitField name="DMAC" start="6" size="1" />
-      <BitField name="USB" start="7" size="1" />
-      <BitField name="EVSYS" start="8" size="1" />
-      <BitField name="SERCOM0" start="9" size="1" />
-      <BitField name="SERCOM1" start="10" size="1" />
-      <BitField name="SERCOM2" start="11" size="1" />
-      <BitField name="SERCOM3" start="12" size="1" />
-      <BitField name="SERCOM4" start="13" size="1" />
-      <BitField name="SERCOM5" start="14" size="1" />
-      <BitField name="TCC0" start="15" size="1" />
-      <BitField name="TCC1" start="16" size="1" />
-      <BitField name="TCC2" start="17" size="1" />
-      <BitField name="TC3" start="18" size="1" />
-      <BitField name="TC4" start="19" size="1" />
-      <BitField name="TC5" start="20" size="1" />
-      <BitField name="ADC" start="23" size="1" />
-      <BitField name="AC" start="24" size="1" />
-      <BitField name="DAC" start="25" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="PM" start="6" size="2" />
-      <BitField name="SYSCTRL" start="14" size="2" />
-      <BitField name="WDT" start="22" size="2" />
-      <BitField name="RTC" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="EIC" start="6" size="2" />
-      <BitField name="NVMCTRL" start="14" size="2" />
-      <BitField name="DMAC" start="22" size="2" />
-      <BitField name="USB" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="EVSYS" start="6" size="2" />
-      <BitField name="SERCOM0" start="14" size="2" />
-      <BitField name="SERCOM1" start="22" size="2" />
-      <BitField name="SERCOM2" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="SERCOM3" start="6" size="2" />
-      <BitField name="SERCOM4" start="14" size="2" />
-      <BitField name="SERCOM5" start="22" size="2" />
-      <BitField name="TCC0" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="TCC1" start="6" size="2" />
-      <BitField name="TCC2" start="14" size="2" />
-      <BitField name="TC3" start="22" size="2" />
-      <BitField name="TC4" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="TC5" start="6" size="2" />
-      <BitField name="ADC" start="30" size="2" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="AC" start="6" size="2" />
-      <BitField name="DAC" start="14" size="2" />
-      <BitField name="I2S" start="30" size="2" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="30" size="2" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="30" size="2" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="22" size="2" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_Vectors.s b/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_Vectors.s
deleted file mode 100644
index 5cecbd23..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/ATSAMD21G18A_Vectors.s
+++ /dev/null
@@ -1,331 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak PM_Handler
-  .thumb_set PM_Handler,Dummy_Handler
-
-  .weak SYSCTRL_Handler
-  .thumb_set SYSCTRL_Handler,Dummy_Handler
-
-  .weak WDT_Handler
-  .thumb_set WDT_Handler,Dummy_Handler
-
-  .weak RTC_Handler
-  .thumb_set RTC_Handler,Dummy_Handler
-
-  .weak EIC_Handler
-  .thumb_set EIC_Handler,Dummy_Handler
-
-  .weak NVMCTRL_Handler
-  .thumb_set NVMCTRL_Handler,Dummy_Handler
-
-  .weak DMAC_Handler
-  .thumb_set DMAC_Handler,Dummy_Handler
-
-  .weak USB_Handler
-  .thumb_set USB_Handler,Dummy_Handler
-
-  .weak EVSYS_Handler
-  .thumb_set EVSYS_Handler,Dummy_Handler
-
-  .weak SERCOM0_Handler
-  .thumb_set SERCOM0_Handler,Dummy_Handler
-
-  .weak SERCOM1_Handler
-  .thumb_set SERCOM1_Handler,Dummy_Handler
-
-  .weak SERCOM2_Handler
-  .thumb_set SERCOM2_Handler,Dummy_Handler
-
-  .weak SERCOM3_Handler
-  .thumb_set SERCOM3_Handler,Dummy_Handler
-
-  .weak SERCOM4_Handler
-  .thumb_set SERCOM4_Handler,Dummy_Handler
-
-  .weak SERCOM5_Handler
-  .thumb_set SERCOM5_Handler,Dummy_Handler
-
-  .weak TCC0_Handler
-  .thumb_set TCC0_Handler,Dummy_Handler
-
-  .weak TCC1_Handler
-  .thumb_set TCC1_Handler,Dummy_Handler
-
-  .weak TCC2_Handler
-  .thumb_set TCC2_Handler,Dummy_Handler
-
-  .weak TC3_Handler
-  .thumb_set TC3_Handler,Dummy_Handler
-
-  .weak TC4_Handler
-  .thumb_set TC4_Handler,Dummy_Handler
-
-  .weak TC5_Handler
-  .thumb_set TC5_Handler,Dummy_Handler
-
-  .weak ADC_Handler
-  .thumb_set ADC_Handler,Dummy_Handler
-
-  .weak AC_Handler
-  .thumb_set AC_Handler,Dummy_Handler
-
-  .weak DAC_Handler
-  .thumb_set DAC_Handler,Dummy_Handler
-
-  .weak I2S_Handler
-  .thumb_set I2S_Handler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak PM_Handler
-PM_Handler:
-  b .
-
-  .thumb_func
-  .weak SYSCTRL_Handler
-SYSCTRL_Handler:
-  b .
-
-  .thumb_func
-  .weak WDT_Handler
-WDT_Handler:
-  b .
-
-  .thumb_func
-  .weak RTC_Handler
-RTC_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_Handler
-EIC_Handler:
-  b .
-
-  .thumb_func
-  .weak NVMCTRL_Handler
-NVMCTRL_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_Handler
-DMAC_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_Handler
-USB_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_Handler
-EVSYS_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_Handler
-SERCOM0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_Handler
-SERCOM1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_Handler
-SERCOM2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_Handler
-SERCOM3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_Handler
-SERCOM4_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_Handler
-SERCOM5_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_Handler
-TCC0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_Handler
-TCC1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_Handler
-TCC2_Handler:
-  b .
-
-  .thumb_func
-  .weak TC3_Handler
-TC3_Handler:
-  b .
-
-  .thumb_func
-  .weak TC4_Handler
-TC4_Handler:
-  b .
-
-  .thumb_func
-  .weak TC5_Handler
-TC5_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC_Handler
-ADC_Handler:
-  b .
-
-  .thumb_func
-  .weak AC_Handler
-AC_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_Handler
-DAC_Handler:
-  b .
-
-  .thumb_func
-  .weak I2S_Handler
-I2S_Handler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word PM_Handler
-  .word SYSCTRL_Handler
-  .word WDT_Handler
-  .word RTC_Handler
-  .word EIC_Handler
-  .word NVMCTRL_Handler
-  .word DMAC_Handler
-  .word USB_Handler
-  .word EVSYS_Handler
-  .word SERCOM0_Handler
-  .word SERCOM1_Handler
-  .word SERCOM2_Handler
-  .word SERCOM3_Handler
-  .word SERCOM4_Handler
-  .word SERCOM5_Handler
-  .word TCC0_Handler
-  .word TCC1_Handler
-  .word TCC2_Handler
-  .word TC3_Handler
-  .word TC4_Handler
-  .word TC5_Handler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word ADC_Handler
-  .word AC_Handler
-  .word DAC_Handler
-  .word Dummy_Handler /* Reserved */
-  .word I2S_Handler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/SAMD21_Startup.s b/examples/device/cdc_msc_freertos/ses/samd21/SAMD21_Startup.s
deleted file mode 100644
index c4b48d35..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/SAMD21_Startup.s
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  ldr r1, =0x7
-  bics r0, r1
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/SAMD21_Target.js b/examples/device/cdc_msc_freertos/ses/samd21/SAMD21_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/SAMD21_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/flash_placement.xml b/examples/device/cdc_msc_freertos/ses/samd21/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/samd21.emProject b/examples/device/cdc_msc_freertos/ses/samd21/samd21.emProject
deleted file mode 100644
index b3db856d..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/samd21.emProject
+++ /dev/null
@@ -1,142 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="samd21" target="8" version="2">
-  <project Name="samd21">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="nRF52840_xxAA"
-      arm_architecture="v6M"
-      arm_core_type="Cortex-M0+"
-      arm_endian="Little"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 20000000,00030000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="ATSAMD21G18A"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="__SAMD21G18A__;__SAMD21_FAMILY;__SAM_D21_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;CONF_XOSC32K_CONFIG=1;CONF_OSC32K_ENABLE=1;CONF_OSC32K_EN32K=1;CONF_XOSC32K_STARTUP=CONF_XOSC32K_STARTUP_TIME_2000092MCS;CONF_DFLL_ONDEMAND=0;CONF_DFLL_OVERWRITE_CALIBRATION=0;BOARD_METRO_M0_EXPRESS;CFG_TUSB_MCU=OPT_MCU_SAMD21"
-      c_user_include_directories="./;../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(asf4Dir)/hpl/pm;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM0"
-      debug_register_definition_file="ATSAMD21G18A_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="$(ProjectDir)/ATSAMD21G18A_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
-      macros="DeviceFamily=SAMD21;Target=ATSAMD21G18A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd21;freertosDir=../../../../../lib/FreeRTOS"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/SAMD21_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="metro_m0_express">
-          <file file_name="../../../../../hw/bsp/metro_m0_express/board_metro_m0_express.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="microchip">
-          <folder Name="samd">
-            <folder Name="asf4">
-              <folder Name="samd21">
-                <folder Name="gcc">
-                  <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/gcc/system_samd21.c" />
-                </folder>
-                <folder Name="hpl">
-                  <folder Name="core">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/core/hpl_init.c" />
-                  </folder>
-                  <folder Name="gclk">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/gclk/hpl_gclk.c" />
-                  </folder>
-                  <folder Name="pm">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/pm/hpl_pm.c" />
-                  </folder>
-                  <folder Name="sysctrl">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c" />
-                  </folder>
-                </folder>
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="ATSAMD21G18A_MemoryMap.xml" />
-      <file file_name="ATSAMD21G18A_Registers.xml" />
-      <file file_name="ATSAMD21G18A_Vectors.s" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="SAMD21_Startup.s" />
-      <file file_name="SAMD21_Target.js" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder Name="lib">
-      <folder Name="FreeRTOS">
-        <folder Name="Source">
-          <folder Name="include">
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/croutine.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/deprecated_definitions.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/event_groups.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/FreeRTOS.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/list.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/message_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_prototypes.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_wrappers.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/portable.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/projdefs.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/queue.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/semphr.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stack_macros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/StackMacros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stream_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/task.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/timers.h" />
-          </folder>
-          <folder Name="portable">
-            <folder Name="GCC">
-              <folder Name="ARM_CM0">
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM0/port.c" />
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM0/portmacro.h" />
-              </folder>
-            </folder>
-            <folder Name="MemMang">
-              <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/MemMang/heap_4.c" />
-            </folder>
-          </folder>
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/list.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/queue.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/tasks.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/timers.c" />
-        </folder>
-        <file file_name="../../../../../lib/FreeRTOS/freertos_hook.c" />
-      </folder>
-    </folder>
-  </project>
-  <configuration Name="Metro M0 Express" />
-</solution>
diff --git a/examples/device/cdc_msc_freertos/ses/samd21/thumb_crt0.s b/examples/device/cdc_msc_freertos/ses/samd21/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd21/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_MemoryMap.xml b/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_MemoryMap.xml
deleted file mode 100644
index 49d9a9cb..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="ATSAMD51J19A">
-  <MemorySegment name="FLASH" start="0x00004000" size="0x0007C000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x20000000" size="0x00030000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x47000000" size="0x00002000" access="Read/Write" />
-</root>
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_Registers.xml b/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_Registers.xml
deleted file mode 100644
index 83fe837f..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_Registers.xml
+++ /dev/null
@@ -1,23643 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="ATSAMD51J19A" description="Atmel ATSAMD51J19A device: Cortex-M4 Microcontroller with 512KB Flash, 192KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD51J19A.aspx for more)">
-  <RegisterGroup name="AC" start="0x42002000" description="Analog Comparators">
-    <Register start="+0x00" size="1" name="AC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x01" size="1" name="AC_CTRLB" access="WriteOnly" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START0" description="Comparator 0 Start Comparison" />
-      <BitField start="1" size="1" name="START1" description="Comparator 1 Start Comparison" />
-    </Register>
-    <Register start="+0x02" size="2" name="AC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMPEO0" description="Comparator 0 Event Output Enable" />
-      <BitField start="1" size="1" name="COMPEO1" description="Comparator 1 Event Output Enable" />
-      <BitField start="4" size="1" name="WINEO0" description="Window 0 Event Output Enable" />
-      <BitField start="8" size="1" name="COMPEI0" description="Comparator 0 Event Input Enable" />
-      <BitField start="9" size="1" name="COMPEI1" description="Comparator 1 Event Input Enable" />
-      <BitField start="12" size="1" name="INVEI0" description="Comparator 0 Input Event Invert Enable" />
-      <BitField start="13" size="1" name="INVEI1" description="Comparator 1 Input Event Invert Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="AC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="AC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0 Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="AC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="COMP0" description="Comparator 0" />
-      <BitField start="1" size="1" name="COMP1" description="Comparator 1" />
-      <BitField start="4" size="1" name="WIN0" description="Window 0" />
-    </Register>
-    <Register start="+0x07" size="1" name="AC_STATUSA" access="ReadOnly" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATE0" description="Comparator 0 Current State" />
-      <BitField start="1" size="1" name="STATE1" description="Comparator 1 Current State" />
-      <BitField start="4" size="2" name="WSTATE0" description="Window 0 Current State">
-        <Enum name="ABOVE" start="0x0" description="Signal is above window" />
-        <Enum name="INSIDE" start="0x1" description="Signal is inside window" />
-        <Enum name="BELOW" start="0x2" description="Signal is below window" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="1" name="AC_STATUSB" access="ReadOnly" description="Status B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY0" description="Comparator 0 Ready" />
-      <BitField start="1" size="1" name="READY1" description="Comparator 1 Ready" />
-    </Register>
-    <Register start="+0x09" size="1" name="AC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x0A" size="1" name="AC_WINCTRL" access="Read/Write" description="Window Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WEN0" description="Window 0 Mode Enable" />
-      <BitField start="1" size="2" name="WINTSEL0" description="Window 0 Interrupt Selection">
-        <Enum name="ABOVE" start="0x0" description="Interrupt on signal above window" />
-        <Enum name="INSIDE" start="0x1" description="Interrupt on signal inside window" />
-        <Enum name="BELOW" start="0x2" description="Interrupt on signal below window" />
-        <Enum name="OUTSIDE" start="0x3" description="Interrupt on signal outside window" />
-      </BitField>
-    </Register>
-    <Register start="+0x0C+0" size="1" name="AC_SCALER0" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x0C+1" size="1" name="AC_SCALER1" access="Read/Write" description="Scaler n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="VALUE" description="Scaler Value" />
-    </Register>
-    <Register start="+0x10+0" size="4" name="AC_COMPCTRL0" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="3" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="3" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="VSCALE" start="0x4" description="VDD Scaler" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="HIGH" start="0x3" description="High speed" />
-      </BitField>
-      <BitField start="19" size="1" name="HYSTEN" description="Hysteresis Enable" />
-      <BitField start="20" size="2" name="HYST" description="Hysteresis Level">
-        <Enum name="HYST50" start="0x0" description="50mV" />
-        <Enum name="HYST100" start="0x1" description="100mV" />
-        <Enum name="HYST150" start="0x2" description="150mV" />
-      </BitField>
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-      <BitField start="28" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-    </Register>
-    <Register start="+0x10+4" size="4" name="AC_COMPCTRL1" access="Read/Write" description="Comparator Control n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="SINGLE" description="Single-Shot Mode" />
-      <BitField start="3" size="2" name="INTSEL" description="Interrupt Selection">
-        <Enum name="TOGGLE" start="0x0" description="Interrupt on comparator output toggle" />
-        <Enum name="RISING" start="0x1" description="Interrupt on comparator output rising" />
-        <Enum name="FALLING" start="0x2" description="Interrupt on comparator output falling" />
-        <Enum name="EOC" start="0x3" description="Interrupt on end of comparison (single-shot mode only)" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="3" name="MUXNEG" description="Negative Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="GND" start="0x4" description="Ground" />
-        <Enum name="VSCALE" start="0x5" description="VDD scaler" />
-        <Enum name="BANDGAP" start="0x6" description="Internal bandgap voltage" />
-        <Enum name="DAC" start="0x7" description="DAC output" />
-      </BitField>
-      <BitField start="12" size="3" name="MUXPOS" description="Positive Input Mux Selection">
-        <Enum name="PIN0" start="0x0" description="I/O pin 0" />
-        <Enum name="PIN1" start="0x1" description="I/O pin 1" />
-        <Enum name="PIN2" start="0x2" description="I/O pin 2" />
-        <Enum name="PIN3" start="0x3" description="I/O pin 3" />
-        <Enum name="VSCALE" start="0x4" description="VDD Scaler" />
-      </BitField>
-      <BitField start="15" size="1" name="SWAP" description="Swap Inputs and Invert" />
-      <BitField start="16" size="2" name="SPEED" description="Speed Selection">
-        <Enum name="HIGH" start="0x3" description="High speed" />
-      </BitField>
-      <BitField start="19" size="1" name="HYSTEN" description="Hysteresis Enable" />
-      <BitField start="20" size="2" name="HYST" description="Hysteresis Level">
-        <Enum name="HYST50" start="0x0" description="50mV" />
-        <Enum name="HYST100" start="0x1" description="100mV" />
-        <Enum name="HYST150" start="0x2" description="150mV" />
-      </BitField>
-      <BitField start="24" size="3" name="FLEN" description="Filter Length">
-        <Enum name="OFF" start="0x0" description="No filtering" />
-        <Enum name="MAJ3" start="0x1" description="3-bit majority function (2 of 3)" />
-        <Enum name="MAJ5" start="0x2" description="5-bit majority function (3 of 5)" />
-      </BitField>
-      <BitField start="28" size="2" name="OUT" description="Output">
-        <Enum name="OFF" start="0x0" description="The output of COMPn is not routed to the COMPn I/O port" />
-        <Enum name="ASYNC" start="0x1" description="The asynchronous output of COMPn is routed to the COMPn I/O port" />
-        <Enum name="SYNC" start="0x2" description="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" />
-      </BitField>
-    </Register>
-    <Register start="+0x20" size="4" name="AC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="WINCTRL" description="WINCTRL Synchronization Busy" />
-      <BitField start="3" size="1" name="COMPCTRL0" description="COMPCTRL 0 Synchronization Busy" />
-      <BitField start="4" size="1" name="COMPCTRL1" description="COMPCTRL 1 Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="2" name="AC_CALIB" access="Read/Write" description="Calibration" reset_value="0x0101" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BIAS0" description="COMP0/1 Bias Scaling" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x43001C00" description="Analog Digital Converter 0">
-    <Register start="+0x00" size="2" name="ADC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="3" size="2" name="DUALSEL" description="Dual Mode Trigger Selection">
-        <Enum name="BOTH" start="0x0" description="Start event or software trigger will start a conversion on both ADCs" />
-        <Enum name="INTERLEAVE" start="0x1" description="START event or software trigger will alternatingly start a conversion on ADC0 and ADC1" />
-      </BitField>
-      <BitField start="5" size="1" name="SLAVEEN" description="Slave Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler Configuration">
-        <Enum name="DIV2" start="0x0" description="Peripheral clock divided by 2" />
-        <Enum name="DIV4" start="0x1" description="Peripheral clock divided by 4" />
-        <Enum name="DIV8" start="0x2" description="Peripheral clock divided by 8" />
-        <Enum name="DIV16" start="0x3" description="Peripheral clock divided by 16" />
-        <Enum name="DIV32" start="0x4" description="Peripheral clock divided by 32" />
-        <Enum name="DIV64" start="0x5" description="Peripheral clock divided by 64" />
-        <Enum name="DIV128" start="0x6" description="Peripheral clock divided by 128" />
-        <Enum name="DIV256" start="0x7" description="Peripheral clock divided by 256" />
-      </BitField>
-      <BitField start="15" size="1" name="R2R" description="Rail to Rail Operation Enable" />
-    </Register>
-    <Register start="+0x02" size="1" name="ADC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSHEI" description="Flush Event Input Enable" />
-      <BitField start="1" size="1" name="STARTEI" description="Start Conversion Event Input Enable" />
-      <BitField start="2" size="1" name="FLUSHINV" description="Flush Event Invert Enable" />
-      <BitField start="3" size="1" name="STARTINV" description="Start Conversion Event Invert Enable" />
-      <BitField start="4" size="1" name="RESRDYEO" description="Result Ready Event Out" />
-      <BitField start="5" size="1" name="WINMONEO" description="Window Monitor Event Out" />
-    </Register>
-    <Register start="+0x03" size="1" name="ADC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x04" size="2" name="ADC_INPUTCTRL" access="Read/Write" description="Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MUXPOS" description="Positive Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="AIN8" start="0x8" description="ADC AIN8 Pin" />
-        <Enum name="AIN9" start="0x9" description="ADC AIN9 Pin" />
-        <Enum name="AIN10" start="0xa" description="ADC AIN10 Pin" />
-        <Enum name="AIN11" start="0xb" description="ADC AIN11 Pin" />
-        <Enum name="AIN12" start="0xc" description="ADC AIN12 Pin" />
-        <Enum name="AIN13" start="0xd" description="ADC AIN13 Pin" />
-        <Enum name="AIN14" start="0xe" description="ADC AIN14 Pin" />
-        <Enum name="AIN15" start="0xf" description="ADC AIN15 Pin" />
-        <Enum name="AIN16" start="0x10" description="ADC AIN16 Pin" />
-        <Enum name="AIN17" start="0x11" description="ADC AIN17 Pin" />
-        <Enum name="AIN18" start="0x12" description="ADC AIN18 Pin" />
-        <Enum name="AIN19" start="0x13" description="ADC AIN19 Pin" />
-        <Enum name="AIN20" start="0x14" description="ADC AIN20 Pin" />
-        <Enum name="AIN21" start="0x15" description="ADC AIN21 Pin" />
-        <Enum name="AIN22" start="0x16" description="ADC AIN22 Pin" />
-        <Enum name="AIN23" start="0x17" description="ADC AIN23 Pin" />
-        <Enum name="SCALEDCOREVCC" start="0x18" description="1/4 Scaled Core Supply" />
-        <Enum name="SCALEDVBAT" start="0x19" description="1/4 Scaled VBAT Supply" />
-        <Enum name="SCALEDIOVCC" start="0x1a" description="1/4 Scaled I/O Supply" />
-        <Enum name="BANDGAP" start="0x1b" description="Bandgap Voltage" />
-        <Enum name="PTAT" start="0x1c" description="Temperature Sensor" />
-        <Enum name="CTAT" start="0x1d" description="Temperature Sensor" />
-        <Enum name="DAC" start="0x1e" description="DAC Output" />
-        <Enum name="PTC" start="0x1f" description="PTC output (only on ADC0)" />
-      </BitField>
-      <BitField start="7" size="1" name="DIFFMODE" description="Differential Mode" />
-      <BitField start="8" size="5" name="MUXNEG" description="Negative Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="GND" start="0x18" description="Internal Ground" />
-      </BitField>
-      <BitField start="15" size="1" name="DSEQSTOP" description="Stop DMA Sequencing" />
-    </Register>
-    <Register start="+0x06" size="2" name="ADC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left-Adjusted Result" />
-      <BitField start="1" size="1" name="FREERUN" description="Free Running Mode" />
-      <BitField start="2" size="1" name="CORREN" description="Digital Correction Logic Enable" />
-      <BitField start="3" size="2" name="RESSEL" description="Conversion Result Resolution">
-        <Enum name="12BIT" start="0x0" description="12-bit result" />
-        <Enum name="16BIT" start="0x1" description="For averaging mode output" />
-        <Enum name="10BIT" start="0x2" description="10-bit result" />
-        <Enum name="8BIT" start="0x3" description="8-bit result" />
-      </BitField>
-      <BitField start="8" size="3" name="WINMODE" description="Window Monitor Mode">
-        <Enum name="DISABLE" start="0x0" description="No window mode (default)" />
-        <Enum name="MODE1" start="0x1" description="RESULT &gt; WINLT" />
-        <Enum name="MODE2" start="0x2" description="RESULT &lt; WINUT" />
-        <Enum name="MODE3" start="0x3" description="WINLT &lt; RESULT &lt; WINUT" />
-        <Enum name="MODE4" start="0x4" description="!(WINLT &lt; RESULT &lt; WINUT)" />
-      </BitField>
-      <BitField start="11" size="1" name="WINSS" description="Window Single Sample" />
-    </Register>
-    <Register start="+0x08" size="1" name="ADC_REFCTRL" access="Read/Write" description="Reference Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference Selection">
-        <Enum name="INTREF" start="0x0" description="Internal Bandgap Reference" />
-        <Enum name="INTVCC0" start="0x2" description="1/2 VDDANA" />
-        <Enum name="INTVCC1" start="0x3" description="VDDANA" />
-        <Enum name="AREFA" start="0x4" description="External Reference" />
-        <Enum name="AREFB" start="0x5" description="External Reference" />
-        <Enum name="AREFC" start="0x6" description="External Reference (only on ADC1)" />
-      </BitField>
-      <BitField start="7" size="1" name="REFCOMP" description="Reference Buffer Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="ADC_AVGCTRL" access="Read/Write" description="Average Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLENUM" description="Number of Samples to be Collected">
-        <Enum name="1" start="0x0" description="1 sample" />
-        <Enum name="2" start="0x1" description="2 samples" />
-        <Enum name="4" start="0x2" description="4 samples" />
-        <Enum name="8" start="0x3" description="8 samples" />
-        <Enum name="16" start="0x4" description="16 samples" />
-        <Enum name="32" start="0x5" description="32 samples" />
-        <Enum name="64" start="0x6" description="64 samples" />
-        <Enum name="128" start="0x7" description="128 samples" />
-        <Enum name="256" start="0x8" description="256 samples" />
-        <Enum name="512" start="0x9" description="512 samples" />
-        <Enum name="1024" start="0xa" description="1024 samples" />
-      </BitField>
-      <BitField start="4" size="3" name="ADJRES" description="Adjusting Result / Division Coefficient" />
-    </Register>
-    <Register start="+0x0B" size="1" name="ADC_SAMPCTRL" access="Read/Write" description="Sample Time Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SAMPLEN" description="Sampling Time Length" />
-      <BitField start="7" size="1" name="OFFCOMP" description="Comparator Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="ADC_WINLT" access="Read/Write" description="Window Monitor Lower Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINLT" description="Window Lower Threshold" />
-    </Register>
-    <Register start="+0x0E" size="2" name="ADC_WINUT" access="Read/Write" description="Window Monitor Upper Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINUT" description="Window Upper Threshold" />
-    </Register>
-    <Register start="+0x10" size="2" name="ADC_GAINCORR" access="Read/Write" description="Gain Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="GAINCORR" description="Gain Correction Value" />
-    </Register>
-    <Register start="+0x12" size="2" name="ADC_OFFSETCORR" access="Read/Write" description="Offset Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="OFFSETCORR" description="Offset Correction Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="ADC_SWTRIG" access="Read/Write" description="Software Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSH" description="ADC Conversion Flush" />
-      <BitField start="1" size="1" name="START" description="Start ADC Conversion" />
-    </Register>
-    <Register start="+0x2C" size="1" name="ADC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Disable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Disable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Disable" />
-    </Register>
-    <Register start="+0x2D" size="1" name="ADC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-    </Register>
-    <Register start="+0x2E" size="1" name="ADC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Flag" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Flag" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Flag" />
-    </Register>
-    <Register start="+0x2F" size="1" name="ADC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADCBUSY" description="ADC Busy Status" />
-      <BitField start="2" size="6" name="WCC" description="Window Comparator Counter" />
-    </Register>
-    <Register start="+0x30" size="4" name="ADC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="SWRST Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="ENABLE Synchronization Busy" />
-      <BitField start="2" size="1" name="INPUTCTRL" description="Input Control Synchronization Busy" />
-      <BitField start="3" size="1" name="CTRLB" description="Control B Synchronization Busy" />
-      <BitField start="4" size="1" name="REFCTRL" description="Reference Control Synchronization Busy" />
-      <BitField start="5" size="1" name="AVGCTRL" description="Average Control Synchronization Busy" />
-      <BitField start="6" size="1" name="SAMPCTRL" description="Sampling Time Control Synchronization Busy" />
-      <BitField start="7" size="1" name="WINLT" description="Window Monitor Lower Threshold Synchronization Busy" />
-      <BitField start="8" size="1" name="WINUT" description="Window Monitor Upper Threshold Synchronization Busy" />
-      <BitField start="9" size="1" name="GAINCORR" description="Gain Correction Synchronization Busy" />
-      <BitField start="10" size="1" name="OFFSETCORR" description="Offset Correction Synchronization Busy" />
-      <BitField start="11" size="1" name="SWTRIG" description="Software Trigger Synchronization Busy" />
-    </Register>
-    <Register start="+0x34" size="4" name="ADC_DSEQDATA" access="WriteOnly" description="DMA Sequencial Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="DMA Sequential Data" />
-    </Register>
-    <Register start="+0x38" size="4" name="ADC_DSEQCTRL" access="Read/Write" description="DMA Sequential Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="AUTOSTART" description="ADC Auto-Start Conversion" />
-    </Register>
-    <Register start="+0x3C" size="4" name="ADC_DSEQSTAT" access="ReadOnly" description="DMA Sequencial Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="BUSY" description="DMA Sequencing Busy" />
-    </Register>
-    <Register start="+0x40" size="2" name="ADC_RESULT" access="ReadOnly" description="Result Conversion Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Result Conversion Value" />
-    </Register>
-    <Register start="+0x44" size="2" name="ADC_RESS" access="ReadOnly" description="Last Sample Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESS" description="Last ADC conversion result" />
-    </Register>
-    <Register start="+0x48" size="2" name="ADC_CALIB" access="Read/Write" description="Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="BIASCOMP" description="Bias Comparator Scaling" />
-      <BitField start="4" size="3" name="BIASR2R" description="Bias R2R Ampli scaling" />
-      <BitField start="8" size="3" name="BIASREFBUF" description="Bias  Reference Buffer Scaling" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x43002000" description="Analog Digital Converter 1">
-    <Register start="+0x00" size="2" name="ADC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="3" size="2" name="DUALSEL" description="Dual Mode Trigger Selection">
-        <Enum name="BOTH" start="0x0" description="Start event or software trigger will start a conversion on both ADCs" />
-        <Enum name="INTERLEAVE" start="0x1" description="START event or software trigger will alternatingly start a conversion on ADC0 and ADC1" />
-      </BitField>
-      <BitField start="5" size="1" name="SLAVEEN" description="Slave Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler Configuration">
-        <Enum name="DIV2" start="0x0" description="Peripheral clock divided by 2" />
-        <Enum name="DIV4" start="0x1" description="Peripheral clock divided by 4" />
-        <Enum name="DIV8" start="0x2" description="Peripheral clock divided by 8" />
-        <Enum name="DIV16" start="0x3" description="Peripheral clock divided by 16" />
-        <Enum name="DIV32" start="0x4" description="Peripheral clock divided by 32" />
-        <Enum name="DIV64" start="0x5" description="Peripheral clock divided by 64" />
-        <Enum name="DIV128" start="0x6" description="Peripheral clock divided by 128" />
-        <Enum name="DIV256" start="0x7" description="Peripheral clock divided by 256" />
-      </BitField>
-      <BitField start="15" size="1" name="R2R" description="Rail to Rail Operation Enable" />
-    </Register>
-    <Register start="+0x02" size="1" name="ADC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSHEI" description="Flush Event Input Enable" />
-      <BitField start="1" size="1" name="STARTEI" description="Start Conversion Event Input Enable" />
-      <BitField start="2" size="1" name="FLUSHINV" description="Flush Event Invert Enable" />
-      <BitField start="3" size="1" name="STARTINV" description="Start Conversion Event Invert Enable" />
-      <BitField start="4" size="1" name="RESRDYEO" description="Result Ready Event Out" />
-      <BitField start="5" size="1" name="WINMONEO" description="Window Monitor Event Out" />
-    </Register>
-    <Register start="+0x03" size="1" name="ADC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x04" size="2" name="ADC_INPUTCTRL" access="Read/Write" description="Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MUXPOS" description="Positive Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="AIN8" start="0x8" description="ADC AIN8 Pin" />
-        <Enum name="AIN9" start="0x9" description="ADC AIN9 Pin" />
-        <Enum name="AIN10" start="0xa" description="ADC AIN10 Pin" />
-        <Enum name="AIN11" start="0xb" description="ADC AIN11 Pin" />
-        <Enum name="AIN12" start="0xc" description="ADC AIN12 Pin" />
-        <Enum name="AIN13" start="0xd" description="ADC AIN13 Pin" />
-        <Enum name="AIN14" start="0xe" description="ADC AIN14 Pin" />
-        <Enum name="AIN15" start="0xf" description="ADC AIN15 Pin" />
-        <Enum name="AIN16" start="0x10" description="ADC AIN16 Pin" />
-        <Enum name="AIN17" start="0x11" description="ADC AIN17 Pin" />
-        <Enum name="AIN18" start="0x12" description="ADC AIN18 Pin" />
-        <Enum name="AIN19" start="0x13" description="ADC AIN19 Pin" />
-        <Enum name="AIN20" start="0x14" description="ADC AIN20 Pin" />
-        <Enum name="AIN21" start="0x15" description="ADC AIN21 Pin" />
-        <Enum name="AIN22" start="0x16" description="ADC AIN22 Pin" />
-        <Enum name="AIN23" start="0x17" description="ADC AIN23 Pin" />
-        <Enum name="SCALEDCOREVCC" start="0x18" description="1/4 Scaled Core Supply" />
-        <Enum name="SCALEDVBAT" start="0x19" description="1/4 Scaled VBAT Supply" />
-        <Enum name="SCALEDIOVCC" start="0x1a" description="1/4 Scaled I/O Supply" />
-        <Enum name="BANDGAP" start="0x1b" description="Bandgap Voltage" />
-        <Enum name="PTAT" start="0x1c" description="Temperature Sensor" />
-        <Enum name="CTAT" start="0x1d" description="Temperature Sensor" />
-        <Enum name="DAC" start="0x1e" description="DAC Output" />
-        <Enum name="PTC" start="0x1f" description="PTC output (only on ADC0)" />
-      </BitField>
-      <BitField start="7" size="1" name="DIFFMODE" description="Differential Mode" />
-      <BitField start="8" size="5" name="MUXNEG" description="Negative Mux Input Selection">
-        <Enum name="AIN0" start="0x0" description="ADC AIN0 Pin" />
-        <Enum name="AIN1" start="0x1" description="ADC AIN1 Pin" />
-        <Enum name="AIN2" start="0x2" description="ADC AIN2 Pin" />
-        <Enum name="AIN3" start="0x3" description="ADC AIN3 Pin" />
-        <Enum name="AIN4" start="0x4" description="ADC AIN4 Pin" />
-        <Enum name="AIN5" start="0x5" description="ADC AIN5 Pin" />
-        <Enum name="AIN6" start="0x6" description="ADC AIN6 Pin" />
-        <Enum name="AIN7" start="0x7" description="ADC AIN7 Pin" />
-        <Enum name="GND" start="0x18" description="Internal Ground" />
-      </BitField>
-      <BitField start="15" size="1" name="DSEQSTOP" description="Stop DMA Sequencing" />
-    </Register>
-    <Register start="+0x06" size="2" name="ADC_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left-Adjusted Result" />
-      <BitField start="1" size="1" name="FREERUN" description="Free Running Mode" />
-      <BitField start="2" size="1" name="CORREN" description="Digital Correction Logic Enable" />
-      <BitField start="3" size="2" name="RESSEL" description="Conversion Result Resolution">
-        <Enum name="12BIT" start="0x0" description="12-bit result" />
-        <Enum name="16BIT" start="0x1" description="For averaging mode output" />
-        <Enum name="10BIT" start="0x2" description="10-bit result" />
-        <Enum name="8BIT" start="0x3" description="8-bit result" />
-      </BitField>
-      <BitField start="8" size="3" name="WINMODE" description="Window Monitor Mode">
-        <Enum name="DISABLE" start="0x0" description="No window mode (default)" />
-        <Enum name="MODE1" start="0x1" description="RESULT &gt; WINLT" />
-        <Enum name="MODE2" start="0x2" description="RESULT &lt; WINUT" />
-        <Enum name="MODE3" start="0x3" description="WINLT &lt; RESULT &lt; WINUT" />
-        <Enum name="MODE4" start="0x4" description="!(WINLT &lt; RESULT &lt; WINUT)" />
-      </BitField>
-      <BitField start="11" size="1" name="WINSS" description="Window Single Sample" />
-    </Register>
-    <Register start="+0x08" size="1" name="ADC_REFCTRL" access="Read/Write" description="Reference Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="REFSEL" description="Reference Selection">
-        <Enum name="INTREF" start="0x0" description="Internal Bandgap Reference" />
-        <Enum name="INTVCC0" start="0x2" description="1/2 VDDANA" />
-        <Enum name="INTVCC1" start="0x3" description="VDDANA" />
-        <Enum name="AREFA" start="0x4" description="External Reference" />
-        <Enum name="AREFB" start="0x5" description="External Reference" />
-        <Enum name="AREFC" start="0x6" description="External Reference (only on ADC1)" />
-      </BitField>
-      <BitField start="7" size="1" name="REFCOMP" description="Reference Buffer Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="ADC_AVGCTRL" access="Read/Write" description="Average Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLENUM" description="Number of Samples to be Collected">
-        <Enum name="1" start="0x0" description="1 sample" />
-        <Enum name="2" start="0x1" description="2 samples" />
-        <Enum name="4" start="0x2" description="4 samples" />
-        <Enum name="8" start="0x3" description="8 samples" />
-        <Enum name="16" start="0x4" description="16 samples" />
-        <Enum name="32" start="0x5" description="32 samples" />
-        <Enum name="64" start="0x6" description="64 samples" />
-        <Enum name="128" start="0x7" description="128 samples" />
-        <Enum name="256" start="0x8" description="256 samples" />
-        <Enum name="512" start="0x9" description="512 samples" />
-        <Enum name="1024" start="0xa" description="1024 samples" />
-      </BitField>
-      <BitField start="4" size="3" name="ADJRES" description="Adjusting Result / Division Coefficient" />
-    </Register>
-    <Register start="+0x0B" size="1" name="ADC_SAMPCTRL" access="Read/Write" description="Sample Time Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SAMPLEN" description="Sampling Time Length" />
-      <BitField start="7" size="1" name="OFFCOMP" description="Comparator Offset Compensation Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="ADC_WINLT" access="Read/Write" description="Window Monitor Lower Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINLT" description="Window Lower Threshold" />
-    </Register>
-    <Register start="+0x0E" size="2" name="ADC_WINUT" access="Read/Write" description="Window Monitor Upper Threshold" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WINUT" description="Window Upper Threshold" />
-    </Register>
-    <Register start="+0x10" size="2" name="ADC_GAINCORR" access="Read/Write" description="Gain Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="GAINCORR" description="Gain Correction Value" />
-    </Register>
-    <Register start="+0x12" size="2" name="ADC_OFFSETCORR" access="Read/Write" description="Offset Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="OFFSETCORR" description="Offset Correction Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="ADC_SWTRIG" access="Read/Write" description="Software Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLUSH" description="ADC Conversion Flush" />
-      <BitField start="1" size="1" name="START" description="Start ADC Conversion" />
-    </Register>
-    <Register start="+0x2C" size="1" name="ADC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Disable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Disable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Disable" />
-    </Register>
-    <Register start="+0x2D" size="1" name="ADC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Enable" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Enable" />
-    </Register>
-    <Register start="+0x2E" size="1" name="ADC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESRDY" description="Result Ready Interrupt Flag" />
-      <BitField start="1" size="1" name="OVERRUN" description="Overrun Interrupt Flag" />
-      <BitField start="2" size="1" name="WINMON" description="Window Monitor Interrupt Flag" />
-    </Register>
-    <Register start="+0x2F" size="1" name="ADC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADCBUSY" description="ADC Busy Status" />
-      <BitField start="2" size="6" name="WCC" description="Window Comparator Counter" />
-    </Register>
-    <Register start="+0x30" size="4" name="ADC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="SWRST Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="ENABLE Synchronization Busy" />
-      <BitField start="2" size="1" name="INPUTCTRL" description="Input Control Synchronization Busy" />
-      <BitField start="3" size="1" name="CTRLB" description="Control B Synchronization Busy" />
-      <BitField start="4" size="1" name="REFCTRL" description="Reference Control Synchronization Busy" />
-      <BitField start="5" size="1" name="AVGCTRL" description="Average Control Synchronization Busy" />
-      <BitField start="6" size="1" name="SAMPCTRL" description="Sampling Time Control Synchronization Busy" />
-      <BitField start="7" size="1" name="WINLT" description="Window Monitor Lower Threshold Synchronization Busy" />
-      <BitField start="8" size="1" name="WINUT" description="Window Monitor Upper Threshold Synchronization Busy" />
-      <BitField start="9" size="1" name="GAINCORR" description="Gain Correction Synchronization Busy" />
-      <BitField start="10" size="1" name="OFFSETCORR" description="Offset Correction Synchronization Busy" />
-      <BitField start="11" size="1" name="SWTRIG" description="Software Trigger Synchronization Busy" />
-    </Register>
-    <Register start="+0x34" size="4" name="ADC_DSEQDATA" access="WriteOnly" description="DMA Sequencial Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="DMA Sequential Data" />
-    </Register>
-    <Register start="+0x38" size="4" name="ADC_DSEQCTRL" access="Read/Write" description="DMA Sequential Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="AUTOSTART" description="ADC Auto-Start Conversion" />
-    </Register>
-    <Register start="+0x3C" size="4" name="ADC_DSEQSTAT" access="ReadOnly" description="DMA Sequencial Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INPUTCTRL" description="Input Control" />
-      <BitField start="1" size="1" name="CTRLB" description="Control B" />
-      <BitField start="2" size="1" name="REFCTRL" description="Reference Control" />
-      <BitField start="3" size="1" name="AVGCTRL" description="Average Control" />
-      <BitField start="4" size="1" name="SAMPCTRL" description="Sampling Time Control" />
-      <BitField start="5" size="1" name="WINLT" description="Window Monitor Lower Threshold" />
-      <BitField start="6" size="1" name="WINUT" description="Window Monitor Upper Threshold" />
-      <BitField start="7" size="1" name="GAINCORR" description="Gain Correction" />
-      <BitField start="8" size="1" name="OFFSETCORR" description="Offset Correction" />
-      <BitField start="31" size="1" name="BUSY" description="DMA Sequencing Busy" />
-    </Register>
-    <Register start="+0x40" size="2" name="ADC_RESULT" access="ReadOnly" description="Result Conversion Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Result Conversion Value" />
-    </Register>
-    <Register start="+0x44" size="2" name="ADC_RESS" access="ReadOnly" description="Last Sample Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESS" description="Last ADC conversion result" />
-    </Register>
-    <Register start="+0x48" size="2" name="ADC_CALIB" access="Read/Write" description="Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="BIASCOMP" description="Bias Comparator Scaling" />
-      <BitField start="4" size="3" name="BIASR2R" description="Bias R2R Ampli scaling" />
-      <BitField start="8" size="3" name="BIASREFBUF" description="Bias  Reference Buffer Scaling" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="AES" start="0x42002400" description="Advanced Encryption Standard">
-    <Register start="+0x00" size="4" name="AES_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="AESMODE" description="AES Modes of operation">
-        <Enum name="ECB" start="0x0" description="Electronic code book mode" />
-        <Enum name="CBC" start="0x1" description="Cipher block chaining mode" />
-        <Enum name="OFB" start="0x2" description="Output feedback mode" />
-        <Enum name="CFB" start="0x3" description="Cipher feedback mode" />
-        <Enum name="COUNTER" start="0x4" description="Counter mode" />
-        <Enum name="CCM" start="0x5" description="CCM mode" />
-        <Enum name="GCM" start="0x6" description="Galois counter mode" />
-      </BitField>
-      <BitField start="5" size="3" name="CFBS" description="Cipher Feedback Block Size">
-        <Enum name="128BIT" start="0x0" description="128-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="64BIT" start="0x1" description="64-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="32BIT" start="0x2" description="32-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="16BIT" start="0x3" description="16-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-        <Enum name="8BIT" start="0x4" description="8-bit Input data block for Encryption/Decryption in Cipher Feedback mode" />
-      </BitField>
-      <BitField start="8" size="2" name="KEYSIZE" description="Encryption Key Size">
-        <Enum name="128BIT" start="0x0" description="128-bit Key for Encryption / Decryption" />
-        <Enum name="192BIT" start="0x1" description="192-bit Key for Encryption / Decryption" />
-        <Enum name="256BIT" start="0x2" description="256-bit Key for Encryption / Decryption" />
-      </BitField>
-      <BitField start="10" size="1" name="CIPHER" description="Cipher Mode">
-        <Enum name="DEC" start="0x0" description="Decryption" />
-        <Enum name="ENC" start="0x1" description="Encryption" />
-      </BitField>
-      <BitField start="11" size="1" name="STARTMODE" description="Start Mode Select">
-        <Enum name="MANUAL" start="0x0" description="Start Encryption / Decryption in Manual mode" />
-        <Enum name="AUTO" start="0x1" description="Start Encryption / Decryption in Auto mode" />
-      </BitField>
-      <BitField start="12" size="1" name="LOD" description="Last Output Data Mode">
-        <Enum name="NONE" start="0x0" description="No effect" />
-        <Enum name="LAST" start="0x1" description="Start encryption in Last Output Data mode" />
-      </BitField>
-      <BitField start="13" size="1" name="KEYGEN" description="Last Key Generation">
-        <Enum name="NONE" start="0x0" description="No effect" />
-        <Enum name="LAST" start="0x1" description="Start Computation of the last NK words of the expanded key" />
-      </BitField>
-      <BitField start="14" size="1" name="XORKEY" description="XOR Key Operation">
-        <Enum name="NONE" start="0x0" description="No effect" />
-        <Enum name="XOR" start="0x1" description="The user keyword gets XORed with the previous keyword register content." />
-      </BitField>
-      <BitField start="16" size="4" name="CTYPE" description="Counter Measure Type" />
-    </Register>
-    <Register start="+0x04" size="1" name="AES_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start Encryption/Decryption" />
-      <BitField start="1" size="1" name="NEWMSG" description="New message" />
-      <BitField start="2" size="1" name="EOM" description="End of message" />
-      <BitField start="3" size="1" name="GFMUL" description="GF Multiplication" />
-    </Register>
-    <Register start="+0x05" size="1" name="AES_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENCCMP" description="Encryption Complete Interrupt Enable" />
-      <BitField start="1" size="1" name="GFMCMP" description="GF Multiplication Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="AES_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENCCMP" description="Encryption Complete Interrupt Enable" />
-      <BitField start="1" size="1" name="GFMCMP" description="GF Multiplication Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x07" size="1" name="AES_INTFLAG" access="Read/Write" description="Interrupt Flag Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENCCMP" description="Encryption Complete" />
-      <BitField start="1" size="1" name="GFMCMP" description="GF Multiplication Complete" />
-    </Register>
-    <Register start="+0x08" size="1" name="AES_DATABUFPTR" access="Read/Write" description="Data buffer pointer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="INDATAPTR" description="Input Data Pointer" />
-    </Register>
-    <Register start="+0x09" size="1" name="AES_DBGCTRL" access="Read/Write" description="Debug control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x0C+0" size="4" name="AES_KEYWORD0" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+4" size="4" name="AES_KEYWORD1" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+8" size="4" name="AES_KEYWORD2" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+12" size="4" name="AES_KEYWORD3" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+16" size="4" name="AES_KEYWORD4" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+20" size="4" name="AES_KEYWORD5" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+24" size="4" name="AES_KEYWORD6" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x0C+28" size="4" name="AES_KEYWORD7" access="WriteOnly" description="Keyword n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x38" size="4" name="AES_INDATA" access="Read/Write" description="Indata" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+0" size="4" name="AES_INTVECTV0" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+4" size="4" name="AES_INTVECTV1" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+8" size="4" name="AES_INTVECTV2" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x3C+12" size="4" name="AES_INTVECTV3" access="WriteOnly" description="Initialisation Vector n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+0" size="4" name="AES_HASHKEY0" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+4" size="4" name="AES_HASHKEY1" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+8" size="4" name="AES_HASHKEY2" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x5C+12" size="4" name="AES_HASHKEY3" access="Read/Write" description="Hash key n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+0" size="4" name="AES_GHASH0" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+4" size="4" name="AES_GHASH1" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+8" size="4" name="AES_GHASH2" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x6C+12" size="4" name="AES_GHASH3" access="Read/Write" description="Galois Hash n" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x80" size="4" name="AES_CIPLEN" access="Read/Write" description="Cipher Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x84" size="4" name="AES_RANDSEED" access="Read/Write" description="Random Seed" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="CCL" start="0x42003800" description="Configurable Custom Logic">
-    <Register start="+0x0" size="1" name="CCL_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x4+0" size="1" name="CCL_SEQCTRL0" access="Read/Write" description="SEQ Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SEQSEL" description="Sequential Selection">
-        <Enum name="DISABLE" start="0x0" description="Sequential logic is disabled" />
-        <Enum name="DFF" start="0x1" description="D flip flop" />
-        <Enum name="JK" start="0x2" description="JK flip flop" />
-        <Enum name="LATCH" start="0x3" description="D latch" />
-        <Enum name="RS" start="0x4" description="RS latch" />
-      </BitField>
-    </Register>
-    <Register start="+0x4+1" size="1" name="CCL_SEQCTRL1" access="Read/Write" description="SEQ Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SEQSEL" description="Sequential Selection">
-        <Enum name="DISABLE" start="0x0" description="Sequential logic is disabled" />
-        <Enum name="DFF" start="0x1" description="D flip flop" />
-        <Enum name="JK" start="0x2" description="JK flip flop" />
-        <Enum name="LATCH" start="0x3" description="D latch" />
-        <Enum name="RS" start="0x4" description="RS latch" />
-      </BitField>
-    </Register>
-    <Register start="+0x8+0" size="4" name="CCL_LUTCTRL0" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-    <Register start="+0x8+4" size="4" name="CCL_LUTCTRL1" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-    <Register start="+0x8+8" size="4" name="CCL_LUTCTRL2" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-    <Register start="+0x8+12" size="4" name="CCL_LUTCTRL3" access="Read/Write" description="LUT Control x" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="LUT Enable" />
-      <BitField start="4" size="2" name="FILTSEL" description="Filter Selection">
-        <Enum name="DISABLE" start="0x0" description="Filter disabled" />
-        <Enum name="SYNCH" start="0x1" description="Synchronizer enabled" />
-        <Enum name="FILTER" start="0x2" description="Filter enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="EDGESEL" description="Edge Selection" />
-      <BitField start="8" size="4" name="INSEL0" description="Input Selection 0">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="12" size="4" name="INSEL1" description="Input Selection 1">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="16" size="4" name="INSEL2" description="Input Selection 2">
-        <Enum name="MASK" start="0x0" description="Masked input" />
-        <Enum name="FEEDBACK" start="0x1" description="Feedback input source" />
-        <Enum name="LINK" start="0x2" description="Linked LUT input source" />
-        <Enum name="EVENT" start="0x3" description="Event input source" />
-        <Enum name="IO" start="0x4" description="I/O pin input source" />
-        <Enum name="AC" start="0x5" description="AC input source" />
-        <Enum name="TC" start="0x6" description="TC input source" />
-        <Enum name="ALTTC" start="0x7" description="Alternate TC input source" />
-        <Enum name="TCC" start="0x8" description="TCC input source" />
-        <Enum name="SERCOM" start="0x9" description="SERCOM input source" />
-      </BitField>
-      <BitField start="20" size="1" name="INVEI" description="Inverted Event Input Enable" />
-      <BitField start="21" size="1" name="LUTEI" description="LUT Event Input Enable" />
-      <BitField start="22" size="1" name="LUTEO" description="LUT Event Output Enable" />
-      <BitField start="24" size="8" name="TRUTH" description="Truth Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CMCC" start="0x41006000" description="Cortex M Cache Controller">
-    <Register start="+0x00" size="4" name="CMCC_TYPE" access="ReadOnly" description="Cache Type Register" reset_value="0x000012D2" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="GCLK" description="dynamic Clock Gating supported" />
-      <BitField start="4" size="1" name="RRP" description="Round Robin Policy supported" />
-      <BitField start="5" size="2" name="WAYNUM" description="Number of Way">
-        <Enum name="DMAPPED" start="0x0" description="Direct Mapped Cache" />
-        <Enum name="ARCH2WAY" start="0x1" description="2-WAY set associative" />
-        <Enum name="ARCH4WAY" start="0x2" description="4-WAY set associative" />
-      </BitField>
-      <BitField start="7" size="1" name="LCKDOWN" description="Lock Down supported" />
-      <BitField start="8" size="3" name="CSIZE" description="Cache Size">
-        <Enum name="CSIZE_1KB" start="0x0" description="Cache Size is 1 KB" />
-        <Enum name="CSIZE_2KB" start="0x1" description="Cache Size is 2 KB" />
-        <Enum name="CSIZE_4KB" start="0x2" description="Cache Size is 4 KB" />
-        <Enum name="CSIZE_8KB" start="0x3" description="Cache Size is 8 KB" />
-        <Enum name="CSIZE_16KB" start="0x4" description="Cache Size is 16 KB" />
-        <Enum name="CSIZE_32KB" start="0x5" description="Cache Size is 32 KB" />
-        <Enum name="CSIZE_64KB" start="0x6" description="Cache Size is 64 KB" />
-      </BitField>
-      <BitField start="11" size="3" name="CLSIZE" description="Cache Line Size">
-        <Enum name="CLSIZE_4B" start="0x0" description="Cache Line Size is 4 bytes" />
-        <Enum name="CLSIZE_8B" start="0x1" description="Cache Line Size is 8 bytes" />
-        <Enum name="CLSIZE_16B" start="0x2" description="Cache Line Size is 16 bytes" />
-        <Enum name="CLSIZE_32B" start="0x3" description="Cache Line Size is 32 bytes" />
-        <Enum name="CLSIZE_64B" start="0x4" description="Cache Line Size is 64 bytes" />
-        <Enum name="CLSIZE_128B" start="0x5" description="Cache Line Size is 128 bytes" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="CMCC_CFG" access="Read/Write" description="Cache Configuration Register" reset_value="0x00000020" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ICDIS" description="Instruction Cache Disable" />
-      <BitField start="2" size="1" name="DCDIS" description="Data Cache Disable" />
-      <BitField start="4" size="3" name="CSIZESW" description="Cache size configured by software">
-        <Enum name="CONF_CSIZE_1KB" start="0x0" description="the Cache Size is configured to 1KB" />
-        <Enum name="CONF_CSIZE_2KB" start="0x1" description="the Cache Size is configured to 2KB" />
-        <Enum name="CONF_CSIZE_4KB" start="0x2" description="the Cache Size is configured to 4KB" />
-        <Enum name="CONF_CSIZE_8KB" start="0x3" description="the Cache Size is configured to 8KB" />
-        <Enum name="CONF_CSIZE_16KB" start="0x4" description="the Cache Size is configured to 16KB" />
-        <Enum name="CONF_CSIZE_32KB" start="0x5" description="the Cache Size is configured to 32KB" />
-        <Enum name="CONF_CSIZE_64KB" start="0x6" description="the Cache Size is configured to 64KB" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="CMCC_CTRL" access="WriteOnly" description="Cache Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="Cache Controller Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="CMCC_SR" access="ReadOnly" description="Cache Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTS" description="Cache Controller Status" />
-    </Register>
-    <Register start="+0x10" size="4" name="CMCC_LCKWAY" access="Read/Write" description="Cache Lock per Way Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="LCKWAY" description="Lockdown way Register" />
-    </Register>
-    <Register start="+0x20" size="4" name="CMCC_MAINT0" access="WriteOnly" description="Cache Maintenance Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVALL" description="Cache Controller invalidate All" />
-    </Register>
-    <Register start="+0x24" size="4" name="CMCC_MAINT1" access="WriteOnly" description="Cache Maintenance Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="8" name="INDEX" description="Invalidate Index" />
-      <BitField start="28" size="4" name="WAY" description="Invalidate Way">
-        <Enum name="WAY0" start="0x0" description="Way 0 is selection for index invalidation" />
-        <Enum name="WAY1" start="0x1" description="Way 1 is selection for index invalidation" />
-        <Enum name="WAY2" start="0x2" description="Way 2 is selection for index invalidation" />
-        <Enum name="WAY3" start="0x3" description="Way 3 is selection for index invalidation" />
-      </BitField>
-    </Register>
-    <Register start="+0x28" size="4" name="CMCC_MCFG" access="Read/Write" description="Cache Monitor Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MODE" description="Cache Controller Monitor Counter Mode">
-        <Enum name="CYCLE_COUNT" start="0x0" description="cycle counter" />
-        <Enum name="IHIT_COUNT" start="0x1" description="instruction hit counter" />
-        <Enum name="DHIT_COUNT" start="0x2" description="data hit counter" />
-      </BitField>
-    </Register>
-    <Register start="+0x2C" size="4" name="CMCC_MEN" access="Read/Write" description="Cache Monitor Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MENABLE" description="Cache Controller Monitor Enable" />
-    </Register>
-    <Register start="+0x30" size="4" name="CMCC_MCTRL" access="WriteOnly" description="Cache Monitor Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Cache Controller Software Reset" />
-    </Register>
-    <Register start="+0x34" size="4" name="CMCC_MSR" access="ReadOnly" description="Cache Monitor Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="EVENT_CNT" description="Monitor Event Counter" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x43002400" description="Digital-to-Analog Converter">
-    <Register start="+0x00" size="1" name="DAC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable DAC Controller" />
-    </Register>
-    <Register start="+0x01" size="1" name="DAC_CTRLB" access="Read/Write" description="Control B" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIFF" description="Differential mode enable" />
-      <BitField start="1" size="2" name="REFSEL" description="Reference Selection for DAC0/1">
-        <Enum name="VREFPU" start="0x0" description="External reference unbuffered" />
-        <Enum name="VDDANA" start="0x1" description="Analog supply" />
-        <Enum name="VREFPB" start="0x2" description="External reference buffered" />
-        <Enum name="INTREF" start="0x3" description="Internal bandgap reference" />
-      </BitField>
-    </Register>
-    <Register start="+0x02" size="1" name="DAC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STARTEI0" description="Start Conversion Event Input DAC 0" />
-      <BitField start="1" size="1" name="STARTEI1" description="Start Conversion Event Input DAC 1" />
-      <BitField start="2" size="1" name="EMPTYEO0" description="Data Buffer Empty Event Output DAC 0" />
-      <BitField start="3" size="1" name="EMPTYEO1" description="Data Buffer Empty Event Output DAC 1" />
-      <BitField start="4" size="1" name="INVEI0" description="Enable Invertion of DAC 0 input event" />
-      <BitField start="5" size="1" name="INVEI1" description="Enable Invertion of DAC 1 input event" />
-      <BitField start="6" size="1" name="RESRDYEO0" description="Result Ready Event Output 0" />
-      <BitField start="7" size="1" name="RESRDYEO1" description="Result Ready Event Output 1" />
-    </Register>
-    <Register start="+0x04" size="1" name="DAC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN0" description="Underrun 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="UNDERRUN1" description="Underrun 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="EMPTY0" description="Data Buffer 0 Empty Interrupt Enable" />
-      <BitField start="3" size="1" name="EMPTY1" description="Data Buffer 1 Empty Interrupt Enable" />
-      <BitField start="4" size="1" name="RESRDY0" description="Result 0 Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="RESRDY1" description="Result 1 Ready Interrupt Enable" />
-      <BitField start="6" size="1" name="OVERRUN0" description="Overrun 0 Interrupt Enable" />
-      <BitField start="7" size="1" name="OVERRUN1" description="Overrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="DAC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN0" description="Underrun 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="UNDERRUN1" description="Underrun 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="EMPTY0" description="Data Buffer 0 Empty Interrupt Enable" />
-      <BitField start="3" size="1" name="EMPTY1" description="Data Buffer 1 Empty Interrupt Enable" />
-      <BitField start="4" size="1" name="RESRDY0" description="Result 0 Ready Interrupt Enable" />
-      <BitField start="5" size="1" name="RESRDY1" description="Result 1 Ready Interrupt Enable" />
-      <BitField start="6" size="1" name="OVERRUN0" description="Overrun 0 Interrupt Enable" />
-      <BitField start="7" size="1" name="OVERRUN1" description="Overrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="DAC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNDERRUN0" description="Result 0 Underrun" />
-      <BitField start="1" size="1" name="UNDERRUN1" description="Result 1 Underrun" />
-      <BitField start="2" size="1" name="EMPTY0" description="Data Buffer 0 Empty" />
-      <BitField start="3" size="1" name="EMPTY1" description="Data Buffer 1 Empty" />
-      <BitField start="4" size="1" name="RESRDY0" description="Result 0 Ready" />
-      <BitField start="5" size="1" name="RESRDY1" description="Result 1 Ready" />
-      <BitField start="6" size="1" name="OVERRUN0" description="Result 0 Overrun" />
-      <BitField start="7" size="1" name="OVERRUN1" description="Result 1 Overrun" />
-    </Register>
-    <Register start="+0x07" size="1" name="DAC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY0" description="DAC 0 Startup Ready" />
-      <BitField start="1" size="1" name="READY1" description="DAC 1 Startup Ready" />
-      <BitField start="2" size="1" name="EOC0" description="DAC 0 End of Conversion" />
-      <BitField start="3" size="1" name="EOC1" description="DAC 1 End of Conversion" />
-    </Register>
-    <Register start="+0x08" size="4" name="DAC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="DAC Enable Status" />
-      <BitField start="2" size="1" name="DATA0" description="Data DAC 0" />
-      <BitField start="3" size="1" name="DATA1" description="Data DAC 1" />
-      <BitField start="4" size="1" name="DATABUF0" description="Data Buffer DAC 0" />
-      <BitField start="5" size="1" name="DATABUF1" description="Data Buffer DAC 1" />
-    </Register>
-    <Register start="+0x0C+0" size="2" name="DAC_DACCTRL0" access="Read/Write" description="DAC n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left Adjusted Data" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable DAC0" />
-      <BitField start="2" size="2" name="CCTRL" description="Current Control">
-        <Enum name="CC100K" start="0x0" description="GCLK_DAC &lt;= 1.2MHz (100kSPS)" />
-        <Enum name="CC1M" start="0x1" description="1.2MHz &lt; GCLK_DAC  &lt;= 6MHz (500kSPS)" />
-        <Enum name="CC12M" start="0x2" description="6MHz &lt; GCLK_DAC &lt;= 12MHz (1MSPS)" />
-      </BitField>
-      <BitField start="5" size="1" name="FEXT" description="Standalone Filter" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="DITHER" description="Dithering Mode" />
-      <BitField start="8" size="4" name="REFRESH" description="Refresh period" />
-      <BitField start="13" size="3" name="OSR" description="Sampling Rate" />
-    </Register>
-    <Register start="+0x0C+2" size="2" name="DAC_DACCTRL1" access="Read/Write" description="DAC n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEFTADJ" description="Left Adjusted Data" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable DAC0" />
-      <BitField start="2" size="2" name="CCTRL" description="Current Control">
-        <Enum name="CC100K" start="0x0" description="GCLK_DAC &lt;= 1.2MHz (100kSPS)" />
-        <Enum name="CC1M" start="0x1" description="1.2MHz &lt; GCLK_DAC  &lt;= 6MHz (500kSPS)" />
-        <Enum name="CC12M" start="0x2" description="6MHz &lt; GCLK_DAC &lt;= 12MHz (1MSPS)" />
-      </BitField>
-      <BitField start="5" size="1" name="FEXT" description="Standalone Filter" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="DITHER" description="Dithering Mode" />
-      <BitField start="8" size="4" name="REFRESH" description="Refresh period" />
-      <BitField start="13" size="3" name="OSR" description="Sampling Rate" />
-    </Register>
-    <Register start="+0x10+0" size="2" name="DAC_DATA0" access="WriteOnly" description="DAC n Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="DAC0 Data" />
-    </Register>
-    <Register start="+0x10+2" size="2" name="DAC_DATA1" access="WriteOnly" description="DAC n Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="DAC0 Data" />
-    </Register>
-    <Register start="+0x14+0" size="2" name="DAC_DATABUF0" access="WriteOnly" description="DAC n Data Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATABUF" description="DAC0 Data Buffer" />
-    </Register>
-    <Register start="+0x14+2" size="2" name="DAC_DATABUF1" access="WriteOnly" description="DAC n Data Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATABUF" description="DAC0 Data Buffer" />
-    </Register>
-    <Register start="+0x18" size="1" name="DAC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="DAC_RESULT0" access="ReadOnly" description="Filter Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Filter Result" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="DAC_RESULT1" access="ReadOnly" description="Filter Result" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RESULT" description="Filter Result" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DMAC" start="0x4100A000" description="Direct Memory Access Controller">
-    <Register start="+0x00" size="2" name="DMAC_CTRL" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="DMAENABLE" description="DMA Enable" />
-      <BitField start="8" size="1" name="LVLEN0" description="Priority Level 0 Enable" />
-      <BitField start="9" size="1" name="LVLEN1" description="Priority Level 1 Enable" />
-      <BitField start="10" size="1" name="LVLEN2" description="Priority Level 2 Enable" />
-      <BitField start="11" size="1" name="LVLEN3" description="Priority Level 3 Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="DMAC_CRCCTRL" access="Read/Write" description="CRC Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRCBEATSIZE" description="CRC Beat Size">
-        <Enum name="BYTE" start="0x0" description="8-bit bus transfer" />
-        <Enum name="HWORD" start="0x1" description="16-bit bus transfer" />
-        <Enum name="WORD" start="0x2" description="32-bit bus transfer" />
-      </BitField>
-      <BitField start="2" size="2" name="CRCPOLY" description="CRC Polynomial Type">
-        <Enum name="CRC16" start="0x0" description="CRC-16 (CRC-CCITT)" />
-        <Enum name="CRC32" start="0x1" description="CRC32 (IEEE 802.3)" />
-      </BitField>
-      <BitField start="8" size="6" name="CRCSRC" description="CRC Input Source">
-        <Enum name="DISABLE" start="0x0" description="CRC Disabled" />
-        <Enum name="IO" start="0x1" description="I/O interface" />
-      </BitField>
-      <BitField start="14" size="2" name="CRCMODE" description="CRC Operating Mode">
-        <Enum name="DEFAULT" start="0x0" description="Default operating mode" />
-        <Enum name="CRCMON" start="0x2" description="Memory CRC monitor operating mode" />
-        <Enum name="CRCGEN" start="0x3" description="Memory CRC generation operating mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="DMAC_CRCDATAIN" access="Read/Write" description="CRC Data Input" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCDATAIN" description="CRC Data Input" />
-    </Register>
-    <Register start="+0x08" size="4" name="DMAC_CRCCHKSUM" access="Read/Write" description="CRC Checksum" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRCCHKSUM" description="CRC Checksum" />
-    </Register>
-    <Register start="+0x0C" size="1" name="DMAC_CRCSTATUS" access="Read/Write" description="CRC Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCBUSY" description="CRC Module Busy" />
-      <BitField start="1" size="1" name="CRCZERO" description="CRC Zero" />
-      <BitField start="2" size="1" name="CRCERR" description="CRC Error" />
-    </Register>
-    <Register start="+0x0D" size="1" name="DMAC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run" />
-    </Register>
-    <Register start="+0x10" size="4" name="DMAC_SWTRIGCTRL" access="Read/Write" description="Software Trigger Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWTRIG0" description="Channel 0 Software Trigger" />
-      <BitField start="1" size="1" name="SWTRIG1" description="Channel 1 Software Trigger" />
-      <BitField start="2" size="1" name="SWTRIG2" description="Channel 2 Software Trigger" />
-      <BitField start="3" size="1" name="SWTRIG3" description="Channel 3 Software Trigger" />
-      <BitField start="4" size="1" name="SWTRIG4" description="Channel 4 Software Trigger" />
-      <BitField start="5" size="1" name="SWTRIG5" description="Channel 5 Software Trigger" />
-      <BitField start="6" size="1" name="SWTRIG6" description="Channel 6 Software Trigger" />
-      <BitField start="7" size="1" name="SWTRIG7" description="Channel 7 Software Trigger" />
-      <BitField start="8" size="1" name="SWTRIG8" description="Channel 8 Software Trigger" />
-      <BitField start="9" size="1" name="SWTRIG9" description="Channel 9 Software Trigger" />
-      <BitField start="10" size="1" name="SWTRIG10" description="Channel 10 Software Trigger" />
-      <BitField start="11" size="1" name="SWTRIG11" description="Channel 11 Software Trigger" />
-      <BitField start="12" size="1" name="SWTRIG12" description="Channel 12 Software Trigger" />
-      <BitField start="13" size="1" name="SWTRIG13" description="Channel 13 Software Trigger" />
-      <BitField start="14" size="1" name="SWTRIG14" description="Channel 14 Software Trigger" />
-      <BitField start="15" size="1" name="SWTRIG15" description="Channel 15 Software Trigger" />
-      <BitField start="16" size="1" name="SWTRIG16" description="Channel 16 Software Trigger" />
-      <BitField start="17" size="1" name="SWTRIG17" description="Channel 17 Software Trigger" />
-      <BitField start="18" size="1" name="SWTRIG18" description="Channel 18 Software Trigger" />
-      <BitField start="19" size="1" name="SWTRIG19" description="Channel 19 Software Trigger" />
-      <BitField start="20" size="1" name="SWTRIG20" description="Channel 20 Software Trigger" />
-      <BitField start="21" size="1" name="SWTRIG21" description="Channel 21 Software Trigger" />
-      <BitField start="22" size="1" name="SWTRIG22" description="Channel 22 Software Trigger" />
-      <BitField start="23" size="1" name="SWTRIG23" description="Channel 23 Software Trigger" />
-      <BitField start="24" size="1" name="SWTRIG24" description="Channel 24 Software Trigger" />
-      <BitField start="25" size="1" name="SWTRIG25" description="Channel 25 Software Trigger" />
-      <BitField start="26" size="1" name="SWTRIG26" description="Channel 26 Software Trigger" />
-      <BitField start="27" size="1" name="SWTRIG27" description="Channel 27 Software Trigger" />
-      <BitField start="28" size="1" name="SWTRIG28" description="Channel 28 Software Trigger" />
-      <BitField start="29" size="1" name="SWTRIG29" description="Channel 29 Software Trigger" />
-      <BitField start="30" size="1" name="SWTRIG30" description="Channel 30 Software Trigger" />
-      <BitField start="31" size="1" name="SWTRIG31" description="Channel 31 Software Trigger" />
-    </Register>
-    <Register start="+0x14" size="4" name="DMAC_PRICTRL0" access="Read/Write" description="Priority Control 0" reset_value="0x40404040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="LVLPRI0" description="Level 0 Channel Priority Number" />
-      <BitField start="5" size="2" name="QOS0" description="Level 0 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="7" size="1" name="RRLVLEN0" description="Level 0 Round-Robin Scheduling Enable" />
-      <BitField start="8" size="5" name="LVLPRI1" description="Level 1 Channel Priority Number" />
-      <BitField start="13" size="2" name="QOS1" description="Level 1 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="15" size="1" name="RRLVLEN1" description="Level 1 Round-Robin Scheduling Enable" />
-      <BitField start="16" size="5" name="LVLPRI2" description="Level 2 Channel Priority Number" />
-      <BitField start="21" size="2" name="QOS2" description="Level 2 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="23" size="1" name="RRLVLEN2" description="Level 2 Round-Robin Scheduling Enable" />
-      <BitField start="24" size="5" name="LVLPRI3" description="Level 3 Channel Priority Number" />
-      <BitField start="29" size="2" name="QOS3" description="Level 3 Quality of Service">
-        <Enum name="REGULAR" start="0x0" description="Regular delivery" />
-        <Enum name="SHORTAGE" start="0x1" description="Bandwidth shortage" />
-        <Enum name="SENSITIVE" start="0x2" description="Latency sensitive" />
-        <Enum name="CRITICAL" start="0x3" description="Latency critical" />
-      </BitField>
-      <BitField start="31" size="1" name="RRLVLEN3" description="Level 3 Round-Robin Scheduling Enable" />
-    </Register>
-    <Register start="+0x20" size="2" name="DMAC_INTPEND" access="Read/Write" description="Interrupt Pending" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ID" description="Channel ID" />
-      <BitField start="8" size="1" name="TERR" description="Transfer Error" />
-      <BitField start="9" size="1" name="TCMPL" description="Transfer Complete" />
-      <BitField start="10" size="1" name="SUSP" description="Channel Suspend" />
-      <BitField start="12" size="1" name="CRCERR" description="CRC Error" />
-      <BitField start="13" size="1" name="FERR" description="Fetch Error" />
-      <BitField start="14" size="1" name="BUSY" description="Busy" />
-      <BitField start="15" size="1" name="PEND" description="Pending" />
-    </Register>
-    <Register start="+0x24" size="4" name="DMAC_INTSTATUS" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHINT0" description="Channel 0 Pending Interrupt" />
-      <BitField start="1" size="1" name="CHINT1" description="Channel 1 Pending Interrupt" />
-      <BitField start="2" size="1" name="CHINT2" description="Channel 2 Pending Interrupt" />
-      <BitField start="3" size="1" name="CHINT3" description="Channel 3 Pending Interrupt" />
-      <BitField start="4" size="1" name="CHINT4" description="Channel 4 Pending Interrupt" />
-      <BitField start="5" size="1" name="CHINT5" description="Channel 5 Pending Interrupt" />
-      <BitField start="6" size="1" name="CHINT6" description="Channel 6 Pending Interrupt" />
-      <BitField start="7" size="1" name="CHINT7" description="Channel 7 Pending Interrupt" />
-      <BitField start="8" size="1" name="CHINT8" description="Channel 8 Pending Interrupt" />
-      <BitField start="9" size="1" name="CHINT9" description="Channel 9 Pending Interrupt" />
-      <BitField start="10" size="1" name="CHINT10" description="Channel 10 Pending Interrupt" />
-      <BitField start="11" size="1" name="CHINT11" description="Channel 11 Pending Interrupt" />
-      <BitField start="12" size="1" name="CHINT12" description="Channel 12 Pending Interrupt" />
-      <BitField start="13" size="1" name="CHINT13" description="Channel 13 Pending Interrupt" />
-      <BitField start="14" size="1" name="CHINT14" description="Channel 14 Pending Interrupt" />
-      <BitField start="15" size="1" name="CHINT15" description="Channel 15 Pending Interrupt" />
-      <BitField start="16" size="1" name="CHINT16" description="Channel 16 Pending Interrupt" />
-      <BitField start="17" size="1" name="CHINT17" description="Channel 17 Pending Interrupt" />
-      <BitField start="18" size="1" name="CHINT18" description="Channel 18 Pending Interrupt" />
-      <BitField start="19" size="1" name="CHINT19" description="Channel 19 Pending Interrupt" />
-      <BitField start="20" size="1" name="CHINT20" description="Channel 20 Pending Interrupt" />
-      <BitField start="21" size="1" name="CHINT21" description="Channel 21 Pending Interrupt" />
-      <BitField start="22" size="1" name="CHINT22" description="Channel 22 Pending Interrupt" />
-      <BitField start="23" size="1" name="CHINT23" description="Channel 23 Pending Interrupt" />
-      <BitField start="24" size="1" name="CHINT24" description="Channel 24 Pending Interrupt" />
-      <BitField start="25" size="1" name="CHINT25" description="Channel 25 Pending Interrupt" />
-      <BitField start="26" size="1" name="CHINT26" description="Channel 26 Pending Interrupt" />
-      <BitField start="27" size="1" name="CHINT27" description="Channel 27 Pending Interrupt" />
-      <BitField start="28" size="1" name="CHINT28" description="Channel 28 Pending Interrupt" />
-      <BitField start="29" size="1" name="CHINT29" description="Channel 29 Pending Interrupt" />
-      <BitField start="30" size="1" name="CHINT30" description="Channel 30 Pending Interrupt" />
-      <BitField start="31" size="1" name="CHINT31" description="Channel 31 Pending Interrupt" />
-    </Register>
-    <Register start="+0x28" size="4" name="DMAC_BUSYCH" access="ReadOnly" description="Busy Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSYCH0" description="Busy Channel 0" />
-      <BitField start="1" size="1" name="BUSYCH1" description="Busy Channel 1" />
-      <BitField start="2" size="1" name="BUSYCH2" description="Busy Channel 2" />
-      <BitField start="3" size="1" name="BUSYCH3" description="Busy Channel 3" />
-      <BitField start="4" size="1" name="BUSYCH4" description="Busy Channel 4" />
-      <BitField start="5" size="1" name="BUSYCH5" description="Busy Channel 5" />
-      <BitField start="6" size="1" name="BUSYCH6" description="Busy Channel 6" />
-      <BitField start="7" size="1" name="BUSYCH7" description="Busy Channel 7" />
-      <BitField start="8" size="1" name="BUSYCH8" description="Busy Channel 8" />
-      <BitField start="9" size="1" name="BUSYCH9" description="Busy Channel 9" />
-      <BitField start="10" size="1" name="BUSYCH10" description="Busy Channel 10" />
-      <BitField start="11" size="1" name="BUSYCH11" description="Busy Channel 11" />
-      <BitField start="12" size="1" name="BUSYCH12" description="Busy Channel 12" />
-      <BitField start="13" size="1" name="BUSYCH13" description="Busy Channel 13" />
-      <BitField start="14" size="1" name="BUSYCH14" description="Busy Channel 14" />
-      <BitField start="15" size="1" name="BUSYCH15" description="Busy Channel 15" />
-      <BitField start="16" size="1" name="BUSYCH16" description="Busy Channel 16" />
-      <BitField start="17" size="1" name="BUSYCH17" description="Busy Channel 17" />
-      <BitField start="18" size="1" name="BUSYCH18" description="Busy Channel 18" />
-      <BitField start="19" size="1" name="BUSYCH19" description="Busy Channel 19" />
-      <BitField start="20" size="1" name="BUSYCH20" description="Busy Channel 20" />
-      <BitField start="21" size="1" name="BUSYCH21" description="Busy Channel 21" />
-      <BitField start="22" size="1" name="BUSYCH22" description="Busy Channel 22" />
-      <BitField start="23" size="1" name="BUSYCH23" description="Busy Channel 23" />
-      <BitField start="24" size="1" name="BUSYCH24" description="Busy Channel 24" />
-      <BitField start="25" size="1" name="BUSYCH25" description="Busy Channel 25" />
-      <BitField start="26" size="1" name="BUSYCH26" description="Busy Channel 26" />
-      <BitField start="27" size="1" name="BUSYCH27" description="Busy Channel 27" />
-      <BitField start="28" size="1" name="BUSYCH28" description="Busy Channel 28" />
-      <BitField start="29" size="1" name="BUSYCH29" description="Busy Channel 29" />
-      <BitField start="30" size="1" name="BUSYCH30" description="Busy Channel 30" />
-      <BitField start="31" size="1" name="BUSYCH31" description="Busy Channel 31" />
-    </Register>
-    <Register start="+0x2C" size="4" name="DMAC_PENDCH" access="ReadOnly" description="Pending Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PENDCH0" description="Pending Channel 0" />
-      <BitField start="1" size="1" name="PENDCH1" description="Pending Channel 1" />
-      <BitField start="2" size="1" name="PENDCH2" description="Pending Channel 2" />
-      <BitField start="3" size="1" name="PENDCH3" description="Pending Channel 3" />
-      <BitField start="4" size="1" name="PENDCH4" description="Pending Channel 4" />
-      <BitField start="5" size="1" name="PENDCH5" description="Pending Channel 5" />
-      <BitField start="6" size="1" name="PENDCH6" description="Pending Channel 6" />
-      <BitField start="7" size="1" name="PENDCH7" description="Pending Channel 7" />
-      <BitField start="8" size="1" name="PENDCH8" description="Pending Channel 8" />
-      <BitField start="9" size="1" name="PENDCH9" description="Pending Channel 9" />
-      <BitField start="10" size="1" name="PENDCH10" description="Pending Channel 10" />
-      <BitField start="11" size="1" name="PENDCH11" description="Pending Channel 11" />
-      <BitField start="12" size="1" name="PENDCH12" description="Pending Channel 12" />
-      <BitField start="13" size="1" name="PENDCH13" description="Pending Channel 13" />
-      <BitField start="14" size="1" name="PENDCH14" description="Pending Channel 14" />
-      <BitField start="15" size="1" name="PENDCH15" description="Pending Channel 15" />
-      <BitField start="16" size="1" name="PENDCH16" description="Pending Channel 16" />
-      <BitField start="17" size="1" name="PENDCH17" description="Pending Channel 17" />
-      <BitField start="18" size="1" name="PENDCH18" description="Pending Channel 18" />
-      <BitField start="19" size="1" name="PENDCH19" description="Pending Channel 19" />
-      <BitField start="20" size="1" name="PENDCH20" description="Pending Channel 20" />
-      <BitField start="21" size="1" name="PENDCH21" description="Pending Channel 21" />
-      <BitField start="22" size="1" name="PENDCH22" description="Pending Channel 22" />
-      <BitField start="23" size="1" name="PENDCH23" description="Pending Channel 23" />
-      <BitField start="24" size="1" name="PENDCH24" description="Pending Channel 24" />
-      <BitField start="25" size="1" name="PENDCH25" description="Pending Channel 25" />
-      <BitField start="26" size="1" name="PENDCH26" description="Pending Channel 26" />
-      <BitField start="27" size="1" name="PENDCH27" description="Pending Channel 27" />
-      <BitField start="28" size="1" name="PENDCH28" description="Pending Channel 28" />
-      <BitField start="29" size="1" name="PENDCH29" description="Pending Channel 29" />
-      <BitField start="30" size="1" name="PENDCH30" description="Pending Channel 30" />
-      <BitField start="31" size="1" name="PENDCH31" description="Pending Channel 31" />
-    </Register>
-    <Register start="+0x30" size="4" name="DMAC_ACTIVE" access="ReadOnly" description="Active Channel and Levels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LVLEX0" description="Level 0 Channel Trigger Request Executing" />
-      <BitField start="1" size="1" name="LVLEX1" description="Level 1 Channel Trigger Request Executing" />
-      <BitField start="2" size="1" name="LVLEX2" description="Level 2 Channel Trigger Request Executing" />
-      <BitField start="3" size="1" name="LVLEX3" description="Level 3 Channel Trigger Request Executing" />
-      <BitField start="8" size="5" name="ID" description="Active Channel ID" />
-      <BitField start="15" size="1" name="ABUSY" description="Active Channel Busy" />
-      <BitField start="16" size="16" name="BTCNT" description="Active Channel Block Transfer Count" />
-    </Register>
-    <Register start="+0x34" size="4" name="DMAC_BASEADDR" access="Read/Write" description="Descriptor Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BASEADDR" description="Descriptor Memory Base Address" />
-    </Register>
-    <Register start="+0x38" size="4" name="DMAC_WRBADDR" access="Read/Write" description="Write-Back Memory Section Base Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WRBADDR" description="Write-Back Memory Base Address" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="DMAC_CHCTRLA0" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+16" size="4" name="DMAC_CHCTRLA1" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+32" size="4" name="DMAC_CHCTRLA2" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+48" size="4" name="DMAC_CHCTRLA3" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+64" size="4" name="DMAC_CHCTRLA4" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+80" size="4" name="DMAC_CHCTRLA5" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+96" size="4" name="DMAC_CHCTRLA6" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+112" size="4" name="DMAC_CHCTRLA7" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+128" size="4" name="DMAC_CHCTRLA8" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+144" size="4" name="DMAC_CHCTRLA9" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+160" size="4" name="DMAC_CHCTRLA10" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+176" size="4" name="DMAC_CHCTRLA11" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+192" size="4" name="DMAC_CHCTRLA12" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+208" size="4" name="DMAC_CHCTRLA13" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+224" size="4" name="DMAC_CHCTRLA14" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+240" size="4" name="DMAC_CHCTRLA15" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+256" size="4" name="DMAC_CHCTRLA16" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+272" size="4" name="DMAC_CHCTRLA17" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+288" size="4" name="DMAC_CHCTRLA18" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+304" size="4" name="DMAC_CHCTRLA19" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+320" size="4" name="DMAC_CHCTRLA20" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+336" size="4" name="DMAC_CHCTRLA21" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+352" size="4" name="DMAC_CHCTRLA22" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+368" size="4" name="DMAC_CHCTRLA23" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+384" size="4" name="DMAC_CHCTRLA24" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+400" size="4" name="DMAC_CHCTRLA25" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+416" size="4" name="DMAC_CHCTRLA26" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+432" size="4" name="DMAC_CHCTRLA27" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+448" size="4" name="DMAC_CHCTRLA28" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+464" size="4" name="DMAC_CHCTRLA29" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+480" size="4" name="DMAC_CHCTRLA30" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+496" size="4" name="DMAC_CHCTRLA31" access="Read/Write" description="Channel n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Channel Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Channel Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Channel Run in Standby" />
-      <BitField start="8" size="7" name="TRIGSRC" description="Trigger Source">
-        <Enum name="DISABLE" start="0x0" description="Only software/event triggers" />
-      </BitField>
-      <BitField start="20" size="2" name="TRIGACT" description="Trigger Action">
-        <Enum name="BLOCK" start="0x0" description="One trigger required for each block transfer" />
-        <Enum name="BURST" start="0x2" description="One trigger required for each burst transfer" />
-        <Enum name="TRANSACTION" start="0x3" description="One trigger required for each transaction" />
-      </BitField>
-      <BitField start="24" size="4" name="BURSTLEN" description="Burst Length">
-        <Enum name="SINGLE" start="0x0" description="Single-beat burst length" />
-        <Enum name="2BEAT" start="0x1" description="2-beats burst length" />
-        <Enum name="3BEAT" start="0x2" description="3-beats burst length" />
-        <Enum name="4BEAT" start="0x3" description="4-beats burst length" />
-        <Enum name="5BEAT" start="0x4" description="5-beats burst length" />
-        <Enum name="6BEAT" start="0x5" description="6-beats burst length" />
-        <Enum name="7BEAT" start="0x6" description="7-beats burst length" />
-        <Enum name="8BEAT" start="0x7" description="8-beats burst length" />
-        <Enum name="9BEAT" start="0x8" description="9-beats burst length" />
-        <Enum name="10BEAT" start="0x9" description="10-beats burst length" />
-        <Enum name="11BEAT" start="0xa" description="11-beats burst length" />
-        <Enum name="12BEAT" start="0xb" description="12-beats burst length" />
-        <Enum name="13BEAT" start="0xc" description="13-beats burst length" />
-        <Enum name="14BEAT" start="0xd" description="14-beats burst length" />
-        <Enum name="15BEAT" start="0xe" description="15-beats burst length" />
-        <Enum name="16BEAT" start="0xf" description="16-beats burst length" />
-      </BitField>
-      <BitField start="28" size="2" name="THRESHOLD" description="FIFO Threshold">
-        <Enum name="1BEAT" start="0x0" description="Destination write starts after each beat source address read" />
-        <Enum name="2BEATS" start="0x1" description="Destination write starts after 2-beats source address read" />
-        <Enum name="4BEATS" start="0x2" description="Destination write starts after 4-beats source address read" />
-        <Enum name="8BEATS" start="0x3" description="Destination write starts after 8-beats source address read" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+0" size="1" name="DMAC_CHCTRLB0" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+16" size="1" name="DMAC_CHCTRLB1" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+32" size="1" name="DMAC_CHCTRLB2" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+48" size="1" name="DMAC_CHCTRLB3" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+64" size="1" name="DMAC_CHCTRLB4" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+80" size="1" name="DMAC_CHCTRLB5" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+96" size="1" name="DMAC_CHCTRLB6" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+112" size="1" name="DMAC_CHCTRLB7" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+128" size="1" name="DMAC_CHCTRLB8" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+144" size="1" name="DMAC_CHCTRLB9" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+160" size="1" name="DMAC_CHCTRLB10" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+176" size="1" name="DMAC_CHCTRLB11" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+192" size="1" name="DMAC_CHCTRLB12" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+208" size="1" name="DMAC_CHCTRLB13" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+224" size="1" name="DMAC_CHCTRLB14" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+240" size="1" name="DMAC_CHCTRLB15" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+256" size="1" name="DMAC_CHCTRLB16" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+272" size="1" name="DMAC_CHCTRLB17" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+288" size="1" name="DMAC_CHCTRLB18" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+304" size="1" name="DMAC_CHCTRLB19" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+320" size="1" name="DMAC_CHCTRLB20" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+336" size="1" name="DMAC_CHCTRLB21" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+352" size="1" name="DMAC_CHCTRLB22" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+368" size="1" name="DMAC_CHCTRLB23" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+384" size="1" name="DMAC_CHCTRLB24" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+400" size="1" name="DMAC_CHCTRLB25" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+416" size="1" name="DMAC_CHCTRLB26" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+432" size="1" name="DMAC_CHCTRLB27" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+448" size="1" name="DMAC_CHCTRLB28" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+464" size="1" name="DMAC_CHCTRLB29" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+480" size="1" name="DMAC_CHCTRLB30" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x44+496" size="1" name="DMAC_CHCTRLB31" access="Read/Write" description="Channel n Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMD" description="Software Command">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="SUSPEND" start="0x1" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x2" description="Channel resume operation" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+0" size="1" name="DMAC_CHPRILVL0" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+16" size="1" name="DMAC_CHPRILVL1" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+32" size="1" name="DMAC_CHPRILVL2" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+48" size="1" name="DMAC_CHPRILVL3" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+64" size="1" name="DMAC_CHPRILVL4" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+80" size="1" name="DMAC_CHPRILVL5" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+96" size="1" name="DMAC_CHPRILVL6" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+112" size="1" name="DMAC_CHPRILVL7" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+128" size="1" name="DMAC_CHPRILVL8" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+144" size="1" name="DMAC_CHPRILVL9" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+160" size="1" name="DMAC_CHPRILVL10" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+176" size="1" name="DMAC_CHPRILVL11" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+192" size="1" name="DMAC_CHPRILVL12" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+208" size="1" name="DMAC_CHPRILVL13" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+224" size="1" name="DMAC_CHPRILVL14" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+240" size="1" name="DMAC_CHPRILVL15" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+256" size="1" name="DMAC_CHPRILVL16" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+272" size="1" name="DMAC_CHPRILVL17" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+288" size="1" name="DMAC_CHPRILVL18" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+304" size="1" name="DMAC_CHPRILVL19" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+320" size="1" name="DMAC_CHPRILVL20" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+336" size="1" name="DMAC_CHPRILVL21" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+352" size="1" name="DMAC_CHPRILVL22" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+368" size="1" name="DMAC_CHPRILVL23" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+384" size="1" name="DMAC_CHPRILVL24" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+400" size="1" name="DMAC_CHPRILVL25" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+416" size="1" name="DMAC_CHPRILVL26" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+432" size="1" name="DMAC_CHPRILVL27" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+448" size="1" name="DMAC_CHPRILVL28" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+464" size="1" name="DMAC_CHPRILVL29" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+480" size="1" name="DMAC_CHPRILVL30" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x45+496" size="1" name="DMAC_CHPRILVL31" access="Read/Write" description="Channel n Priority Level" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PRILVL" description="Channel Priority Level">
-        <Enum name="LVL0" start="0x0" description="Channel Priority Level 0 (Lowest Level)" />
-        <Enum name="LVL1" start="0x1" description="Channel Priority Level 1" />
-        <Enum name="LVL2" start="0x2" description="Channel Priority Level 2" />
-        <Enum name="LVL3" start="0x3" description="Channel Priority Level 3" />
-        <Enum name="LVL4" start="0x4" description="Channel Priority Level 4" />
-        <Enum name="LVL5" start="0x5" description="Channel Priority Level 5" />
-        <Enum name="LVL6" start="0x6" description="Channel Priority Level 6" />
-        <Enum name="LVL7" start="0x7" description="Channel Priority Level 7 (Highest Level)" />
-      </BitField>
-    </Register>
-    <Register start="+0x46+0" size="1" name="DMAC_CHEVCTRL0" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+16" size="1" name="DMAC_CHEVCTRL1" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+32" size="1" name="DMAC_CHEVCTRL2" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+48" size="1" name="DMAC_CHEVCTRL3" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+64" size="1" name="DMAC_CHEVCTRL4" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+80" size="1" name="DMAC_CHEVCTRL5" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+96" size="1" name="DMAC_CHEVCTRL6" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+112" size="1" name="DMAC_CHEVCTRL7" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+128" size="1" name="DMAC_CHEVCTRL8" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+144" size="1" name="DMAC_CHEVCTRL9" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+160" size="1" name="DMAC_CHEVCTRL10" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+176" size="1" name="DMAC_CHEVCTRL11" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+192" size="1" name="DMAC_CHEVCTRL12" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+208" size="1" name="DMAC_CHEVCTRL13" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+224" size="1" name="DMAC_CHEVCTRL14" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+240" size="1" name="DMAC_CHEVCTRL15" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+256" size="1" name="DMAC_CHEVCTRL16" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+272" size="1" name="DMAC_CHEVCTRL17" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+288" size="1" name="DMAC_CHEVCTRL18" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+304" size="1" name="DMAC_CHEVCTRL19" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+320" size="1" name="DMAC_CHEVCTRL20" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+336" size="1" name="DMAC_CHEVCTRL21" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+352" size="1" name="DMAC_CHEVCTRL22" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+368" size="1" name="DMAC_CHEVCTRL23" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+384" size="1" name="DMAC_CHEVCTRL24" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+400" size="1" name="DMAC_CHEVCTRL25" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+416" size="1" name="DMAC_CHEVCTRL26" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+432" size="1" name="DMAC_CHEVCTRL27" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+448" size="1" name="DMAC_CHEVCTRL28" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+464" size="1" name="DMAC_CHEVCTRL29" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+480" size="1" name="DMAC_CHEVCTRL30" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x46+496" size="1" name="DMAC_CHEVCTRL31" access="Read/Write" description="Channel n Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Channel Event Input Action">
-        <Enum name="NOACT" start="0x0" description="No action" />
-        <Enum name="TRIG" start="0x1" description="Transfer and periodic transfer trigger" />
-        <Enum name="CTRIG" start="0x2" description="Conditional transfer trigger" />
-        <Enum name="CBLOCK" start="0x3" description="Conditional block transfer" />
-        <Enum name="SUSPEND" start="0x4" description="Channel suspend operation" />
-        <Enum name="RESUME" start="0x5" description="Channel resume operation" />
-        <Enum name="SSKIP" start="0x6" description="Skip next block suspend action" />
-        <Enum name="INCPRI" start="0x7" description="Increase priority" />
-      </BitField>
-      <BitField start="4" size="2" name="EVOMODE" description="Channel Event Output Mode">
-        <Enum name="DEFAULT" start="0x0" description="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." />
-        <Enum name="TRIGACT" start="0x1" description="Ongoing trigger action" />
-      </BitField>
-      <BitField start="6" size="1" name="EVIE" description="Channel Event Input Enable" />
-      <BitField start="7" size="1" name="EVOE" description="Channel Event Output Enable" />
-    </Register>
-    <Register start="+0x4C+0" size="1" name="DMAC_CHINTENCLR0" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+16" size="1" name="DMAC_CHINTENCLR1" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+32" size="1" name="DMAC_CHINTENCLR2" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+48" size="1" name="DMAC_CHINTENCLR3" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+64" size="1" name="DMAC_CHINTENCLR4" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+80" size="1" name="DMAC_CHINTENCLR5" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+96" size="1" name="DMAC_CHINTENCLR6" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+112" size="1" name="DMAC_CHINTENCLR7" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+128" size="1" name="DMAC_CHINTENCLR8" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+144" size="1" name="DMAC_CHINTENCLR9" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+160" size="1" name="DMAC_CHINTENCLR10" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+176" size="1" name="DMAC_CHINTENCLR11" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+192" size="1" name="DMAC_CHINTENCLR12" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+208" size="1" name="DMAC_CHINTENCLR13" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+224" size="1" name="DMAC_CHINTENCLR14" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+240" size="1" name="DMAC_CHINTENCLR15" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+256" size="1" name="DMAC_CHINTENCLR16" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+272" size="1" name="DMAC_CHINTENCLR17" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+288" size="1" name="DMAC_CHINTENCLR18" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+304" size="1" name="DMAC_CHINTENCLR19" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+320" size="1" name="DMAC_CHINTENCLR20" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+336" size="1" name="DMAC_CHINTENCLR21" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+352" size="1" name="DMAC_CHINTENCLR22" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+368" size="1" name="DMAC_CHINTENCLR23" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+384" size="1" name="DMAC_CHINTENCLR24" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+400" size="1" name="DMAC_CHINTENCLR25" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+416" size="1" name="DMAC_CHINTENCLR26" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+432" size="1" name="DMAC_CHINTENCLR27" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+448" size="1" name="DMAC_CHINTENCLR28" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+464" size="1" name="DMAC_CHINTENCLR29" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+480" size="1" name="DMAC_CHINTENCLR30" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4C+496" size="1" name="DMAC_CHINTENCLR31" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+0" size="1" name="DMAC_CHINTENSET0" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+16" size="1" name="DMAC_CHINTENSET1" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+32" size="1" name="DMAC_CHINTENSET2" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+48" size="1" name="DMAC_CHINTENSET3" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+64" size="1" name="DMAC_CHINTENSET4" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+80" size="1" name="DMAC_CHINTENSET5" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+96" size="1" name="DMAC_CHINTENSET6" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+112" size="1" name="DMAC_CHINTENSET7" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+128" size="1" name="DMAC_CHINTENSET8" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+144" size="1" name="DMAC_CHINTENSET9" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+160" size="1" name="DMAC_CHINTENSET10" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+176" size="1" name="DMAC_CHINTENSET11" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+192" size="1" name="DMAC_CHINTENSET12" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+208" size="1" name="DMAC_CHINTENSET13" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+224" size="1" name="DMAC_CHINTENSET14" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+240" size="1" name="DMAC_CHINTENSET15" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+256" size="1" name="DMAC_CHINTENSET16" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+272" size="1" name="DMAC_CHINTENSET17" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+288" size="1" name="DMAC_CHINTENSET18" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+304" size="1" name="DMAC_CHINTENSET19" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+320" size="1" name="DMAC_CHINTENSET20" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+336" size="1" name="DMAC_CHINTENSET21" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+352" size="1" name="DMAC_CHINTENSET22" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+368" size="1" name="DMAC_CHINTENSET23" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+384" size="1" name="DMAC_CHINTENSET24" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+400" size="1" name="DMAC_CHINTENSET25" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+416" size="1" name="DMAC_CHINTENSET26" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+432" size="1" name="DMAC_CHINTENSET27" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+448" size="1" name="DMAC_CHINTENSET28" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+464" size="1" name="DMAC_CHINTENSET29" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+480" size="1" name="DMAC_CHINTENSET30" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4D+496" size="1" name="DMAC_CHINTENSET31" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error Interrupt Enable" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x4E+0" size="1" name="DMAC_CHINTFLAG0" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+16" size="1" name="DMAC_CHINTFLAG1" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+32" size="1" name="DMAC_CHINTFLAG2" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+48" size="1" name="DMAC_CHINTFLAG3" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+64" size="1" name="DMAC_CHINTFLAG4" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+80" size="1" name="DMAC_CHINTFLAG5" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+96" size="1" name="DMAC_CHINTFLAG6" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+112" size="1" name="DMAC_CHINTFLAG7" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+128" size="1" name="DMAC_CHINTFLAG8" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+144" size="1" name="DMAC_CHINTFLAG9" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+160" size="1" name="DMAC_CHINTFLAG10" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+176" size="1" name="DMAC_CHINTFLAG11" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+192" size="1" name="DMAC_CHINTFLAG12" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+208" size="1" name="DMAC_CHINTFLAG13" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+224" size="1" name="DMAC_CHINTFLAG14" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+240" size="1" name="DMAC_CHINTFLAG15" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+256" size="1" name="DMAC_CHINTFLAG16" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+272" size="1" name="DMAC_CHINTFLAG17" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+288" size="1" name="DMAC_CHINTFLAG18" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+304" size="1" name="DMAC_CHINTFLAG19" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+320" size="1" name="DMAC_CHINTFLAG20" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+336" size="1" name="DMAC_CHINTFLAG21" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+352" size="1" name="DMAC_CHINTFLAG22" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+368" size="1" name="DMAC_CHINTFLAG23" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+384" size="1" name="DMAC_CHINTFLAG24" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+400" size="1" name="DMAC_CHINTFLAG25" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+416" size="1" name="DMAC_CHINTFLAG26" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+432" size="1" name="DMAC_CHINTFLAG27" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+448" size="1" name="DMAC_CHINTFLAG28" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+464" size="1" name="DMAC_CHINTFLAG29" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+480" size="1" name="DMAC_CHINTFLAG30" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4E+496" size="1" name="DMAC_CHINTFLAG31" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TERR" description="Channel Transfer Error" />
-      <BitField start="1" size="1" name="TCMPL" description="Channel Transfer Complete" />
-      <BitField start="2" size="1" name="SUSP" description="Channel Suspend" />
-    </Register>
-    <Register start="+0x4F+0" size="1" name="DMAC_CHSTATUS0" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+16" size="1" name="DMAC_CHSTATUS1" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+32" size="1" name="DMAC_CHSTATUS2" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+48" size="1" name="DMAC_CHSTATUS3" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+64" size="1" name="DMAC_CHSTATUS4" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+80" size="1" name="DMAC_CHSTATUS5" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+96" size="1" name="DMAC_CHSTATUS6" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+112" size="1" name="DMAC_CHSTATUS7" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+128" size="1" name="DMAC_CHSTATUS8" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+144" size="1" name="DMAC_CHSTATUS9" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+160" size="1" name="DMAC_CHSTATUS10" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+176" size="1" name="DMAC_CHSTATUS11" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+192" size="1" name="DMAC_CHSTATUS12" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+208" size="1" name="DMAC_CHSTATUS13" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+224" size="1" name="DMAC_CHSTATUS14" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+240" size="1" name="DMAC_CHSTATUS15" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+256" size="1" name="DMAC_CHSTATUS16" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+272" size="1" name="DMAC_CHSTATUS17" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+288" size="1" name="DMAC_CHSTATUS18" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+304" size="1" name="DMAC_CHSTATUS19" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+320" size="1" name="DMAC_CHSTATUS20" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+336" size="1" name="DMAC_CHSTATUS21" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+352" size="1" name="DMAC_CHSTATUS22" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+368" size="1" name="DMAC_CHSTATUS23" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+384" size="1" name="DMAC_CHSTATUS24" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+400" size="1" name="DMAC_CHSTATUS25" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+416" size="1" name="DMAC_CHSTATUS26" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+432" size="1" name="DMAC_CHSTATUS27" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+448" size="1" name="DMAC_CHSTATUS28" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+464" size="1" name="DMAC_CHSTATUS29" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+480" size="1" name="DMAC_CHSTATUS30" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-    <Register start="+0x4F+496" size="1" name="DMAC_CHSTATUS31" access="Read/Write" description="Channel n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEND" description="Channel Pending" />
-      <BitField start="1" size="1" name="BUSY" description="Channel Busy" />
-      <BitField start="2" size="1" name="FERR" description="Channel Fetch Error" />
-      <BitField start="3" size="1" name="CRCERR" description="Channel CRC Error" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DSU" start="0x41002000" description="Device Service Unit">
-    <Register start="+0x0000" size="1" name="DSU_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="2" size="1" name="CRC" description="32-bit Cyclic Redundancy Code" />
-      <BitField start="3" size="1" name="MBIST" description="Memory built-in self-test" />
-      <BitField start="4" size="1" name="CE" description="Chip-Erase" />
-      <BitField start="6" size="1" name="ARR" description="Auxiliary Row Read" />
-      <BitField start="7" size="1" name="SMSA" description="Start Memory Stream Access" />
-    </Register>
-    <Register start="+0x0001" size="1" name="DSU_STATUSA" access="Read/Write" description="Status A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Done" />
-      <BitField start="1" size="1" name="CRSTEXT" description="CPU Reset Phase Extension" />
-      <BitField start="2" size="1" name="BERR" description="Bus Error" />
-      <BitField start="3" size="1" name="FAIL" description="Failure" />
-      <BitField start="4" size="1" name="PERR" description="Protection Error" />
-    </Register>
-    <Register start="+0x0002" size="1" name="DSU_STATUSB" access="ReadOnly" description="Status B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PROT" description="Protected" />
-      <BitField start="1" size="1" name="DBGPRES" description="Debugger Present" />
-      <BitField start="2" size="1" name="DCCD0" description="Debug Communication Channel 0 Dirty" />
-      <BitField start="3" size="1" name="DCCD1" description="Debug Communication Channel 1 Dirty" />
-      <BitField start="4" size="1" name="HPE" description="Hot-Plugging Enable" />
-      <BitField start="5" size="1" name="CELCK" description="Chip Erase Locked" />
-      <BitField start="6" size="1" name="TDCCD0" description="Test Debug Communication Channel 0 Dirty" />
-      <BitField start="7" size="1" name="TDCCD1" description="Test Debug Communication Channel 1 Dirty" />
-    </Register>
-    <Register start="+0x0004" size="4" name="DSU_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AMOD" description="Access Mode" />
-      <BitField start="2" size="30" name="ADDR" description="Address" />
-    </Register>
-    <Register start="+0x0008" size="4" name="DSU_LENGTH" access="Read/Write" description="Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="30" name="LENGTH" description="Length" />
-    </Register>
-    <Register start="+0x000C" size="4" name="DSU_DATA" access="Read/Write" description="Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+0" size="4" name="DSU_DCC0" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0010+4" size="4" name="DSU_DCC1" access="Read/Write" description="Debug Communication Channel n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data" />
-    </Register>
-    <Register start="+0x0018" size="4" name="DSU_DID" access="ReadOnly" description="Device Identification" reset_value="0x60060005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DEVSEL" description="Device Select" />
-      <BitField start="8" size="4" name="REVISION" description="Revision Number" />
-      <BitField start="12" size="4" name="DIE" description="Die Number" />
-      <BitField start="16" size="6" name="SERIES" description="Series">
-        <Enum name="0" start="0x0" description="Cortex-M0+ processor, basic feature set" />
-        <Enum name="1" start="0x1" description="Cortex-M0+ processor, USB" />
-      </BitField>
-      <BitField start="23" size="5" name="FAMILY" description="Family">
-        <Enum name="0" start="0x0" description="General purpose microcontroller" />
-        <Enum name="1" start="0x1" description="PicoPower" />
-      </BitField>
-      <BitField start="28" size="4" name="PROCESSOR" description="Processor">
-        <Enum name="CM0P" start="0x1" description="Cortex-M0+" />
-        <Enum name="CM23" start="0x2" description="Cortex-M23" />
-        <Enum name="CM3" start="0x3" description="Cortex-M3" />
-        <Enum name="CM4" start="0x5" description="Cortex-M4" />
-        <Enum name="CM4F" start="0x6" description="Cortex-M4 with FPU" />
-        <Enum name="CM33" start="0x7" description="Cortex-M33" />
-      </BitField>
-    </Register>
-    <Register start="+0x001C" size="4" name="DSU_CFG" access="Read/Write" description="Configuration" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LQOS" description="Latency Quality Of Service" />
-      <BitField start="2" size="2" name="DCCDMALEVEL" description="DMA Trigger Level">
-        <Enum name="EMPTY" start="0x0" description="Trigger rises when DCC is empty" />
-        <Enum name="FULL" start="0x1" description="Trigger rises when DCC is full" />
-      </BitField>
-      <BitField start="4" size="1" name="ETBRAMEN" description="Trace Control" />
-    </Register>
-    <Register start="+0x0040" size="4" name="DSU_MBCTRL" access="Read/Write" description="MBIST Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="MBIST Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="MBIST Enable" />
-    </Register>
-    <Register start="+0x0044" size="4" name="DSU_MBCONFIG" access="Read/Write" description="MBIST Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="ALGO" description="MBIST Algorithm">
-        <Enum name="MEMCLEAR" start="0x0" description="Memory Clear (1n)" />
-        <Enum name="VERIFY" start="0x1" description="Memory Verify (1n)" />
-        <Enum name="CLEARVER" start="0x2" description="Memory Clear and Verify (2n)" />
-        <Enum name="ADDR_DEC" start="0x3" description="Address Decoder (2n)" />
-        <Enum name="MARCH_LR" start="0x4" description="March LR (14n)" />
-        <Enum name="MARCH_SR" start="0x5" description="March SR (14n)" />
-        <Enum name="MARCH_SS" start="0x6" description="March SS (22n)" />
-        <Enum name="CRC_UP" start="0x8" description="CRC increasing address (1n)" />
-        <Enum name="CRC_DOWN" start="0x9" description="CRC decreasing address (1n)" />
-      </BitField>
-      <BitField start="6" size="1" name="DEFRDMARGIN" description="Force Default Read Margin" />
-      <BitField start="7" size="1" name="DBG" description="Enable Debug Mode" />
-    </Register>
-    <Register start="+0x0048" size="4" name="DSU_MBWORD" access="Read/Write" description="MBIST Background Word" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="MBIST Background Word" />
-    </Register>
-    <Register start="+0x004C" size="4" name="DSU_MBGSTAT" access="Read/Write" description="MBIST Global Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ALLDONE" description="MBIST Completed" />
-      <BitField start="1" size="1" name="FAILED" description="MBIST Failed" />
-      <BitField start="2" size="1" name="ERRINFO" description="MBIST Error Info Present" />
-      <BitField start="3" size="1" name="CONFIGURED" description="MBIST Configuration Sent" />
-    </Register>
-    <Register start="+0x0050" size="4" name="DSU_MBDFAIL" access="ReadOnly" description="MBIST Fail Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Error Data Read" />
-    </Register>
-    <Register start="+0x0054" size="4" name="DSU_MBDEXP" access="ReadOnly" description="MBIST Expected Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Expected Data" />
-    </Register>
-    <Register start="+0x0058" size="4" name="DSU_MBAFAIL" access="ReadOnly" description="MBIST Fail Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="ADDR" description="Error Address" />
-    </Register>
-    <Register start="+0x005C" size="4" name="DSU_MBCONTEXT" access="ReadOnly" description="MBIST Fail Context" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="SUBSTEP" description="Algorithm Sub-step">
-        <Enum name="R0_1" start="0x1" />
-        <Enum name="R1_1" start="0x3" />
-        <Enum name="R0_2" start="0x5" />
-        <Enum name="R1_2" start="0x7" />
-        <Enum name="R0_3" start="0x9" />
-        <Enum name="R1_3" start="0xb" />
-      </BitField>
-      <BitField start="5" size="5" name="STEP" description="Algorithm Step">
-        <Enum name="DOWN_R0W1" start="0x2" />
-        <Enum name="UP_R1W0R0W1" start="0x3" />
-        <Enum name="UP_R1W0" start="0x4" />
-        <Enum name="UP_R0W1R1W0" start="0x5" />
-        <Enum name="UP_R0" start="0x6" />
-        <Enum name="UP_R0R0W0R0W1" start="0x7" />
-        <Enum name="UP_R1R1W1R1W0" start="0x8" />
-        <Enum name="DOWN_R0R0W0R0W1" start="0x9" />
-        <Enum name="DOWN_R1R1W1R1W0" start="0xa" />
-        <Enum name="UP_R0R0" start="0xc" />
-        <Enum name="DOWN_R1W0R0W1" start="0xe" />
-        <Enum name="DOWN_R1R1" start="0xf" />
-      </BitField>
-      <BitField start="10" size="1" name="PORT" description="DPRAM Port Index" />
-    </Register>
-    <Register start="+0x0060" size="4" name="DSU_MBENABLE0" access="Read/Write" description="MBIST Memory Enable 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE0" description="Memory 0 MBIST Enable" />
-      <BitField start="1" size="1" name="ENABLE1" description="Memory 1 MBIST Enable" />
-      <BitField start="2" size="1" name="ENABLE2" description="Memory 2 MBIST Enable" />
-      <BitField start="3" size="1" name="ENABLE3" description="Memory 3 MBIST Enable" />
-      <BitField start="4" size="1" name="ENABLE4" description="Memory 4 MBIST Enable" />
-      <BitField start="5" size="1" name="ENABLE5" description="Memory 5 MBIST Enable" />
-      <BitField start="6" size="1" name="ENABLE6" description="Memory 6 MBIST Enable" />
-      <BitField start="7" size="1" name="ENABLE7" description="Memory 7 MBIST Enable" />
-      <BitField start="8" size="1" name="ENABLE8" description="Memory 8 MBIST Enable" />
-      <BitField start="9" size="1" name="ENABLE9" description="Memory 9 MBIST Enable" />
-      <BitField start="10" size="1" name="ENABLE10" description="Memory 10 MBIST Enable" />
-      <BitField start="11" size="1" name="ENABLE11" description="Memory 11 MBIST Enable" />
-      <BitField start="12" size="1" name="ENABLE12" description="Memory 12 MBIST Enable" />
-      <BitField start="13" size="1" name="ENABLE13" description="Memory 13 MBIST Enable" />
-      <BitField start="14" size="1" name="ENABLE14" description="Memory 14 MBIST Enable" />
-      <BitField start="15" size="1" name="ENABLE15" description="Memory 15 MBIST Enable" />
-      <BitField start="16" size="1" name="ENABLE16" description="Memory 16 MBIST Enable" />
-      <BitField start="17" size="1" name="ENABLE17" description="Memory 17 MBIST Enable" />
-      <BitField start="18" size="1" name="ENABLE18" description="Memory 18 MBIST Enable" />
-      <BitField start="19" size="1" name="ENABLE19" description="Memory 19 MBIST Enable" />
-      <BitField start="20" size="1" name="ENABLE20" description="Memory 20 MBIST Enable" />
-      <BitField start="21" size="1" name="ENABLE21" description="Memory 21 MBIST Enable" />
-      <BitField start="22" size="1" name="ENABLE22" description="Memory 22 MBIST Enable" />
-      <BitField start="23" size="1" name="ENABLE23" description="Memory 23 MBIST Enable" />
-      <BitField start="24" size="1" name="ENABLE24" description="Memory 24 MBIST Enable" />
-      <BitField start="25" size="1" name="ENABLE25" description="Memory 25 MBIST Enable" />
-      <BitField start="26" size="1" name="ENABLE26" description="Memory 26 MBIST Enable" />
-      <BitField start="27" size="1" name="ENABLE27" description="Memory 27 MBIST Enable" />
-      <BitField start="28" size="1" name="ENABLE28" description="Memory 28 MBIST Enable" />
-    </Register>
-    <Register start="+0x0068" size="4" name="DSU_MBBUSY0" access="ReadOnly" description="MBIST Memory Busy 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY0" description="Memory 0 BIST Busy" />
-      <BitField start="1" size="1" name="BUSY1" description="Memory 1 BIST Busy" />
-      <BitField start="2" size="1" name="BUSY2" description="Memory 2 BIST Busy" />
-      <BitField start="3" size="1" name="BUSY3" description="Memory 3 BIST Busy" />
-      <BitField start="4" size="1" name="BUSY4" description="Memory 4 BIST Busy" />
-      <BitField start="5" size="1" name="BUSY5" description="Memory 5 BIST Busy" />
-      <BitField start="6" size="1" name="BUSY6" description="Memory 6 BIST Busy" />
-      <BitField start="7" size="1" name="BUSY7" description="Memory 7 BIST Busy" />
-      <BitField start="8" size="1" name="BUSY8" description="Memory 8 BIST Busy" />
-      <BitField start="9" size="1" name="BUSY9" description="Memory 9 BIST Busy" />
-      <BitField start="10" size="1" name="BUSY10" description="Memory 10 BIST Busy" />
-      <BitField start="11" size="1" name="BUSY11" description="Memory 11 BIST Busy" />
-      <BitField start="12" size="1" name="BUSY12" description="Memory 12 BIST Busy" />
-      <BitField start="13" size="1" name="BUSY13" description="Memory 13 BIST Busy" />
-      <BitField start="14" size="1" name="BUSY14" description="Memory 14 BIST Busy" />
-      <BitField start="15" size="1" name="BUSY15" description="Memory 15 BIST Busy" />
-      <BitField start="16" size="1" name="BUSY16" description="Memory 16 BIST Busy" />
-      <BitField start="17" size="1" name="BUSY17" description="Memory 17 BIST Busy" />
-      <BitField start="18" size="1" name="BUSY18" description="Memory 18 BIST Busy" />
-      <BitField start="19" size="1" name="BUSY19" description="Memory 19 BIST Busy" />
-      <BitField start="20" size="1" name="BUSY20" description="Memory 20 BIST Busy" />
-      <BitField start="21" size="1" name="BUSY21" description="Memory 21 BIST Busy" />
-      <BitField start="22" size="1" name="BUSY22" description="Memory 22 BIST Busy" />
-      <BitField start="23" size="1" name="BUSY23" description="Memory 23 BIST Busy" />
-      <BitField start="24" size="1" name="BUSY24" description="Memory 24 BIST Busy" />
-      <BitField start="25" size="1" name="BUSY25" description="Memory 25 BIST Busy" />
-      <BitField start="26" size="1" name="BUSY26" description="Memory 26 BIST Busy" />
-      <BitField start="27" size="1" name="BUSY27" description="Memory 27 BIST Busy" />
-      <BitField start="28" size="1" name="BUSY28" description="Memory 28 BIST Busy" />
-    </Register>
-    <Register start="+0x0070" size="4" name="DSU_MBSTATUS0" access="Read/Write" description="MBIST Memory Status 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATUS0" description="Memory 0 MBIST Status" />
-      <BitField start="1" size="1" name="STATUS1" description="Memory 1 MBIST Status" />
-      <BitField start="2" size="1" name="STATUS2" description="Memory 2 MBIST Status" />
-      <BitField start="3" size="1" name="STATUS3" description="Memory 3 MBIST Status" />
-      <BitField start="4" size="1" name="STATUS4" description="Memory 4 MBIST Status" />
-      <BitField start="5" size="1" name="STATUS5" description="Memory 5 MBIST Status" />
-      <BitField start="6" size="1" name="STATUS6" description="Memory 6 MBIST Status" />
-      <BitField start="7" size="1" name="STATUS7" description="Memory 7 MBIST Status" />
-      <BitField start="8" size="1" name="STATUS8" description="Memory 8 MBIST Status" />
-      <BitField start="9" size="1" name="STATUS9" description="Memory 9 MBIST Status" />
-      <BitField start="10" size="1" name="STATUS10" description="Memory 10 MBIST Status" />
-      <BitField start="11" size="1" name="STATUS11" description="Memory 11 MBIST Status" />
-      <BitField start="12" size="1" name="STATUS12" description="Memory 12 MBIST Status" />
-      <BitField start="13" size="1" name="STATUS13" description="Memory 13 MBIST Status" />
-      <BitField start="14" size="1" name="STATUS14" description="Memory 14 MBIST Status" />
-      <BitField start="15" size="1" name="STATUS15" description="Memory 15 MBIST Status" />
-      <BitField start="16" size="1" name="STATUS16" description="Memory 16 MBIST Status" />
-      <BitField start="17" size="1" name="STATUS17" description="Memory 17 MBIST Status" />
-      <BitField start="18" size="1" name="STATUS18" description="Memory 18 MBIST Status" />
-      <BitField start="19" size="1" name="STATUS19" description="Memory 19 MBIST Status" />
-      <BitField start="20" size="1" name="STATUS20" description="Memory 20 MBIST Status" />
-      <BitField start="21" size="1" name="STATUS21" description="Memory 21 MBIST Status" />
-      <BitField start="22" size="1" name="STATUS22" description="Memory 22 MBIST Status" />
-      <BitField start="23" size="1" name="STATUS23" description="Memory 23 MBIST Status" />
-      <BitField start="24" size="1" name="STATUS24" description="Memory 24 MBIST Status" />
-      <BitField start="25" size="1" name="STATUS25" description="Memory 25 MBIST Status" />
-      <BitField start="26" size="1" name="STATUS26" description="Memory 26 MBIST Status" />
-      <BitField start="27" size="1" name="STATUS27" description="Memory 27 MBIST Status" />
-      <BitField start="28" size="1" name="STATUS28" description="Memory 28 MBIST Status" />
-    </Register>
-    <Register start="+0x00F0+0" size="4" name="DSU_DCFG0" access="Read/Write" description="Device Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DCFG" description="Device Configuration" />
-    </Register>
-    <Register start="+0x00F0+4" size="4" name="DSU_DCFG1" access="Read/Write" description="Device Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DCFG" description="Device Configuration" />
-    </Register>
-    <Register start="+0x1000" size="4" name="DSU_ENTRY0" access="ReadOnly" description="CoreSight ROM Table Entry 0" reset_value="0x9F0FC002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRES" description="Entry Present" />
-      <BitField start="1" size="1" name="FMT" description="Format" />
-      <BitField start="12" size="20" name="ADDOFF" description="Address Offset" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DSU_ENTRY1" access="ReadOnly" description="CoreSight ROM Table Entry 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1008" size="4" name="DSU_END" access="ReadOnly" description="CoreSight ROM Table End" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="END" description="End Marker" />
-    </Register>
-    <Register start="+0x1FCC" size="4" name="DSU_MEMTYPE" access="ReadOnly" description="CoreSight ROM Table Memory Type" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SMEMP" description="System Memory Present" />
-    </Register>
-    <Register start="+0x1FD0" size="4" name="DSU_PID4" access="ReadOnly" description="Peripheral Identification 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="JEPCC" description="JEP-106 Continuation Code" />
-      <BitField start="4" size="4" name="FKBC" description="4KB count" />
-    </Register>
-    <Register start="+0x1FD4" size="4" name="DSU_PID5" access="ReadOnly" description="Peripheral Identification 5" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1FD8" size="4" name="DSU_PID6" access="ReadOnly" description="Peripheral Identification 6" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1FDC" size="4" name="DSU_PID7" access="ReadOnly" description="Peripheral Identification 7" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x1FE0" size="4" name="DSU_PID0" access="ReadOnly" description="Peripheral Identification 0" reset_value="0x000000D0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PARTNBL" description="Part Number Low" />
-    </Register>
-    <Register start="+0x1FE4" size="4" name="DSU_PID1" access="ReadOnly" description="Peripheral Identification 1" reset_value="0x000000FC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PARTNBH" description="Part Number High" />
-      <BitField start="4" size="4" name="JEPIDCL" description="Low part of the JEP-106 Identity Code" />
-    </Register>
-    <Register start="+0x1FE8" size="4" name="DSU_PID2" access="ReadOnly" description="Peripheral Identification 2" reset_value="0x00000009" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="JEPIDCH" description="JEP-106 Identity Code High" />
-      <BitField start="3" size="1" name="JEPU" description="JEP-106 Identity Code is used" />
-      <BitField start="4" size="4" name="REVISION" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FEC" size="4" name="DSU_PID3" access="ReadOnly" description="Peripheral Identification 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CUSMOD" description="ARM CUSMOD" />
-      <BitField start="4" size="4" name="REVAND" description="Revision Number" />
-    </Register>
-    <Register start="+0x1FF0" size="4" name="DSU_CID0" access="ReadOnly" description="Component Identification 0" reset_value="0x0000000D" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB0" description="Preamble Byte 0" />
-    </Register>
-    <Register start="+0x1FF4" size="4" name="DSU_CID1" access="ReadOnly" description="Component Identification 1" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PREAMBLE" description="Preamble" />
-      <BitField start="4" size="4" name="CCLASS" description="Component Class" />
-    </Register>
-    <Register start="+0x1FF8" size="4" name="DSU_CID2" access="ReadOnly" description="Component Identification 2" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB2" description="Preamble Byte 2" />
-    </Register>
-    <Register start="+0x1FFC" size="4" name="DSU_CID3" access="ReadOnly" description="Component Identification 3" reset_value="0x000000B1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PREAMBLEB3" description="Preamble Byte 3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EIC" start="0x40002800" description="External Interrupt Controller">
-    <Register start="+0x00" size="1" name="EIC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="4" size="1" name="CKSEL" description="Clock Selection" />
-    </Register>
-    <Register start="+0x01" size="1" name="EIC_NMICTRL" access="Read/Write" description="Non-Maskable Interrupt Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="NMISENSE" description="Non-Maskable Interrupt Sense Configuration">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising-edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling-edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both-edges detection" />
-        <Enum name="HIGH" start="0x4" description="High-level detection" />
-        <Enum name="LOW" start="0x5" description="Low-level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="NMIFILTEN" description="Non-Maskable Interrupt Filter Enable" />
-      <BitField start="4" size="1" name="NMIASYNCH" description="Asynchronous Edge Detection Mode" />
-    </Register>
-    <Register start="+0x02" size="2" name="EIC_NMIFLAG" access="Read/Write" description="Non-Maskable Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMI" description="Non-Maskable Interrupt" />
-    </Register>
-    <Register start="+0x04" size="4" name="EIC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy Status" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy Status" />
-    </Register>
-    <Register start="+0x08" size="4" name="EIC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINTEO" description="External Interrupt Event Output Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="EIC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINT" description="External Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="EIC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINT" description="External Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="4" name="EIC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="EXTINT" description="External Interrupt" />
-    </Register>
-    <Register start="+0x18" size="4" name="EIC_ASYNCH" access="Read/Write" description="External Interrupt Asynchronous Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ASYNCH" description="Asynchronous Edge Detection Mode" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="EIC_CONFIG0" access="Read/Write" description="External Interrupt Sense Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense Configuration 0">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter Enable 0" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense Configuration 1">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter Enable 1" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense Configuration 2">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter Enable 2" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense Configuration 3">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter Enable 3" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense Configuration 4">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter Enable 4" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense Configuration 5">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter Enable 5" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense Configuration 6">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter Enable 6" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense Configuration 7">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter Enable 7" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="EIC_CONFIG1" access="Read/Write" description="External Interrupt Sense Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SENSE0" description="Input Sense Configuration 0">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="3" size="1" name="FILTEN0" description="Filter Enable 0" />
-      <BitField start="4" size="3" name="SENSE1" description="Input Sense Configuration 1">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="7" size="1" name="FILTEN1" description="Filter Enable 1" />
-      <BitField start="8" size="3" name="SENSE2" description="Input Sense Configuration 2">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="11" size="1" name="FILTEN2" description="Filter Enable 2" />
-      <BitField start="12" size="3" name="SENSE3" description="Input Sense Configuration 3">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="15" size="1" name="FILTEN3" description="Filter Enable 3" />
-      <BitField start="16" size="3" name="SENSE4" description="Input Sense Configuration 4">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="19" size="1" name="FILTEN4" description="Filter Enable 4" />
-      <BitField start="20" size="3" name="SENSE5" description="Input Sense Configuration 5">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="23" size="1" name="FILTEN5" description="Filter Enable 5" />
-      <BitField start="24" size="3" name="SENSE6" description="Input Sense Configuration 6">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="27" size="1" name="FILTEN6" description="Filter Enable 6" />
-      <BitField start="28" size="3" name="SENSE7" description="Input Sense Configuration 7">
-        <Enum name="NONE" start="0x0" description="No detection" />
-        <Enum name="RISE" start="0x1" description="Rising edge detection" />
-        <Enum name="FALL" start="0x2" description="Falling edge detection" />
-        <Enum name="BOTH" start="0x3" description="Both edges detection" />
-        <Enum name="HIGH" start="0x4" description="High level detection" />
-        <Enum name="LOW" start="0x5" description="Low level detection" />
-      </BitField>
-      <BitField start="31" size="1" name="FILTEN7" description="Filter Enable 7" />
-    </Register>
-    <Register start="+0x30" size="4" name="EIC_DEBOUNCEN" access="Read/Write" description="Debouncer Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DEBOUNCEN" description="Debouncer Enable" />
-    </Register>
-    <Register start="+0x34" size="4" name="EIC_DPRESCALER" access="Read/Write" description="Debouncer Prescaler" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="PRESCALER0" description="Debouncer Prescaler" />
-      <BitField start="4" size="3" name="PRESCALER1" description="Debouncer Prescaler" />
-      <BitField start="3" size="1" name="STATES0" description="Debouncer number of states" />
-      <BitField start="7" size="1" name="STATES1" description="Debouncer number of states" />
-      <BitField start="16" size="1" name="TICKON" description="Pin Sampler frequency selection" />
-    </Register>
-    <Register start="+0x38" size="4" name="EIC_PINSTATE" access="ReadOnly" description="Pin State" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINSTATE" description="Pin State" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVSYS" start="0x4100E000" description="Event System Interface">
-    <Register start="+0x000" size="1" name="EVSYS_CTRLA" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-    </Register>
-    <Register start="+0x004" size="4" name="EVSYS_SWEVT" access="WriteOnly" description="Software Event" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHANNEL0" description="Channel 0 Software Selection" />
-      <BitField start="1" size="1" name="CHANNEL1" description="Channel 1 Software Selection" />
-      <BitField start="2" size="1" name="CHANNEL2" description="Channel 2 Software Selection" />
-      <BitField start="3" size="1" name="CHANNEL3" description="Channel 3 Software Selection" />
-      <BitField start="4" size="1" name="CHANNEL4" description="Channel 4 Software Selection" />
-      <BitField start="5" size="1" name="CHANNEL5" description="Channel 5 Software Selection" />
-      <BitField start="6" size="1" name="CHANNEL6" description="Channel 6 Software Selection" />
-      <BitField start="7" size="1" name="CHANNEL7" description="Channel 7 Software Selection" />
-      <BitField start="8" size="1" name="CHANNEL8" description="Channel 8 Software Selection" />
-      <BitField start="9" size="1" name="CHANNEL9" description="Channel 9 Software Selection" />
-      <BitField start="10" size="1" name="CHANNEL10" description="Channel 10 Software Selection" />
-      <BitField start="11" size="1" name="CHANNEL11" description="Channel 11 Software Selection" />
-      <BitField start="12" size="1" name="CHANNEL12" description="Channel 12 Software Selection" />
-      <BitField start="13" size="1" name="CHANNEL13" description="Channel 13 Software Selection" />
-      <BitField start="14" size="1" name="CHANNEL14" description="Channel 14 Software Selection" />
-      <BitField start="15" size="1" name="CHANNEL15" description="Channel 15 Software Selection" />
-      <BitField start="16" size="1" name="CHANNEL16" description="Channel 16 Software Selection" />
-      <BitField start="17" size="1" name="CHANNEL17" description="Channel 17 Software Selection" />
-      <BitField start="18" size="1" name="CHANNEL18" description="Channel 18 Software Selection" />
-      <BitField start="19" size="1" name="CHANNEL19" description="Channel 19 Software Selection" />
-      <BitField start="20" size="1" name="CHANNEL20" description="Channel 20 Software Selection" />
-      <BitField start="21" size="1" name="CHANNEL21" description="Channel 21 Software Selection" />
-      <BitField start="22" size="1" name="CHANNEL22" description="Channel 22 Software Selection" />
-      <BitField start="23" size="1" name="CHANNEL23" description="Channel 23 Software Selection" />
-      <BitField start="24" size="1" name="CHANNEL24" description="Channel 24 Software Selection" />
-      <BitField start="25" size="1" name="CHANNEL25" description="Channel 25 Software Selection" />
-      <BitField start="26" size="1" name="CHANNEL26" description="Channel 26 Software Selection" />
-      <BitField start="27" size="1" name="CHANNEL27" description="Channel 27 Software Selection" />
-      <BitField start="28" size="1" name="CHANNEL28" description="Channel 28 Software Selection" />
-      <BitField start="29" size="1" name="CHANNEL29" description="Channel 29 Software Selection" />
-      <BitField start="30" size="1" name="CHANNEL30" description="Channel 30 Software Selection" />
-      <BitField start="31" size="1" name="CHANNEL31" description="Channel 31 Software Selection" />
-    </Register>
-    <Register start="+0x008" size="1" name="EVSYS_PRICTRL" access="Read/Write" description="Priority Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRI" description="Channel Priority Number" />
-      <BitField start="7" size="1" name="RREN" description="Round-Robin Scheduling Enable" />
-    </Register>
-    <Register start="+0x010" size="2" name="EVSYS_INTPEND" access="Read/Write" description="Channel Pending Interrupt" reset_value="0x4000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="ID" description="Channel ID" />
-      <BitField start="8" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="9" size="1" name="EVD" description="Channel Event Detected" />
-      <BitField start="14" size="1" name="READY" description="Ready" />
-      <BitField start="15" size="1" name="BUSY" description="Busy" />
-    </Register>
-    <Register start="+0x014" size="4" name="EVSYS_INTSTATUS" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CHINT0" description="Channel 0 Pending Interrupt" />
-      <BitField start="1" size="1" name="CHINT1" description="Channel 1 Pending Interrupt" />
-      <BitField start="2" size="1" name="CHINT2" description="Channel 2 Pending Interrupt" />
-      <BitField start="3" size="1" name="CHINT3" description="Channel 3 Pending Interrupt" />
-      <BitField start="4" size="1" name="CHINT4" description="Channel 4 Pending Interrupt" />
-      <BitField start="5" size="1" name="CHINT5" description="Channel 5 Pending Interrupt" />
-      <BitField start="6" size="1" name="CHINT6" description="Channel 6 Pending Interrupt" />
-      <BitField start="7" size="1" name="CHINT7" description="Channel 7 Pending Interrupt" />
-      <BitField start="8" size="1" name="CHINT8" description="Channel 8 Pending Interrupt" />
-      <BitField start="9" size="1" name="CHINT9" description="Channel 9 Pending Interrupt" />
-      <BitField start="10" size="1" name="CHINT10" description="Channel 10 Pending Interrupt" />
-      <BitField start="11" size="1" name="CHINT11" description="Channel 11 Pending Interrupt" />
-    </Register>
-    <Register start="+0x018" size="4" name="EVSYS_BUSYCH" access="ReadOnly" description="Busy Channels" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSYCH0" description="Busy Channel 0" />
-      <BitField start="1" size="1" name="BUSYCH1" description="Busy Channel 1" />
-      <BitField start="2" size="1" name="BUSYCH2" description="Busy Channel 2" />
-      <BitField start="3" size="1" name="BUSYCH3" description="Busy Channel 3" />
-      <BitField start="4" size="1" name="BUSYCH4" description="Busy Channel 4" />
-      <BitField start="5" size="1" name="BUSYCH5" description="Busy Channel 5" />
-      <BitField start="6" size="1" name="BUSYCH6" description="Busy Channel 6" />
-      <BitField start="7" size="1" name="BUSYCH7" description="Busy Channel 7" />
-      <BitField start="8" size="1" name="BUSYCH8" description="Busy Channel 8" />
-      <BitField start="9" size="1" name="BUSYCH9" description="Busy Channel 9" />
-      <BitField start="10" size="1" name="BUSYCH10" description="Busy Channel 10" />
-      <BitField start="11" size="1" name="BUSYCH11" description="Busy Channel 11" />
-    </Register>
-    <Register start="+0x01C" size="4" name="EVSYS_READYUSR" access="ReadOnly" description="Ready Users" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READYUSR0" description="Ready User for Channel 0" />
-      <BitField start="1" size="1" name="READYUSR1" description="Ready User for Channel 1" />
-      <BitField start="2" size="1" name="READYUSR2" description="Ready User for Channel 2" />
-      <BitField start="3" size="1" name="READYUSR3" description="Ready User for Channel 3" />
-      <BitField start="4" size="1" name="READYUSR4" description="Ready User for Channel 4" />
-      <BitField start="5" size="1" name="READYUSR5" description="Ready User for Channel 5" />
-      <BitField start="6" size="1" name="READYUSR6" description="Ready User for Channel 6" />
-      <BitField start="7" size="1" name="READYUSR7" description="Ready User for Channel 7" />
-      <BitField start="8" size="1" name="READYUSR8" description="Ready User for Channel 8" />
-      <BitField start="9" size="1" name="READYUSR9" description="Ready User for Channel 9" />
-      <BitField start="10" size="1" name="READYUSR10" description="Ready User for Channel 10" />
-      <BitField start="11" size="1" name="READYUSR11" description="Ready User for Channel 11" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="EVSYS_CHANNEL0" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+8" size="4" name="EVSYS_CHANNEL1" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+16" size="4" name="EVSYS_CHANNEL2" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+24" size="4" name="EVSYS_CHANNEL3" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+32" size="4" name="EVSYS_CHANNEL4" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+40" size="4" name="EVSYS_CHANNEL5" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+48" size="4" name="EVSYS_CHANNEL6" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+56" size="4" name="EVSYS_CHANNEL7" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+64" size="4" name="EVSYS_CHANNEL8" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+72" size="4" name="EVSYS_CHANNEL9" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+80" size="4" name="EVSYS_CHANNEL10" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+88" size="4" name="EVSYS_CHANNEL11" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="EVSYS_CHANNEL12" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+104" size="4" name="EVSYS_CHANNEL13" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+112" size="4" name="EVSYS_CHANNEL14" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+120" size="4" name="EVSYS_CHANNEL15" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+128" size="4" name="EVSYS_CHANNEL16" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+136" size="4" name="EVSYS_CHANNEL17" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+144" size="4" name="EVSYS_CHANNEL18" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+152" size="4" name="EVSYS_CHANNEL19" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+160" size="4" name="EVSYS_CHANNEL20" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+168" size="4" name="EVSYS_CHANNEL21" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+176" size="4" name="EVSYS_CHANNEL22" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+184" size="4" name="EVSYS_CHANNEL23" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+192" size="4" name="EVSYS_CHANNEL24" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+200" size="4" name="EVSYS_CHANNEL25" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+208" size="4" name="EVSYS_CHANNEL26" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+216" size="4" name="EVSYS_CHANNEL27" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+224" size="4" name="EVSYS_CHANNEL28" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+232" size="4" name="EVSYS_CHANNEL29" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+240" size="4" name="EVSYS_CHANNEL30" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x020+248" size="4" name="EVSYS_CHANNEL31" access="Read/Write" description="Channel n Control" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="EVGEN" description="Event Generator Selection" />
-      <BitField start="8" size="2" name="PATH" description="Path Selection">
-        <Enum name="SYNCHRONOUS" start="0x0" description="Synchronous path" />
-        <Enum name="RESYNCHRONIZED" start="0x1" description="Resynchronized path" />
-        <Enum name="ASYNCHRONOUS" start="0x2" description="Asynchronous path" />
-      </BitField>
-      <BitField start="10" size="2" name="EDGSEL" description="Edge Detection Selection">
-        <Enum name="NO_EVT_OUTPUT" start="0x0" description="No event output when using the resynchronized or synchronous path" />
-        <Enum name="RISING_EDGE" start="0x1" description="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="FALLING_EDGE" start="0x2" description="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" />
-        <Enum name="BOTH_EDGES" start="0x3" description="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" />
-      </BitField>
-      <BitField start="14" size="1" name="RUNSTDBY" description="Run in standby" />
-      <BitField start="15" size="1" name="ONDEMAND" description="Generic Clock On Demand" />
-    </Register>
-    <Register start="+0x024+0" size="1" name="EVSYS_CHINTENCLR0" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+8" size="1" name="EVSYS_CHINTENCLR1" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+16" size="1" name="EVSYS_CHINTENCLR2" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+24" size="1" name="EVSYS_CHINTENCLR3" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+32" size="1" name="EVSYS_CHINTENCLR4" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+40" size="1" name="EVSYS_CHINTENCLR5" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+48" size="1" name="EVSYS_CHINTENCLR6" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+56" size="1" name="EVSYS_CHINTENCLR7" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+64" size="1" name="EVSYS_CHINTENCLR8" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+72" size="1" name="EVSYS_CHINTENCLR9" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+80" size="1" name="EVSYS_CHINTENCLR10" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+88" size="1" name="EVSYS_CHINTENCLR11" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+96" size="1" name="EVSYS_CHINTENCLR12" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+104" size="1" name="EVSYS_CHINTENCLR13" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+112" size="1" name="EVSYS_CHINTENCLR14" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+120" size="1" name="EVSYS_CHINTENCLR15" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+128" size="1" name="EVSYS_CHINTENCLR16" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+136" size="1" name="EVSYS_CHINTENCLR17" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+144" size="1" name="EVSYS_CHINTENCLR18" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+152" size="1" name="EVSYS_CHINTENCLR19" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+160" size="1" name="EVSYS_CHINTENCLR20" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+168" size="1" name="EVSYS_CHINTENCLR21" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+176" size="1" name="EVSYS_CHINTENCLR22" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+184" size="1" name="EVSYS_CHINTENCLR23" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+192" size="1" name="EVSYS_CHINTENCLR24" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+200" size="1" name="EVSYS_CHINTENCLR25" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+208" size="1" name="EVSYS_CHINTENCLR26" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+216" size="1" name="EVSYS_CHINTENCLR27" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+224" size="1" name="EVSYS_CHINTENCLR28" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+232" size="1" name="EVSYS_CHINTENCLR29" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+240" size="1" name="EVSYS_CHINTENCLR30" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x024+248" size="1" name="EVSYS_CHINTENCLR31" access="Read/Write" description="Channel n Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Disable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Disable" />
-    </Register>
-    <Register start="+0x025+0" size="1" name="EVSYS_CHINTENSET0" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+8" size="1" name="EVSYS_CHINTENSET1" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+16" size="1" name="EVSYS_CHINTENSET2" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+24" size="1" name="EVSYS_CHINTENSET3" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+32" size="1" name="EVSYS_CHINTENSET4" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+40" size="1" name="EVSYS_CHINTENSET5" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+48" size="1" name="EVSYS_CHINTENSET6" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+56" size="1" name="EVSYS_CHINTENSET7" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+64" size="1" name="EVSYS_CHINTENSET8" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+72" size="1" name="EVSYS_CHINTENSET9" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+80" size="1" name="EVSYS_CHINTENSET10" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+88" size="1" name="EVSYS_CHINTENSET11" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+96" size="1" name="EVSYS_CHINTENSET12" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+104" size="1" name="EVSYS_CHINTENSET13" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+112" size="1" name="EVSYS_CHINTENSET14" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+120" size="1" name="EVSYS_CHINTENSET15" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+128" size="1" name="EVSYS_CHINTENSET16" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+136" size="1" name="EVSYS_CHINTENSET17" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+144" size="1" name="EVSYS_CHINTENSET18" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+152" size="1" name="EVSYS_CHINTENSET19" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+160" size="1" name="EVSYS_CHINTENSET20" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+168" size="1" name="EVSYS_CHINTENSET21" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+176" size="1" name="EVSYS_CHINTENSET22" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+184" size="1" name="EVSYS_CHINTENSET23" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+192" size="1" name="EVSYS_CHINTENSET24" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+200" size="1" name="EVSYS_CHINTENSET25" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+208" size="1" name="EVSYS_CHINTENSET26" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+216" size="1" name="EVSYS_CHINTENSET27" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+224" size="1" name="EVSYS_CHINTENSET28" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+232" size="1" name="EVSYS_CHINTENSET29" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+240" size="1" name="EVSYS_CHINTENSET30" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x025+248" size="1" name="EVSYS_CHINTENSET31" access="Read/Write" description="Channel n Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun Interrupt Enable" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected Interrupt Enable" />
-    </Register>
-    <Register start="+0x026+0" size="1" name="EVSYS_CHINTFLAG0" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+8" size="1" name="EVSYS_CHINTFLAG1" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+16" size="1" name="EVSYS_CHINTFLAG2" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+24" size="1" name="EVSYS_CHINTFLAG3" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+32" size="1" name="EVSYS_CHINTFLAG4" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+40" size="1" name="EVSYS_CHINTFLAG5" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+48" size="1" name="EVSYS_CHINTFLAG6" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+56" size="1" name="EVSYS_CHINTFLAG7" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+64" size="1" name="EVSYS_CHINTFLAG8" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+72" size="1" name="EVSYS_CHINTFLAG9" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+80" size="1" name="EVSYS_CHINTFLAG10" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+88" size="1" name="EVSYS_CHINTFLAG11" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+96" size="1" name="EVSYS_CHINTFLAG12" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+104" size="1" name="EVSYS_CHINTFLAG13" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+112" size="1" name="EVSYS_CHINTFLAG14" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+120" size="1" name="EVSYS_CHINTFLAG15" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+128" size="1" name="EVSYS_CHINTFLAG16" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+136" size="1" name="EVSYS_CHINTFLAG17" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+144" size="1" name="EVSYS_CHINTFLAG18" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+152" size="1" name="EVSYS_CHINTFLAG19" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+160" size="1" name="EVSYS_CHINTFLAG20" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+168" size="1" name="EVSYS_CHINTFLAG21" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+176" size="1" name="EVSYS_CHINTFLAG22" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+184" size="1" name="EVSYS_CHINTFLAG23" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+192" size="1" name="EVSYS_CHINTFLAG24" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+200" size="1" name="EVSYS_CHINTFLAG25" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+208" size="1" name="EVSYS_CHINTFLAG26" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+216" size="1" name="EVSYS_CHINTFLAG27" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+224" size="1" name="EVSYS_CHINTFLAG28" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+232" size="1" name="EVSYS_CHINTFLAG29" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+240" size="1" name="EVSYS_CHINTFLAG30" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x026+248" size="1" name="EVSYS_CHINTFLAG31" access="Read/Write" description="Channel n Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVR" description="Channel Overrun" />
-      <BitField start="1" size="1" name="EVD" description="Channel Event Detected" />
-    </Register>
-    <Register start="+0x027+0" size="1" name="EVSYS_CHSTATUS0" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+8" size="1" name="EVSYS_CHSTATUS1" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+16" size="1" name="EVSYS_CHSTATUS2" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+24" size="1" name="EVSYS_CHSTATUS3" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+32" size="1" name="EVSYS_CHSTATUS4" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+40" size="1" name="EVSYS_CHSTATUS5" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+48" size="1" name="EVSYS_CHSTATUS6" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+56" size="1" name="EVSYS_CHSTATUS7" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+64" size="1" name="EVSYS_CHSTATUS8" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+72" size="1" name="EVSYS_CHSTATUS9" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+80" size="1" name="EVSYS_CHSTATUS10" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+88" size="1" name="EVSYS_CHSTATUS11" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+96" size="1" name="EVSYS_CHSTATUS12" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+104" size="1" name="EVSYS_CHSTATUS13" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+112" size="1" name="EVSYS_CHSTATUS14" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+120" size="1" name="EVSYS_CHSTATUS15" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+128" size="1" name="EVSYS_CHSTATUS16" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+136" size="1" name="EVSYS_CHSTATUS17" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+144" size="1" name="EVSYS_CHSTATUS18" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+152" size="1" name="EVSYS_CHSTATUS19" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+160" size="1" name="EVSYS_CHSTATUS20" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+168" size="1" name="EVSYS_CHSTATUS21" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+176" size="1" name="EVSYS_CHSTATUS22" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+184" size="1" name="EVSYS_CHSTATUS23" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+192" size="1" name="EVSYS_CHSTATUS24" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+200" size="1" name="EVSYS_CHSTATUS25" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+208" size="1" name="EVSYS_CHSTATUS26" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+216" size="1" name="EVSYS_CHSTATUS27" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+224" size="1" name="EVSYS_CHSTATUS28" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+232" size="1" name="EVSYS_CHSTATUS29" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+240" size="1" name="EVSYS_CHSTATUS30" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x027+248" size="1" name="EVSYS_CHSTATUS31" access="ReadOnly" description="Channel n Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDYUSR" description="Ready User" />
-      <BitField start="1" size="1" name="BUSYCH" description="Busy Channel" />
-    </Register>
-    <Register start="+0x120+0" size="4" name="EVSYS_USER0" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+4" size="4" name="EVSYS_USER1" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+8" size="4" name="EVSYS_USER2" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+12" size="4" name="EVSYS_USER3" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+16" size="4" name="EVSYS_USER4" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+20" size="4" name="EVSYS_USER5" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+24" size="4" name="EVSYS_USER6" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+28" size="4" name="EVSYS_USER7" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+32" size="4" name="EVSYS_USER8" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+36" size="4" name="EVSYS_USER9" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+40" size="4" name="EVSYS_USER10" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+44" size="4" name="EVSYS_USER11" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+48" size="4" name="EVSYS_USER12" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+52" size="4" name="EVSYS_USER13" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+56" size="4" name="EVSYS_USER14" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+60" size="4" name="EVSYS_USER15" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+64" size="4" name="EVSYS_USER16" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+68" size="4" name="EVSYS_USER17" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+72" size="4" name="EVSYS_USER18" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+76" size="4" name="EVSYS_USER19" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+80" size="4" name="EVSYS_USER20" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+84" size="4" name="EVSYS_USER21" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+88" size="4" name="EVSYS_USER22" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+92" size="4" name="EVSYS_USER23" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+96" size="4" name="EVSYS_USER24" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+100" size="4" name="EVSYS_USER25" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+104" size="4" name="EVSYS_USER26" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+108" size="4" name="EVSYS_USER27" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+112" size="4" name="EVSYS_USER28" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+116" size="4" name="EVSYS_USER29" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+120" size="4" name="EVSYS_USER30" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+124" size="4" name="EVSYS_USER31" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+128" size="4" name="EVSYS_USER32" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+132" size="4" name="EVSYS_USER33" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+136" size="4" name="EVSYS_USER34" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+140" size="4" name="EVSYS_USER35" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+144" size="4" name="EVSYS_USER36" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+148" size="4" name="EVSYS_USER37" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+152" size="4" name="EVSYS_USER38" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+156" size="4" name="EVSYS_USER39" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+160" size="4" name="EVSYS_USER40" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+164" size="4" name="EVSYS_USER41" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+168" size="4" name="EVSYS_USER42" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+172" size="4" name="EVSYS_USER43" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+176" size="4" name="EVSYS_USER44" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+180" size="4" name="EVSYS_USER45" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+184" size="4" name="EVSYS_USER46" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+188" size="4" name="EVSYS_USER47" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+192" size="4" name="EVSYS_USER48" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+196" size="4" name="EVSYS_USER49" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+200" size="4" name="EVSYS_USER50" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+204" size="4" name="EVSYS_USER51" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+208" size="4" name="EVSYS_USER52" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+212" size="4" name="EVSYS_USER53" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+216" size="4" name="EVSYS_USER54" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+220" size="4" name="EVSYS_USER55" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+224" size="4" name="EVSYS_USER56" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+228" size="4" name="EVSYS_USER57" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+232" size="4" name="EVSYS_USER58" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+236" size="4" name="EVSYS_USER59" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+240" size="4" name="EVSYS_USER60" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+244" size="4" name="EVSYS_USER61" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+248" size="4" name="EVSYS_USER62" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+252" size="4" name="EVSYS_USER63" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+256" size="4" name="EVSYS_USER64" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+260" size="4" name="EVSYS_USER65" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-    <Register start="+0x120+264" size="4" name="EVSYS_USER66" access="Read/Write" description="User Multiplexer n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CHANNEL" description="Channel Event Selection" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FREQM" start="0x40002C00" description="Frequency Meter">
-    <Register start="+0x00" size="1" name="FREQM_CTRLA" access="Read/Write" description="Control A Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x01" size="1" name="FREQM_CTRLB" access="WriteOnly" description="Control B Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start Measurement" />
-    </Register>
-    <Register start="+0x02" size="2" name="FREQM_CFGA" access="Read/Write" description="Config A register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="REFNUM" description="Number of Reference Clock Cycles" />
-    </Register>
-    <Register start="+0x08" size="1" name="FREQM_INTENCLR" access="Read/Write" description="Interrupt Enable Clear Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Measurement Done Interrupt Enable" />
-    </Register>
-    <Register start="+0x09" size="1" name="FREQM_INTENSET" access="Read/Write" description="Interrupt Enable Set Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Measurement Done Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="FREQM_INTFLAG" access="Read/Write" description="Interrupt Flag Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Measurement Done" />
-    </Register>
-    <Register start="+0x0B" size="1" name="FREQM_STATUS" access="Read/Write" description="Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="FREQM Status" />
-      <BitField start="1" size="1" name="OVF" description="Sticky Count Value Overflow" />
-    </Register>
-    <Register start="+0x0C" size="4" name="FREQM_SYNCBUSY" access="ReadOnly" description="Synchronization Busy Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="FREQM_VALUE" access="ReadOnly" description="Count Value Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="VALUE" description="Measurement Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GCLK" start="0x40001C00" description="Generic Clock Generator">
-    <Register start="+0x00" size="1" name="GCLK_CTRLA" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-    </Register>
-    <Register start="+0x04" size="4" name="GCLK_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchroniation Busy bit" />
-      <BitField start="2" size="1" name="GENCTRL0" description="Generic Clock Generator Control 0 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="3" size="1" name="GENCTRL1" description="Generic Clock Generator Control 1 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="4" size="1" name="GENCTRL2" description="Generic Clock Generator Control 2 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="5" size="1" name="GENCTRL3" description="Generic Clock Generator Control 3 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="GENCTRL4" description="Generic Clock Generator Control 4 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="7" size="1" name="GENCTRL5" description="Generic Clock Generator Control 5 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="8" size="1" name="GENCTRL6" description="Generic Clock Generator Control 6 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="9" size="1" name="GENCTRL7" description="Generic Clock Generator Control 7 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="10" size="1" name="GENCTRL8" description="Generic Clock Generator Control 8 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="11" size="1" name="GENCTRL9" description="Generic Clock Generator Control 9 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="12" size="1" name="GENCTRL10" description="Generic Clock Generator Control 10 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="13" size="1" name="GENCTRL11" description="Generic Clock Generator Control 11 Synchronization Busy bits">
-        <Enum name="GCLK0" start="0x1" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x2" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x4" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x8" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x10" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x20" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x40" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x80" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x100" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x200" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0x400" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0x800" description="Generic clock generator 11" />
-      </BitField>
-    </Register>
-    <Register start="+0x20+0" size="4" name="GCLK_GENCTRL0" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="GCLK_GENCTRL1" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+8" size="4" name="GCLK_GENCTRL2" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+12" size="4" name="GCLK_GENCTRL3" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+16" size="4" name="GCLK_GENCTRL4" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+20" size="4" name="GCLK_GENCTRL5" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+24" size="4" name="GCLK_GENCTRL6" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+28" size="4" name="GCLK_GENCTRL7" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+32" size="4" name="GCLK_GENCTRL8" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+36" size="4" name="GCLK_GENCTRL9" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+40" size="4" name="GCLK_GENCTRL10" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x20+44" size="4" name="GCLK_GENCTRL11" access="Read/Write" description="Generic Clock Generator Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SRC" description="Source Select">
-        <Enum name="XOSC0" start="0x0" description="XOSC0 oscillator output" />
-        <Enum name="XOSC1" start="0x1" description="XOSC1 oscillator output" />
-        <Enum name="GCLKIN" start="0x2" description="Generator input pad" />
-        <Enum name="GCLKGEN1" start="0x3" description="Generic clock generator 1 output" />
-        <Enum name="OSCULP32K" start="0x4" description="OSCULP32K oscillator output" />
-        <Enum name="XOSC32K" start="0x5" description="XOSC32K oscillator output" />
-        <Enum name="DFLL" start="0x6" description="DFLL output" />
-        <Enum name="DPLL0" start="0x7" description="DPLL0 output" />
-        <Enum name="DPLL1" start="0x8" description="DPLL1 output" />
-      </BitField>
-      <BitField start="8" size="1" name="GENEN" description="Generic Clock Generator Enable" />
-      <BitField start="9" size="1" name="IDC" description="Improve Duty Cycle" />
-      <BitField start="10" size="1" name="OOV" description="Output Off Value" />
-      <BitField start="11" size="1" name="OE" description="Output Enable" />
-      <BitField start="12" size="1" name="DIVSEL" description="Divide Selection" />
-      <BitField start="13" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="16" name="DIV" description="Division Factor" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="GCLK_PCHCTRL0" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="GCLK_PCHCTRL1" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="GCLK_PCHCTRL2" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="GCLK_PCHCTRL3" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="GCLK_PCHCTRL4" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="GCLK_PCHCTRL5" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="GCLK_PCHCTRL6" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="GCLK_PCHCTRL7" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+32" size="4" name="GCLK_PCHCTRL8" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+36" size="4" name="GCLK_PCHCTRL9" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+40" size="4" name="GCLK_PCHCTRL10" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+44" size="4" name="GCLK_PCHCTRL11" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+48" size="4" name="GCLK_PCHCTRL12" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+52" size="4" name="GCLK_PCHCTRL13" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+56" size="4" name="GCLK_PCHCTRL14" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+60" size="4" name="GCLK_PCHCTRL15" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+64" size="4" name="GCLK_PCHCTRL16" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+68" size="4" name="GCLK_PCHCTRL17" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+72" size="4" name="GCLK_PCHCTRL18" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+76" size="4" name="GCLK_PCHCTRL19" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+80" size="4" name="GCLK_PCHCTRL20" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+84" size="4" name="GCLK_PCHCTRL21" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+88" size="4" name="GCLK_PCHCTRL22" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+92" size="4" name="GCLK_PCHCTRL23" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+96" size="4" name="GCLK_PCHCTRL24" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+100" size="4" name="GCLK_PCHCTRL25" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+104" size="4" name="GCLK_PCHCTRL26" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+108" size="4" name="GCLK_PCHCTRL27" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+112" size="4" name="GCLK_PCHCTRL28" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+116" size="4" name="GCLK_PCHCTRL29" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+120" size="4" name="GCLK_PCHCTRL30" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+124" size="4" name="GCLK_PCHCTRL31" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+128" size="4" name="GCLK_PCHCTRL32" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+132" size="4" name="GCLK_PCHCTRL33" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+136" size="4" name="GCLK_PCHCTRL34" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+140" size="4" name="GCLK_PCHCTRL35" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+144" size="4" name="GCLK_PCHCTRL36" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+148" size="4" name="GCLK_PCHCTRL37" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+152" size="4" name="GCLK_PCHCTRL38" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+156" size="4" name="GCLK_PCHCTRL39" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+160" size="4" name="GCLK_PCHCTRL40" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+164" size="4" name="GCLK_PCHCTRL41" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+168" size="4" name="GCLK_PCHCTRL42" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+172" size="4" name="GCLK_PCHCTRL43" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+176" size="4" name="GCLK_PCHCTRL44" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+180" size="4" name="GCLK_PCHCTRL45" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+184" size="4" name="GCLK_PCHCTRL46" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-    <Register start="+0x80+188" size="4" name="GCLK_PCHCTRL47" access="Read/Write" description="Peripheral Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="GEN" description="Generic Clock Generator">
-        <Enum name="GCLK0" start="0x0" description="Generic clock generator 0" />
-        <Enum name="GCLK1" start="0x1" description="Generic clock generator 1" />
-        <Enum name="GCLK2" start="0x2" description="Generic clock generator 2" />
-        <Enum name="GCLK3" start="0x3" description="Generic clock generator 3" />
-        <Enum name="GCLK4" start="0x4" description="Generic clock generator 4" />
-        <Enum name="GCLK5" start="0x5" description="Generic clock generator 5" />
-        <Enum name="GCLK6" start="0x6" description="Generic clock generator 6" />
-        <Enum name="GCLK7" start="0x7" description="Generic clock generator 7" />
-        <Enum name="GCLK8" start="0x8" description="Generic clock generator 8" />
-        <Enum name="GCLK9" start="0x9" description="Generic clock generator 9" />
-        <Enum name="GCLK10" start="0xa" description="Generic clock generator 10" />
-        <Enum name="GCLK11" start="0xb" description="Generic clock generator 11" />
-      </BitField>
-      <BitField start="6" size="1" name="CHEN" description="Channel Enable" />
-      <BitField start="7" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="HMATRIX" start="0x4100C000" description="HSB Matrix">
-    <Register start="+0x080+0" size="4" name="HMATRIXB_PRAS0" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+8" size="4" name="HMATRIXB_PRAS1" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+16" size="4" name="HMATRIXB_PRAS2" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+24" size="4" name="HMATRIXB_PRAS3" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+32" size="4" name="HMATRIXB_PRAS4" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+40" size="4" name="HMATRIXB_PRAS5" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+48" size="4" name="HMATRIXB_PRAS6" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+56" size="4" name="HMATRIXB_PRAS7" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+64" size="4" name="HMATRIXB_PRAS8" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+72" size="4" name="HMATRIXB_PRAS9" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+80" size="4" name="HMATRIXB_PRAS10" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+88" size="4" name="HMATRIXB_PRAS11" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+96" size="4" name="HMATRIXB_PRAS12" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+104" size="4" name="HMATRIXB_PRAS13" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+112" size="4" name="HMATRIXB_PRAS14" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x080+120" size="4" name="HMATRIXB_PRAS15" access="Read/Write" description="Priority A for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+0" size="4" name="HMATRIXB_PRBS0" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+8" size="4" name="HMATRIXB_PRBS1" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+16" size="4" name="HMATRIXB_PRBS2" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+24" size="4" name="HMATRIXB_PRBS3" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+32" size="4" name="HMATRIXB_PRBS4" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+40" size="4" name="HMATRIXB_PRBS5" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+48" size="4" name="HMATRIXB_PRBS6" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+56" size="4" name="HMATRIXB_PRBS7" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+64" size="4" name="HMATRIXB_PRBS8" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+72" size="4" name="HMATRIXB_PRBS9" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+80" size="4" name="HMATRIXB_PRBS10" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+88" size="4" name="HMATRIXB_PRBS11" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+96" size="4" name="HMATRIXB_PRBS12" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+104" size="4" name="HMATRIXB_PRBS13" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+112" size="4" name="HMATRIXB_PRBS14" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x084+120" size="4" name="HMATRIXB_PRBS15" access="Read/Write" description="Priority B for Slave" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-  </RegisterGroup>
-  <RegisterGroup name="ICM" start="0x42002C00" description="Integrity Check Monitor">
-    <Register start="+0x00" size="4" name="ICM_CFG" access="Read/Write" description="Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WBDIS" description="Write Back Disable" />
-      <BitField start="1" size="1" name="EOMDIS" description="End of Monitoring Disable" />
-      <BitField start="2" size="1" name="SLBDIS" description="Secondary List Branching Disable" />
-      <BitField start="4" size="4" name="BBC" description="Bus Burden Control" />
-      <BitField start="8" size="1" name="ASCD" description="Automatic Switch To Compare Digest" />
-      <BitField start="9" size="1" name="DUALBUFF" description="Dual Input Buffer" />
-      <BitField start="12" size="1" name="UIHASH" description="User Initial Hash Value" />
-      <BitField start="13" size="3" name="UALGO" description="User SHA Algorithm">
-        <Enum name="SHA1" start="0x0" description="SHA1 Algorithm" />
-        <Enum name="SHA256" start="0x1" description="SHA256 Algorithm" />
-        <Enum name="SHA224" start="0x4" description="SHA224 Algorithm" />
-      </BitField>
-      <BitField start="16" size="6" name="HAPROT" description="Region Hash Area Protection" />
-      <BitField start="24" size="6" name="DAPROT" description="Region Descriptor Area Protection" />
-    </Register>
-    <Register start="+0x04" size="4" name="ICM_CTRL" access="WriteOnly" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="ICM Enable" />
-      <BitField start="1" size="1" name="DISABLE" description="ICM Disable Register" />
-      <BitField start="2" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="4" size="4" name="REHASH" description="Recompute Internal Hash" />
-      <BitField start="8" size="4" name="RMDIS" description="Region Monitoring Disable" />
-      <BitField start="12" size="4" name="RMEN" description="Region Monitoring Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="ICM_SR" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="ICM Controller Enable Register" />
-      <BitField start="8" size="4" name="RAWRMDIS" description="RAW Region Monitoring Disabled Status" />
-      <BitField start="12" size="4" name="RMDIS" description="Region Monitoring Disabled Status" />
-    </Register>
-    <Register start="+0x10" size="4" name="ICM_IER" access="WriteOnly" description="Interrupt Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed Interrupt Enable" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch Interrupt Enable" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error Interrupt Enable" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition detected Interrupt Enable" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition Detected Interrupt Enable" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Interrupt Disable" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="4" name="ICM_IDR" access="WriteOnly" description="Interrupt Disable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed Interrupt Disable" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch Interrupt Disable" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error Interrupt Disable" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition Detected Interrupt Disable" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition detected Interrupt Disable" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Interrupt Disable" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Interrupt Disable" />
-    </Register>
-    <Register start="+0x18" size="4" name="ICM_IMR" access="ReadOnly" description="Interrupt Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed Interrupt Mask" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch Interrupt Mask" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error Interrupt Mask" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition Detected Interrupt Mask" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition Detected Interrupt Mask" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Interrupt Mask" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Interrupt Mask" />
-    </Register>
-    <Register start="+0x1C" size="4" name="ICM_ISR" access="ReadOnly" description="Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RHC" description="Region Hash Completed" />
-      <BitField start="4" size="4" name="RDM" description="Region Digest Mismatch" />
-      <BitField start="8" size="4" name="RBE" description="Region Bus Error" />
-      <BitField start="12" size="4" name="RWC" description="Region Wrap Condition Detected" />
-      <BitField start="16" size="4" name="REC" description="Region End bit Condition Detected" />
-      <BitField start="20" size="4" name="RSU" description="Region Status Updated Detected" />
-      <BitField start="24" size="1" name="URAD" description="Undefined Register Access Detection Status" />
-    </Register>
-    <Register start="+0x20" size="4" name="ICM_UASR" access="ReadOnly" description="Undefined Access Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="URAT" description="Undefined Register Access Trace">
-        <Enum name="UNSPEC_STRUCT_MEMBER" start="0x0" description="Unspecified structure member set to one detected when the descriptor is loaded" />
-        <Enum name="CFG_MODIFIED" start="0x1" description="CFG modified during active monitoring" />
-        <Enum name="DSCR_MODIFIED" start="0x2" description="DSCR modified during active monitoring" />
-        <Enum name="HASH_MODIFIED" start="0x3" description="HASH modified during active monitoring" />
-        <Enum name="READ_ACCESS" start="0x4" description="Write-only register read access" />
-      </BitField>
-    </Register>
-    <Register start="+0x30" size="4" name="ICM_DSCR" access="Read/Write" description="Region Descriptor Area Start Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="26" name="DASA" description="Descriptor Area Start Address" />
-    </Register>
-    <Register start="+0x34" size="4" name="ICM_HASH" access="Read/Write" description="Region Hash Area Start Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="7" size="25" name="HASA" description="Hash Area Start Address" />
-    </Register>
-    <Register start="+0x38+0" size="4" name="ICM_UIHVAL0" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+4" size="4" name="ICM_UIHVAL1" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+8" size="4" name="ICM_UIHVAL2" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+12" size="4" name="ICM_UIHVAL3" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+16" size="4" name="ICM_UIHVAL4" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+20" size="4" name="ICM_UIHVAL5" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+24" size="4" name="ICM_UIHVAL6" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-    <Register start="+0x38+28" size="4" name="ICM_UIHVAL7" access="WriteOnly" description="User Initial Hash Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VAL" description="Initial Hash Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x43002800" description="Inter-IC Sound Interface">
-    <Register start="+0x00" size="1" name="I2S_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable" />
-      <BitField start="4" size="1" name="TXEN" description="Tx Serializer Enable" />
-      <BitField start="5" size="1" name="RXEN" description="Rx Serializer Enable" />
-    </Register>
-    <Register start="+0x04+0" size="4" name="I2S_CLKCTRL0" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="9" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="10" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="11" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="12" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="13" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="14" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="15" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-      <BitField start="16" size="6" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="6" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-    </Register>
-    <Register start="+0x04+4" size="4" name="I2S_CLKCTRL1" access="Read/Write" description="Clock Unit n Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SLOTSIZE" description="Slot Size">
-        <Enum name="8" start="0x0" description="8-bit Slot for Clock Unit n" />
-        <Enum name="16" start="0x1" description="16-bit Slot for Clock Unit n" />
-        <Enum name="24" start="0x2" description="24-bit Slot for Clock Unit n" />
-        <Enum name="32" start="0x3" description="32-bit Slot for Clock Unit n" />
-      </BitField>
-      <BitField start="2" size="3" name="NBSLOTS" description="Number of Slots in Frame" />
-      <BitField start="5" size="2" name="FSWIDTH" description="Frame Sync Width">
-        <Enum name="SLOT" start="0x0" description="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" />
-        <Enum name="HALF" start="0x1" description="Frame Sync Pulse is half a Frame wide" />
-        <Enum name="BIT" start="0x2" description="Frame Sync Pulse is 1 Bit wide" />
-        <Enum name="BURST" start="0x3" description="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" />
-      </BitField>
-      <BitField start="7" size="1" name="BITDELAY" description="Data Delay from Frame Sync">
-        <Enum name="LJ" start="0x0" description="Left Justified (0 Bit Delay)" />
-        <Enum name="I2S" start="0x1" description="I2S (1 Bit Delay)" />
-      </BitField>
-      <BitField start="8" size="1" name="FSSEL" description="Frame Sync Select">
-        <Enum name="SCKDIV" start="0x0" description="Divided Serial Clock n is used as Frame Sync n source" />
-        <Enum name="FSPIN" start="0x1" description="FSn input pin is used as Frame Sync n source" />
-      </BitField>
-      <BitField start="9" size="1" name="FSINV" description="Frame Sync Invert" />
-      <BitField start="10" size="1" name="FSOUTINV" description="Frame Sync Output Invert" />
-      <BitField start="11" size="1" name="SCKSEL" description="Serial Clock Select">
-        <Enum name="MCKDIV" start="0x0" description="Divided Master Clock n is used as Serial Clock n source" />
-        <Enum name="SCKPIN" start="0x1" description="SCKn input pin is used as Serial Clock n source" />
-      </BitField>
-      <BitField start="12" size="1" name="SCKOUTINV" description="Serial Clock Output Invert" />
-      <BitField start="13" size="1" name="MCKSEL" description="Master Clock Select">
-        <Enum name="GCLK" start="0x0" description="GCLK_I2S_n is used as Master Clock n source" />
-        <Enum name="MCKPIN" start="0x1" description="MCKn input pin is used as Master Clock n source" />
-      </BitField>
-      <BitField start="14" size="1" name="MCKEN" description="Master Clock Enable" />
-      <BitField start="15" size="1" name="MCKOUTINV" description="Master Clock Output Invert" />
-      <BitField start="16" size="6" name="MCKDIV" description="Master Clock Division Factor" />
-      <BitField start="24" size="6" name="MCKOUTDIV" description="Master Clock Output Division Factor" />
-    </Register>
-    <Register start="+0x0C" size="2" name="I2S_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="2" name="I2S_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0 Interrupt Enable" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1 Interrupt Enable" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1 Interrupt Enable" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0 Interrupt Enable" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1 Interrupt Enable" />
-    </Register>
-    <Register start="+0x14" size="2" name="I2S_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXRDY0" description="Receive Ready 0" />
-      <BitField start="1" size="1" name="RXRDY1" description="Receive Ready 1" />
-      <BitField start="4" size="1" name="RXOR0" description="Receive Overrun 0" />
-      <BitField start="5" size="1" name="RXOR1" description="Receive Overrun 1" />
-      <BitField start="8" size="1" name="TXRDY0" description="Transmit Ready 0" />
-      <BitField start="9" size="1" name="TXRDY1" description="Transmit Ready 1" />
-      <BitField start="12" size="1" name="TXUR0" description="Transmit Underrun 0" />
-      <BitField start="13" size="1" name="TXUR1" description="Transmit Underrun 1" />
-    </Register>
-    <Register start="+0x18" size="2" name="I2S_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Status" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Status" />
-      <BitField start="2" size="1" name="CKEN0" description="Clock Unit 0 Enable Synchronization Status" />
-      <BitField start="3" size="1" name="CKEN1" description="Clock Unit 1 Enable Synchronization Status" />
-      <BitField start="4" size="1" name="TXEN" description="Tx Serializer Enable Synchronization Status" />
-      <BitField start="5" size="1" name="RXEN" description="Rx Serializer Enable Synchronization Status" />
-      <BitField start="8" size="1" name="TXDATA" description="Tx Data Synchronization Status" />
-      <BitField start="9" size="1" name="RXDATA" description="Rx Data Synchronization Status" />
-    </Register>
-    <Register start="+0x20" size="4" name="I2S_TXCTRL" access="Read/Write" description="Tx Serializer Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="TXDEFAULT" description="Line Default Line when Slot Disabled">
-        <Enum name="ZERO" start="0x0" description="Output Default Value is 0" />
-        <Enum name="ONE" start="0x1" description="Output Default Value is 1" />
-        <Enum name="HIZ" start="0x3" description="Output Default Value is high impedance" />
-      </BitField>
-      <BitField start="4" size="1" name="TXSAME" description="Transmit Data when Underrun">
-        <Enum name="ZERO" start="0x0" description="Zero data transmitted in case of underrun" />
-        <Enum name="SAME" start="0x1" description="Last data transmitted in case of underrun" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-    </Register>
-    <Register start="+0x24" size="4" name="I2S_RXCTRL" access="Read/Write" description="Rx Serializer Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SERMODE" description="Serializer Mode">
-        <Enum name="RX" start="0x0" description="Receive" />
-        <Enum name="PDM2" start="0x2" description="Receive one PDM data on each serial clock edge" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Unit Selection">
-        <Enum name="CLK0" start="0x0" description="Use Clock Unit 0" />
-        <Enum name="CLK1" start="0x1" description="Use Clock Unit 1" />
-      </BitField>
-      <BitField start="7" size="1" name="SLOTADJ" description="Data Slot Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in slot" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in slot" />
-      </BitField>
-      <BitField start="8" size="3" name="DATASIZE" description="Data Word Size">
-        <Enum name="32" start="0x0" description="32 bits" />
-        <Enum name="24" start="0x1" description="24 bits" />
-        <Enum name="20" start="0x2" description="20 bits" />
-        <Enum name="18" start="0x3" description="18 bits" />
-        <Enum name="16" start="0x4" description="16 bits" />
-        <Enum name="16C" start="0x5" description="16 bits compact stereo" />
-        <Enum name="8" start="0x6" description="8 bits" />
-        <Enum name="8C" start="0x7" description="8 bits compact stereo" />
-      </BitField>
-      <BitField start="12" size="1" name="WORDADJ" description="Data Word Formatting Adjust">
-        <Enum name="RIGHT" start="0x0" description="Data is right adjusted in word" />
-        <Enum name="LEFT" start="0x1" description="Data is left adjusted in word" />
-      </BitField>
-      <BitField start="13" size="2" name="EXTEND" description="Data Formatting Bit Extension">
-        <Enum name="ZERO" start="0x0" description="Extend with zeroes" />
-        <Enum name="ONE" start="0x1" description="Extend with ones" />
-        <Enum name="MSBIT" start="0x2" description="Extend with Most Significant Bit" />
-        <Enum name="LSBIT" start="0x3" description="Extend with Least Significant Bit" />
-      </BitField>
-      <BitField start="15" size="1" name="BITREV" description="Data Formatting Bit Reverse">
-        <Enum name="MSBIT" start="0x0" description="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" />
-        <Enum name="LSBIT" start="0x1" description="Transfer Data Least Significant Bit (LSB) first" />
-      </BitField>
-      <BitField start="16" size="1" name="SLOTDIS0" description="Slot 0 Disabled for this Serializer" />
-      <BitField start="17" size="1" name="SLOTDIS1" description="Slot 1 Disabled for this Serializer" />
-      <BitField start="18" size="1" name="SLOTDIS2" description="Slot 2 Disabled for this Serializer" />
-      <BitField start="19" size="1" name="SLOTDIS3" description="Slot 3 Disabled for this Serializer" />
-      <BitField start="20" size="1" name="SLOTDIS4" description="Slot 4 Disabled for this Serializer" />
-      <BitField start="21" size="1" name="SLOTDIS5" description="Slot 5 Disabled for this Serializer" />
-      <BitField start="22" size="1" name="SLOTDIS6" description="Slot 6 Disabled for this Serializer" />
-      <BitField start="23" size="1" name="SLOTDIS7" description="Slot 7 Disabled for this Serializer" />
-      <BitField start="24" size="1" name="MONO" description="Mono Mode">
-        <Enum name="STEREO" start="0x0" description="Normal mode" />
-        <Enum name="MONO" start="0x1" description="Left channel data is duplicated to right channel" />
-      </BitField>
-      <BitField start="25" size="1" name="DMA" description="Single or Multiple DMA Channels">
-        <Enum name="SINGLE" start="0x0" description="Single DMA channel" />
-        <Enum name="MULTIPLE" start="0x1" description="One DMA channel per data channel" />
-      </BitField>
-      <BitField start="26" size="1" name="RXLOOP" description="Loop-back Test Mode" />
-    </Register>
-    <Register start="+0x30" size="4" name="I2S_TXDATA" access="WriteOnly" description="Tx Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-    <Register start="+0x34" size="4" name="I2S_RXDATA" access="ReadOnly" description="Rx Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Sample Data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCLK" start="0x40000800" description="Main Clock">
-    <Register start="+0x01" size="1" name="MCLK_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x02" size="1" name="MCLK_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x03" size="1" name="MCLK_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CKRDY" description="Clock Ready" />
-    </Register>
-    <Register start="+0x04" size="1" name="MCLK_HSDIV" access="ReadOnly" description="HS Clock Division" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="CPU Clock Division Factor">
-        <Enum name="DIV1" start="0x1" description="Divide by 1" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="MCLK_CPUDIV" access="Read/Write" description="CPU Clock Division" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DIV" description="Low-Power Clock Division Factor">
-        <Enum name="DIV1" start="0x1" description="Divide by 1" />
-        <Enum name="DIV2" start="0x2" description="Divide by 2" />
-        <Enum name="DIV4" start="0x4" description="Divide by 4" />
-        <Enum name="DIV8" start="0x8" description="Divide by 8" />
-        <Enum name="DIV16" start="0x10" description="Divide by 16" />
-        <Enum name="DIV32" start="0x20" description="Divide by 32" />
-        <Enum name="DIV64" start="0x40" description="Divide by 64" />
-        <Enum name="DIV128" start="0x80" description="Divide by 128" />
-      </BitField>
-    </Register>
-    <Register start="+0x10" size="4" name="MCLK_AHBMASK" access="Read/Write" description="AHB Mask" reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HPB0_" description="HPB0 AHB Clock Mask" />
-      <BitField start="1" size="1" name="HPB1_" description="HPB1 AHB Clock Mask" />
-      <BitField start="2" size="1" name="HPB2_" description="HPB2 AHB Clock Mask" />
-      <BitField start="3" size="1" name="HPB3_" description="HPB3 AHB Clock Mask" />
-      <BitField start="4" size="1" name="DSU_" description="DSU AHB Clock Mask" />
-      <BitField start="5" size="1" name="HMATRIX_" description="HMATRIX AHB Clock Mask" />
-      <BitField start="6" size="1" name="NVMCTRL_" description="NVMCTRL AHB Clock Mask" />
-      <BitField start="7" size="1" name="HSRAM_" description="HSRAM AHB Clock Mask" />
-      <BitField start="8" size="1" name="CMCC_" description="CMCC AHB Clock Mask" />
-      <BitField start="9" size="1" name="DMAC_" description="DMAC AHB Clock Mask" />
-      <BitField start="10" size="1" name="USB_" description="USB AHB Clock Mask" />
-      <BitField start="11" size="1" name="BKUPRAM_" description="BKUPRAM AHB Clock Mask" />
-      <BitField start="12" size="1" name="PAC_" description="PAC AHB Clock Mask" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI AHB Clock Mask" />
-      <BitField start="15" size="1" name="SDHC0_" description="SDHC0 AHB Clock Mask" />
-      <BitField start="19" size="1" name="ICM_" description="ICM AHB Clock Mask" />
-      <BitField start="20" size="1" name="PUKCC_" description="PUKCC AHB Clock Mask" />
-      <BitField start="21" size="1" name="QSPI_2X_" description="QSPI_2X AHB Clock Mask" />
-      <BitField start="22" size="1" name="NVMCTRL_SMEEPROM_" description="NVMCTRL_SMEEPROM AHB Clock Mask" />
-      <BitField start="23" size="1" name="NVMCTRL_CACHE_" description="NVMCTRL_CACHE AHB Clock Mask" />
-    </Register>
-    <Register start="+0x14" size="4" name="MCLK_APBAMASK" access="Read/Write" description="APBA Mask" reset_value="0x000007FF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC_" description="PAC APB Clock Enable" />
-      <BitField start="1" size="1" name="PM_" description="PM APB Clock Enable" />
-      <BitField start="2" size="1" name="MCLK_" description="MCLK APB Clock Enable" />
-      <BitField start="3" size="1" name="RSTC_" description="RSTC APB Clock Enable" />
-      <BitField start="4" size="1" name="OSCCTRL_" description="OSCCTRL APB Clock Enable" />
-      <BitField start="5" size="1" name="OSC32KCTRL_" description="OSC32KCTRL APB Clock Enable" />
-      <BitField start="6" size="1" name="SUPC_" description="SUPC APB Clock Enable" />
-      <BitField start="7" size="1" name="GCLK_" description="GCLK APB Clock Enable" />
-      <BitField start="8" size="1" name="WDT_" description="WDT APB Clock Enable" />
-      <BitField start="9" size="1" name="RTC_" description="RTC APB Clock Enable" />
-      <BitField start="10" size="1" name="EIC_" description="EIC APB Clock Enable" />
-      <BitField start="11" size="1" name="FREQM_" description="FREQM APB Clock Enable" />
-      <BitField start="12" size="1" name="SERCOM0_" description="SERCOM0 APB Clock Enable" />
-      <BitField start="13" size="1" name="SERCOM1_" description="SERCOM1 APB Clock Enable" />
-      <BitField start="14" size="1" name="TC0_" description="TC0 APB Clock Enable" />
-      <BitField start="15" size="1" name="TC1_" description="TC1 APB Clock Enable" />
-    </Register>
-    <Register start="+0x18" size="4" name="MCLK_APBBMASK" access="Read/Write" description="APBB Mask" reset_value="0x00018056" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_" description="USB APB Clock Enable" />
-      <BitField start="1" size="1" name="DSU_" description="DSU APB Clock Enable" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL APB Clock Enable" />
-      <BitField start="4" size="1" name="PORT_" description="PORT APB Clock Enable" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX APB Clock Enable" />
-      <BitField start="7" size="1" name="EVSYS_" description="EVSYS APB Clock Enable" />
-      <BitField start="9" size="1" name="SERCOM2_" description="SERCOM2 APB Clock Enable" />
-      <BitField start="10" size="1" name="SERCOM3_" description="SERCOM3 APB Clock Enable" />
-      <BitField start="11" size="1" name="TCC0_" description="TCC0 APB Clock Enable" />
-      <BitField start="12" size="1" name="TCC1_" description="TCC1 APB Clock Enable" />
-      <BitField start="13" size="1" name="TC2_" description="TC2 APB Clock Enable" />
-      <BitField start="14" size="1" name="TC3_" description="TC3 APB Clock Enable" />
-      <BitField start="15" size="1" name="TAL_" description="TAL APB Clock Enable" />
-      <BitField start="16" size="1" name="RAMECC_" description="RAMECC APB Clock Enable" />
-    </Register>
-    <Register start="+0x1C" size="4" name="MCLK_APBCMASK" access="Read/Write" description="APBC Mask" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="TCC2_" description="TCC2 APB Clock Enable" />
-      <BitField start="4" size="1" name="TCC3_" description="TCC3 APB Clock Enable" />
-      <BitField start="5" size="1" name="TC4_" description="TC4 APB Clock Enable" />
-      <BitField start="6" size="1" name="TC5_" description="TC5 APB Clock Enable" />
-      <BitField start="7" size="1" name="PDEC_" description="PDEC APB Clock Enable" />
-      <BitField start="8" size="1" name="AC_" description="AC APB Clock Enable" />
-      <BitField start="9" size="1" name="AES_" description="AES APB Clock Enable" />
-      <BitField start="10" size="1" name="TRNG_" description="TRNG APB Clock Enable" />
-      <BitField start="11" size="1" name="ICM_" description="ICM APB Clock Enable" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI APB Clock Enable" />
-      <BitField start="14" size="1" name="CCL_" description="CCL APB Clock Enable" />
-    </Register>
-    <Register start="+0x20" size="4" name="MCLK_APBDMASK" access="Read/Write" description="APBD Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4_" description="SERCOM4 APB Clock Enable" />
-      <BitField start="1" size="1" name="SERCOM5_" description="SERCOM5 APB Clock Enable" />
-      <BitField start="4" size="1" name="TCC4_" description="TCC4 APB Clock Enable" />
-      <BitField start="7" size="1" name="ADC0_" description="ADC0 APB Clock Enable" />
-      <BitField start="8" size="1" name="ADC1_" description="ADC1 APB Clock Enable" />
-      <BitField start="9" size="1" name="DAC_" description="DAC APB Clock Enable" />
-      <BitField start="10" size="1" name="I2S_" description="I2S APB Clock Enable" />
-      <BitField start="11" size="1" name="PCC_" description="PCC APB Clock Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVMCTRL" start="0x41004000" description="Non-Volatile Memory Controller">
-    <Register start="+0x00" size="2" name="NVMCTRL_CTRLA" access="Read/Write" description="Control A" reset_value="0x0004" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="AUTOWS" description="Auto Wait State Enable" />
-      <BitField start="3" size="1" name="SUSPEN" description="Suspend Enable" />
-      <BitField start="4" size="2" name="WMODE" description="Write Mode">
-        <Enum name="MAN" start="0x0" description="Manual Write" />
-        <Enum name="ADW" start="0x1" description="Automatic Double Word Write" />
-        <Enum name="AQW" start="0x2" description="Automatic Quad Word" />
-        <Enum name="AP" start="0x3" description="Automatic Page Write" />
-      </BitField>
-      <BitField start="6" size="2" name="PRM" description="Power Reduction Mode during Sleep">
-        <Enum name="SEMIAUTO" start="0x0" description="NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access." />
-        <Enum name="FULLAUTO" start="0x1" description="NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode." />
-        <Enum name="MANUAL" start="0x3" description="NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access." />
-      </BitField>
-      <BitField start="8" size="4" name="RWS" description="NVM Read Wait States" />
-      <BitField start="12" size="1" name="AHBNS0" description="Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated" />
-      <BitField start="13" size="1" name="AHBNS1" description="Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated" />
-      <BitField start="14" size="1" name="CACHEDIS0" description="AHB0 Cache Disable" />
-      <BitField start="15" size="1" name="CACHEDIS1" description="AHB1 Cache Disable" />
-    </Register>
-    <Register start="+0x04" size="2" name="NVMCTRL_CTRLB" access="WriteOnly" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CMD" description="Command">
-        <Enum name="EP" start="0x0" description="Erase Page - Only supported in the USER and AUX pages." />
-        <Enum name="EB" start="0x1" description="Erase Block - Erases the block addressed by the ADDR register, not supported in the user page" />
-        <Enum name="WP" start="0x3" description="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page" />
-        <Enum name="WQW" start="0x4" description="Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register." />
-        <Enum name="SWRST" start="0x10" description="Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers" />
-        <Enum name="LR" start="0x11" description="Lock Region - Locks the region containing the address location in the ADDR register." />
-        <Enum name="UR" start="0x12" description="Unlock Region - Unlocks the region containing the address location in the ADDR register." />
-        <Enum name="SPRM" start="0x13" description="Sets the power reduction mode." />
-        <Enum name="CPRM" start="0x14" description="Clears the power reduction mode." />
-        <Enum name="PBC" start="0x15" description="Page Buffer Clear - Clears the page buffer." />
-        <Enum name="SSB" start="0x16" description="Set Security Bit" />
-        <Enum name="BKSWRST" start="0x17" description="Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK" />
-        <Enum name="CELCK" start="0x18" description="Chip Erase Lock - DSU.CE command is not available" />
-        <Enum name="CEULCK" start="0x19" description="Chip Erase Unlock - DSU.CE command is available" />
-        <Enum name="SBPDIS" start="0x1a" description="Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence" />
-        <Enum name="CBPDIS" start="0x1b" description="Clears STATUS.BPDIS, Boot loader protection is not discarded" />
-        <Enum name="ASEES0" start="0x30" description="Activate SmartEEPROM Sector 0, deactivate Sector 1" />
-        <Enum name="ASEES1" start="0x31" description="Activate SmartEEPROM Sector 1, deactivate Sector 0" />
-        <Enum name="SEERALOC" start="0x32" description="Starts SmartEEPROM sector reallocation algorithm" />
-        <Enum name="SEEFLUSH" start="0x33" description="Flush SMEE data when in buffered mode" />
-        <Enum name="LSEE" start="0x34" description="Lock access to SmartEEPROM data from any mean" />
-        <Enum name="USEE" start="0x35" description="Unlock access to SmartEEPROM data" />
-        <Enum name="LSEER" start="0x36" description="Lock access to the SmartEEPROM Register Address Space (above 64KB)" />
-        <Enum name="USEER" start="0x37" description="Unlock access to the SmartEEPROM Register Address Space (above 64KB)" />
-      </BitField>
-      <BitField start="8" size="8" name="CMDEX" description="Command Execution">
-        <Enum name="KEY" start="0xa5" description="Execution Key" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="NVMCTRL_PARAM" access="ReadOnly" description="NVM Parameter" reset_value="0x00060000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NVMP" description="NVM Pages" />
-      <BitField start="16" size="3" name="PSZ" description="Page Size">
-        <Enum name="8" start="0x0" description="8 bytes" />
-        <Enum name="16" start="0x1" description="16 bytes" />
-        <Enum name="32" start="0x2" description="32 bytes" />
-        <Enum name="64" start="0x3" description="64 bytes" />
-        <Enum name="128" start="0x4" description="128 bytes" />
-        <Enum name="256" start="0x5" description="256 bytes" />
-        <Enum name="512" start="0x6" description="512 bytes" />
-        <Enum name="1024" start="0x7" description="1024 bytes" />
-      </BitField>
-      <BitField start="31" size="1" name="SEE" description="SmartEEPROM Supported" />
-    </Register>
-    <Register start="+0x0C" size="2" name="NVMCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Command Done Interrupt Clear" />
-      <BitField start="1" size="1" name="ADDRE" description="Address Error" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error Interrupt Clear" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error Interrupt Clear" />
-      <BitField start="4" size="1" name="ECCSE" description="ECC Single Error Interrupt Clear" />
-      <BitField start="5" size="1" name="ECCDE" description="ECC Dual Error Interrupt Clear" />
-      <BitField start="6" size="1" name="NVME" description="NVM Error Interrupt Clear" />
-      <BitField start="7" size="1" name="SUSP" description="Suspended Write Or Erase Interrupt Clear" />
-      <BitField start="8" size="1" name="SEESFULL" description="Active SEES Full Interrupt Clear" />
-      <BitField start="9" size="1" name="SEESOVF" description="Active SEES Overflow Interrupt Clear" />
-      <BitField start="10" size="1" name="SEEWRC" description="SEE Write Completed Interrupt Clear" />
-    </Register>
-    <Register start="+0x0E" size="2" name="NVMCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Command Done Interrupt Enable" />
-      <BitField start="1" size="1" name="ADDRE" description="Address Error Interrupt Enable" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error Interrupt Enable" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error Interrupt Enable" />
-      <BitField start="4" size="1" name="ECCSE" description="ECC Single Error Interrupt Enable" />
-      <BitField start="5" size="1" name="ECCDE" description="ECC Dual Error Interrupt Enable" />
-      <BitField start="6" size="1" name="NVME" description="NVM Error Interrupt Enable" />
-      <BitField start="7" size="1" name="SUSP" description="Suspended Write Or Erase  Interrupt Enable" />
-      <BitField start="8" size="1" name="SEESFULL" description="Active SEES Full Interrupt Enable" />
-      <BitField start="9" size="1" name="SEESOVF" description="Active SEES Overflow Interrupt Enable" />
-      <BitField start="10" size="1" name="SEEWRC" description="SEE Write Completed Interrupt Enable" />
-    </Register>
-    <Register start="+0x10" size="2" name="NVMCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="Command Done" />
-      <BitField start="1" size="1" name="ADDRE" description="Address Error" />
-      <BitField start="2" size="1" name="PROGE" description="Programming Error" />
-      <BitField start="3" size="1" name="LOCKE" description="Lock Error" />
-      <BitField start="4" size="1" name="ECCSE" description="ECC Single Error" />
-      <BitField start="5" size="1" name="ECCDE" description="ECC Dual Error" />
-      <BitField start="6" size="1" name="NVME" description="NVM Error" />
-      <BitField start="7" size="1" name="SUSP" description="Suspended Write Or Erase Operation" />
-      <BitField start="8" size="1" name="SEESFULL" description="Active SEES Full" />
-      <BitField start="9" size="1" name="SEESOVF" description="Active SEES Overflow" />
-      <BitField start="10" size="1" name="SEEWRC" description="SEE Write Completed" />
-    </Register>
-    <Register start="+0x12" size="2" name="NVMCTRL_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READY" description="Ready to accept a command" />
-      <BitField start="1" size="1" name="PRM" description="Power Reduction Mode" />
-      <BitField start="2" size="1" name="LOAD" description="NVM Page Buffer Active Loading" />
-      <BitField start="3" size="1" name="SUSP" description="NVM Write Or Erase Operation Is Suspended" />
-      <BitField start="4" size="1" name="AFIRST" description="BANKA First" />
-      <BitField start="5" size="1" name="BPDIS" description="Boot Loader Protection Disable" />
-      <BitField start="8" size="4" name="BOOTPROT" description="Boot Loader Protection Size" />
-    </Register>
-    <Register start="+0x14" size="4" name="NVMCTRL_ADDR" access="Read/Write" description="Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="ADDR" description="NVM Address" />
-    </Register>
-    <Register start="+0x18" size="4" name="NVMCTRL_RUNLOCK" access="ReadOnly" description="Lock Section" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RUNLOCK" description="Region Un-Lock Bits" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="NVMCTRL_PBLDATA0" access="ReadOnly" description="Page Buffer Load Data x" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Page Buffer Data" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="NVMCTRL_PBLDATA1" access="ReadOnly" description="Page Buffer Load Data x" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Page Buffer Data" />
-    </Register>
-    <Register start="+0x24" size="4" name="NVMCTRL_ECCERR" access="ReadOnly" description="ECC Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="ADDR" description="Error Address" />
-      <BitField start="28" size="2" name="TYPEL" description="Low Double-Word Error Type">
-        <Enum name="None" start="0x0" description="No Error Detected Since Last Read" />
-        <Enum name="Single" start="0x1" description="At Least One Single Error Detected Since last Read" />
-        <Enum name="Dual" start="0x2" description="At Least One Dual Error Detected Since Last Read" />
-      </BitField>
-      <BitField start="30" size="2" name="TYPEH" description="High Double-Word Error Type">
-        <Enum name="None" start="0x0" description="No Error Detected Since Last Read" />
-        <Enum name="Single" start="0x1" description="At Least One Single Error Detected Since last Read" />
-        <Enum name="Dual" start="0x2" description="At Least One Dual Error Detected Since Last Read" />
-      </BitField>
-    </Register>
-    <Register start="+0x28" size="1" name="NVMCTRL_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ECCDIS" description="Debugger ECC Read Disable" />
-      <BitField start="1" size="1" name="ECCELOG" description="Debugger ECC Error Tracking Mode" />
-    </Register>
-    <Register start="+0x2A" size="1" name="NVMCTRL_SEECFG" access="Read/Write" description="SmartEEPROM Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WMODE" description="Write Mode">
-        <Enum name="UNBUFFERED" start="0x0" description="A NVM write command is issued after each write in the pagebuffer" />
-        <Enum name="BUFFERED" start="0x1" description="A NVM write command is issued when a write to a new page is requested" />
-      </BitField>
-      <BitField start="1" size="1" name="APRDIS" description="Automatic Page Reallocation Disable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="NVMCTRL_SEESTAT" access="ReadOnly" description="SmartEEPROM Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ASEES" description="Active SmartEEPROM Sector" />
-      <BitField start="1" size="1" name="LOAD" description="Page Buffer Loaded" />
-      <BitField start="2" size="1" name="BUSY" description="Busy" />
-      <BitField start="3" size="1" name="LOCK" description="SmartEEPROM Write Access Is Locked" />
-      <BitField start="4" size="1" name="RLOCK" description="SmartEEPROM Write Access To Register Address Space Is Locked" />
-      <BitField start="8" size="4" name="SBLK" description="Blocks Number In a Sector" />
-      <BitField start="16" size="3" name="PSZ" description="SmartEEPROM Page Size" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OSCCTRL" start="0x40001000" description="Oscillators Control">
-    <Register start="+0x00" size="1" name="OSCCTRL_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CFDEO0" description="Clock 0 Failure Detector Event Output Enable" />
-      <BitField start="1" size="1" name="CFDEO1" description="Clock 1 Failure Detector Event Output Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="OSCCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector Interrupt Enable" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall Interrupt Enable" />
-      <BitField start="18" size="1" name="DPLL0LTO" description="DPLL0 Lock Timeout Interrupt Enable" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete Interrupt Enable" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise Interrupt Enable" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall Interrupt Enable" />
-      <BitField start="26" size="1" name="DPLL1LTO" description="DPLL1 Lock Timeout Interrupt Enable" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="OSCCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector Interrupt Enable" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector Interrupt Enable" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready Interrupt Enable" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds Interrupt Enable" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine Interrupt Enable" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse Interrupt Enable" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped Interrupt Enable" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise Interrupt Enable" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall Interrupt Enable" />
-      <BitField start="18" size="1" name="DPLL0LTO" description="DPLL0 Lock Timeout Interrupt Enable" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete Interrupt Enable" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise Interrupt Enable" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall Interrupt Enable" />
-      <BitField start="26" size="1" name="DPLL1LTO" description="DPLL1 Lock Timeout Interrupt Enable" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="OSCCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall" />
-      <BitField start="18" size="1" name="DPLL0LTO" description="DPLL0 Lock Timeout" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall" />
-      <BitField start="26" size="1" name="DPLL1LTO" description="DPLL1 Lock Timeout" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete" />
-    </Register>
-    <Register start="+0x10" size="4" name="OSCCTRL_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSCRDY0" description="XOSC 0 Ready" />
-      <BitField start="1" size="1" name="XOSCRDY1" description="XOSC 1 Ready" />
-      <BitField start="2" size="1" name="XOSCFAIL0" description="XOSC 0 Clock Failure Detector" />
-      <BitField start="3" size="1" name="XOSCFAIL1" description="XOSC 1 Clock Failure Detector" />
-      <BitField start="4" size="1" name="XOSCCKSW0" description="XOSC 0 Clock Switch" />
-      <BitField start="5" size="1" name="XOSCCKSW1" description="XOSC 1 Clock Switch" />
-      <BitField start="8" size="1" name="DFLLRDY" description="DFLL Ready" />
-      <BitField start="9" size="1" name="DFLLOOB" description="DFLL Out Of Bounds" />
-      <BitField start="10" size="1" name="DFLLLCKF" description="DFLL Lock Fine" />
-      <BitField start="11" size="1" name="DFLLLCKC" description="DFLL Lock Coarse" />
-      <BitField start="12" size="1" name="DFLLRCS" description="DFLL Reference Clock Stopped" />
-      <BitField start="16" size="1" name="DPLL0LCKR" description="DPLL0 Lock Rise" />
-      <BitField start="17" size="1" name="DPLL0LCKF" description="DPLL0 Lock Fall" />
-      <BitField start="18" size="1" name="DPLL0TO" description="DPLL0 Timeout" />
-      <BitField start="19" size="1" name="DPLL0LDRTO" description="DPLL0 Loop Divider Ratio Update Complete" />
-      <BitField start="24" size="1" name="DPLL1LCKR" description="DPLL1 Lock Rise" />
-      <BitField start="25" size="1" name="DPLL1LCKF" description="DPLL1 Lock Fall" />
-      <BitField start="26" size="1" name="DPLL1TO" description="DPLL1 Timeout" />
-      <BitField start="27" size="1" name="DPLL1LDRTO" description="DPLL1 Loop Divider Ratio Update Complete" />
-    </Register>
-    <Register start="+0x14+0" size="4" name="OSCCTRL_XOSCCTRL0" access="Read/Write" description="External Multipurpose Crystal Oscillator Control" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="1" name="LOWBUFGAIN" description="Low Buffer Gain Enable" />
-      <BitField start="9" size="2" name="IPTAT" description="Oscillator Current Reference" />
-      <BitField start="11" size="4" name="IMULT" description="Oscillator Current Multiplier" />
-      <BitField start="15" size="1" name="ENALC" description="Automatic Loop Control Enable" />
-      <BitField start="16" size="1" name="CFDEN" description="Clock Failure Detector Enable" />
-      <BitField start="17" size="1" name="SWBEN" description="Xosc Clock Switch Enable" />
-      <BitField start="20" size="4" name="STARTUP" description="Start-Up Time" />
-      <BitField start="24" size="4" name="CFDPRESC" description="Clock Failure Detector Prescaler" />
-    </Register>
-    <Register start="+0x14+4" size="4" name="OSCCTRL_XOSCCTRL1" access="Read/Write" description="External Multipurpose Crystal Oscillator Control" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="1" name="LOWBUFGAIN" description="Low Buffer Gain Enable" />
-      <BitField start="9" size="2" name="IPTAT" description="Oscillator Current Reference" />
-      <BitField start="11" size="4" name="IMULT" description="Oscillator Current Multiplier" />
-      <BitField start="15" size="1" name="ENALC" description="Automatic Loop Control Enable" />
-      <BitField start="16" size="1" name="CFDEN" description="Clock Failure Detector Enable" />
-      <BitField start="17" size="1" name="SWBEN" description="Xosc Clock Switch Enable" />
-      <BitField start="20" size="4" name="STARTUP" description="Start-Up Time" />
-      <BitField start="24" size="4" name="CFDPRESC" description="Clock Failure Detector Prescaler" />
-    </Register>
-    <Register start="+0x1C" size="1" name="OSCCTRL_DFLLCTRLA" access="Read/Write" description="DFLL48M Control A" reset_value="0x82" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DFLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-    </Register>
-    <Register start="+0x20" size="1" name="OSCCTRL_DFLLCTRLB" access="Read/Write" description="DFLL48M Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Operating Mode Selection" />
-      <BitField start="1" size="1" name="STABLE" description="Stable DFLL Frequency" />
-      <BitField start="2" size="1" name="LLAW" description="Lose Lock After Wake" />
-      <BitField start="3" size="1" name="USBCRM" description="USB Clock Recovery Mode" />
-      <BitField start="4" size="1" name="CCDIS" description="Chill Cycle Disable" />
-      <BitField start="5" size="1" name="QLDIS" description="Quick Lock Disable" />
-      <BitField start="6" size="1" name="BPLCKC" description="Bypass Coarse Lock" />
-      <BitField start="7" size="1" name="WAITLOCK" description="Wait Lock" />
-    </Register>
-    <Register start="+0x24" size="4" name="OSCCTRL_DFLLVAL" access="Read/Write" description="DFLL48M Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FINE" description="Fine Value" />
-      <BitField start="10" size="6" name="COARSE" description="Coarse Value" />
-      <BitField start="16" size="16" name="DIFF" description="Multiplication Ratio Difference" />
-    </Register>
-    <Register start="+0x28" size="4" name="OSCCTRL_DFLLMUL" access="Read/Write" description="DFLL48M Multiplier" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MUL" description="DFLL Multiply Factor" />
-      <BitField start="16" size="8" name="FSTEP" description="Fine Maximum Step" />
-      <BitField start="26" size="6" name="CSTEP" description="Coarse Maximum Step" />
-    </Register>
-    <Register start="+0x2C" size="1" name="OSCCTRL_DFLLSYNC" access="Read/Write" description="DFLL48M Synchronization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="ENABLE Synchronization Busy" />
-      <BitField start="2" size="1" name="DFLLCTRLB" description="DFLLCTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="DFLLVAL" description="DFLLVAL Synchronization Busy" />
-      <BitField start="4" size="1" name="DFLLMUL" description="DFLLMUL Synchronization Busy" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="OSCCTRL_DPLLCTRLA0" access="Read/Write" description="DPLL Control A" reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-    </Register>
-    <Register start="+0x30+20" size="1" name="OSCCTRL_DPLLCTRLA1" access="Read/Write" description="DPLL Control A" reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-    </Register>
-    <Register start="+0x34+0" size="4" name="OSCCTRL_DPLLRATIO0" access="Read/Write" description="DPLL Ratio Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="LDR" description="Loop Divider Ratio" />
-      <BitField start="16" size="5" name="LDRFRAC" description="Loop Divider Ratio Fractional Part" />
-    </Register>
-    <Register start="+0x34+20" size="4" name="OSCCTRL_DPLLRATIO1" access="Read/Write" description="DPLL Ratio Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="LDR" description="Loop Divider Ratio" />
-      <BitField start="16" size="5" name="LDRFRAC" description="Loop Divider Ratio Fractional Part" />
-    </Register>
-    <Register start="+0x38+0" size="4" name="OSCCTRL_DPLLCTRLB0" access="Read/Write" description="DPLL Control B" reset_value="0x00000020" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FILTER" description="Proportional Integral Filter Selection" />
-      <BitField start="4" size="1" name="WUF" description="Wake Up Fast" />
-      <BitField start="5" size="3" name="REFCLK" description="Reference Clock Selection">
-        <Enum name="GCLK" start="0x0" description="Dedicated GCLK clock reference" />
-        <Enum name="XOSC32" start="0x1" description="XOSC32K clock reference" />
-        <Enum name="XOSC0" start="0x2" description="XOSC0 clock reference" />
-        <Enum name="XOSC1" start="0x3" description="XOSC1 clock reference" />
-      </BitField>
-      <BitField start="8" size="3" name="LTIME" description="Lock Time">
-        <Enum name="DEFAULT" start="0x0" description="No time-out. Automatic lock" />
-        <Enum name="800US" start="0x4" description="Time-out if no lock within 800us" />
-        <Enum name="900US" start="0x5" description="Time-out if no lock within 900us" />
-        <Enum name="1MS" start="0x6" description="Time-out if no lock within 1ms" />
-        <Enum name="1P1MS" start="0x7" description="Time-out if no lock within 1.1ms" />
-      </BitField>
-      <BitField start="11" size="1" name="LBYPASS" description="Lock Bypass" />
-      <BitField start="12" size="3" name="DCOFILTER" description="Sigma-Delta DCO Filter Selection" />
-      <BitField start="15" size="1" name="DCOEN" description="DCO Filter Enable" />
-      <BitField start="16" size="11" name="DIV" description="Clock Divider" />
-    </Register>
-    <Register start="+0x38+20" size="4" name="OSCCTRL_DPLLCTRLB1" access="Read/Write" description="DPLL Control B" reset_value="0x00000020" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FILTER" description="Proportional Integral Filter Selection" />
-      <BitField start="4" size="1" name="WUF" description="Wake Up Fast" />
-      <BitField start="5" size="3" name="REFCLK" description="Reference Clock Selection">
-        <Enum name="GCLK" start="0x0" description="Dedicated GCLK clock reference" />
-        <Enum name="XOSC32" start="0x1" description="XOSC32K clock reference" />
-        <Enum name="XOSC0" start="0x2" description="XOSC0 clock reference" />
-        <Enum name="XOSC1" start="0x3" description="XOSC1 clock reference" />
-      </BitField>
-      <BitField start="8" size="3" name="LTIME" description="Lock Time">
-        <Enum name="DEFAULT" start="0x0" description="No time-out. Automatic lock" />
-        <Enum name="800US" start="0x4" description="Time-out if no lock within 800us" />
-        <Enum name="900US" start="0x5" description="Time-out if no lock within 900us" />
-        <Enum name="1MS" start="0x6" description="Time-out if no lock within 1ms" />
-        <Enum name="1P1MS" start="0x7" description="Time-out if no lock within 1.1ms" />
-      </BitField>
-      <BitField start="11" size="1" name="LBYPASS" description="Lock Bypass" />
-      <BitField start="12" size="3" name="DCOFILTER" description="Sigma-Delta DCO Filter Selection" />
-      <BitField start="15" size="1" name="DCOEN" description="DCO Filter Enable" />
-      <BitField start="16" size="11" name="DIV" description="Clock Divider" />
-    </Register>
-    <Register start="+0x3C+0" size="4" name="OSCCTRL_DPLLSYNCBUSY0" access="ReadOnly" description="DPLL Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable Synchronization Status" />
-      <BitField start="2" size="1" name="DPLLRATIO" description="DPLL Loop Divider Ratio Synchronization Status" />
-    </Register>
-    <Register start="+0x3C+20" size="4" name="OSCCTRL_DPLLSYNCBUSY1" access="ReadOnly" description="DPLL Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="DPLL Enable Synchronization Status" />
-      <BitField start="2" size="1" name="DPLLRATIO" description="DPLL Loop Divider Ratio Synchronization Status" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="OSCCTRL_DPLLSTATUS0" access="ReadOnly" description="DPLL Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="DPLL Lock Status" />
-      <BitField start="1" size="1" name="CLKRDY" description="DPLL Clock Ready" />
-    </Register>
-    <Register start="+0x40+20" size="4" name="OSCCTRL_DPLLSTATUS1" access="ReadOnly" description="DPLL Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="DPLL Lock Status" />
-      <BitField start="1" size="1" name="CLKRDY" description="DPLL Clock Ready" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="OSC32KCTRL" start="0x40001400" description="32kHz Oscillators Control">
-    <Register start="+0x00" size="4" name="OSC32KCTRL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector Interrupt Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="OSC32KCTRL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready Interrupt Enable" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="OSC32KCTRL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector" />
-    </Register>
-    <Register start="+0x0C" size="4" name="OSC32KCTRL_STATUS" access="ReadOnly" description="Power and Clocks Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="XOSC32KRDY" description="XOSC32K Ready" />
-      <BitField start="2" size="1" name="XOSC32KFAIL" description="XOSC32K Clock Failure Detector" />
-      <BitField start="3" size="1" name="XOSC32KSW" description="XOSC32K Clock switch" />
-    </Register>
-    <Register start="+0x10" size="1" name="OSC32KCTRL_RTCCTRL" access="Read/Write" description="RTC Clock Selection" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RTCSEL" description="RTC Clock Selection">
-        <Enum name="ULP1K" start="0x0" description="1.024kHz from 32kHz internal ULP oscillator" />
-        <Enum name="ULP32K" start="0x1" description="32.768kHz from 32kHz internal ULP oscillator" />
-        <Enum name="XOSC1K" start="0x4" description="1.024kHz from 32.768kHz internal oscillator" />
-        <Enum name="XOSC32K" start="0x5" description="32.768kHz from 32.768kHz external crystal oscillator" />
-      </BitField>
-    </Register>
-    <Register start="+0x14" size="2" name="OSC32KCTRL_XOSC32K" access="Read/Write" description="32kHz External Crystal Oscillator (XOSC32K) Control" reset_value="0x2080" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Oscillator Enable" />
-      <BitField start="2" size="1" name="XTALEN" description="Crystal Oscillator Enable" />
-      <BitField start="3" size="1" name="EN32K" description="32kHz Output Enable" />
-      <BitField start="4" size="1" name="EN1K" description="1kHz Output Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Control" />
-      <BitField start="8" size="3" name="STARTUP" description="Oscillator Start-Up Time" />
-      <BitField start="12" size="1" name="WRTLOCK" description="Write Lock" />
-      <BitField start="13" size="2" name="CGM" description="Control Gain Mode">
-        <Enum name="XT" start="0x1" description="Standard mode" />
-        <Enum name="HS" start="0x2" description="High Speed mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x16" size="1" name="OSC32KCTRL_CFDCTRL" access="Read/Write" description="Clock Failure Detector Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CFDEN" description="Clock Failure Detector Enable" />
-      <BitField start="1" size="1" name="SWBACK" description="Clock Switch Back" />
-      <BitField start="2" size="1" name="CFDPRESC" description="Clock Failure Detector Prescaler" />
-    </Register>
-    <Register start="+0x17" size="1" name="OSC32KCTRL_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CFDEO" description="Clock Failure Detector Event Output Enable" />
-    </Register>
-    <Register start="+0x1C" size="4" name="OSC32KCTRL_OSCULP32K" access="Read/Write" description="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="EN32K" description="Enable Out 32k" />
-      <BitField start="2" size="1" name="EN1K" description="Enable Out 1k" />
-      <BitField start="8" size="6" name="CALIB" description="Oscillator Calibration" />
-      <BitField start="15" size="1" name="WRTLOCK" description="Write Lock" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PAC" start="0x40000000" description="Peripheral Access Controller">
-    <Register start="+0x00" size="4" name="PAC_WRCTRL" access="Read/Write" description="Write control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PERID" description="Peripheral identifier" />
-      <BitField start="16" size="8" name="KEY" description="Peripheral access control key">
-        <Enum name="OFF" start="0x0" description="No action" />
-        <Enum name="CLR" start="0x1" description="Clear protection" />
-        <Enum name="SET" start="0x2" description="Set protection" />
-        <Enum name="SETLCK" start="0x3" description="Set and lock protection" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="PAC_EVCTRL" access="Read/Write" description="Event control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERREO" description="Peripheral acess error event output" />
-    </Register>
-    <Register start="+0x08" size="1" name="PAC_INTENCLR" access="Read/Write" description="Interrupt enable clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERR" description="Peripheral access error interrupt disable" />
-    </Register>
-    <Register start="+0x09" size="1" name="PAC_INTENSET" access="Read/Write" description="Interrupt enable set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERR" description="Peripheral access error interrupt enable" />
-    </Register>
-    <Register start="+0x10" size="4" name="PAC_INTFLAGAHB" access="Read/Write" description="Bridge interrupt flag status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLASH_" description="FLASH" />
-      <BitField start="1" size="1" name="FLASH_ALT_" description="FLASH_ALT" />
-      <BitField start="2" size="1" name="SEEPROM_" description="SEEPROM" />
-      <BitField start="3" size="1" name="RAMCM4S_" description="RAMCM4S" />
-      <BitField start="4" size="1" name="RAMPPPDSU_" description="RAMPPPDSU" />
-      <BitField start="5" size="1" name="RAMDMAWR_" description="RAMDMAWR" />
-      <BitField start="6" size="1" name="RAMDMACICM_" description="RAMDMACICM" />
-      <BitField start="7" size="1" name="HPB0_" description="HPB0" />
-      <BitField start="8" size="1" name="HPB1_" description="HPB1" />
-      <BitField start="9" size="1" name="HPB2_" description="HPB2" />
-      <BitField start="10" size="1" name="HPB3_" description="HPB3" />
-      <BitField start="11" size="1" name="PUKCC_" description="PUKCC" />
-      <BitField start="12" size="1" name="SDHC0_" description="SDHC0" />
-      <BitField start="14" size="1" name="QSPI_" description="QSPI" />
-      <BitField start="15" size="1" name="BKUPRAM_" description="BKUPRAM" />
-    </Register>
-    <Register start="+0x14" size="4" name="PAC_INTFLAGA" access="Read/Write" description="Peripheral interrupt flag status - Bridge A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC_" description="PAC" />
-      <BitField start="1" size="1" name="PM_" description="PM" />
-      <BitField start="2" size="1" name="MCLK_" description="MCLK" />
-      <BitField start="3" size="1" name="RSTC_" description="RSTC" />
-      <BitField start="4" size="1" name="OSCCTRL_" description="OSCCTRL" />
-      <BitField start="5" size="1" name="OSC32KCTRL_" description="OSC32KCTRL" />
-      <BitField start="6" size="1" name="SUPC_" description="SUPC" />
-      <BitField start="7" size="1" name="GCLK_" description="GCLK" />
-      <BitField start="8" size="1" name="WDT_" description="WDT" />
-      <BitField start="9" size="1" name="RTC_" description="RTC" />
-      <BitField start="10" size="1" name="EIC_" description="EIC" />
-      <BitField start="11" size="1" name="FREQM_" description="FREQM" />
-      <BitField start="12" size="1" name="SERCOM0_" description="SERCOM0" />
-      <BitField start="13" size="1" name="SERCOM1_" description="SERCOM1" />
-      <BitField start="14" size="1" name="TC0_" description="TC0" />
-      <BitField start="15" size="1" name="TC1_" description="TC1" />
-    </Register>
-    <Register start="+0x18" size="4" name="PAC_INTFLAGB" access="Read/Write" description="Peripheral interrupt flag status - Bridge B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_" description="USB" />
-      <BitField start="1" size="1" name="DSU_" description="DSU" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL" />
-      <BitField start="3" size="1" name="CMCC_" description="CMCC" />
-      <BitField start="4" size="1" name="PORT_" description="PORT" />
-      <BitField start="5" size="1" name="DMAC_" description="DMAC" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX" />
-      <BitField start="7" size="1" name="EVSYS_" description="EVSYS" />
-      <BitField start="9" size="1" name="SERCOM2_" description="SERCOM2" />
-      <BitField start="10" size="1" name="SERCOM3_" description="SERCOM3" />
-      <BitField start="11" size="1" name="TCC0_" description="TCC0" />
-      <BitField start="12" size="1" name="TCC1_" description="TCC1" />
-      <BitField start="13" size="1" name="TC2_" description="TC2" />
-      <BitField start="14" size="1" name="TC3_" description="TC3" />
-      <BitField start="15" size="1" name="TAL_" description="TAL" />
-      <BitField start="16" size="1" name="RAMECC_" description="RAMECC" />
-    </Register>
-    <Register start="+0x1C" size="4" name="PAC_INTFLAGC" access="Read/Write" description="Peripheral interrupt flag status - Bridge C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="TCC2_" description="TCC2" />
-      <BitField start="4" size="1" name="TCC3_" description="TCC3" />
-      <BitField start="5" size="1" name="TC4_" description="TC4" />
-      <BitField start="6" size="1" name="TC5_" description="TC5" />
-      <BitField start="7" size="1" name="PDEC_" description="PDEC" />
-      <BitField start="8" size="1" name="AC_" description="AC" />
-      <BitField start="9" size="1" name="AES_" description="AES" />
-      <BitField start="10" size="1" name="TRNG_" description="TRNG" />
-      <BitField start="11" size="1" name="ICM_" description="ICM" />
-      <BitField start="12" size="1" name="PUKCC_" description="PUKCC" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI" />
-      <BitField start="14" size="1" name="CCL_" description="CCL" />
-    </Register>
-    <Register start="+0x20" size="4" name="PAC_INTFLAGD" access="Read/Write" description="Peripheral interrupt flag status - Bridge D" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4_" description="SERCOM4" />
-      <BitField start="1" size="1" name="SERCOM5_" description="SERCOM5" />
-      <BitField start="4" size="1" name="TCC4_" description="TCC4" />
-      <BitField start="7" size="1" name="ADC0_" description="ADC0" />
-      <BitField start="8" size="1" name="ADC1_" description="ADC1" />
-      <BitField start="9" size="1" name="DAC_" description="DAC" />
-      <BitField start="10" size="1" name="I2S_" description="I2S" />
-      <BitField start="11" size="1" name="PCC_" description="PCC" />
-    </Register>
-    <Register start="+0x34" size="4" name="PAC_STATUSA" access="ReadOnly" description="Peripheral write protection status - Bridge A" reset_value="0x00010000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC_" description="PAC APB Protect Enable" />
-      <BitField start="1" size="1" name="PM_" description="PM APB Protect Enable" />
-      <BitField start="2" size="1" name="MCLK_" description="MCLK APB Protect Enable" />
-      <BitField start="3" size="1" name="RSTC_" description="RSTC APB Protect Enable" />
-      <BitField start="4" size="1" name="OSCCTRL_" description="OSCCTRL APB Protect Enable" />
-      <BitField start="5" size="1" name="OSC32KCTRL_" description="OSC32KCTRL APB Protect Enable" />
-      <BitField start="6" size="1" name="SUPC_" description="SUPC APB Protect Enable" />
-      <BitField start="7" size="1" name="GCLK_" description="GCLK APB Protect Enable" />
-      <BitField start="8" size="1" name="WDT_" description="WDT APB Protect Enable" />
-      <BitField start="9" size="1" name="RTC_" description="RTC APB Protect Enable" />
-      <BitField start="10" size="1" name="EIC_" description="EIC APB Protect Enable" />
-      <BitField start="11" size="1" name="FREQM_" description="FREQM APB Protect Enable" />
-      <BitField start="12" size="1" name="SERCOM0_" description="SERCOM0 APB Protect Enable" />
-      <BitField start="13" size="1" name="SERCOM1_" description="SERCOM1 APB Protect Enable" />
-      <BitField start="14" size="1" name="TC0_" description="TC0 APB Protect Enable" />
-      <BitField start="15" size="1" name="TC1_" description="TC1 APB Protect Enable" />
-    </Register>
-    <Register start="+0x38" size="4" name="PAC_STATUSB" access="ReadOnly" description="Peripheral write protection status - Bridge B" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_" description="USB APB Protect Enable" />
-      <BitField start="1" size="1" name="DSU_" description="DSU APB Protect Enable" />
-      <BitField start="2" size="1" name="NVMCTRL_" description="NVMCTRL APB Protect Enable" />
-      <BitField start="3" size="1" name="CMCC_" description="CMCC APB Protect Enable" />
-      <BitField start="4" size="1" name="PORT_" description="PORT APB Protect Enable" />
-      <BitField start="5" size="1" name="DMAC_" description="DMAC APB Protect Enable" />
-      <BitField start="6" size="1" name="HMATRIX_" description="HMATRIX APB Protect Enable" />
-      <BitField start="7" size="1" name="EVSYS_" description="EVSYS APB Protect Enable" />
-      <BitField start="9" size="1" name="SERCOM2_" description="SERCOM2 APB Protect Enable" />
-      <BitField start="10" size="1" name="SERCOM3_" description="SERCOM3 APB Protect Enable" />
-      <BitField start="11" size="1" name="TCC0_" description="TCC0 APB Protect Enable" />
-      <BitField start="12" size="1" name="TCC1_" description="TCC1 APB Protect Enable" />
-      <BitField start="13" size="1" name="TC2_" description="TC2 APB Protect Enable" />
-      <BitField start="14" size="1" name="TC3_" description="TC3 APB Protect Enable" />
-      <BitField start="15" size="1" name="TAL_" description="TAL APB Protect Enable" />
-      <BitField start="16" size="1" name="RAMECC_" description="RAMECC APB Protect Enable" />
-    </Register>
-    <Register start="+0x3C" size="4" name="PAC_STATUSC" access="ReadOnly" description="Peripheral write protection status - Bridge C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="3" size="1" name="TCC2_" description="TCC2 APB Protect Enable" />
-      <BitField start="4" size="1" name="TCC3_" description="TCC3 APB Protect Enable" />
-      <BitField start="5" size="1" name="TC4_" description="TC4 APB Protect Enable" />
-      <BitField start="6" size="1" name="TC5_" description="TC5 APB Protect Enable" />
-      <BitField start="7" size="1" name="PDEC_" description="PDEC APB Protect Enable" />
-      <BitField start="8" size="1" name="AC_" description="AC APB Protect Enable" />
-      <BitField start="9" size="1" name="AES_" description="AES APB Protect Enable" />
-      <BitField start="10" size="1" name="TRNG_" description="TRNG APB Protect Enable" />
-      <BitField start="11" size="1" name="ICM_" description="ICM APB Protect Enable" />
-      <BitField start="12" size="1" name="PUKCC_" description="PUKCC APB Protect Enable" />
-      <BitField start="13" size="1" name="QSPI_" description="QSPI APB Protect Enable" />
-      <BitField start="14" size="1" name="CCL_" description="CCL APB Protect Enable" />
-    </Register>
-    <Register start="+0x40" size="4" name="PAC_STATUSD" access="ReadOnly" description="Peripheral write protection status - Bridge D" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4_" description="SERCOM4 APB Protect Enable" />
-      <BitField start="1" size="1" name="SERCOM5_" description="SERCOM5 APB Protect Enable" />
-      <BitField start="4" size="1" name="TCC4_" description="TCC4 APB Protect Enable" />
-      <BitField start="7" size="1" name="ADC0_" description="ADC0 APB Protect Enable" />
-      <BitField start="8" size="1" name="ADC1_" description="ADC1 APB Protect Enable" />
-      <BitField start="9" size="1" name="DAC_" description="DAC APB Protect Enable" />
-      <BitField start="10" size="1" name="I2S_" description="I2S APB Protect Enable" />
-      <BitField start="11" size="1" name="PCC_" description="PCC APB Protect Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PCC" start="0x43002C00" description="Parallel Capture Controller">
-    <Register start="+0x00" size="4" name="PCC_MR" access="Read/Write" description="Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCEN" description="Parallel Capture Enable" />
-      <BitField start="4" size="2" name="DSIZE" description="Data size" />
-      <BitField start="8" size="1" name="SCALE" description="Scale data" />
-      <BitField start="9" size="1" name="ALWYS" description="Always Sampling" />
-      <BitField start="10" size="1" name="HALFS" description="Half Sampling" />
-      <BitField start="11" size="1" name="FRSTS" description="First sample" />
-      <BitField start="16" size="3" name="ISIZE" description="Input Data Size" />
-      <BitField start="30" size="2" name="CID" description="Clear If Disabled" />
-    </Register>
-    <Register start="+0x04" size="4" name="PCC_IER" access="WriteOnly" description="Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Enable" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="PCC_IDR" access="WriteOnly" description="Interrupt Disable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Disable" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x0C" size="4" name="PCC_IMR" access="ReadOnly" description="Interrupt Mask Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Mask" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Mask" />
-    </Register>
-    <Register start="+0x10" size="4" name="PCC_ISR" access="ReadOnly" description="Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRDY" description="Data Ready Interrupt Status" />
-      <BitField start="1" size="1" name="OVRE" description="Overrun Error Interrupt Status" />
-    </Register>
-    <Register start="+0x14" size="4" name="PCC_RHR" access="ReadOnly" description="Reception Holding Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RDATA" description="Reception Data" />
-    </Register>
-    <Register start="+0xE0" size="4" name="PCC_WPMR" access="Read/Write" description="Write Protection Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WPEN" description="Write Protection Enable" />
-      <BitField start="8" size="24" name="WPKEY" description="Write Protection Key" />
-    </Register>
-    <Register start="+0xE4" size="4" name="PCC_WPSR" access="ReadOnly" description="Write Protection Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WPVS" description="Write Protection Violation Source" />
-      <BitField start="8" size="16" name="WPVSRC" description="Write Protection Violation Status" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PDEC" start="0x42001C00" description="Quadrature Decodeur">
-    <Register start="+0x00" size="4" name="PDEC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operation Mode">
-        <Enum name="QDEC" start="0x0" description="QDEC operating mode" />
-        <Enum name="HALL" start="0x1" description="HALL operating mode" />
-        <Enum name="COUNTER" start="0x2" description="COUNTER operating mode" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="8" size="3" name="CONF" description="PDEC Configuration">
-        <Enum name="X4" start="0x0" description="Quadrature decoder direction" />
-        <Enum name="X4S" start="0x1" description="Secure Quadrature decoder direction" />
-        <Enum name="X2" start="0x2" description="Decoder direction" />
-        <Enum name="X2S" start="0x3" description="Secure decoder direction" />
-        <Enum name="AUTOC" start="0x4" description="Auto correction mode" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="14" size="1" name="SWAP" description="PDEC Phase A and B Swap" />
-      <BitField start="15" size="1" name="PEREN" description="Period Enable" />
-      <BitField start="16" size="1" name="PINEN0" description="PDEC Input From Pin 0 Enable" />
-      <BitField start="17" size="1" name="PINEN1" description="PDEC Input From Pin 1 Enable" />
-      <BitField start="18" size="1" name="PINEN2" description="PDEC Input From Pin 2 Enable" />
-      <BitField start="20" size="1" name="PINVEN0" description="IO Pin 0 Invert Enable" />
-      <BitField start="21" size="1" name="PINVEN1" description="IO Pin 1 Invert Enable" />
-      <BitField start="22" size="1" name="PINVEN2" description="IO Pin 2 Invert Enable" />
-      <BitField start="24" size="3" name="ANGULAR" description="Angular Counter Length" />
-      <BitField start="28" size="4" name="MAXCMP" description="Maximum Consecutive Missing Pulses" />
-    </Register>
-    <Register start="+0x04" size="1" name="PDEC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a counter restart or retrigger" />
-        <Enum name="UPDATE" start="0x2" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x3" description="Force a read synchronization of COUNT" />
-        <Enum name="START" start="0x4" description="Start QDEC/HALL" />
-        <Enum name="STOP" start="0x5" description="Stop QDEC/HALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="PDEC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a counter restart or retrigger" />
-        <Enum name="UPDATE" start="0x2" description="Force update of double buffered registers" />
-        <Enum name="READSYNC" start="0x3" description="Force a read synchronization of COUNT" />
-        <Enum name="Start" start="0x4" description="Start QDEC/HALL" />
-        <Enum name="Stop" start="0x5" description="Stop QDEC/HALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="PDEC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-      </BitField>
-      <BitField start="2" size="3" name="EVINV" description="Inverted Event Input Enable" />
-      <BitField start="5" size="3" name="EVEI" description="Event Input Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="ERREO" description="Error  Output Event Enable" />
-      <BitField start="10" size="1" name="DIREO" description="Direction Output Event Enable" />
-      <BitField start="11" size="1" name="VLCEO" description="Velocity Output Event Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="Match Channel 0 Event Output Enable" />
-      <BitField start="13" size="1" name="MCEO1" description="Match Channel 1 Event Output Enable" />
-    </Register>
-    <Register start="+0x08" size="1" name="PDEC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow/Underflow Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Disable" />
-      <BitField start="2" size="1" name="DIR" description="Direction Interrupt Disable" />
-      <BitField start="3" size="1" name="VLC" description="Velocity Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="Channel 0 Compare Match Disable" />
-      <BitField start="5" size="1" name="MC1" description="Channel 1 Compare Match Disable" />
-    </Register>
-    <Register start="+0x09" size="1" name="PDEC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow/Underflow Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="2" size="1" name="DIR" description="Direction Interrupt Enable" />
-      <BitField start="3" size="1" name="VLC" description="Velocity Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="Channel 0 Compare Match Enable" />
-      <BitField start="5" size="1" name="MC1" description="Channel 1 Compare Match Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="PDEC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow/Underflow" />
-      <BitField start="1" size="1" name="ERR" description="Error" />
-      <BitField start="2" size="1" name="DIR" description="Direction Change" />
-      <BitField start="3" size="1" name="VLC" description="Velocity" />
-      <BitField start="4" size="1" name="MC0" description="Channel 0 Compare Match" />
-      <BitField start="5" size="1" name="MC1" description="Channel 1 Compare Match" />
-    </Register>
-    <Register start="+0x0C" size="2" name="PDEC_STATUS" access="Read/Write" description="Status" reset_value="0x0040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="QERR" description="Quadrature Error Flag" />
-      <BitField start="1" size="1" name="IDXERR" description="Index Error Flag" />
-      <BitField start="2" size="1" name="MPERR" description="Missing Pulse Error flag" />
-      <BitField start="4" size="1" name="WINERR" description="Window Error Flag" />
-      <BitField start="5" size="1" name="HERR" description="Hall Error Flag" />
-      <BitField start="6" size="1" name="STOP" description="Stop" />
-      <BitField start="7" size="1" name="DIR" description="Direction Status Flag" />
-      <BitField start="8" size="1" name="PRESCBUFV" description="Prescaler Buffer Valid" />
-      <BitField start="9" size="1" name="FILTERBUFV" description="Filter Buffer Valid" />
-      <BitField start="12" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="13" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-    </Register>
-    <Register start="+0x0F" size="1" name="PDEC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Run Mode" />
-    </Register>
-    <Register start="+0x10" size="4" name="PDEC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Control B Synchronization Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Synchronization Busy" />
-      <BitField start="4" size="1" name="PRESC" description="Prescaler Synchronization Busy" />
-      <BitField start="5" size="1" name="FILTER" description="Filter Synchronization Busy" />
-      <BitField start="6" size="1" name="COUNT" description="Count Synchronization Busy" />
-      <BitField start="7" size="1" name="CC0" description="Compare Channel 0 Synchronization Busy" />
-      <BitField start="8" size="1" name="CC1" description="Compare Channel 1 Synchronization Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="PDEC_PRESC" access="Read/Write" description="Prescaler Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESC" description="Prescaler Value">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-        <Enum name="DIV256" start="0x8" description="Divide by 256" />
-        <Enum name="DIV512" start="0x9" description="Divide by 512" />
-        <Enum name="DIV1024" start="0xa" description="Divide by 1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x15" size="1" name="PDEC_FILTER" access="Read/Write" description="Filter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FILTER" description="Filter Value" />
-    </Register>
-    <Register start="+0x18" size="1" name="PDEC_PRESCBUF" access="Read/Write" description="Prescaler Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PRESCBUF" description="Prescaler Buffer Value">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV32" start="0x5" description="Divide by 32" />
-        <Enum name="DIV64" start="0x6" description="Divide by 64" />
-        <Enum name="DIV128" start="0x7" description="Divide by 128" />
-        <Enum name="DIV256" start="0x8" description="Divide by 256" />
-        <Enum name="DIV512" start="0x9" description="Divide by 512" />
-        <Enum name="DIV1024" start="0xa" description="Divide by 1024" />
-      </BitField>
-    </Register>
-    <Register start="+0x19" size="1" name="PDEC_FILTERBUF" access="Read/Write" description="Filter Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FILTERBUF" description="Filter Buffer Value" />
-    </Register>
-    <Register start="+0x1C" size="4" name="PDEC_COUNT" access="Read/Write" description="Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="PDEC_CC0" access="Read/Write" description="Channel n Compare Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Channel Compare Value" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="PDEC_CC1" access="Read/Write" description="Channel n Compare Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Channel Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="PDEC_CCBUF0" access="Read/Write" description="Channel Compare Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Channel Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="PDEC_CCBUF1" access="Read/Write" description="Channel Compare Buffer Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Channel Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PM" start="0x40000400" description="Power Manager">
-    <Register start="+0x00" size="1" name="PM_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="IORET" description="I/O Retention" />
-    </Register>
-    <Register start="+0x01" size="1" name="PM_SLEEPCFG" access="Read/Write" description="Sleep Configuration" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SLEEPMODE" description="Sleep Mode">
-        <Enum name="IDLE0" start="0x0" description="CPU clock is OFF" />
-        <Enum name="IDLE1" start="0x1" description="AHB clock is OFF" />
-        <Enum name="IDLE2" start="0x2" description="APB clock are OFF" />
-        <Enum name="STANDBY" start="0x4" description="All Clocks are OFF" />
-        <Enum name="HIBERNATE" start="0x5" description="Backup domain is ON as well as some PDRAMs" />
-        <Enum name="BACKUP" start="0x6" description="Only Backup domain is powered ON" />
-        <Enum name="OFF" start="0x7" description="All power domains are powered OFF" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="PM_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEPRDY" description="Sleep Mode Entry Ready Enable" />
-    </Register>
-    <Register start="+0x05" size="1" name="PM_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEPRDY" description="Sleep Mode Entry Ready Enable" />
-    </Register>
-    <Register start="+0x06" size="1" name="PM_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SLEEPRDY" description="Sleep Mode Entry Ready" />
-    </Register>
-    <Register start="+0x08" size="1" name="PM_STDBYCFG" access="Read/Write" description="Standby Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAMCFG" description="Ram Configuration">
-        <Enum name="RET" start="0x0" description="All the RAMs are retained" />
-        <Enum name="PARTIAL" start="0x1" description="Only the first 32K bytes are retained" />
-        <Enum name="OFF" start="0x2" description="All the RAMs are OFF" />
-      </BitField>
-      <BitField start="4" size="2" name="FASTWKUP" description="Fast Wakeup" />
-    </Register>
-    <Register start="+0x09" size="1" name="PM_HIBCFG" access="Read/Write" description="Hibernate Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAMCFG" description="Ram Configuration" />
-      <BitField start="2" size="2" name="BRAMCFG" description="Backup Ram Configuration" />
-    </Register>
-    <Register start="+0x0A" size="1" name="PM_BKUPCFG" access="Read/Write" description="Backup Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRAMCFG" description="Ram Configuration" />
-    </Register>
-    <Register start="+0x12" size="1" name="PM_PWSAKDLY" access="Read/Write" description="Power Switch Acknowledge Delay" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DLYVAL" description="Delay Value" />
-      <BitField start="7" size="1" name="IGNACK" description="Ignore Acknowledge" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PORT" start="0x41008000" description="Port Module">
-    <Register start="+0x00+0" size="4" name="PORT_DIR0" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x00+128" size="4" name="PORT_DIR1" access="Read/Write" description="Data Direction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIR" description="Port Data Direction" />
-    </Register>
-    <Register start="+0x04+0" size="4" name="PORT_DIRCLR0" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x04+128" size="4" name="PORT_DIRCLR1" access="Read/Write" description="Data Direction Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRCLR" description="Port Data Direction Clear" />
-    </Register>
-    <Register start="+0x08+0" size="4" name="PORT_DIRSET0" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x08+128" size="4" name="PORT_DIRSET1" access="Read/Write" description="Data Direction Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRSET" description="Port Data Direction Set" />
-    </Register>
-    <Register start="+0x0C+0" size="4" name="PORT_DIRTGL0" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x0C+128" size="4" name="PORT_DIRTGL1" access="Read/Write" description="Data Direction Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DIRTGL" description="Port Data Direction Toggle" />
-    </Register>
-    <Register start="+0x10+0" size="4" name="PORT_OUT0" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="PORT Data Output Value" />
-    </Register>
-    <Register start="+0x10+128" size="4" name="PORT_OUT1" access="Read/Write" description="Data Output Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUT" description="PORT Data Output Value" />
-    </Register>
-    <Register start="+0x14+0" size="4" name="PORT_OUTCLR0" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="PORT Data Output Value Clear" />
-    </Register>
-    <Register start="+0x14+128" size="4" name="PORT_OUTCLR1" access="Read/Write" description="Data Output Value Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTCLR" description="PORT Data Output Value Clear" />
-    </Register>
-    <Register start="+0x18+0" size="4" name="PORT_OUTSET0" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="PORT Data Output Value Set" />
-    </Register>
-    <Register start="+0x18+128" size="4" name="PORT_OUTSET1" access="Read/Write" description="Data Output Value Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTSET" description="PORT Data Output Value Set" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="PORT_OUTTGL0" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="PORT Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x1C+128" size="4" name="PORT_OUTTGL1" access="Read/Write" description="Data Output Value Toggle" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="OUTTGL" description="PORT Data Output Value Toggle" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="PORT_IN0" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="PORT Data Input Value" />
-    </Register>
-    <Register start="+0x20+128" size="4" name="PORT_IN1" access="ReadOnly" description="Data Input Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IN" description="PORT Data Input Value" />
-    </Register>
-    <Register start="+0x24+0" size="4" name="PORT_CTRL0" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x24+128" size="4" name="PORT_CTRL1" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SAMPLING" description="Input Sampling Mode" />
-    </Register>
-    <Register start="+0x28+0" size="4" name="PORT_WRCONFIG0" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-    <Register start="+0x28+128" size="4" name="PORT_WRCONFIG1" access="WriteOnly" description="Write Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PINMASK" description="Pin Mask for Multiple Pin Configuration" />
-      <BitField start="16" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="17" size="1" name="INEN" description="Input Enable" />
-      <BitField start="18" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="22" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-      <BitField start="24" size="4" name="PMUX" description="Peripheral Multiplexing" />
-      <BitField start="28" size="1" name="WRPMUX" description="Write PMUX" />
-      <BitField start="30" size="1" name="WRPINCFG" description="Write PINCFG" />
-      <BitField start="31" size="1" name="HWSEL" description="Half-Word Select" />
-    </Register>
-    <Register start="+0x2C+0" size="4" name="PORT_EVCTRL0" access="Read/Write" description="Event Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PID0" description="PORT Event Pin Identifier 0" />
-      <BitField start="5" size="2" name="EVACT0" description="PORT Event Action 0">
-        <Enum name="OUT" start="0x0" description="Event output to pin" />
-        <Enum name="SET" start="0x1" description="Set output register of pin on event" />
-        <Enum name="CLR" start="0x2" description="Clear output register of pin on event" />
-        <Enum name="TGL" start="0x3" description="Toggle output register of pin on event" />
-      </BitField>
-      <BitField start="7" size="1" name="PORTEI0" description="PORT Event Input Enable 0" />
-      <BitField start="8" size="5" name="PID1" description="PORT Event Pin Identifier 1" />
-      <BitField start="13" size="2" name="EVACT1" description="PORT Event Action 1" />
-      <BitField start="15" size="1" name="PORTEI1" description="PORT Event Input Enable 1" />
-      <BitField start="16" size="5" name="PID2" description="PORT Event Pin Identifier 2" />
-      <BitField start="21" size="2" name="EVACT2" description="PORT Event Action 2" />
-      <BitField start="23" size="1" name="PORTEI2" description="PORT Event Input Enable 2" />
-      <BitField start="24" size="5" name="PID3" description="PORT Event Pin Identifier 3" />
-      <BitField start="29" size="2" name="EVACT3" description="PORT Event Action 3" />
-      <BitField start="31" size="1" name="PORTEI3" description="PORT Event Input Enable 3" />
-    </Register>
-    <Register start="+0x2C+128" size="4" name="PORT_EVCTRL1" access="Read/Write" description="Event Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PID0" description="PORT Event Pin Identifier 0" />
-      <BitField start="5" size="2" name="EVACT0" description="PORT Event Action 0">
-        <Enum name="OUT" start="0x0" description="Event output to pin" />
-        <Enum name="SET" start="0x1" description="Set output register of pin on event" />
-        <Enum name="CLR" start="0x2" description="Clear output register of pin on event" />
-        <Enum name="TGL" start="0x3" description="Toggle output register of pin on event" />
-      </BitField>
-      <BitField start="7" size="1" name="PORTEI0" description="PORT Event Input Enable 0" />
-      <BitField start="8" size="5" name="PID1" description="PORT Event Pin Identifier 1" />
-      <BitField start="13" size="2" name="EVACT1" description="PORT Event Action 1" />
-      <BitField start="15" size="1" name="PORTEI1" description="PORT Event Input Enable 1" />
-      <BitField start="16" size="5" name="PID2" description="PORT Event Pin Identifier 2" />
-      <BitField start="21" size="2" name="EVACT2" description="PORT Event Action 2" />
-      <BitField start="23" size="1" name="PORTEI2" description="PORT Event Input Enable 2" />
-      <BitField start="24" size="5" name="PID3" description="PORT Event Pin Identifier 3" />
-      <BitField start="29" size="2" name="EVACT3" description="PORT Event Action 3" />
-      <BitField start="31" size="1" name="PORTEI3" description="PORT Event Input Enable 3" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="PORT_PMUX0_0" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="PORT_PMUX0_1" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+2" size="1" name="PORT_PMUX0_2" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+3" size="1" name="PORT_PMUX0_3" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+4" size="1" name="PORT_PMUX0_4" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+5" size="1" name="PORT_PMUX0_5" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+6" size="1" name="PORT_PMUX0_6" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+7" size="1" name="PORT_PMUX0_7" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+8" size="1" name="PORT_PMUX0_8" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+9" size="1" name="PORT_PMUX0_9" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+10" size="1" name="PORT_PMUX0_10" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+11" size="1" name="PORT_PMUX0_11" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+12" size="1" name="PORT_PMUX0_12" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+13" size="1" name="PORT_PMUX0_13" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+14" size="1" name="PORT_PMUX0_14" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x30+15" size="1" name="PORT_PMUX0_15" access="Read/Write" description="Peripheral Multiplexing - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+0" size="1" name="PORT_PMUX1_0" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+1" size="1" name="PORT_PMUX1_1" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+2" size="1" name="PORT_PMUX1_2" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+3" size="1" name="PORT_PMUX1_3" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+4" size="1" name="PORT_PMUX1_4" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+5" size="1" name="PORT_PMUX1_5" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+6" size="1" name="PORT_PMUX1_6" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+7" size="1" name="PORT_PMUX1_7" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+8" size="1" name="PORT_PMUX1_8" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+9" size="1" name="PORT_PMUX1_9" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+10" size="1" name="PORT_PMUX1_10" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+11" size="1" name="PORT_PMUX1_11" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+12" size="1" name="PORT_PMUX1_12" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+13" size="1" name="PORT_PMUX1_13" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+14" size="1" name="PORT_PMUX1_14" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0xb0+15" size="1" name="PORT_PMUX1_15" access="Read/Write" description="Peripheral Multiplexing - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PMUXE" description="Peripheral Multiplexing for Even-Numbered Pin" />
-      <BitField start="4" size="4" name="PMUXO" description="Peripheral Multiplexing for Odd-Numbered Pin" />
-    </Register>
-    <Register start="+0x40+0" size="1" name="PORT_PINCFG0_0" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+1" size="1" name="PORT_PINCFG0_1" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+2" size="1" name="PORT_PINCFG0_2" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+3" size="1" name="PORT_PINCFG0_3" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+4" size="1" name="PORT_PINCFG0_4" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+5" size="1" name="PORT_PINCFG0_5" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+6" size="1" name="PORT_PINCFG0_6" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+7" size="1" name="PORT_PINCFG0_7" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+8" size="1" name="PORT_PINCFG0_8" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+9" size="1" name="PORT_PINCFG0_9" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+10" size="1" name="PORT_PINCFG0_10" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+11" size="1" name="PORT_PINCFG0_11" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+12" size="1" name="PORT_PINCFG0_12" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+13" size="1" name="PORT_PINCFG0_13" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+14" size="1" name="PORT_PINCFG0_14" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+15" size="1" name="PORT_PINCFG0_15" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+16" size="1" name="PORT_PINCFG0_16" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+17" size="1" name="PORT_PINCFG0_17" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+18" size="1" name="PORT_PINCFG0_18" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+19" size="1" name="PORT_PINCFG0_19" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+20" size="1" name="PORT_PINCFG0_20" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+21" size="1" name="PORT_PINCFG0_21" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+22" size="1" name="PORT_PINCFG0_22" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+23" size="1" name="PORT_PINCFG0_23" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+24" size="1" name="PORT_PINCFG0_24" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+25" size="1" name="PORT_PINCFG0_25" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+26" size="1" name="PORT_PINCFG0_26" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+27" size="1" name="PORT_PINCFG0_27" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+28" size="1" name="PORT_PINCFG0_28" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+29" size="1" name="PORT_PINCFG0_29" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+30" size="1" name="PORT_PINCFG0_30" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0x40+31" size="1" name="PORT_PINCFG0_31" access="Read/Write" description="Pin Configuration - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+0" size="1" name="PORT_PINCFG1_0" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+1" size="1" name="PORT_PINCFG1_1" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+2" size="1" name="PORT_PINCFG1_2" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+3" size="1" name="PORT_PINCFG1_3" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+4" size="1" name="PORT_PINCFG1_4" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+5" size="1" name="PORT_PINCFG1_5" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+6" size="1" name="PORT_PINCFG1_6" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+7" size="1" name="PORT_PINCFG1_7" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+8" size="1" name="PORT_PINCFG1_8" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+9" size="1" name="PORT_PINCFG1_9" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+10" size="1" name="PORT_PINCFG1_10" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+11" size="1" name="PORT_PINCFG1_11" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+12" size="1" name="PORT_PINCFG1_12" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+13" size="1" name="PORT_PINCFG1_13" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+14" size="1" name="PORT_PINCFG1_14" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+15" size="1" name="PORT_PINCFG1_15" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+16" size="1" name="PORT_PINCFG1_16" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+17" size="1" name="PORT_PINCFG1_17" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+18" size="1" name="PORT_PINCFG1_18" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+19" size="1" name="PORT_PINCFG1_19" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+20" size="1" name="PORT_PINCFG1_20" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+21" size="1" name="PORT_PINCFG1_21" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+22" size="1" name="PORT_PINCFG1_22" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+23" size="1" name="PORT_PINCFG1_23" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+24" size="1" name="PORT_PINCFG1_24" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+25" size="1" name="PORT_PINCFG1_25" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+26" size="1" name="PORT_PINCFG1_26" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+27" size="1" name="PORT_PINCFG1_27" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+28" size="1" name="PORT_PINCFG1_28" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+29" size="1" name="PORT_PINCFG1_29" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+30" size="1" name="PORT_PINCFG1_30" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-    <Register start="+0xc0+31" size="1" name="PORT_PINCFG1_31" access="Read/Write" description="Pin Configuration - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMUXEN" description="Peripheral Multiplexer Enable" />
-      <BitField start="1" size="1" name="INEN" description="Input Enable" />
-      <BitField start="2" size="1" name="PULLEN" description="Pull Enable" />
-      <BitField start="6" size="1" name="DRVSTR" description="Output Driver Strength Selection" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QSPI" start="0x42003400" description="Quad SPI interface">
-    <Register start="+0x00" size="4" name="QSPI_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="24" size="1" name="LASTXFER" description="Last Transfer" />
-    </Register>
-    <Register start="+0x04" size="4" name="QSPI_CTRLB" access="Read/Write" description="Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MODE" description="Serial Memory Mode">
-        <Enum name="SPI" start="0x0" description="SPI operating mode" />
-        <Enum name="MEMORY" start="0x1" description="Serial Memory operating mode" />
-      </BitField>
-      <BitField start="1" size="1" name="LOOPEN" description="Local Loopback Enable" />
-      <BitField start="2" size="1" name="WDRBT" description="Wait Data Read Before Transfer" />
-      <BitField start="3" size="1" name="SMEMREG" description="Serial Memory reg" />
-      <BitField start="4" size="2" name="CSMODE" description="Chip Select Mode">
-        <Enum name="NORELOAD" start="0x0" description="The chip select is deasserted if TD has not been reloaded before the end of the current transfer." />
-        <Enum name="LASTXFER" start="0x1" description="The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred." />
-        <Enum name="SYSTEMATICALLY" start="0x2" description="The chip select is deasserted systematically after each transfer." />
-      </BitField>
-      <BitField start="8" size="4" name="DATALEN" description="Data Length">
-        <Enum name="8BITS" start="0x0" description="8-bits transfer" />
-        <Enum name="9BITS" start="0x1" description="9 bits transfer" />
-        <Enum name="10BITS" start="0x2" description="10-bits transfer" />
-        <Enum name="11BITS" start="0x3" description="11-bits transfer" />
-        <Enum name="12BITS" start="0x4" description="12-bits transfer" />
-        <Enum name="13BITS" start="0x5" description="13-bits transfer" />
-        <Enum name="14BITS" start="0x6" description="14-bits transfer" />
-        <Enum name="15BITS" start="0x7" description="15-bits transfer" />
-        <Enum name="16BITS" start="0x8" description="16-bits transfer" />
-      </BitField>
-      <BitField start="16" size="8" name="DLYBCT" description="Delay Between Consecutive Transfers" />
-      <BitField start="24" size="8" name="DLYCS" description="Minimum Inactive CS Delay" />
-    </Register>
-    <Register start="+0x08" size="4" name="QSPI_BAUD" access="Read/Write" description="Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="1" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="8" size="8" name="BAUD" description="Serial Clock Baud Rate" />
-      <BitField start="16" size="8" name="DLYBS" description="Delay Before SCK" />
-    </Register>
-    <Register start="+0x0C" size="4" name="QSPI_RXDATA" access="ReadOnly" description="Receive Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Receive Data" />
-    </Register>
-    <Register start="+0x10" size="4" name="QSPI_TXDATA" access="WriteOnly" description="Transmit Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Transmit Data" />
-    </Register>
-    <Register start="+0x14" size="4" name="QSPI_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXC" description="Receive Data Register Full Interrupt Disable" />
-      <BitField start="1" size="1" name="DRE" description="Transmit Data Register Empty Interrupt Disable" />
-      <BitField start="2" size="1" name="TXC" description="Transmission Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="ERROR" description="Overrun Error Interrupt Disable" />
-      <BitField start="8" size="1" name="CSRISE" description="Chip Select Rise Interrupt Disable" />
-      <BitField start="10" size="1" name="INSTREND" description="Instruction End Interrupt Disable" />
-    </Register>
-    <Register start="+0x18" size="4" name="QSPI_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXC" description="Receive Data Register Full Interrupt Enable" />
-      <BitField start="1" size="1" name="DRE" description="Transmit Data Register Empty Interrupt Enable" />
-      <BitField start="2" size="1" name="TXC" description="Transmission Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="ERROR" description="Overrun Error Interrupt Enable" />
-      <BitField start="8" size="1" name="CSRISE" description="Chip Select Rise Interrupt Enable" />
-      <BitField start="10" size="1" name="INSTREND" description="Instruction End Interrupt Enable" />
-    </Register>
-    <Register start="+0x1C" size="4" name="QSPI_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXC" description="Receive Data Register Full" />
-      <BitField start="1" size="1" name="DRE" description="Transmit Data Register Empty" />
-      <BitField start="2" size="1" name="TXC" description="Transmission Complete" />
-      <BitField start="3" size="1" name="ERROR" description="Overrun Error" />
-      <BitField start="8" size="1" name="CSRISE" description="Chip Select Rise" />
-      <BitField start="10" size="1" name="INSTREND" description="Instruction End" />
-    </Register>
-    <Register start="+0x20" size="4" name="QSPI_STATUS" access="ReadOnly" description="Status Register" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="9" size="1" name="CSSTATUS" description="Chip Select" />
-    </Register>
-    <Register start="+0x30" size="4" name="QSPI_INSTRADDR" access="Read/Write" description="Instruction Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="Instruction Address" />
-    </Register>
-    <Register start="+0x34" size="4" name="QSPI_INSTRCTRL" access="Read/Write" description="Instruction Code" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="INSTR" description="Instruction Code" />
-      <BitField start="16" size="8" name="OPTCODE" description="Option Code" />
-    </Register>
-    <Register start="+0x38" size="4" name="QSPI_INSTRFRAME" access="Read/Write" description="Instruction Frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WIDTH" description="Instruction Code, Address, Option Code and Data Width">
-        <Enum name="SINGLE_BIT_SPI" start="0x0" description="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI" />
-        <Enum name="DUAL_OUTPUT" start="0x1" description="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI" />
-        <Enum name="QUAD_OUTPUT" start="0x2" description="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI" />
-        <Enum name="DUAL_IO" start="0x3" description="Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI" />
-        <Enum name="QUAD_IO" start="0x4" description="Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI" />
-        <Enum name="DUAL_CMD" start="0x5" description="Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI" />
-        <Enum name="QUAD_CMD" start="0x6" description="Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI" />
-      </BitField>
-      <BitField start="4" size="1" name="INSTREN" description="Instruction Enable" />
-      <BitField start="5" size="1" name="ADDREN" description="Address Enable" />
-      <BitField start="6" size="1" name="OPTCODEEN" description="Option Enable" />
-      <BitField start="7" size="1" name="DATAEN" description="Data Enable" />
-      <BitField start="8" size="2" name="OPTCODELEN" description="Option Code Length">
-        <Enum name="1BIT" start="0x0" description="1-bit length option code" />
-        <Enum name="2BITS" start="0x1" description="2-bits length option code" />
-        <Enum name="4BITS" start="0x2" description="4-bits length option code" />
-        <Enum name="8BITS" start="0x3" description="8-bits length option code" />
-      </BitField>
-      <BitField start="10" size="1" name="ADDRLEN" description="Address Length">
-        <Enum name="24BITS" start="0x0" description="24-bits address length" />
-        <Enum name="32BITS" start="0x1" description="32-bits address length" />
-      </BitField>
-      <BitField start="12" size="2" name="TFRTYPE" description="Data Transfer Type">
-        <Enum name="READ" start="0x0" description="Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible." />
-        <Enum name="READMEMORY" start="0x1" description="Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible." />
-        <Enum name="WRITE" start="0x2" description="Write transfer into the serial memory.Scrambling is not performed." />
-        <Enum name="WRITEMEMORY" start="0x3" description="Write data transfer into the serial memory.If enabled, scrambling is performed." />
-      </BitField>
-      <BitField start="14" size="1" name="CRMODE" description="Continuous Read Mode" />
-      <BitField start="15" size="1" name="DDREN" description="Double Data Rate Enable" />
-      <BitField start="16" size="5" name="DUMMYLEN" description="Dummy Cycles Length" />
-    </Register>
-    <Register start="+0x40" size="4" name="QSPI_SCRAMBCTRL" access="Read/Write" description="Scrambling Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Scrambling/Unscrambling Enable" />
-      <BitField start="1" size="1" name="RANDOMDIS" description="Scrambling/Unscrambling Random Value Disable" />
-    </Register>
-    <Register start="+0x44" size="4" name="QSPI_SCRAMBKEY" access="WriteOnly" description="Scrambling Key" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="KEY" description="Scrambling User Key" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RAMECC" start="0x41020000" description="RAM ECC">
-    <Register start="+0x0" size="1" name="RAMECC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SINGLEE" description="Single Bit ECC Error Interrupt Enable Clear" />
-      <BitField start="1" size="1" name="DUALE" description="Dual Bit ECC Error Interrupt Enable Clear" />
-    </Register>
-    <Register start="+0x1" size="1" name="RAMECC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SINGLEE" description="Single Bit ECC Error Interrupt Enable Set" />
-      <BitField start="1" size="1" name="DUALE" description="Dual Bit ECC Error Interrupt Enable Set" />
-    </Register>
-    <Register start="+0x2" size="1" name="RAMECC_INTFLAG" access="Read/Write" description="Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SINGLEE" description="Single Bit ECC Error Interrupt" />
-      <BitField start="1" size="1" name="DUALE" description="Dual Bit ECC Error Interrupt" />
-    </Register>
-    <Register start="+0x3" size="1" name="RAMECC_STATUS" access="ReadOnly" description="Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ECCDIS" description="ECC Disable" />
-    </Register>
-    <Register start="+0x4" size="4" name="RAMECC_ERRADDR" access="ReadOnly" description="Error Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="ERRADDR" description="Error Address" />
-    </Register>
-    <Register start="+0xF" size="1" name="RAMECC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ECCDIS" description="ECC Disable" />
-      <BitField start="1" size="1" name="ECCELOG" description="ECC Error Log" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RSTC" start="0x40000C00" description="Reset Controller">
-    <Register start="+0x00" size="1" name="RSTC_RCAUSE" access="ReadOnly" description="Reset Cause" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POR" description="Power On Reset" />
-      <BitField start="1" size="1" name="BODCORE" description="Brown Out CORE Detector Reset" />
-      <BitField start="2" size="1" name="BODVDD" description="Brown Out VDD Detector Reset" />
-      <BitField start="3" size="1" name="NVM" description="NVM Reset" />
-      <BitField start="4" size="1" name="EXT" description="External Reset" />
-      <BitField start="5" size="1" name="WDT" description="Watchdog Reset" />
-      <BitField start="6" size="1" name="SYST" description="System Reset Request" />
-      <BitField start="7" size="1" name="BACKUP" description="Backup Reset" />
-    </Register>
-    <Register start="+0x02" size="1" name="RSTC_BKUPEXIT" access="ReadOnly" description="Backup Exit Source" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RTC" description="Real Timer Counter Interrupt" />
-      <BitField start="2" size="1" name="BBPS" description="Battery Backup Power Switch" />
-      <BitField start="7" size="1" name="HIB" description="Hibernate" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE0)" start="0x40002400" description="Real-Time Counter">
-    <Register start="+0x00" size="2" name="RTC_CTRLA" access="Read/Write" description="MODE0 Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="OFF" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV1" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xb" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-      <BitField start="13" size="1" name="BKTRST" description="BKUP Registers Reset On Tamper Enable" />
-      <BitField start="14" size="1" name="GPTRST" description="GP Registers Reset On Tamper Enable" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Read Synchronization Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_CTRLB" access="Read/Write" description="MODE0 Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GP0EN" description="General Purpose 0 Enable" />
-      <BitField start="1" size="1" name="GP2EN" description="General Purpose 2 Enable" />
-      <BitField start="4" size="1" name="DEBMAJ" description="Debouncer Majority Enable" />
-      <BitField start="5" size="1" name="DEBASYNC" description="Debouncer Asynchronous Enable" />
-      <BitField start="6" size="1" name="RTCOUT" description="RTC Output Enable" />
-      <BitField start="7" size="1" name="DMAEN" description="DMA Enable" />
-      <BitField start="8" size="3" name="DEBF" description="Debounce Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_DEB = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_DEB = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_DEB = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_DEB = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_DEB = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_DEB = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_DEB = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_DEB = CLK_RTC/256" />
-      </BitField>
-      <BitField start="12" size="3" name="ACTF" description="Active Layer Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_OUT = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_OUT = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_OUT = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_OUT = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_OUT = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_OUT = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_OUT = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_OUT = CLK_RTC/256" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="RTC_EVCTRL" access="Read/Write" description="MODE0 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="9" size="1" name="CMPEO1" description="Compare 1 Event Output Enable" />
-      <BitField start="14" size="1" name="TAMPEREO" description="Tamper Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-      <BitField start="16" size="1" name="TAMPEVEI" description="Tamper Event Input Enable" />
-    </Register>
-    <Register start="+0x08" size="2" name="RTC_INTENCLR" access="Read/Write" description="MODE0 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="2" name="RTC_INTENSET" access="Read/Write" description="MODE0 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="RTC_INTFLAG" access="Read/Write" description="MODE0 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper" />
-      <BitField start="15" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x0E" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_SYNCBUSY" access="ReadOnly" description="MODE0 Synchronization Busy Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Bit Busy" />
-      <BitField start="2" size="1" name="FREQCORR" description="FREQCORR Register Busy" />
-      <BitField start="3" size="1" name="COUNT" description="COUNT Register Busy" />
-      <BitField start="5" size="1" name="COMP0" description="COMP 0 Register Busy" />
-      <BitField start="6" size="1" name="COMP1" description="COMP 1 Register Busy" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Synchronization Enable Bit Busy" />
-      <BitField start="16" size="1" name="GP0" description="General Purpose 0 Register Busy" />
-      <BitField start="17" size="1" name="GP1" description="General Purpose 1 Register Busy" />
-      <BitField start="18" size="1" name="GP2" description="General Purpose 2 Register Busy" />
-      <BitField start="19" size="1" name="GP3" description="General Purpose 3 Register Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x18" size="4" name="RTC_COUNT" access="Read/Write" description="MODE0 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="RTC_COMP0" access="Read/Write" description="MODE0 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+4" size="4" name="RTC_COMP1" access="Read/Write" description="MODE0 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="RTC_GP0" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+4" size="4" name="RTC_GP1" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+8" size="4" name="RTC_GP2" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+12" size="4" name="RTC_GP3" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x60" size="4" name="RTC_TAMPCTRL" access="Read/Write" description="Tamper Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IN0ACT" description="Tamper Input 0 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN0 to OUT" />
-      </BitField>
-      <BitField start="2" size="2" name="IN1ACT" description="Tamper Input 1 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN1 to OUT" />
-      </BitField>
-      <BitField start="4" size="2" name="IN2ACT" description="Tamper Input 2 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN2 to OUT" />
-      </BitField>
-      <BitField start="6" size="2" name="IN3ACT" description="Tamper Input 3 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN3 to OUT" />
-      </BitField>
-      <BitField start="8" size="2" name="IN4ACT" description="Tamper Input 4 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN4 to OUT" />
-      </BitField>
-      <BitField start="16" size="1" name="TAMLVL0" description="Tamper Level Select 0" />
-      <BitField start="17" size="1" name="TAMLVL1" description="Tamper Level Select 1" />
-      <BitField start="18" size="1" name="TAMLVL2" description="Tamper Level Select 2" />
-      <BitField start="19" size="1" name="TAMLVL3" description="Tamper Level Select 3" />
-      <BitField start="20" size="1" name="TAMLVL4" description="Tamper Level Select 4" />
-      <BitField start="24" size="1" name="DEBNC0" description="Debouncer Enable 0" />
-      <BitField start="25" size="1" name="DEBNC1" description="Debouncer Enable 1" />
-      <BitField start="26" size="1" name="DEBNC2" description="Debouncer Enable 2" />
-      <BitField start="27" size="1" name="DEBNC3" description="Debouncer Enable 3" />
-      <BitField start="28" size="1" name="DEBNC4" description="Debouncer Enable 4" />
-    </Register>
-    <Register start="+0x64" size="4" name="RTC_TIMESTAMP" access="ReadOnly" description="MODE0 Timestamp" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Count Timestamp Value" />
-    </Register>
-    <Register start="+0x68" size="4" name="RTC_TAMPID" access="Read/Write" description="Tamper ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TAMPID0" description="Tamper Input 0 Detected" />
-      <BitField start="1" size="1" name="TAMPID1" description="Tamper Input 1 Detected" />
-      <BitField start="2" size="1" name="TAMPID2" description="Tamper Input 2 Detected" />
-      <BitField start="3" size="1" name="TAMPID3" description="Tamper Input 3 Detected" />
-      <BitField start="4" size="1" name="TAMPID4" description="Tamper Input 4 Detected" />
-      <BitField start="31" size="1" name="TAMPEVT" description="Tamper Event Detected" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="RTC_BKUP0" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="RTC_BKUP1" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="RTC_BKUP2" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="RTC_BKUP3" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="RTC_BKUP4" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="RTC_BKUP5" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="RTC_BKUP6" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="RTC_BKUP7" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE1)" start="0x40002400" description="Real-Time Counter">
-    <Register start="+0x00" size="2" name="RTC_CTRLA" access="Read/Write" description="MODE1 Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="OFF" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV1" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xb" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-      <BitField start="13" size="1" name="BKTRST" description="BKUP Registers Reset On Tamper Enable" />
-      <BitField start="14" size="1" name="GPTRST" description="GP Registers Reset On Tamper Enable" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Read Synchronization Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_CTRLB" access="Read/Write" description="MODE1 Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GP0EN" description="General Purpose 0 Enable" />
-      <BitField start="1" size="1" name="GP2EN" description="General Purpose 2 Enable" />
-      <BitField start="4" size="1" name="DEBMAJ" description="Debouncer Majority Enable" />
-      <BitField start="5" size="1" name="DEBASYNC" description="Debouncer Asynchronous Enable" />
-      <BitField start="6" size="1" name="RTCOUT" description="RTC Output Enable" />
-      <BitField start="7" size="1" name="DMAEN" description="DMA Enable" />
-      <BitField start="8" size="3" name="DEBF" description="Debounce Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_DEB = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_DEB = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_DEB = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_DEB = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_DEB = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_DEB = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_DEB = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_DEB = CLK_RTC/256" />
-      </BitField>
-      <BitField start="12" size="3" name="ACTF" description="Active Layer Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_OUT = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_OUT = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_OUT = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_OUT = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_OUT = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_OUT = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_OUT = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_OUT = CLK_RTC/256" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="RTC_EVCTRL" access="Read/Write" description="MODE1 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="CMPEO0" description="Compare 0 Event Output Enable" />
-      <BitField start="9" size="1" name="CMPEO1" description="Compare 1 Event Output Enable" />
-      <BitField start="10" size="1" name="CMPEO2" description="Compare 2 Event Output Enable" />
-      <BitField start="11" size="1" name="CMPEO3" description="Compare 3 Event Output Enable" />
-      <BitField start="14" size="1" name="TAMPEREO" description="Tamper Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-      <BitField start="16" size="1" name="TAMPEVEI" description="Tamper Event Input Enable" />
-    </Register>
-    <Register start="+0x08" size="2" name="RTC_INTENCLR" access="Read/Write" description="MODE1 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="10" size="1" name="CMP2" description="Compare 2 Interrupt Enable" />
-      <BitField start="11" size="1" name="CMP3" description="Compare 3 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="2" name="RTC_INTENSET" access="Read/Write" description="MODE1 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1 Interrupt Enable" />
-      <BitField start="10" size="1" name="CMP2" description="Compare 2 Interrupt Enable" />
-      <BitField start="11" size="1" name="CMP3" description="Compare 3 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="RTC_INTFLAG" access="Read/Write" description="MODE1 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7" />
-      <BitField start="8" size="1" name="CMP0" description="Compare 0" />
-      <BitField start="9" size="1" name="CMP1" description="Compare 1" />
-      <BitField start="10" size="1" name="CMP2" description="Compare 2" />
-      <BitField start="11" size="1" name="CMP3" description="Compare 3" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper" />
-      <BitField start="15" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x0E" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_SYNCBUSY" access="ReadOnly" description="MODE1 Synchronization Busy Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Bit Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Bit Busy" />
-      <BitField start="2" size="1" name="FREQCORR" description="FREQCORR Register Busy" />
-      <BitField start="3" size="1" name="COUNT" description="COUNT Register Busy" />
-      <BitField start="4" size="1" name="PER" description="PER Register Busy" />
-      <BitField start="5" size="1" name="COMP0" description="COMP 0 Register Busy" />
-      <BitField start="6" size="1" name="COMP1" description="COMP 1 Register Busy" />
-      <BitField start="7" size="1" name="COMP2" description="COMP 2 Register Busy" />
-      <BitField start="8" size="1" name="COMP3" description="COMP 3 Register Busy" />
-      <BitField start="15" size="1" name="COUNTSYNC" description="Count Synchronization Enable Bit Busy" />
-      <BitField start="16" size="1" name="GP0" description="General Purpose 0 Register Busy" />
-      <BitField start="17" size="1" name="GP1" description="General Purpose 1 Register Busy" />
-      <BitField start="18" size="1" name="GP2" description="General Purpose 2 Register Busy" />
-      <BitField start="19" size="1" name="GP3" description="General Purpose 3 Register Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x18" size="2" name="RTC_COUNT" access="Read/Write" description="MODE1 Counter Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C" size="2" name="RTC_PER" access="Read/Write" description="MODE1 Counter Period" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PER" description="Counter Period" />
-    </Register>
-    <Register start="+0x20+0" size="2" name="RTC_COMP0" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+2" size="2" name="RTC_COMP1" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+4" size="2" name="RTC_COMP2" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x20+6" size="2" name="RTC_COMP3" access="Read/Write" description="MODE1 Compare n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COMP" description="Compare Value" />
-    </Register>
-    <Register start="+0x40+0" size="4" name="RTC_GP0" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+4" size="4" name="RTC_GP1" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+8" size="4" name="RTC_GP2" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+12" size="4" name="RTC_GP3" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x60" size="4" name="RTC_TAMPCTRL" access="Read/Write" description="Tamper Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IN0ACT" description="Tamper Input 0 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN0 to OUT" />
-      </BitField>
-      <BitField start="2" size="2" name="IN1ACT" description="Tamper Input 1 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN1 to OUT" />
-      </BitField>
-      <BitField start="4" size="2" name="IN2ACT" description="Tamper Input 2 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN2 to OUT" />
-      </BitField>
-      <BitField start="6" size="2" name="IN3ACT" description="Tamper Input 3 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN3 to OUT" />
-      </BitField>
-      <BitField start="8" size="2" name="IN4ACT" description="Tamper Input 4 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN4 to OUT" />
-      </BitField>
-      <BitField start="16" size="1" name="TAMLVL0" description="Tamper Level Select 0" />
-      <BitField start="17" size="1" name="TAMLVL1" description="Tamper Level Select 1" />
-      <BitField start="18" size="1" name="TAMLVL2" description="Tamper Level Select 2" />
-      <BitField start="19" size="1" name="TAMLVL3" description="Tamper Level Select 3" />
-      <BitField start="20" size="1" name="TAMLVL4" description="Tamper Level Select 4" />
-      <BitField start="24" size="1" name="DEBNC0" description="Debouncer Enable 0" />
-      <BitField start="25" size="1" name="DEBNC1" description="Debouncer Enable 1" />
-      <BitField start="26" size="1" name="DEBNC2" description="Debouncer Enable 2" />
-      <BitField start="27" size="1" name="DEBNC3" description="Debouncer Enable 3" />
-      <BitField start="28" size="1" name="DEBNC4" description="Debouncer Enable 4" />
-    </Register>
-    <Register start="+0x64" size="4" name="RTC_TIMESTAMP" access="ReadOnly" description="MODE1 Timestamp" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Count Timestamp Value" />
-    </Register>
-    <Register start="+0x68" size="4" name="RTC_TAMPID" access="Read/Write" description="Tamper ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TAMPID0" description="Tamper Input 0 Detected" />
-      <BitField start="1" size="1" name="TAMPID1" description="Tamper Input 1 Detected" />
-      <BitField start="2" size="1" name="TAMPID2" description="Tamper Input 2 Detected" />
-      <BitField start="3" size="1" name="TAMPID3" description="Tamper Input 3 Detected" />
-      <BitField start="4" size="1" name="TAMPID4" description="Tamper Input 4 Detected" />
-      <BitField start="31" size="1" name="TAMPEVT" description="Tamper Event Detected" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="RTC_BKUP0" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="RTC_BKUP1" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="RTC_BKUP2" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="RTC_BKUP3" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="RTC_BKUP4" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="RTC_BKUP5" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="RTC_BKUP6" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="RTC_BKUP7" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC (MODE2)" start="0x40002400" description="Real-Time Counter">
-    <Register start="+0x00" size="2" name="RTC_CTRLA" access="Read/Write" description="MODE2 Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Operating Mode">
-        <Enum name="COUNT32" start="0x0" description="Mode 0: 32-bit Counter" />
-        <Enum name="COUNT16" start="0x1" description="Mode 1: 16-bit Counter" />
-        <Enum name="CLOCK" start="0x2" description="Mode 2: Clock/Calendar" />
-      </BitField>
-      <BitField start="6" size="1" name="CLKREP" description="Clock Representation" />
-      <BitField start="7" size="1" name="MATCHCLR" description="Clear on Match" />
-      <BitField start="8" size="4" name="PRESCALER" description="Prescaler">
-        <Enum name="OFF" start="0x0" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV1" start="0x1" description="CLK_RTC_CNT = GCLK_RTC/1" />
-        <Enum name="DIV2" start="0x2" description="CLK_RTC_CNT = GCLK_RTC/2" />
-        <Enum name="DIV4" start="0x3" description="CLK_RTC_CNT = GCLK_RTC/4" />
-        <Enum name="DIV8" start="0x4" description="CLK_RTC_CNT = GCLK_RTC/8" />
-        <Enum name="DIV16" start="0x5" description="CLK_RTC_CNT = GCLK_RTC/16" />
-        <Enum name="DIV32" start="0x6" description="CLK_RTC_CNT = GCLK_RTC/32" />
-        <Enum name="DIV64" start="0x7" description="CLK_RTC_CNT = GCLK_RTC/64" />
-        <Enum name="DIV128" start="0x8" description="CLK_RTC_CNT = GCLK_RTC/128" />
-        <Enum name="DIV256" start="0x9" description="CLK_RTC_CNT = GCLK_RTC/256" />
-        <Enum name="DIV512" start="0xa" description="CLK_RTC_CNT = GCLK_RTC/512" />
-        <Enum name="DIV1024" start="0xb" description="CLK_RTC_CNT = GCLK_RTC/1024" />
-      </BitField>
-      <BitField start="13" size="1" name="BKTRST" description="BKUP Registers Reset On Tamper Enable" />
-      <BitField start="14" size="1" name="GPTRST" description="GP Registers Reset On Tamper Enable" />
-      <BitField start="15" size="1" name="CLOCKSYNC" description="Clock Read Synchronization Enable" />
-    </Register>
-    <Register start="+0x02" size="2" name="RTC_CTRLB" access="Read/Write" description="MODE2 Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GP0EN" description="General Purpose 0 Enable" />
-      <BitField start="1" size="1" name="GP2EN" description="General Purpose 2 Enable" />
-      <BitField start="4" size="1" name="DEBMAJ" description="Debouncer Majority Enable" />
-      <BitField start="5" size="1" name="DEBASYNC" description="Debouncer Asynchronous Enable" />
-      <BitField start="6" size="1" name="RTCOUT" description="RTC Output Enable" />
-      <BitField start="7" size="1" name="DMAEN" description="DMA Enable" />
-      <BitField start="8" size="3" name="DEBF" description="Debounce Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_DEB = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_DEB = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_DEB = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_DEB = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_DEB = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_DEB = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_DEB = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_DEB = CLK_RTC/256" />
-      </BitField>
-      <BitField start="12" size="3" name="ACTF" description="Active Layer Freqnuency">
-        <Enum name="DIV2" start="0x0" description="CLK_RTC_OUT = CLK_RTC/2" />
-        <Enum name="DIV4" start="0x1" description="CLK_RTC_OUT = CLK_RTC/4" />
-        <Enum name="DIV8" start="0x2" description="CLK_RTC_OUT = CLK_RTC/8" />
-        <Enum name="DIV16" start="0x3" description="CLK_RTC_OUT = CLK_RTC/16" />
-        <Enum name="DIV32" start="0x4" description="CLK_RTC_OUT = CLK_RTC/32" />
-        <Enum name="DIV64" start="0x5" description="CLK_RTC_OUT = CLK_RTC/64" />
-        <Enum name="DIV128" start="0x6" description="CLK_RTC_OUT = CLK_RTC/128" />
-        <Enum name="DIV256" start="0x7" description="CLK_RTC_OUT = CLK_RTC/256" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="4" name="RTC_EVCTRL" access="Read/Write" description="MODE2 Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PEREO0" description="Periodic Interval 0 Event Output Enable" />
-      <BitField start="1" size="1" name="PEREO1" description="Periodic Interval 1 Event Output Enable" />
-      <BitField start="2" size="1" name="PEREO2" description="Periodic Interval 2 Event Output Enable" />
-      <BitField start="3" size="1" name="PEREO3" description="Periodic Interval 3 Event Output Enable" />
-      <BitField start="4" size="1" name="PEREO4" description="Periodic Interval 4 Event Output Enable" />
-      <BitField start="5" size="1" name="PEREO5" description="Periodic Interval 5 Event Output Enable" />
-      <BitField start="6" size="1" name="PEREO6" description="Periodic Interval 6 Event Output Enable" />
-      <BitField start="7" size="1" name="PEREO7" description="Periodic Interval 7 Event Output Enable" />
-      <BitField start="8" size="1" name="ALARMEO0" description="Alarm 0 Event Output Enable" />
-      <BitField start="9" size="1" name="ALARMEO1" description="Alarm 1 Event Output Enable" />
-      <BitField start="14" size="1" name="TAMPEREO" description="Tamper Event Output Enable" />
-      <BitField start="15" size="1" name="OVFEO" description="Overflow Event Output Enable" />
-      <BitField start="16" size="1" name="TAMPEVEI" description="Tamper Event Input Enable" />
-    </Register>
-    <Register start="+0x08" size="2" name="RTC_INTENCLR" access="Read/Write" description="MODE2 Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Interrupt Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Interrupt Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Interrupt Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Interrupt Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Interrupt Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Interrupt Enable" />
-      <BitField start="8" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="ALARM1" description="Alarm 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="2" name="RTC_INTENSET" access="Read/Write" description="MODE2 Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0 Enable" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1 Enable" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2 Enable" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3 Enable" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4 Enable" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5 Enable" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6 Enable" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7 Enable" />
-      <BitField start="8" size="1" name="ALARM0" description="Alarm 0 Interrupt Enable" />
-      <BitField start="9" size="1" name="ALARM1" description="Alarm 1 Interrupt Enable" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper Enable" />
-      <BitField start="15" size="1" name="OVF" description="Overflow Interrupt Enable" />
-    </Register>
-    <Register start="+0x0C" size="2" name="RTC_INTFLAG" access="Read/Write" description="MODE2 Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PER0" description="Periodic Interval 0" />
-      <BitField start="1" size="1" name="PER1" description="Periodic Interval 1" />
-      <BitField start="2" size="1" name="PER2" description="Periodic Interval 2" />
-      <BitField start="3" size="1" name="PER3" description="Periodic Interval 3" />
-      <BitField start="4" size="1" name="PER4" description="Periodic Interval 4" />
-      <BitField start="5" size="1" name="PER5" description="Periodic Interval 5" />
-      <BitField start="6" size="1" name="PER6" description="Periodic Interval 6" />
-      <BitField start="7" size="1" name="PER7" description="Periodic Interval 7" />
-      <BitField start="8" size="1" name="ALARM0" description="Alarm 0" />
-      <BitField start="9" size="1" name="ALARM1" description="Alarm 1" />
-      <BitField start="14" size="1" name="TAMPER" description="Tamper" />
-      <BitField start="15" size="1" name="OVF" description="Overflow" />
-    </Register>
-    <Register start="+0x0E" size="1" name="RTC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="RTC_SYNCBUSY" access="ReadOnly" description="MODE2 Synchronization Busy Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Bit Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Bit Busy" />
-      <BitField start="2" size="1" name="FREQCORR" description="FREQCORR Register Busy" />
-      <BitField start="3" size="1" name="CLOCK" description="CLOCK Register Busy" />
-      <BitField start="5" size="1" name="ALARM0" description="ALARM 0 Register Busy" />
-      <BitField start="6" size="1" name="ALARM1" description="ALARM 1 Register Busy" />
-      <BitField start="11" size="1" name="MASK0" description="MASK 0 Register Busy" />
-      <BitField start="12" size="1" name="MASK1" description="MASK 1 Register Busy" />
-      <BitField start="15" size="1" name="CLOCKSYNC" description="Clock Synchronization Enable Bit Busy" />
-      <BitField start="16" size="1" name="GP0" description="General Purpose 0 Register Busy" />
-      <BitField start="17" size="1" name="GP1" description="General Purpose 1 Register Busy" />
-      <BitField start="18" size="1" name="GP2" description="General Purpose 2 Register Busy" />
-      <BitField start="19" size="1" name="GP3" description="General Purpose 3 Register Busy" />
-    </Register>
-    <Register start="+0x14" size="1" name="RTC_FREQCORR" access="Read/Write" description="Frequency Correction" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="VALUE" description="Correction Value" />
-      <BitField start="7" size="1" name="SIGN" description="Correction Sign" />
-    </Register>
-    <Register start="+0x18" size="4" name="RTC_CLOCK" access="Read/Write" description="MODE2 Clock Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="AM" start="0x0" description="AM when CLKREP in 12-hour" />
-        <Enum name="PM" start="0x10" description="PM when CLKREP in 12-hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x20+0" size="4" name="RTC_ALARM0" access="Read/Write" description="MODE2 Alarm n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="AM" start="0x0" description="Morning hour" />
-        <Enum name="PM" start="0x10" description="Afternoon hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x20+8" size="4" name="RTC_ALARM1" access="Read/Write" description="MODE2 Alarm n Value" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute" />
-      <BitField start="12" size="5" name="HOUR" description="Hour">
-        <Enum name="AM" start="0x0" description="Morning hour" />
-        <Enum name="PM" start="0x10" description="Afternoon hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day" />
-      <BitField start="22" size="4" name="MONTH" description="Month" />
-      <BitField start="26" size="6" name="YEAR" description="Year" />
-    </Register>
-    <Register start="+0x24+0" size="1" name="RTC_MASK0" access="Read/Write" description="MODE2 Alarm n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SEL" description="Alarm Mask Selection">
-        <Enum name="OFF" start="0x0" description="Alarm Disabled" />
-        <Enum name="SS" start="0x1" description="Match seconds only" />
-        <Enum name="MMSS" start="0x2" description="Match seconds and minutes only" />
-        <Enum name="HHMMSS" start="0x3" description="Match seconds, minutes, and hours only" />
-        <Enum name="DDHHMMSS" start="0x4" description="Match seconds, minutes, hours, and days only" />
-        <Enum name="MMDDHHMMSS" start="0x5" description="Match seconds, minutes, hours, days, and months only" />
-        <Enum name="YYMMDDHHMMSS" start="0x6" description="Match seconds, minutes, hours, days, months, and years" />
-      </BitField>
-    </Register>
-    <Register start="+0x24+8" size="1" name="RTC_MASK1" access="Read/Write" description="MODE2 Alarm n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="SEL" description="Alarm Mask Selection">
-        <Enum name="OFF" start="0x0" description="Alarm Disabled" />
-        <Enum name="SS" start="0x1" description="Match seconds only" />
-        <Enum name="MMSS" start="0x2" description="Match seconds and minutes only" />
-        <Enum name="HHMMSS" start="0x3" description="Match seconds, minutes, and hours only" />
-        <Enum name="DDHHMMSS" start="0x4" description="Match seconds, minutes, hours, and days only" />
-        <Enum name="MMDDHHMMSS" start="0x5" description="Match seconds, minutes, hours, days, and months only" />
-        <Enum name="YYMMDDHHMMSS" start="0x6" description="Match seconds, minutes, hours, days, months, and years" />
-      </BitField>
-    </Register>
-    <Register start="+0x40+0" size="4" name="RTC_GP0" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+4" size="4" name="RTC_GP1" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+8" size="4" name="RTC_GP2" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x40+12" size="4" name="RTC_GP3" access="Read/Write" description="General Purpose" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="GP" description="General Purpose" />
-    </Register>
-    <Register start="+0x60" size="4" name="RTC_TAMPCTRL" access="Read/Write" description="Tamper Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="IN0ACT" description="Tamper Input 0 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN0 to OUT" />
-      </BitField>
-      <BitField start="2" size="2" name="IN1ACT" description="Tamper Input 1 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN1 to OUT" />
-      </BitField>
-      <BitField start="4" size="2" name="IN2ACT" description="Tamper Input 2 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN2 to OUT" />
-      </BitField>
-      <BitField start="6" size="2" name="IN3ACT" description="Tamper Input 3 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN3 to OUT" />
-      </BitField>
-      <BitField start="8" size="2" name="IN4ACT" description="Tamper Input 4 Action">
-        <Enum name="OFF" start="0x0" description="Off (Disabled)" />
-        <Enum name="WAKE" start="0x1" description="Wake without timestamp" />
-        <Enum name="CAPTURE" start="0x2" description="Capture timestamp" />
-        <Enum name="ACTL" start="0x3" description="Compare IN4 to OUT" />
-      </BitField>
-      <BitField start="16" size="1" name="TAMLVL0" description="Tamper Level Select 0" />
-      <BitField start="17" size="1" name="TAMLVL1" description="Tamper Level Select 1" />
-      <BitField start="18" size="1" name="TAMLVL2" description="Tamper Level Select 2" />
-      <BitField start="19" size="1" name="TAMLVL3" description="Tamper Level Select 3" />
-      <BitField start="20" size="1" name="TAMLVL4" description="Tamper Level Select 4" />
-      <BitField start="24" size="1" name="DEBNC0" description="Debouncer Enable 0" />
-      <BitField start="25" size="1" name="DEBNC1" description="Debouncer Enable 1" />
-      <BitField start="26" size="1" name="DEBNC2" description="Debouncer Enable 2" />
-      <BitField start="27" size="1" name="DEBNC3" description="Debouncer Enable 3" />
-      <BitField start="28" size="1" name="DEBNC4" description="Debouncer Enable 4" />
-    </Register>
-    <Register start="+0x64" size="4" name="RTC_TIMESTAMP" access="ReadOnly" description="MODE2 Timestamp" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECOND" description="Second Timestamp Value" />
-      <BitField start="6" size="6" name="MINUTE" description="Minute Timestamp Value" />
-      <BitField start="12" size="5" name="HOUR" description="Hour Timestamp Value">
-        <Enum name="AM" start="0x0" description="AM when CLKREP in 12-hour" />
-        <Enum name="PM" start="0x10" description="PM when CLKREP in 12-hour" />
-      </BitField>
-      <BitField start="17" size="5" name="DAY" description="Day Timestamp Value" />
-      <BitField start="22" size="4" name="MONTH" description="Month Timestamp Value" />
-      <BitField start="26" size="6" name="YEAR" description="Year Timestamp Value" />
-    </Register>
-    <Register start="+0x68" size="4" name="RTC_TAMPID" access="Read/Write" description="Tamper ID" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TAMPID0" description="Tamper Input 0 Detected" />
-      <BitField start="1" size="1" name="TAMPID1" description="Tamper Input 1 Detected" />
-      <BitField start="2" size="1" name="TAMPID2" description="Tamper Input 2 Detected" />
-      <BitField start="3" size="1" name="TAMPID3" description="Tamper Input 3 Detected" />
-      <BitField start="4" size="1" name="TAMPID4" description="Tamper Input 4 Detected" />
-      <BitField start="31" size="1" name="TAMPEVT" description="Tamper Event Detected" />
-    </Register>
-    <Register start="+0x80+0" size="4" name="RTC_BKUP0" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+4" size="4" name="RTC_BKUP1" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+8" size="4" name="RTC_BKUP2" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+12" size="4" name="RTC_BKUP3" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+16" size="4" name="RTC_BKUP4" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+20" size="4" name="RTC_BKUP5" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+24" size="4" name="RTC_BKUP6" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-    <Register start="+0x80+28" size="4" name="RTC_BKUP7" access="Read/Write" description="Backup" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BKUP" description="Backup" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDHC0" start="0x45000000" description="SD/MMC Host Controller">
-    <Register start="+0x000" size="4" name="SDHC_SSAR" access="Read/Write" description="SDMA System Address / Argument 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="SDMA System Address" />
-    </Register>
-    <Register start="+0x000" size="4" name="SDHC_SSAR_CMD23" access="Read/Write" description="SDMA System Address / Argument 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ARG2" description="Argument 2" />
-    </Register>
-    <Register start="+0x004" size="2" name="SDHC_BSR" access="Read/Write" description="Block Size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BLOCKSIZE" description="Transfer Block Size" />
-      <BitField start="12" size="3" name="BOUNDARY" description="SDMA Buffer Boundary">
-        <Enum name="4K" start="0x0" description="4k bytes" />
-        <Enum name="8K" start="0x1" description="8k bytes" />
-        <Enum name="16K" start="0x2" description="16k bytes" />
-        <Enum name="32K" start="0x3" description="32k bytes" />
-        <Enum name="64K" start="0x4" description="64k bytes" />
-        <Enum name="128K" start="0x5" description="128k bytes" />
-        <Enum name="256K" start="0x6" description="256k bytes" />
-        <Enum name="512K" start="0x7" description="512k bytes" />
-      </BitField>
-    </Register>
-    <Register start="+0x006" size="2" name="SDHC_BCR" access="Read/Write" description="Block Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BCNT" description="Blocks Count for Current Transfer" />
-    </Register>
-    <Register start="+0x008" size="4" name="SDHC_ARG1R" access="Read/Write" description="Argument 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ARG" description="Argument 1" />
-    </Register>
-    <Register start="+0x00C" size="2" name="SDHC_TMR" access="Read/Write" description="Transfer Mode" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMAEN" description="DMA Enable">
-        <Enum name="DISABLE" start="0x0" description="No data transfer or Non DMA data transfer" />
-        <Enum name="ENABLE" start="0x1" description="DMA data transfer" />
-      </BitField>
-      <BitField start="1" size="1" name="BCEN" description="Block Count Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="2" name="ACMDEN" description="Auto Command Enable">
-        <Enum name="DISABLED" start="0x0" description="Auto Command Disabled" />
-        <Enum name="CMD12" start="0x1" description="Auto CMD12 Enable" />
-        <Enum name="CMD23" start="0x2" description="Auto CMD23 Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="DTDSEL" description="Data Transfer Direction Selection">
-        <Enum name="WRITE" start="0x0" description="Write (Host to Card)" />
-        <Enum name="READ" start="0x1" description="Read (Card to Host)" />
-      </BitField>
-      <BitField start="5" size="1" name="MSBSEL" description="Multi/Single Block Selection">
-        <Enum name="SINGLE" start="0x0" description="Single Block" />
-        <Enum name="MULTIPLE" start="0x1" description="Multiple Block" />
-      </BitField>
-    </Register>
-    <Register start="+0x00E" size="2" name="SDHC_CR" access="Read/Write" description="Command" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESPTYP" description="Response Type">
-        <Enum name="NONE" start="0x0" description="No response" />
-        <Enum name="136_BIT" start="0x1" description="136-bit response" />
-        <Enum name="48_BIT" start="0x2" description="48-bit response" />
-        <Enum name="48_BIT_BUSY" start="0x3" description="48-bit response check busy after response" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDCCEN" description="Command CRC Check Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="4" size="1" name="CMDICEN" description="Command Index Check Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="DPSEL" description="Data Present Select">
-        <Enum name="NO_DATA" start="0x0" description="No Data Present" />
-        <Enum name="DATA" start="0x1" description="Data Present" />
-      </BitField>
-      <BitField start="6" size="2" name="CMDTYP" description="Command Type">
-        <Enum name="NORMAL" start="0x0" description="Other commands" />
-        <Enum name="SUSPEND" start="0x1" description="CMD52 for writing Bus Suspend in CCCR" />
-        <Enum name="RESUME" start="0x2" description="CMD52 for writing Function Select in CCCR" />
-        <Enum name="ABORT" start="0x3" description="CMD12, CMD52 for writing I/O Abort in CCCR" />
-      </BitField>
-      <BitField start="8" size="6" name="CMDIDX" description="Command Index" />
-    </Register>
-    <Register start="+0x010+0" size="4" name="SDHC_RR0" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x010+4" size="4" name="SDHC_RR1" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x010+8" size="4" name="SDHC_RR2" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x010+12" size="4" name="SDHC_RR3" access="ReadOnly" description="Response" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMDRESP" description="Command Response" />
-    </Register>
-    <Register start="+0x020" size="4" name="SDHC_BDPR" access="Read/Write" description="Buffer Data Port" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BUFDATA" description="Buffer Data" />
-    </Register>
-    <Register start="+0x024" size="4" name="SDHC_PSR" access="ReadOnly" description="Present State" reset_value="0x00F80000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDINHC" description="Command Inhibit (CMD)">
-        <Enum name="CAN" start="0x0" description="Can issue command using only CMD line" />
-        <Enum name="CANNOT" start="0x1" description="Cannot issue command" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDINHD" description="Command Inhibit (DAT)">
-        <Enum name="CAN" start="0x0" description="Can issue command which uses the DAT line" />
-        <Enum name="CANNOT" start="0x1" description="Cannot issue command which uses the DAT line" />
-      </BitField>
-      <BitField start="2" size="1" name="DLACT" description="DAT Line Active">
-        <Enum name="INACTIVE" start="0x0" description="DAT Line Inactive" />
-        <Enum name="ACTIVE" start="0x1" description="DAT Line Active" />
-      </BitField>
-      <BitField start="3" size="1" name="RTREQ" description="Re-Tuning Request">
-        <Enum name="OK" start="0x0" description="Fixed or well-tuned sampling clock" />
-        <Enum name="REQUIRED" start="0x1" description="Sampling clock needs re-tuning" />
-      </BitField>
-      <BitField start="8" size="1" name="WTACT" description="Write Transfer Active">
-        <Enum name="NO" start="0x0" description="No valid data" />
-        <Enum name="YES" start="0x1" description="Transferring data" />
-      </BitField>
-      <BitField start="9" size="1" name="RTACT" description="Read Transfer Active">
-        <Enum name="NO" start="0x0" description="No valid data" />
-        <Enum name="YES" start="0x1" description="Transferring data" />
-      </BitField>
-      <BitField start="10" size="1" name="BUFWREN" description="Buffer Write Enable">
-        <Enum name="DISABLE" start="0x0" description="Write disable" />
-        <Enum name="ENABLE" start="0x1" description="Write enable" />
-      </BitField>
-      <BitField start="11" size="1" name="BUFRDEN" description="Buffer Read Enable">
-        <Enum name="DISABLE" start="0x0" description="Read disable" />
-        <Enum name="ENABLE" start="0x1" description="Read enable" />
-      </BitField>
-      <BitField start="16" size="1" name="CARDINS" description="Card Inserted">
-        <Enum name="NO" start="0x0" description="Reset or Debouncing or No Card" />
-        <Enum name="YES" start="0x1" description="Card inserted" />
-      </BitField>
-      <BitField start="17" size="1" name="CARDSS" description="Card State Stable">
-        <Enum name="NO" start="0x0" description="Reset or Debouncing" />
-        <Enum name="YES" start="0x1" description="No Card or Insered" />
-      </BitField>
-      <BitField start="18" size="1" name="CARDDPL" description="Card Detect Pin Level">
-        <Enum name="NO" start="0x0" description="No card present (SDCD#=1)" />
-        <Enum name="YES" start="0x1" description="Card present (SDCD#=0)" />
-      </BitField>
-      <BitField start="19" size="1" name="WRPPL" description="Write Protect Pin Level">
-        <Enum name="PROTECTED" start="0x0" description="Write protected (SDWP#=0)" />
-        <Enum name="ENABLED" start="0x1" description="Write enabled (SDWP#=1)" />
-      </BitField>
-      <BitField start="20" size="4" name="DATLL" description="DAT[3:0] Line Level" />
-      <BitField start="24" size="1" name="CMDLL" description="CMD Line Level" />
-    </Register>
-    <Register start="+0x028" size="1" name="SDHC_HC1R" access="Read/Write" description="Host Control 1" reset_value="0xE00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LEDCTRL" description="LED Control">
-        <Enum name="OFF" start="0x0" description="LED off" />
-        <Enum name="ON" start="0x1" description="LED on" />
-      </BitField>
-      <BitField start="1" size="1" name="DW" description="Data Width">
-        <Enum name="1BIT" start="0x0" description="1-bit mode" />
-        <Enum name="4BIT" start="0x1" description="4-bit mode" />
-      </BitField>
-      <BitField start="2" size="1" name="HSEN" description="High Speed Enable">
-        <Enum name="NORMAL" start="0x0" description="Normal Speed mode" />
-        <Enum name="HIGH" start="0x1" description="High Speed mode" />
-      </BitField>
-      <BitField start="3" size="2" name="DMASEL" description="DMA Select">
-        <Enum name="SDMA" start="0x0" description="SDMA is selected" />
-        <Enum name="32BIT" start="0x2" description="32-bit Address ADMA2 is selected" />
-      </BitField>
-      <BitField start="6" size="1" name="CARDDTL" description="Card Detect Test Level">
-        <Enum name="NO" start="0x0" description="No Card" />
-        <Enum name="YES" start="0x1" description="Card Inserted" />
-      </BitField>
-      <BitField start="7" size="1" name="CARDDSEL" description="Card Detect Signal Selection">
-        <Enum name="NORMAL" start="0x0" description="SDCD# is selected (for normal use)" />
-        <Enum name="TEST" start="0x1" description="The Card Select Test Level is selected (for test purpose)" />
-      </BitField>
-    </Register>
-    <Register start="+0x028" size="1" name="SDHC_HC1R_EMMC" access="Read/Write" description="Host Control 1" reset_value="0xE00" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="DW" description="Data Width">
-        <Enum name="1BIT" start="0x0" description="1-bit mode" />
-        <Enum name="4BIT" start="0x1" description="4-bit mode" />
-      </BitField>
-      <BitField start="2" size="1" name="HSEN" description="High Speed Enable">
-        <Enum name="NORMAL" start="0x0" description="Normal Speed mode" />
-        <Enum name="HIGH" start="0x1" description="High Speed mode" />
-      </BitField>
-      <BitField start="3" size="2" name="DMASEL" description="DMA Select">
-        <Enum name="SDMA" start="0x0" description="SDMA is selected" />
-        <Enum name="32BIT" start="0x2" description="32-bit Address ADMA2 is selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x029" size="1" name="SDHC_PCR" access="Read/Write" description="Power Control" reset_value="0x0E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDBPWR" description="SD Bus Power">
-        <Enum name="OFF" start="0x0" description="Power off" />
-        <Enum name="ON" start="0x1" description="Power on" />
-      </BitField>
-      <BitField start="1" size="3" name="SDBVSEL" description="SD Bus Voltage Select">
-        <Enum name="1V8" start="0x5" description="1.8V (Typ.)" />
-        <Enum name="3V0" start="0x6" description="3.0V (Typ.)" />
-        <Enum name="3V3" start="0x7" description="3.3V (Typ.)" />
-      </BitField>
-    </Register>
-    <Register start="+0x02A" size="1" name="SDHC_BGCR" access="Read/Write" description="Block Gap Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STPBGR" description="Stop at Block Gap Request">
-        <Enum name="TRANSFER" start="0x0" description="Transfer" />
-        <Enum name="STOP" start="0x1" description="Stop" />
-      </BitField>
-      <BitField start="1" size="1" name="CONTR" description="Continue Request">
-        <Enum name="GO_ON" start="0x0" description="Not affected" />
-        <Enum name="RESTART" start="0x1" description="Restart" />
-      </BitField>
-      <BitField start="2" size="1" name="RWCTRL" description="Read Wait Control">
-        <Enum name="DISABLE" start="0x0" description="Disable Read Wait Control" />
-        <Enum name="ENABLE" start="0x1" description="Enable Read Wait Control" />
-      </BitField>
-      <BitField start="3" size="1" name="INTBG" description="Interrupt at Block Gap">
-        <Enum name="DISABLED" start="0x0" description="Disabled" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x02A" size="1" name="SDHC_BGCR_EMMC" access="Read/Write" description="Block Gap Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STPBGR" description="Stop at Block Gap Request">
-        <Enum name="TRANSFER" start="0x0" description="Transfer" />
-        <Enum name="STOP" start="0x1" description="Stop" />
-      </BitField>
-      <BitField start="1" size="1" name="CONTR" description="Continue Request">
-        <Enum name="GO_ON" start="0x0" description="Not affected" />
-        <Enum name="RESTART" start="0x1" description="Restart" />
-      </BitField>
-    </Register>
-    <Register start="+0x02B" size="1" name="SDHC_WCR" access="Read/Write" description="Wakeup Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WKENCINT" description="Wakeup Event Enable on Card Interrupt">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="1" size="1" name="WKENCINS" description="Wakeup Event Enable on Card Insertion">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="2" size="1" name="WKENCREM" description="Wakeup Event Enable on Card Removal">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-    </Register>
-    <Register start="+0x02C" size="2" name="SDHC_CCR" access="Read/Write" description="Clock Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTCLKEN" description="Internal Clock Enable">
-        <Enum name="OFF" start="0x0" description="Stop" />
-        <Enum name="ON" start="0x1" description="Oscillate" />
-      </BitField>
-      <BitField start="1" size="1" name="INTCLKS" description="Internal Clock Stable">
-        <Enum name="NOT_READY" start="0x0" description="Not Ready" />
-        <Enum name="READY" start="0x1" description="Ready" />
-      </BitField>
-      <BitField start="2" size="1" name="SDCLKEN" description="SD Clock Enable">
-        <Enum name="DISABLE" start="0x0" description="Disable" />
-        <Enum name="ENABLE" start="0x1" description="Enable" />
-      </BitField>
-      <BitField start="5" size="1" name="CLKGSEL" description="Clock Generator Select">
-        <Enum name="DIV" start="0x0" description="Divided Clock Mode" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Mode" />
-      </BitField>
-      <BitField start="6" size="2" name="USDCLKFSEL" description="Upper Bits of SDCLK Frequency Select" />
-      <BitField start="8" size="8" name="SDCLKFSEL" description="SDCLK Frequency Select" />
-    </Register>
-    <Register start="+0x02E" size="1" name="SDHC_TCR" access="Read/Write" description="Timeout Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DTCVAL" description="Data Timeout Counter Value" />
-    </Register>
-    <Register start="+0x02F" size="1" name="SDHC_SRR" access="Read/Write" description="Software Reset" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRSTALL" description="Software Reset For All">
-        <Enum name="WORK" start="0x0" description="Work" />
-        <Enum name="RESET" start="0x1" description="Reset" />
-      </BitField>
-      <BitField start="1" size="1" name="SWRSTCMD" description="Software Reset For CMD Line">
-        <Enum name="WORK" start="0x0" description="Work" />
-        <Enum name="RESET" start="0x1" description="Reset" />
-      </BitField>
-      <BitField start="2" size="1" name="SWRSTDAT" description="Software Reset For DAT Line">
-        <Enum name="WORK" start="0x0" description="Work" />
-        <Enum name="RESET" start="0x1" description="Reset" />
-      </BitField>
-    </Register>
-    <Register start="+0x030" size="2" name="SDHC_NISTR" access="Read/Write" description="Normal Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete">
-        <Enum name="NO" start="0x0" description="No command complete" />
-        <Enum name="YES" start="0x1" description="Command complete" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete">
-        <Enum name="NO" start="0x0" description="Not complete" />
-        <Enum name="YES" start="0x1" description="Command execution is completed" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event">
-        <Enum name="NO" start="0x0" description="No Block Gap Event" />
-        <Enum name="STOP" start="0x1" description="Transaction stopped at block gap" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt">
-        <Enum name="NO" start="0x0" description="No DMA Interrupt" />
-        <Enum name="YES" start="0x1" description="DMA Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready">
-        <Enum name="NO" start="0x0" description="Not ready to write buffer" />
-        <Enum name="YES" start="0x1" description="Ready to write buffer" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready">
-        <Enum name="NO" start="0x0" description="Not ready to read buffer" />
-        <Enum name="YES" start="0x1" description="Ready to read buffer" />
-      </BitField>
-      <BitField start="6" size="1" name="CINS" description="Card Insertion">
-        <Enum name="NO" start="0x0" description="Card state stable or Debouncing" />
-        <Enum name="YES" start="0x1" description="Card inserted" />
-      </BitField>
-      <BitField start="7" size="1" name="CREM" description="Card Removal">
-        <Enum name="NO" start="0x0" description="Card state stable or Debouncing" />
-        <Enum name="YES" start="0x1" description="Card Removed" />
-      </BitField>
-      <BitField start="8" size="1" name="CINT" description="Card Interrupt">
-        <Enum name="NO" start="0x0" description="No Card Interrupt" />
-        <Enum name="YES" start="0x1" description="Generate Card Interrupt" />
-      </BitField>
-      <BitField start="15" size="1" name="ERRINT" description="Error Interrupt">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x030" size="2" name="SDHC_NISTR_EMMC" access="Read/Write" description="Normal Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete">
-        <Enum name="NO" start="0x0" description="No command complete" />
-        <Enum name="YES" start="0x1" description="Command complete" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete">
-        <Enum name="NO" start="0x0" description="Not complete" />
-        <Enum name="YES" start="0x1" description="Command execution is completed" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event">
-        <Enum name="NO" start="0x0" description="No Block Gap Event" />
-        <Enum name="STOP" start="0x1" description="Transaction stopped at block gap" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt">
-        <Enum name="NO" start="0x0" description="No DMA Interrupt" />
-        <Enum name="YES" start="0x1" description="DMA Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready">
-        <Enum name="NO" start="0x0" description="Not ready to write buffer" />
-        <Enum name="YES" start="0x1" description="Ready to write buffer" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready">
-        <Enum name="NO" start="0x0" description="Not ready to read buffer" />
-        <Enum name="YES" start="0x1" description="Ready to read buffer" />
-      </BitField>
-      <BitField start="14" size="1" name="BOOTAR" description="Boot Acknowledge Received" />
-      <BitField start="15" size="1" name="ERRINT" description="Error Interrupt">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x032" size="2" name="SDHC_EISTR" access="Read/Write" description="Error Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="CRC Error Generated" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="End Bit Error Generated" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Power Fail" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x032" size="2" name="SDHC_EISTR_EMMC" access="Read/Write" description="Error Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="CRC Error Generated" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="End Bit Error Generated" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Power Fail" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Boot Acknowledge Error">
-        <Enum name="0" start="0x0" description="FIFO contains at least one byte" />
-        <Enum name="1" start="0x1" description="FIFO is empty" />
-      </BitField>
-    </Register>
-    <Register start="+0x034" size="2" name="SDHC_NISTER" access="Read/Write" description="Normal Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CINS" description="Card Insertion Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CREM" description="Card Removal Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CINT" description="Card Interrupt Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x034" size="2" name="SDHC_NISTER_EMMC" access="Read/Write" description="Normal Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BOOTAR" description="Boot Acknowledge Received Status Enable" />
-    </Register>
-    <Register start="+0x036" size="2" name="SDHC_EISTER" access="Read/Write" description="Error Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x036" size="2" name="SDHC_EISTER_EMMC" access="Read/Write" description="Error Interrupt Status Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Status Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Boot Acknowledge Error Status Enable" />
-    </Register>
-    <Register start="+0x038" size="2" name="SDHC_NISIER" access="Read/Write" description="Normal Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="CINS" description="Card Insertion Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CREM" description="Card Removal Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="CINT" description="Card Interrupt Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x038" size="2" name="SDHC_NISIER_EMMC" access="Read/Write" description="Normal Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDC" description="Command Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="TRFC" description="Transfer Complete Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="BLKGE" description="Block Gap Event Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="DMAINT" description="DMA Interrupt Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="BWRRDY" description="Buffer Write Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="BRDRDY" description="Buffer Read Ready Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="14" size="1" name="BOOTAR" description="Boot Acknowledge Received Signal Enable" />
-    </Register>
-    <Register start="+0x03A" size="2" name="SDHC_EISIER" access="Read/Write" description="Error Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x03A" size="2" name="SDHC_EISIER_EMMC" access="Read/Write" description="Error Interrupt Signal Enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Command Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Command CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Command End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Command Index Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Data Timeout Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Data CRC Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Data End Bit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Current Limit Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Auto CMD Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="ADMA Error Signal Enable">
-        <Enum name="MASKED" start="0x0" description="Masked" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Boot Acknowledge Error Signal Enable" />
-    </Register>
-    <Register start="+0x03C" size="2" name="SDHC_ACESR" access="ReadOnly" description="Auto CMD Error Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACMD12NE" description="Auto CMD12 Not Executed">
-        <Enum name="EXEC" start="0x0" description="Executed" />
-        <Enum name="NOT_EXEC" start="0x1" description="Not executed" />
-      </BitField>
-      <BitField start="1" size="1" name="ACMDTEO" description="Auto CMD Timeout Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="Timeout" />
-      </BitField>
-      <BitField start="2" size="1" name="ACMDCRC" description="Auto CMD CRC Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="CRC Error Generated" />
-      </BitField>
-      <BitField start="3" size="1" name="ACMDEND" description="Auto CMD End Bit Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="End Bit Error Generated" />
-      </BitField>
-      <BitField start="4" size="1" name="ACMDIDX" description="Auto CMD Index Error">
-        <Enum name="NO" start="0x0" description="No error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-      <BitField start="7" size="1" name="CMDNI" description="Command not Issued By Auto CMD12 Error">
-        <Enum name="OK" start="0x0" description="No error" />
-        <Enum name="NOT_ISSUED" start="0x1" description="Not Issued" />
-      </BitField>
-    </Register>
-    <Register start="+0x03E" size="2" name="SDHC_HC2R" access="Read/Write" description="Host Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="UHSMS" description="UHS Mode Select">
-        <Enum name="SDR12" start="0x0" description="SDR12" />
-        <Enum name="SDR25" start="0x1" description="SDR25" />
-        <Enum name="SDR50" start="0x2" description="SDR50" />
-        <Enum name="SDR104" start="0x3" description="SDR104" />
-        <Enum name="DDR50" start="0x4" description="DDR50" />
-      </BitField>
-      <BitField start="3" size="1" name="VS18EN" description="1.8V Signaling Enable">
-        <Enum name="S33V" start="0x0" description="3.3V Signaling" />
-        <Enum name="S18V" start="0x1" description="1.8V Signaling" />
-      </BitField>
-      <BitField start="4" size="2" name="DRVSEL" description="Driver Strength Select">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected (Default)" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-      <BitField start="6" size="1" name="EXTUN" description="Execute Tuning">
-        <Enum name="NO" start="0x0" description="Not Tuned or Tuning Completed" />
-        <Enum name="REQUESTED" start="0x1" description="Execute Tuning" />
-      </BitField>
-      <BitField start="7" size="1" name="SLCKSEL" description="Sampling Clock Select">
-        <Enum name="FIXED" start="0x0" description="Fixed clock is used to sample data" />
-        <Enum name="TUNED" start="0x1" description="Tuned clock is used to sample data" />
-      </BitField>
-      <BitField start="14" size="1" name="ASINTEN" description="Asynchronous Interrupt Enable">
-        <Enum name="DISABLED" start="0x0" description="Disabled" />
-        <Enum name="ENABLED" start="0x1" description="Enabled" />
-      </BitField>
-      <BitField start="15" size="1" name="PVALEN" description="Preset Value Enable">
-        <Enum name="HOST" start="0x0" description="SDCLK and Driver Strength are controlled by Host Controller" />
-        <Enum name="AUTO" start="0x1" description="Automatic Selection by Preset Value is Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x03E" size="2" name="SDHC_HC2R_EMMC" access="Read/Write" description="Host Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="HS200EN" description="HS200 Mode Enable">
-        <Enum name="SDR12" start="0x0" description="SDR12" />
-        <Enum name="SDR25" start="0x1" description="SDR25" />
-        <Enum name="SDR50" start="0x2" description="SDR50" />
-        <Enum name="SDR104" start="0x3" description="SDR104" />
-        <Enum name="DDR50" start="0x4" description="DDR50" />
-      </BitField>
-      <BitField start="4" size="2" name="DRVSEL" description="Driver Strength Select">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected (Default)" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-      <BitField start="6" size="1" name="EXTUN" description="Execute Tuning">
-        <Enum name="NO" start="0x0" description="Not Tuned or Tuning Completed" />
-        <Enum name="REQUESTED" start="0x1" description="Execute Tuning" />
-      </BitField>
-      <BitField start="7" size="1" name="SLCKSEL" description="Sampling Clock Select">
-        <Enum name="FIXED" start="0x0" description="Fixed clock is used to sample data" />
-        <Enum name="TUNED" start="0x1" description="Tuned clock is used to sample data" />
-      </BitField>
-      <BitField start="15" size="1" name="PVALEN" description="Preset Value Enable">
-        <Enum name="HOST" start="0x0" description="SDCLK and Driver Strength are controlled by Host Controller" />
-        <Enum name="AUTO" start="0x1" description="Automatic Selection by Preset Value is Enabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x040" size="4" name="SDHC_CA0R" access="ReadOnly" description="Capabilities 0" reset_value="0x27E80080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TEOCLKF" description="Timeout Clock Frequency">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-      </BitField>
-      <BitField start="7" size="1" name="TEOCLKU" description="Timeout Clock Unit">
-        <Enum name="KHZ" start="0x0" description="kHz" />
-        <Enum name="MHZ" start="0x1" description="MHz" />
-      </BitField>
-      <BitField start="8" size="8" name="BASECLKF" description="Base Clock Frequency">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-      </BitField>
-      <BitField start="16" size="2" name="MAXBLKL" description="Max Block Length">
-        <Enum name="512" start="0x0" description="512 bytes" />
-        <Enum name="1024" start="0x1" description="1024 bytes" />
-        <Enum name="2048" start="0x2" description="2048 bytes" />
-      </BitField>
-      <BitField start="18" size="1" name="ED8SUP" description="8-bit Support for Embedded Device">
-        <Enum name="NO" start="0x0" description="8-bit Bus Width not Supported" />
-        <Enum name="YES" start="0x1" description="8-bit Bus Width Supported" />
-      </BitField>
-      <BitField start="19" size="1" name="ADMA2SUP" description="ADMA2 Support">
-        <Enum name="NO" start="0x0" description="ADMA2 not Supported" />
-        <Enum name="YES" start="0x1" description="ADMA2 Supported" />
-      </BitField>
-      <BitField start="21" size="1" name="HSSUP" description="High Speed Support">
-        <Enum name="NO" start="0x0" description="High Speed not Supported" />
-        <Enum name="YES" start="0x1" description="High Speed Supported" />
-      </BitField>
-      <BitField start="22" size="1" name="SDMASUP" description="SDMA Support">
-        <Enum name="NO" start="0x0" description="SDMA not Supported" />
-        <Enum name="YES" start="0x1" description="SDMA Supported" />
-      </BitField>
-      <BitField start="23" size="1" name="SRSUP" description="Suspend/Resume Support">
-        <Enum name="NO" start="0x0" description="Suspend/Resume not Supported" />
-        <Enum name="YES" start="0x1" description="Suspend/Resume Supported" />
-      </BitField>
-      <BitField start="24" size="1" name="V33VSUP" description="Voltage Support 3.3V">
-        <Enum name="NO" start="0x0" description="3.3V Not Supported" />
-        <Enum name="YES" start="0x1" description="3.3V Supported" />
-      </BitField>
-      <BitField start="25" size="1" name="V30VSUP" description="Voltage Support 3.0V">
-        <Enum name="NO" start="0x0" description="3.0V Not Supported" />
-        <Enum name="YES" start="0x1" description="3.0V Supported" />
-      </BitField>
-      <BitField start="26" size="1" name="V18VSUP" description="Voltage Support 1.8V">
-        <Enum name="NO" start="0x0" description="1.8V Not Supported" />
-        <Enum name="YES" start="0x1" description="1.8V Supported" />
-      </BitField>
-      <BitField start="28" size="1" name="SB64SUP" description="64-Bit System Bus Support">
-        <Enum name="NO" start="0x0" description="32-bit Address Descriptors and System Bus" />
-        <Enum name="YES" start="0x1" description="64-bit Address Descriptors and System Bus" />
-      </BitField>
-      <BitField start="29" size="1" name="ASINTSUP" description="Asynchronous Interrupt Support">
-        <Enum name="NO" start="0x0" description="Asynchronous Interrupt not Supported" />
-        <Enum name="YES" start="0x1" description="Asynchronous Interrupt supported" />
-      </BitField>
-      <BitField start="30" size="2" name="SLTYPE" description="Slot Type">
-        <Enum name="REMOVABLE" start="0x0" description="Removable Card Slot" />
-        <Enum name="EMBEDDED" start="0x1" description="Embedded Slot for One Device" />
-      </BitField>
-    </Register>
-    <Register start="+0x044" size="4" name="SDHC_CA1R" access="ReadOnly" description="Capabilities 1" reset_value="0x00000070" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDR50SUP" description="SDR50 Support">
-        <Enum name="NO" start="0x0" description="SDR50 is Not Supported" />
-        <Enum name="YES" start="0x1" description="SDR50 is Supported" />
-      </BitField>
-      <BitField start="1" size="1" name="SDR104SUP" description="SDR104 Support">
-        <Enum name="NO" start="0x0" description="SDR104 is Not Supported" />
-        <Enum name="YES" start="0x1" description="SDR104 is Supported" />
-      </BitField>
-      <BitField start="2" size="1" name="DDR50SUP" description="DDR50 Support">
-        <Enum name="NO" start="0x0" description="DDR50 is Not Supported" />
-        <Enum name="YES" start="0x1" description="DDR50 is Supported" />
-      </BitField>
-      <BitField start="4" size="1" name="DRVASUP" description="Driver Type A Support">
-        <Enum name="NO" start="0x0" description="Driver Type A is Not Supported" />
-        <Enum name="YES" start="0x1" description="Driver Type A is Supported" />
-      </BitField>
-      <BitField start="5" size="1" name="DRVCSUP" description="Driver Type C Support">
-        <Enum name="NO" start="0x0" description="Driver Type C is Not Supported" />
-        <Enum name="YES" start="0x1" description="Driver Type C is Supported" />
-      </BitField>
-      <BitField start="6" size="1" name="DRVDSUP" description="Driver Type D Support">
-        <Enum name="NO" start="0x0" description="Driver Type D is Not Supported" />
-        <Enum name="YES" start="0x1" description="Driver Type D is Supported" />
-      </BitField>
-      <BitField start="8" size="4" name="TCNTRT" description="Timer Count for Re-Tuning">
-        <Enum name="DISABLED" start="0x0" description="Re-Tuning Timer disabled" />
-        <Enum name="1S" start="0x1" description="1 second" />
-        <Enum name="2S" start="0x2" description="2 seconds" />
-        <Enum name="4S" start="0x3" description="4 seconds" />
-        <Enum name="8S" start="0x4" description="8 seconds" />
-        <Enum name="16S" start="0x5" description="16 seconds" />
-        <Enum name="32S" start="0x6" description="32 seconds" />
-        <Enum name="64S" start="0x7" description="64 seconds" />
-        <Enum name="128S" start="0x8" description="128 seconds" />
-        <Enum name="256S" start="0x9" description="256 seconds" />
-        <Enum name="512S" start="0xa" description="512 seconds" />
-        <Enum name="1024S" start="0xb" description="1024 seconds" />
-        <Enum name="OTHER" start="0xf" description="Get information from other source" />
-      </BitField>
-      <BitField start="13" size="1" name="TSDR50" description="Use Tuning for SDR50">
-        <Enum name="NO" start="0x0" description="SDR50 does not require tuning" />
-        <Enum name="YES" start="0x1" description="SDR50 requires tuning" />
-      </BitField>
-      <BitField start="16" size="8" name="CLKMULT" description="Clock Multiplier">
-        <Enum name="NO" start="0x0" description="Clock Multiplier is Not Supported" />
-      </BitField>
-    </Register>
-    <Register start="+0x048" size="4" name="SDHC_MCCAR" access="ReadOnly" description="Maximum Current Capabilities" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="MAXCUR33V" description="Maximum Current for 3.3V">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-        <Enum name="4MA" start="0x1" description="4mA" />
-        <Enum name="8MA" start="0x2" description="8mA" />
-        <Enum name="12MA" start="0x3" description="12mA" />
-      </BitField>
-      <BitField start="8" size="8" name="MAXCUR30V" description="Maximum Current for 3.0V">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-        <Enum name="4MA" start="0x1" description="4mA" />
-        <Enum name="8MA" start="0x2" description="8mA" />
-        <Enum name="12MA" start="0x3" description="12mA" />
-      </BitField>
-      <BitField start="16" size="8" name="MAXCUR18V" description="Maximum Current for 1.8V">
-        <Enum name="OTHER" start="0x0" description="Get information via another method" />
-        <Enum name="4MA" start="0x1" description="4mA" />
-        <Enum name="8MA" start="0x2" description="8mA" />
-        <Enum name="12MA" start="0x3" description="12mA" />
-      </BitField>
-    </Register>
-    <Register start="+0x050" size="2" name="SDHC_FERACES" access="WriteOnly" description="Force Event for Auto CMD Error Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACMD12NE" description="Force Event for Auto CMD12 Not Executed">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="1" size="1" name="ACMDTEO" description="Force Event for Auto CMD Timeout Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="2" size="1" name="ACMDCRC" description="Force Event for Auto CMD CRC Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="3" size="1" name="ACMDEND" description="Force Event for Auto CMD End Bit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="ACMDIDX" description="Force Event for Auto CMD Index Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="7" size="1" name="CMDNI" description="Force Event for Command Not Issued By Auto CMD12 Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-    </Register>
-    <Register start="+0x052" size="2" name="SDHC_FEREIS" access="WriteOnly" description="Force Event for Error Interrupt Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDTEO" description="Force Event for Command Timeout Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="1" size="1" name="CMDCRC" description="Force Event for Command CRC Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="2" size="1" name="CMDEND" description="Force Event for Command End Bit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="3" size="1" name="CMDIDX" description="Force Event for Command Index Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="4" size="1" name="DATTEO" description="Force Event for Data Timeout Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="5" size="1" name="DATCRC" description="Force Event for Data CRC Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="6" size="1" name="DATEND" description="Force Event for Data End Bit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="7" size="1" name="CURLIM" description="Force Event for Current Limit Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="8" size="1" name="ACMD" description="Force Event for Auto CMD Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="9" size="1" name="ADMA" description="Force Event for ADMA Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-      <BitField start="12" size="1" name="BOOTAE" description="Force Event for Boot Acknowledge Error">
-        <Enum name="NO" start="0x0" description="No Interrupt" />
-        <Enum name="YES" start="0x1" description="Interrupt is generated" />
-      </BitField>
-    </Register>
-    <Register start="+0x054" size="1" name="SDHC_AESR" access="ReadOnly" description="ADMA Error Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="ERRST" description="ADMA Error State">
-        <Enum name="STOP" start="0x0" description="ST_STOP (Stop DMA)" />
-        <Enum name="FDS" start="0x1" description="ST_FDS (Fetch Descriptor)" />
-        <Enum name="TFR" start="0x3" description="ST_TFR (Transfer Data)" />
-      </BitField>
-      <BitField start="2" size="1" name="LMIS" description="ADMA Length Mismatch Error">
-        <Enum name="NO" start="0x0" description="No Error" />
-        <Enum name="YES" start="0x1" description="Error" />
-      </BitField>
-    </Register>
-    <Register start="+0x058+0" size="4" name="SDHC_ASAR0" access="Read/Write" description="ADMA System Address n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADMASA" description="ADMA System Address" />
-    </Register>
-    <Register start="+0x060+0" size="2" name="SDHC_PVR0" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+2" size="2" name="SDHC_PVR1" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+4" size="2" name="SDHC_PVR2" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+6" size="2" name="SDHC_PVR3" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+8" size="2" name="SDHC_PVR4" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+10" size="2" name="SDHC_PVR5" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+12" size="2" name="SDHC_PVR6" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x060+14" size="2" name="SDHC_PVR7" access="Read/Write" description="Preset Value n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="SDCLKFSEL" description="SDCLK Frequency Select Value for Initialization" />
-      <BitField start="10" size="1" name="CLKGSEL" description="Clock Generator Select Value for Initialization">
-        <Enum name="DIV" start="0x0" description="Host Controller Ver2.00 Compatible Clock Generator (Divider)" />
-        <Enum name="PROG" start="0x1" description="Programmable Clock Generator" />
-      </BitField>
-      <BitField start="14" size="2" name="DRVSEL" description="Driver Strength Select Value for Initialization">
-        <Enum name="B" start="0x0" description="Driver Type B is Selected" />
-        <Enum name="A" start="0x1" description="Driver Type A is Selected" />
-        <Enum name="C" start="0x2" description="Driver Type C is Selected" />
-        <Enum name="D" start="0x3" description="Driver Type D is Selected" />
-      </BitField>
-    </Register>
-    <Register start="+0x0FC" size="2" name="SDHC_SISR" access="ReadOnly" description="Slot Interrupt Status" reset_value="0x20000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSSL" description="Interrupt Signal for Each Slot" />
-    </Register>
-    <Register start="+0x0FE" size="2" name="SDHC_HCVR" access="ReadOnly" description="Host Controller Version" reset_value="0x1802" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SVER" description="Spec Version" />
-      <BitField start="8" size="8" name="VVER" description="Vendor Version" />
-    </Register>
-    <Register start="+0x204" size="1" name="SDHC_MC1R" access="Read/Write" description="MMC Control 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMDTYP" description="e.MMC Command Type">
-        <Enum name="NORMAL" start="0x0" description="Not a MMC specific command" />
-        <Enum name="WAITIRQ" start="0x1" description="Wait IRQ Command" />
-        <Enum name="STREAM" start="0x2" description="Stream Command" />
-        <Enum name="BOOT" start="0x3" description="Boot Command" />
-      </BitField>
-      <BitField start="3" size="1" name="DDR" description="e.MMC HSDDR Mode" />
-      <BitField start="4" size="1" name="OPD" description="e.MMC Open Drain Mode" />
-      <BitField start="5" size="1" name="BOOTA" description="e.MMC Boot Acknowledge Enable" />
-      <BitField start="6" size="1" name="RSTN" description="e.MMC Reset Signal" />
-      <BitField start="7" size="1" name="FCD" description="e.MMC Force Card Detect" />
-    </Register>
-    <Register start="+0x205" size="1" name="SDHC_MC2R" access="WriteOnly" description="MMC Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SRESP" description="e.MMC Abort Wait IRQ" />
-      <BitField start="1" size="1" name="ABOOT" description="e.MMC Abort Boot" />
-    </Register>
-    <Register start="+0x208" size="4" name="SDHC_ACR" access="Read/Write" description="AHB Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BMAX" description="AHB Maximum Burst">
-        <Enum name="INCR16" start="0x0" />
-        <Enum name="INCR8" start="0x1" />
-        <Enum name="INCR4" start="0x2" />
-        <Enum name="SINGLE" start="0x3" />
-      </BitField>
-    </Register>
-    <Register start="+0x20C" size="4" name="SDHC_CC2R" access="Read/Write" description="Clock Control 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FSDCLKD" description="Force SDCK Disabled">
-        <Enum name="NOEFFECT" start="0x0" description="No effect" />
-        <Enum name="DISABLE" start="0x1" description="SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled" />
-      </BitField>
-    </Register>
-    <Register start="+0x230" size="4" name="SDHC_CACR" access="Read/Write" description="Capabilities Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAPWREN" description="Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)" />
-      <BitField start="8" size="8" name="KEY" description="Key (0x46)" />
-    </Register>
-    <Register start="+0x234" size="1" name="SDHC_DBGR" access="Read/Write" description="Debug" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NIDBG" description="Non-intrusive debug enable">
-        <Enum name="IDBG" start="0x0" description="Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer)" />
-        <Enum name="NIDBG" start="0x1" description="Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CM)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (I2CS)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (SPI)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM0 (USART)" start="0x40003000" description="Serial Communication Interface 0">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CM)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (I2CS)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (SPI)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM1 (USART)" start="0x40003400" description="Serial Communication Interface 1">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CM)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (I2CS)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (SPI)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM2 (USART)" start="0x41012000" description="Serial Communication Interface 2">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CM)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (I2CS)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (SPI)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM3 (USART)" start="0x41014000" description="Serial Communication Interface 3">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CM)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (I2CS)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (SPI)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM4 (USART)" start="0x43000000" description="Serial Communication Interface 4">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CM)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CM Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="22" size="1" name="MEXTTOEN" description="Master SCL Low Extend Timeout" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="28" size="2" name="INACTOUT" description="Inactive Time-Out" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CM Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="QCEN" description="Quick Command Enable" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CM Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SERCOM_BAUD" access="Read/Write" description="I2CM Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-      <BitField start="8" size="8" name="BAUDLOW" description="Baud Rate Value Low" />
-      <BitField start="16" size="8" name="HSBAUD" description="High Speed Baud Rate Value" />
-      <BitField start="24" size="8" name="HSBAUDLOW" description="High Speed Baud Rate Value Low" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CM Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Disable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CM Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt Enable" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CM Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MB" description="Master On Bus Interrupt" />
-      <BitField start="1" size="1" name="SB" description="Slave On Bus Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CM Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="ARBLOST" description="Arbitration Lost" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="4" size="2" name="BUSSTATE" description="Bus State" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="8" size="1" name="MEXTTOUT" description="Master SCL Low Extend Timeout" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="LENERR" description="Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CM Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="SYSOP" description="System Operation Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CM Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ADDR" description="Address Value" />
-      <BitField start="13" size="1" name="LENEN" description="Length Enable" />
-      <BitField start="14" size="1" name="HS" description="High Speed Mode" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="16" size="8" name="LEN" description="Length" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CM Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="I2CM Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (I2CS)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="I2CS Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="16" size="1" name="PINOUT" description="Pin Usage" />
-      <BitField start="20" size="2" name="SDAHOLD" description="SDA Hold Time" />
-      <BitField start="23" size="1" name="SEXTTOEN" description="Slave SCL Low Extend Timeout" />
-      <BitField start="24" size="2" name="SPEED" description="Transfer Speed" />
-      <BitField start="27" size="1" name="SCLSM" description="SCL Clock Stretch Mode" />
-      <BitField start="30" size="1" name="LOWTOUTEN" description="SCL Low Timeout Enable" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="I2CS Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="8" size="1" name="SMEN" description="Smart Mode Enable" />
-      <BitField start="9" size="1" name="GCMD" description="PMBus Group Command" />
-      <BitField start="10" size="1" name="AACKEN" description="Automatic Address Acknowledge" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="16" size="2" name="CMD" description="Command" />
-      <BitField start="18" size="1" name="ACKACT" description="Acknowledge Action" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="I2CS Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SDASETUP" description="SDA Setup Time" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="I2CS Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Disable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Disable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="I2CS Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt Enable" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt Enable" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="I2CS Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PREC" description="Stop Received Interrupt" />
-      <BitField start="1" size="1" name="AMATCH" description="Address Match Interrupt" />
-      <BitField start="2" size="1" name="DRDY" description="Data Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="I2CS Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSERR" description="Bus Error" />
-      <BitField start="1" size="1" name="COLL" description="Transmit Collision" />
-      <BitField start="2" size="1" name="RXNACK" description="Received Not Acknowledge" />
-      <BitField start="3" size="1" name="DIR" description="Read/Write Direction" />
-      <BitField start="4" size="1" name="SR" description="Repeated Start" />
-      <BitField start="6" size="1" name="LOWTOUT" description="SCL Low Timeout" />
-      <BitField start="7" size="1" name="CLKHOLD" description="Clock Hold" />
-      <BitField start="9" size="1" name="SEXTTOUT" description="Slave SCL Low Extend Timeout" />
-      <BitField start="10" size="1" name="HS" description="High Speed" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="I2CS Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="Length Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="I2CS Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="I2CS Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GENCEN" description="General Call Address Enable" />
-      <BitField start="1" size="10" name="ADDR" description="Address Value" />
-      <BitField start="15" size="1" name="TENBITEN" description="Ten Bit Addressing Enable" />
-      <BitField start="17" size="10" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="I2CS Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (SPI)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="SPI Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="16" size="2" name="DOPO" description="Data Out Pinout" />
-      <BitField start="20" size="2" name="DIPO" description="Data In Pinout" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CPHA" description="Clock Phase" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="SPI Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="PLOADEN" description="Data Preload Enable" />
-      <BitField start="9" size="1" name="SSDE" description="Slave Select Low Detect Enable" />
-      <BitField start="13" size="1" name="MSSEN" description="Master Slave Select Enable" />
-      <BitField start="14" size="2" name="AMODE" description="Address Mode" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="SPI Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="ICSPACE" description="Inter-Character Spacing" />
-      <BitField start="24" size="1" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="1" name="SERCOM_BAUD" access="Read/Write" description="SPI Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="SPI Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="SPI Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="SPI Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="SSL" description="Slave Select Low Interrupt Flag" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="SPI Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="11" size="1" name="LENERR" description="Transaction Length Error" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="SPI Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="SPI Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="1" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SERCOM_ADDR" access="Read/Write" description="SPI Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADDR" description="Address Value" />
-      <BitField start="16" size="8" name="ADDRMASK" description="Address Mask" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="SPI Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="SPI Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SERCOM5 (USART)" start="0x43000400" description="Serial Communication Interface 5">
-    <Register start="+0x00" size="4" name="SERCOM_CTRLA" access="Read/Write" description="USART Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="3" name="MODE" description="Operating Mode" />
-      <BitField start="7" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="IBON" description="Immediate Buffer Overflow Notification" />
-      <BitField start="9" size="1" name="TXINV" description="Transmit Data Invert" />
-      <BitField start="10" size="1" name="RXINV" description="Receive Data Invert" />
-      <BitField start="13" size="3" name="SAMPR" description="Sample" />
-      <BitField start="16" size="2" name="TXPO" description="Transmit Data Pinout" />
-      <BitField start="20" size="2" name="RXPO" description="Receive Data Pinout" />
-      <BitField start="22" size="2" name="SAMPA" description="Sample Adjustment" />
-      <BitField start="24" size="4" name="FORM" description="Frame Format" />
-      <BitField start="28" size="1" name="CMODE" description="Communication Mode" />
-      <BitField start="29" size="1" name="CPOL" description="Clock Polarity" />
-      <BitField start="30" size="1" name="DORD" description="Data Order" />
-    </Register>
-    <Register start="+0x04" size="4" name="SERCOM_CTRLB" access="Read/Write" description="USART Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHSIZE" description="Character Size" />
-      <BitField start="6" size="1" name="SBMODE" description="Stop Bit Mode" />
-      <BitField start="8" size="1" name="COLDEN" description="Collision Detection Enable" />
-      <BitField start="9" size="1" name="SFDE" description="Start of Frame Detection Enable" />
-      <BitField start="10" size="1" name="ENC" description="Encoding Format" />
-      <BitField start="13" size="1" name="PMODE" description="Parity Mode" />
-      <BitField start="16" size="1" name="TXEN" description="Transmitter Enable" />
-      <BitField start="17" size="1" name="RXEN" description="Receiver Enable" />
-      <BitField start="24" size="2" name="LINCMD" description="LIN Command" />
-    </Register>
-    <Register start="+0x08" size="4" name="SERCOM_CTRLC" access="Read/Write" description="USART Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="GTIME" description="Guard Time" />
-      <BitField start="8" size="2" name="BRKLEN" description="LIN Master Break Length" />
-      <BitField start="10" size="2" name="HDRDLY" description="LIN Master Header Delay" />
-      <BitField start="16" size="1" name="INACK" description="Inhibit Not Acknowledge" />
-      <BitField start="17" size="1" name="DSNACK" description="Disable Successive NACK" />
-      <BitField start="20" size="3" name="MAXITER" description="Maximum Iterations" />
-      <BitField start="24" size="2" name="DATA32B" description="Data 32 Bit" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRAC_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_FRACFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="BAUD" description="Baud Rate Value" />
-      <BitField start="13" size="3" name="FP" description="Fractional Part" />
-    </Register>
-    <Register start="+0x0C" size="2" name="SERCOM_BAUD_USARTFP_MODE" access="Read/Write" description="USART Baud Rate" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BAUD" description="Baud Rate Value" />
-    </Register>
-    <Register start="+0x0E" size="1" name="SERCOM_RXPL" access="Read/Write" description="USART Receive Pulse Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPL" description="Receive Pulse Length" />
-    </Register>
-    <Register start="+0x14" size="1" name="SERCOM_INTENCLR" access="Read/Write" description="USART Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Disable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Disable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Disable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Disable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Disable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Disable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Disable" />
-    </Register>
-    <Register start="+0x16" size="1" name="SERCOM_INTENSET" access="Read/Write" description="USART Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt Enable" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt Enable" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt Enable" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt Enable" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt Enable" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt Enable" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt Enable" />
-    </Register>
-    <Register start="+0x18" size="1" name="SERCOM_INTFLAG" access="Read/Write" description="USART Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DRE" description="Data Register Empty Interrupt" />
-      <BitField start="1" size="1" name="TXC" description="Transmit Complete Interrupt" />
-      <BitField start="2" size="1" name="RXC" description="Receive Complete Interrupt" />
-      <BitField start="3" size="1" name="RXS" description="Receive Start Interrupt" />
-      <BitField start="4" size="1" name="CTSIC" description="Clear To Send Input Change Interrupt" />
-      <BitField start="5" size="1" name="RXBRK" description="Break Received Interrupt" />
-      <BitField start="7" size="1" name="ERROR" description="Combined Error Interrupt" />
-    </Register>
-    <Register start="+0x1A" size="2" name="SERCOM_STATUS" access="Read/Write" description="USART Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERR" description="Parity Error" />
-      <BitField start="1" size="1" name="FERR" description="Frame Error" />
-      <BitField start="2" size="1" name="BUFOVF" description="Buffer Overflow" />
-      <BitField start="3" size="1" name="CTS" description="Clear To Send" />
-      <BitField start="4" size="1" name="ISF" description="Inconsistent Sync Field" />
-      <BitField start="5" size="1" name="COLL" description="Collision Detected" />
-      <BitField start="6" size="1" name="TXE" description="Transmitter Empty" />
-      <BitField start="7" size="1" name="ITER" description="Maximum Number of Repetitions Reached" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SERCOM_SYNCBUSY" access="ReadOnly" description="USART Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="SERCOM Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB Synchronization Busy" />
-      <BitField start="3" size="1" name="RXERRCNT" description="RXERRCNT Synchronization Busy" />
-      <BitField start="4" size="1" name="LENGTH" description="LENGTH Synchronization Busy" />
-    </Register>
-    <Register start="+0x20" size="1" name="SERCOM_RXERRCNT" access="ReadOnly" description="USART Receive Error Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x22" size="2" name="SERCOM_LENGTH" access="Read/Write" description="USART Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="LEN" description="Data Length" />
-      <BitField start="8" size="2" name="LENEN" description="Data Length Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="SERCOM_DATA" access="Read/Write" description="USART Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Data Value" />
-    </Register>
-    <Register start="+0x30" size="1" name="SERCOM_DBGCTRL" access="Read/Write" description="USART Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGSTOP" description="Debug Mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SUPC" start="0x40001800" description="Supply Controller">
-    <Register start="+0x00" size="4" name="SUPC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x04" size="4" name="SUPC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x08" size="4" name="SUPC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x0C" size="4" name="SUPC_STATUS" access="ReadOnly" description="Power and Clocks Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BOD33RDY" description="BOD33 Ready" />
-      <BitField start="1" size="1" name="BOD33DET" description="BOD33 Detection" />
-      <BitField start="2" size="1" name="B33SRDY" description="BOD33 Synchronization Ready" />
-      <BitField start="3" size="1" name="BOD12RDY" description="BOD12 Ready" />
-      <BitField start="4" size="1" name="BOD12DET" description="BOD12 Detection" />
-      <BitField start="5" size="1" name="B12SRDY" description="BOD12 Synchronization Ready" />
-      <BitField start="8" size="1" name="VREGRDY" description="Voltage Regulator Ready" />
-      <BitField start="10" size="1" name="VCORERDY" description="VDDCORE Ready" />
-    </Register>
-    <Register start="+0x10" size="4" name="SUPC_BOD33" access="Read/Write" description="BOD33 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="ACTION" description="Action when Threshold Crossed">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RESET" start="0x1" description="The BOD33 generates a reset" />
-        <Enum name="INT" start="0x2" description="The BOD33 generates an interrupt" />
-        <Enum name="BKUP" start="0x3" description="The BOD33 puts the device in backup sleep mode" />
-      </BitField>
-      <BitField start="4" size="1" name="STDBYCFG" description="Configuration in Standby mode" />
-      <BitField start="5" size="1" name="RUNSTDBY" description="Run in Standby mode" />
-      <BitField start="6" size="1" name="RUNHIB" description="Run in Hibernate mode" />
-      <BitField start="7" size="1" name="RUNBKUP" description="Run in Backup mode" />
-      <BitField start="8" size="4" name="HYST" description="Hysteresis value" />
-      <BitField start="12" size="3" name="PSEL" description="Prescaler Select">
-        <Enum name="NODIV" start="0x0" description="Not divided" />
-        <Enum name="DIV4" start="0x1" description="Divide clock by 4" />
-        <Enum name="DIV8" start="0x2" description="Divide clock by 8" />
-        <Enum name="DIV16" start="0x3" description="Divide clock by 16" />
-        <Enum name="DIV32" start="0x4" description="Divide clock by 32" />
-        <Enum name="DIV64" start="0x5" description="Divide clock by 64" />
-        <Enum name="DIV128" start="0x6" description="Divide clock by 128" />
-        <Enum name="DIV256" start="0x7" description="Divide clock by 256" />
-      </BitField>
-      <BitField start="16" size="8" name="LEVEL" description="Threshold Level for VDD" />
-      <BitField start="24" size="8" name="VBATLEVEL" description="Threshold Level in battery backup sleep mode for VBAT" />
-    </Register>
-    <Register start="+0x14" size="4" name="SUPC_BOD12" access="Read/Write" description="BOD12 Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="HYST" description="Hysteresis Enable" />
-      <BitField start="3" size="2" name="ACTION" description="Action when Threshold Crossed">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RESET" start="0x1" description="The BOD12 generates a reset" />
-        <Enum name="INT" start="0x2" description="The BOD12 generates an interrupt" />
-      </BitField>
-      <BitField start="5" size="1" name="STDBYCFG" description="Configuration in Standby mode" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="8" size="1" name="ACTCFG" description="Configuration in Active mode" />
-      <BitField start="12" size="4" name="PSEL" description="Prescaler Select">
-        <Enum name="DIV2" start="0x0" description="Divide clock by 2" />
-        <Enum name="DIV4" start="0x1" description="Divide clock by 4" />
-        <Enum name="DIV8" start="0x2" description="Divide clock by 8" />
-        <Enum name="DIV16" start="0x3" description="Divide clock by 16" />
-        <Enum name="DIV32" start="0x4" description="Divide clock by 32" />
-        <Enum name="DIV64" start="0x5" description="Divide clock by 64" />
-        <Enum name="DIV128" start="0x6" description="Divide clock by 128" />
-        <Enum name="DIV256" start="0x7" description="Divide clock by 256" />
-        <Enum name="DIV512" start="0x8" description="Divide clock by 512" />
-        <Enum name="DIV1024" start="0x9" description="Divide clock by 1024" />
-        <Enum name="DIV2048" start="0xa" description="Divide clock by 2048" />
-        <Enum name="DIV4096" start="0xb" description="Divide clock by 4096" />
-        <Enum name="DIV8192" start="0xc" description="Divide clock by 8192" />
-        <Enum name="DIV16384" start="0xd" description="Divide clock by 16384" />
-        <Enum name="DIV32768" start="0xe" description="Divide clock by 32768" />
-        <Enum name="DIV65536" start="0xf" description="Divide clock by 65536" />
-      </BitField>
-      <BitField start="16" size="6" name="LEVEL" description="Threshold Level" />
-    </Register>
-    <Register start="+0x18" size="4" name="SUPC_VREG" access="Read/Write" description="VREG Control" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="SEL" description="Voltage Regulator Selection">
-        <Enum name="LDO" start="0x0" description="LDO selection" />
-        <Enum name="BUCK" start="0x1" description="Buck selection" />
-      </BitField>
-      <BitField start="7" size="1" name="RUNBKUP" description="Run in Backup mode" />
-      <BitField start="16" size="1" name="VSEN" description="Voltage Scaling Enable" />
-      <BitField start="24" size="3" name="VSPER" description="Voltage Scaling Period" />
-    </Register>
-    <Register start="+0x1C" size="4" name="SUPC_VREF" access="Read/Write" description="VREF Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="TSEN" description="Temperature Sensor Output Enable" />
-      <BitField start="2" size="1" name="VREFOE" description="Voltage Reference Output Enable" />
-      <BitField start="3" size="1" name="TSSEL" description="Temperature Sensor Selection" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="On Demand Contrl" />
-      <BitField start="16" size="4" name="SEL" description="Voltage Reference Selection">
-        <Enum name="1V0" start="0x0" description="1.0V voltage reference typical value" />
-        <Enum name="1V1" start="0x1" description="1.1V voltage reference typical value" />
-        <Enum name="1V2" start="0x2" description="1.2V voltage reference typical value" />
-        <Enum name="1V25" start="0x3" description="1.25V voltage reference typical value" />
-        <Enum name="2V0" start="0x4" description="2.0V voltage reference typical value" />
-        <Enum name="2V2" start="0x5" description="2.2V voltage reference typical value" />
-        <Enum name="2V4" start="0x6" description="2.4V voltage reference typical value" />
-        <Enum name="2V5" start="0x7" description="2.5V voltage reference typical value" />
-      </BitField>
-    </Register>
-    <Register start="+0x20" size="4" name="SUPC_BBPS" access="Read/Write" description="Battery Backup Power Switch" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONF" description="Battery Backup Configuration">
-        <Enum name="BOD33" start="0x0" description="The power switch is handled by the BOD33" />
-        <Enum name="FORCED" start="0x1" description="In Backup Domain, the backup domain is always supplied by battery backup power" />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEEN" description="Wake Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="SUPC_BKOUT" access="Read/Write" description="Backup Output Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="EN" description="Enable Output" />
-      <BitField start="8" size="2" name="CLR" description="Clear Output" />
-      <BitField start="16" size="2" name="SET" description="Set Output" />
-      <BitField start="24" size="2" name="RTCTGL" description="RTC Toggle Output" />
-    </Register>
-    <Register start="+0x28" size="4" name="SUPC_BKIN" access="ReadOnly" description="Backup Input Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BKIN" description="Backup Input Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TAL" start="0x4101E000" description="Trigger Allocator">
-    <Register start="+0x000" size="1" name="TAL_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-    </Register>
-    <Register start="+0x001" size="1" name="TAL_EXTCTRL" access="Read/Write" description="External Break Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Enable BRK Pin" />
-      <BitField start="1" size="1" name="INV" description="Invert BRK Pin" />
-    </Register>
-    <Register start="+0x004" size="2" name="TAL_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRKEI" description="Break Input Event Enable" />
-      <BitField start="1" size="1" name="BRKEO" description="Break Output Event Enable" />
-      <BitField start="2" size="1" name="IRQMONEO0" description="Interrupt Request Monitor 0 Output Event Enable" />
-    </Register>
-    <Register start="+0x008" size="1" name="TAL_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRK" description="Break Interrupt Enable" />
-      <BitField start="1" size="1" name="IPS0" description="Inter-Processor Signal Interrupt Enable for CPU 0" />
-      <BitField start="2" size="1" name="IPS1" description="Inter-Processor Signal Interrupt Enable for CPU 1" />
-    </Register>
-    <Register start="+0x009" size="1" name="TAL_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRK" description="Break Interrupt Enable" />
-      <BitField start="1" size="1" name="IPS0" description="Inter-Processor Signal Interrupt Enable for CPU 0" />
-      <BitField start="2" size="1" name="IPS1" description="Inter-Processor Signal Interrupt Enable for CPU 1" />
-    </Register>
-    <Register start="+0x00A" size="1" name="TAL_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BRK" description="Break" />
-      <BitField start="1" size="1" name="IPS0" description="Inter-Processor Signal for CPU 0" />
-      <BitField start="2" size="1" name="IPS1" description="Inter-Processor Signal for CPU 1" />
-    </Register>
-    <Register start="+0x00B" size="1" name="TAL_GLOBMASK" access="Read/Write" description="Global Break Requests Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x00C" size="1" name="TAL_HALT" access="WriteOnly" description="Debug Halt Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x00D" size="1" name="TAL_RESTART" access="WriteOnly" description="Debug Restart Request" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x00E" size="2" name="TAL_BRKSTATUS" access="ReadOnly" description="Break Request Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CPU0" description="CPU 0 Break Request" />
-      <BitField start="2" size="2" name="CPU1" description="CPU 1 Break Request" />
-      <BitField start="12" size="2" name="EVBRK" description="Event Break Request" />
-      <BitField start="14" size="2" name="EXTBRK" description="External Break Request" />
-    </Register>
-    <Register start="+0x010+0" size="1" name="TAL_CTICTRLA0" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x010+2" size="1" name="TAL_CTICTRLA1" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x010+4" size="1" name="TAL_CTICTRLA2" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x010+6" size="1" name="TAL_CTICTRLA3" access="Read/Write" description="Cross-Trigger Interface n Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="BRK" description="Action when global break issued">
-        <Enum name="BREAK" start="0x0" description="Break when requested" />
-        <Enum name="INTERRUPT" start="0x1" description="Trigger DBG interrupt instead of break" />
-        <Enum name="IGNORE" start="0x2" description="Ignore break request" />
-      </BitField>
-      <BitField start="2" size="1" name="RESTART" description="Action when global restart issued">
-        <Enum name="RESTART" start="0x0" description="Restart when requested" />
-        <Enum name="IGNORE" start="0x1" description="Ignore restart request" />
-      </BitField>
-      <BitField start="3" size="1" name="IPS" description="Action when inter-process resource freed">
-        <Enum name="EVENT" start="0x0" description="Generate CPU Event when awaited resource is freed." />
-        <Enum name="INTERRUPT" start="0x1" description="Generate Interrupt when awaited resource is freed." />
-      </BitField>
-    </Register>
-    <Register start="+0x011+0" size="1" name="TAL_CTIMASK0" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x011+2" size="1" name="TAL_CTIMASK1" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x011+4" size="1" name="TAL_CTIMASK2" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x011+6" size="1" name="TAL_CTIMASK3" access="Read/Write" description="Cross-Trigger Interface n Mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CPU0" description="CPU 0 Break Master" />
-      <BitField start="1" size="1" name="CPU1" description="CPU 1 Break Master" />
-      <BitField start="6" size="1" name="EVBRK" description="Event Break Master" />
-      <BitField start="7" size="1" name="EXTBRK" description="External Break Master" />
-    </Register>
-    <Register start="+0x020+0" size="1" name="TAL_INTSTATUS0" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+1" size="1" name="TAL_INTSTATUS1" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+2" size="1" name="TAL_INTSTATUS2" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+3" size="1" name="TAL_INTSTATUS3" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+4" size="1" name="TAL_INTSTATUS4" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+5" size="1" name="TAL_INTSTATUS5" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+6" size="1" name="TAL_INTSTATUS6" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+7" size="1" name="TAL_INTSTATUS7" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+8" size="1" name="TAL_INTSTATUS8" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+9" size="1" name="TAL_INTSTATUS9" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+10" size="1" name="TAL_INTSTATUS10" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+11" size="1" name="TAL_INTSTATUS11" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+12" size="1" name="TAL_INTSTATUS12" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+13" size="1" name="TAL_INTSTATUS13" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+14" size="1" name="TAL_INTSTATUS14" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+15" size="1" name="TAL_INTSTATUS15" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+16" size="1" name="TAL_INTSTATUS16" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+17" size="1" name="TAL_INTSTATUS17" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+18" size="1" name="TAL_INTSTATUS18" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+19" size="1" name="TAL_INTSTATUS19" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+20" size="1" name="TAL_INTSTATUS20" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+21" size="1" name="TAL_INTSTATUS21" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+22" size="1" name="TAL_INTSTATUS22" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+23" size="1" name="TAL_INTSTATUS23" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+24" size="1" name="TAL_INTSTATUS24" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+25" size="1" name="TAL_INTSTATUS25" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+26" size="1" name="TAL_INTSTATUS26" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+27" size="1" name="TAL_INTSTATUS27" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+28" size="1" name="TAL_INTSTATUS28" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+29" size="1" name="TAL_INTSTATUS29" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+30" size="1" name="TAL_INTSTATUS30" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+31" size="1" name="TAL_INTSTATUS31" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+32" size="1" name="TAL_INTSTATUS32" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+33" size="1" name="TAL_INTSTATUS33" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+34" size="1" name="TAL_INTSTATUS34" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+35" size="1" name="TAL_INTSTATUS35" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+36" size="1" name="TAL_INTSTATUS36" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+37" size="1" name="TAL_INTSTATUS37" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+38" size="1" name="TAL_INTSTATUS38" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+39" size="1" name="TAL_INTSTATUS39" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+40" size="1" name="TAL_INTSTATUS40" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+41" size="1" name="TAL_INTSTATUS41" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+42" size="1" name="TAL_INTSTATUS42" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+43" size="1" name="TAL_INTSTATUS43" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+44" size="1" name="TAL_INTSTATUS44" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+45" size="1" name="TAL_INTSTATUS45" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+46" size="1" name="TAL_INTSTATUS46" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+47" size="1" name="TAL_INTSTATUS47" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+48" size="1" name="TAL_INTSTATUS48" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+49" size="1" name="TAL_INTSTATUS49" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+50" size="1" name="TAL_INTSTATUS50" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+51" size="1" name="TAL_INTSTATUS51" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+52" size="1" name="TAL_INTSTATUS52" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+53" size="1" name="TAL_INTSTATUS53" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+54" size="1" name="TAL_INTSTATUS54" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+55" size="1" name="TAL_INTSTATUS55" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+56" size="1" name="TAL_INTSTATUS56" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+57" size="1" name="TAL_INTSTATUS57" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+58" size="1" name="TAL_INTSTATUS58" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+59" size="1" name="TAL_INTSTATUS59" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+60" size="1" name="TAL_INTSTATUS60" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+61" size="1" name="TAL_INTSTATUS61" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+62" size="1" name="TAL_INTSTATUS62" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+63" size="1" name="TAL_INTSTATUS63" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+64" size="1" name="TAL_INTSTATUS64" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+65" size="1" name="TAL_INTSTATUS65" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+66" size="1" name="TAL_INTSTATUS66" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+67" size="1" name="TAL_INTSTATUS67" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+68" size="1" name="TAL_INTSTATUS68" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+69" size="1" name="TAL_INTSTATUS69" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+70" size="1" name="TAL_INTSTATUS70" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+71" size="1" name="TAL_INTSTATUS71" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+72" size="1" name="TAL_INTSTATUS72" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+73" size="1" name="TAL_INTSTATUS73" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+74" size="1" name="TAL_INTSTATUS74" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+75" size="1" name="TAL_INTSTATUS75" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+76" size="1" name="TAL_INTSTATUS76" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+77" size="1" name="TAL_INTSTATUS77" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+78" size="1" name="TAL_INTSTATUS78" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+79" size="1" name="TAL_INTSTATUS79" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+80" size="1" name="TAL_INTSTATUS80" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+81" size="1" name="TAL_INTSTATUS81" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+82" size="1" name="TAL_INTSTATUS82" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+83" size="1" name="TAL_INTSTATUS83" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+84" size="1" name="TAL_INTSTATUS84" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+85" size="1" name="TAL_INTSTATUS85" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+86" size="1" name="TAL_INTSTATUS86" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+87" size="1" name="TAL_INTSTATUS87" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+88" size="1" name="TAL_INTSTATUS88" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+89" size="1" name="TAL_INTSTATUS89" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+90" size="1" name="TAL_INTSTATUS90" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+91" size="1" name="TAL_INTSTATUS91" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+92" size="1" name="TAL_INTSTATUS92" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+93" size="1" name="TAL_INTSTATUS93" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+94" size="1" name="TAL_INTSTATUS94" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+95" size="1" name="TAL_INTSTATUS95" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+96" size="1" name="TAL_INTSTATUS96" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+97" size="1" name="TAL_INTSTATUS97" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+98" size="1" name="TAL_INTSTATUS98" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+99" size="1" name="TAL_INTSTATUS99" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+100" size="1" name="TAL_INTSTATUS100" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+101" size="1" name="TAL_INTSTATUS101" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+102" size="1" name="TAL_INTSTATUS102" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+103" size="1" name="TAL_INTSTATUS103" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+104" size="1" name="TAL_INTSTATUS104" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+105" size="1" name="TAL_INTSTATUS105" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+106" size="1" name="TAL_INTSTATUS106" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+107" size="1" name="TAL_INTSTATUS107" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+108" size="1" name="TAL_INTSTATUS108" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+109" size="1" name="TAL_INTSTATUS109" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+110" size="1" name="TAL_INTSTATUS110" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+111" size="1" name="TAL_INTSTATUS111" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+112" size="1" name="TAL_INTSTATUS112" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+113" size="1" name="TAL_INTSTATUS113" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+114" size="1" name="TAL_INTSTATUS114" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+115" size="1" name="TAL_INTSTATUS115" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+116" size="1" name="TAL_INTSTATUS116" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+117" size="1" name="TAL_INTSTATUS117" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+118" size="1" name="TAL_INTSTATUS118" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+119" size="1" name="TAL_INTSTATUS119" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+120" size="1" name="TAL_INTSTATUS120" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+121" size="1" name="TAL_INTSTATUS121" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+122" size="1" name="TAL_INTSTATUS122" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+123" size="1" name="TAL_INTSTATUS123" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+124" size="1" name="TAL_INTSTATUS124" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+125" size="1" name="TAL_INTSTATUS125" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+126" size="1" name="TAL_INTSTATUS126" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+127" size="1" name="TAL_INTSTATUS127" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+128" size="1" name="TAL_INTSTATUS128" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+129" size="1" name="TAL_INTSTATUS129" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+130" size="1" name="TAL_INTSTATUS130" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+131" size="1" name="TAL_INTSTATUS131" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+132" size="1" name="TAL_INTSTATUS132" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+133" size="1" name="TAL_INTSTATUS133" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+134" size="1" name="TAL_INTSTATUS134" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+135" size="1" name="TAL_INTSTATUS135" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x020+136" size="1" name="TAL_INTSTATUS136" access="ReadOnly" description="Interrupt n Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ0" description="Interrupt Status for Interrupt Request 0 within Interrupt n" />
-      <BitField start="1" size="1" name="IRQ1" description="Interrupt Status for Interrupt Request 1 within Interrupt n" />
-      <BitField start="2" size="1" name="IRQ2" description="Interrupt Status for Interrupt Request 2 within Interrupt n" />
-      <BitField start="3" size="1" name="IRQ3" description="Interrupt Status for Interrupt Request 3 within Interrupt n" />
-      <BitField start="4" size="1" name="IRQ4" description="Interrupt Status for Interrupt Request 4 within Interrupt n" />
-      <BitField start="5" size="1" name="IRQ5" description="Interrupt Status for Interrupt Request 5 within Interrupt n" />
-      <BitField start="6" size="1" name="IRQ6" description="Interrupt Status for Interrupt Request 6 within Interrupt n" />
-      <BitField start="7" size="1" name="IRQ7" description="Interrupt Status for Interrupt Request 7 within Interrupt n" />
-    </Register>
-    <Register start="+0x110" size="4" name="TAL_DMACPUSEL0" access="Read/Write" description="DMA Channel Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="DMA Channel 0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CH1" description="DMA Channel 1 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="CH2" description="DMA Channel 2 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="CH3" description="DMA Channel 3 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="CH4" description="DMA Channel 4 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="CH5" description="DMA Channel 5 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="CH6" description="DMA Channel 6 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="CH7" description="DMA Channel 7 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="CH8" description="DMA Channel 8 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="CH9" description="DMA Channel 9 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="CH10" description="DMA Channel 10 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="CH11" description="DMA Channel 11 Interrupt CPU Select" />
-      <BitField start="24" size="1" name="CH12" description="DMA Channel 12 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="CH13" description="DMA Channel 13 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="CH14" description="DMA Channel 14 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="CH15" description="DMA Channel 15 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x114" size="4" name="TAL_DMACPUSEL1" access="Read/Write" description="DMA Channel Interrupts CPU Select 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH16" description="DMA Channel 16 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CH17" description="DMA Channel 17 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="CH18" description="DMA Channel 18 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="CH19" description="DMA Channel 19 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="CH20" description="DMA Channel 20 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="CH21" description="DMA Channel 21 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="CH22" description="DMA Channel 22 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="CH23" description="DMA Channel 23 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="CH24" description="DMA Channel 24 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="CH25" description="DMA Channel 25 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="CH26" description="DMA Channel 26 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="CH27" description="DMA Channel 27 Interrupt CPU Select" />
-      <BitField start="24" size="1" name="CH28" description="DMA Channel 28 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="CH29" description="DMA Channel 29 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="CH30" description="DMA Channel 30 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="CH31" description="DMA Channel 31 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x118" size="4" name="TAL_EVCPUSEL0" access="Read/Write" description="EVSYS Channel Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CH0" description="Event Channel 0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CH1" description="Event Channel 1 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="CH2" description="Event Channel 2 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="CH3" description="Event Channel 3 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="CH4" description="Event Channel 4 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="CH5" description="Event Channel 5 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="CH6" description="Event Channel 6 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="CH7" description="Event Channel 7 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="CH8" description="Event Channel 8 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="CH9" description="Event Channel 9 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="CH10" description="Event Channel 10 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="CH11" description="Event Channel 11 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x120" size="4" name="TAL_EICCPUSEL0" access="Read/Write" description="EIC External Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTINT0" description="External Interrupt 0 CPU Select" />
-      <BitField start="2" size="1" name="EXTINT1" description="External Interrupt 1 CPU Select" />
-      <BitField start="4" size="1" name="EXTINT2" description="External Interrupt 2 CPU Select" />
-      <BitField start="6" size="1" name="EXTINT3" description="External Interrupt 3 CPU Select" />
-      <BitField start="8" size="1" name="EXTINT4" description="External Interrupt 4 CPU Select" />
-      <BitField start="10" size="1" name="EXTINT5" description="External Interrupt 5 CPU Select" />
-      <BitField start="12" size="1" name="EXTINT6" description="External Interrupt 6 CPU Select" />
-      <BitField start="14" size="1" name="EXTINT7" description="External Interrupt 7 CPU Select" />
-      <BitField start="16" size="1" name="EXTINT8" description="External Interrupt 8 CPU Select" />
-      <BitField start="18" size="1" name="EXTINT9" description="External Interrupt 9 CPU Select" />
-      <BitField start="20" size="1" name="EXTINT10" description="External Interrupt 10 CPU Select" />
-      <BitField start="22" size="1" name="EXTINT11" description="External Interrupt 11 CPU Select" />
-      <BitField start="24" size="1" name="EXTINT12" description="External Interrupt 12 CPU Select" />
-      <BitField start="26" size="1" name="EXTINT13" description="External Interrupt 13 CPU Select" />
-      <BitField start="28" size="1" name="EXTINT14" description="External Interrupt 14 CPU Select" />
-      <BitField start="30" size="1" name="EXTINT15" description="External Interrupt 15 CPU Select" />
-    </Register>
-    <Register start="+0x128" size="4" name="TAL_INTCPUSEL0" access="Read/Write" description="Interrupts CPU Select 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PAC" description="PAC Interrupt CPU Select" />
-      <BitField start="2" size="1" name="PM" description="PM Interrupt CPU Select" />
-      <BitField start="4" size="1" name="MCLK" description="MCLK Interrupt CPU Select" />
-      <BitField start="8" size="1" name="OSCCTRL" description="OSCCTRL Interrupt CPU Select" />
-      <BitField start="10" size="1" name="OSC32KCTRL" description="OSC32KCTRL Interrupt CPU Select" />
-      <BitField start="12" size="1" name="SUPC" description="SUPC Interrupt CPU Select" />
-      <BitField start="16" size="1" name="WDT" description="WDT Interrupt CPU Select" />
-      <BitField start="18" size="1" name="RTC" description="RTC Interrupt CPU Select" />
-      <BitField start="20" size="1" name="EIC" description="EIC Interrupt CPU Select" />
-      <BitField start="22" size="1" name="FREQM" description="FREQM Interrupt CPU Select" />
-      <BitField start="24" size="1" name="SERCOM0" description="SERCOM0 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="SERCOM1" description="SERCOM1 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="TC0" description="TC0 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="TC1" description="TC1 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TAL_INTCPUSEL1" access="Read/Write" description="Interrupts CPU Select 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x130" size="4" name="TAL_INTCPUSEL2" access="Read/Write" description="Interrupts CPU Select 2" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB" description="USB Interrupt CPU Select" />
-      <BitField start="4" size="1" name="NVMCTRL" description="NVMCTRL Interrupt CPU Select" />
-      <BitField start="10" size="1" name="DMAC" description="DMAC Interrupt CPU Select" />
-      <BitField start="14" size="1" name="EVSYS" description="EVSYS Interrupt CPU Select" />
-      <BitField start="16" size="1" name="PICOP" description="PICOP Interrupt CPU Select" />
-      <BitField start="18" size="1" name="SERCOM2" description="SERCOM2 Interrupt CPU Select" />
-      <BitField start="20" size="1" name="SERCOM3" description="SERCOM3 Interrupt CPU Select" />
-      <BitField start="22" size="1" name="TCC0" description="TCC0 Interrupt CPU Select" />
-      <BitField start="24" size="1" name="TCC1" description="TCC1 Interrupt CPU Select" />
-      <BitField start="26" size="1" name="TC2" description="TC2 Interrupt CPU Select" />
-      <BitField start="28" size="1" name="TC3" description="TC3 Interrupt CPU Select" />
-      <BitField start="30" size="1" name="TAL" description="TAL Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x134" size="4" name="TAL_INTCPUSEL3" access="Read/Write" description="Interrupts CPU Select 3" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAMECC" description="RAMECC Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x138" size="4" name="TAL_INTCPUSEL4" access="Read/Write" description="Interrupts CPU Select 4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAN0" description="CAN0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="CAN1" description="CAN1 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="GMAC" description="GMAC Interrupt CPU Select" />
-      <BitField start="6" size="1" name="TCC2" description="TCC2 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="TCC3" description="TCC3 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="TC4" description="TC4 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="TC5" description="TC5 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="PDEC" description="PDEC Interrupt CPU Select" />
-      <BitField start="16" size="1" name="AC" description="AC Interrupt CPU Select" />
-      <BitField start="18" size="1" name="AES" description="AES Interrupt CPU Select" />
-      <BitField start="20" size="1" name="TRNG" description="TRNG Interrupt CPU Select" />
-      <BitField start="22" size="1" name="ICM" description="ICM Interrupt CPU Select" />
-      <BitField start="24" size="1" name="PUKCC" description="PUKCC Interrupt CPU Select" />
-      <BitField start="26" size="1" name="QSPI" description="QSPI Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x13C" size="4" name="TAL_INTCPUSEL5" access="Read/Write" description="Interrupts CPU Select 5" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x140" size="4" name="TAL_INTCPUSEL6" access="Read/Write" description="Interrupts CPU Select 6" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SERCOM4" description="SERCOM4 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="SERCOM5" description="SERCOM5 Interrupt CPU Select" />
-      <BitField start="4" size="1" name="SERCOM6" description="SERCOM6 Interrupt CPU Select" />
-      <BitField start="6" size="1" name="SERCOM7" description="SERCOM7 Interrupt CPU Select" />
-      <BitField start="8" size="1" name="TCC4" description="TCC4 Interrupt CPU Select" />
-      <BitField start="10" size="1" name="TC6" description="TC6 Interrupt CPU Select" />
-      <BitField start="12" size="1" name="TC7" description="TC7 Interrupt CPU Select" />
-      <BitField start="14" size="1" name="ADC0" description="ADC0 Interrupt CPU Select" />
-      <BitField start="16" size="1" name="ADC1" description="ADC1 Interrupt CPU Select" />
-      <BitField start="18" size="1" name="DAC" description="DAC Interrupt CPU Select" />
-      <BitField start="20" size="1" name="I2S" description="I2S Interrupt CPU Select" />
-      <BitField start="22" size="1" name="PCC" description="PCC Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x144" size="4" name="TAL_INTCPUSEL7" access="Read/Write" description="Interrupts CPU Select 7" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
-    <Register start="+0x148" size="4" name="TAL_INTCPUSEL8" access="Read/Write" description="Interrupts CPU Select 8" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDHC0" description="SDHC0 Interrupt CPU Select" />
-      <BitField start="2" size="1" name="SDHC1" description="SDHC1 Interrupt CPU Select" />
-    </Register>
-    <Register start="+0x164" size="4" name="TAL_IRQTRIG" access="Read/Write" description="Interrupt Trigger" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Trigger Enable" />
-      <BitField start="8" size="8" name="IRQNUM" description="Interrupt Request Number" />
-      <BitField start="16" size="8" name="OVERRIDE" description="Interrupt Request Override Value" />
-    </Register>
-    <Register start="+0x168+0" size="2" name="TAL_IRQMON0" access="Read/Write" description="Interrupt Monitor Select" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTEND" description="Extended Interrupt Request">
-        <Enum name="NO" start="0x0" description="Event is Interrupt Request signal" />
-        <Enum name="YES" start="0x1" description="Event is Interrupt Request signal extended until end of Interrupt Handler" />
-      </BitField>
-      <BitField start="1" size="1" name="DROP" description="Drop Shortened Events" />
-      <BitField start="2" size="1" name="CPUID" description="ID of CPU currently servicing this IRQ" />
-      <BitField start="8" size="8" name="IRQNUM" description="Interrupt Request Number" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="TAL_CPUIRQS0_0" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="TAL_CPUIRQS0_1" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="TAL_CPUIRQS0_2" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+12" size="4" name="TAL_CPUIRQS0_3" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x180+16" size="4" name="TAL_CPUIRQS0_4" access="ReadOnly" description="Interrupt Status m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+0" size="4" name="TAL_CPUIRQS1_0" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+4" size="4" name="TAL_CPUIRQS1_1" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+8" size="4" name="TAL_CPUIRQS1_2" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+12" size="4" name="TAL_CPUIRQS1_3" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x1a0+16" size="4" name="TAL_CPUIRQS1_4" access="ReadOnly" description="Interrupt Status m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CPUIRQS" description="Interrupt Requests for CPU n" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="TAL_SMASK0_0" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="TAL_SMASK0_1" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x208+0" size="4" name="TAL_SMASK1_0" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x208+4" size="4" name="TAL_SMASK1_1" access="Read/Write" description="Inter-Process Signal Mask m for CPU n - Group 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x220+0" size="4" name="TAL_SFLAGCLR0" access="WriteOnly" description="Inter-Process Signal Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x220+4" size="4" name="TAL_SFLAGCLR1" access="WriteOnly" description="Inter-Process Signal Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x228+0" size="4" name="TAL_SFLAGSET0" access="WriteOnly" description="Inter-Process Signal Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x228+4" size="4" name="TAL_SFLAGSET1" access="WriteOnly" description="Inter-Process Signal Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x230+0" size="4" name="TAL_SFLAG0" access="ReadOnly" description="Inter-Process Signal Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x230+4" size="4" name="TAL_SFLAG1" access="ReadOnly" description="Inter-Process Signal Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS0" description="Inter-Process Signal 0" />
-      <BitField start="1" size="1" name="IPS1" description="Inter-Process Signal 1" />
-      <BitField start="2" size="1" name="IPS2" description="Inter-Process Signal 2" />
-      <BitField start="3" size="1" name="IPS3" description="Inter-Process Signal 3" />
-      <BitField start="4" size="1" name="IPS4" description="Inter-Process Signal 4" />
-      <BitField start="5" size="1" name="IPS5" description="Inter-Process Signal 5" />
-      <BitField start="6" size="1" name="IPS6" description="Inter-Process Signal 6" />
-      <BitField start="7" size="1" name="IPS7" description="Inter-Process Signal 7" />
-      <BitField start="8" size="1" name="IPS8" description="Inter-Process Signal 8" />
-      <BitField start="9" size="1" name="IPS9" description="Inter-Process Signal 9" />
-      <BitField start="10" size="1" name="IPS10" description="Inter-Process Signal 10" />
-      <BitField start="11" size="1" name="IPS11" description="Inter-Process Signal 11" />
-      <BitField start="12" size="1" name="IPS12" description="Inter-Process Signal 12" />
-      <BitField start="13" size="1" name="IPS13" description="Inter-Process Signal 13" />
-      <BitField start="14" size="1" name="IPS14" description="Inter-Process Signal 14" />
-      <BitField start="15" size="1" name="IPS15" description="Inter-Process Signal 15" />
-      <BitField start="16" size="1" name="IPS16" description="Inter-Process Signal 16" />
-      <BitField start="17" size="1" name="IPS17" description="Inter-Process Signal 17" />
-      <BitField start="18" size="1" name="IPS18" description="Inter-Process Signal 18" />
-      <BitField start="19" size="1" name="IPS19" description="Inter-Process Signal 19" />
-      <BitField start="20" size="1" name="IPS20" description="Inter-Process Signal 20" />
-      <BitField start="21" size="1" name="IPS21" description="Inter-Process Signal 21" />
-      <BitField start="22" size="1" name="IPS22" description="Inter-Process Signal 22" />
-      <BitField start="23" size="1" name="IPS23" description="Inter-Process Signal 23" />
-      <BitField start="24" size="1" name="IPS24" description="Inter-Process Signal 24" />
-      <BitField start="25" size="1" name="IPS25" description="Inter-Process Signal 25" />
-      <BitField start="26" size="1" name="IPS26" description="Inter-Process Signal 26" />
-      <BitField start="27" size="1" name="IPS27" description="Inter-Process Signal 27" />
-      <BitField start="28" size="1" name="IPS28" description="Inter-Process Signal 28" />
-      <BitField start="29" size="1" name="IPS29" description="Inter-Process Signal 29" />
-      <BitField start="30" size="1" name="IPS30" description="Inter-Process Signal 30" />
-      <BitField start="31" size="1" name="IPS31" description="Inter-Process Signal 31" />
-    </Register>
-    <Register start="+0x300+0" size="1" name="TAL_SFLAGCLRR0" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+1" size="1" name="TAL_SFLAGCLRR1" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+2" size="1" name="TAL_SFLAGCLRR2" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+3" size="1" name="TAL_SFLAGCLRR3" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+4" size="1" name="TAL_SFLAGCLRR4" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+5" size="1" name="TAL_SFLAGCLRR5" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+6" size="1" name="TAL_SFLAGCLRR6" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+7" size="1" name="TAL_SFLAGCLRR7" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+8" size="1" name="TAL_SFLAGCLRR8" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+9" size="1" name="TAL_SFLAGCLRR9" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+10" size="1" name="TAL_SFLAGCLRR10" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+11" size="1" name="TAL_SFLAGCLRR11" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+12" size="1" name="TAL_SFLAGCLRR12" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+13" size="1" name="TAL_SFLAGCLRR13" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+14" size="1" name="TAL_SFLAGCLRR14" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+15" size="1" name="TAL_SFLAGCLRR15" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+16" size="1" name="TAL_SFLAGCLRR16" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+17" size="1" name="TAL_SFLAGCLRR17" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+18" size="1" name="TAL_SFLAGCLRR18" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+19" size="1" name="TAL_SFLAGCLRR19" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+20" size="1" name="TAL_SFLAGCLRR20" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+21" size="1" name="TAL_SFLAGCLRR21" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+22" size="1" name="TAL_SFLAGCLRR22" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+23" size="1" name="TAL_SFLAGCLRR23" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+24" size="1" name="TAL_SFLAGCLRR24" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+25" size="1" name="TAL_SFLAGCLRR25" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+26" size="1" name="TAL_SFLAGCLRR26" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+27" size="1" name="TAL_SFLAGCLRR27" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+28" size="1" name="TAL_SFLAGCLRR28" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+29" size="1" name="TAL_SFLAGCLRR29" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+30" size="1" name="TAL_SFLAGCLRR30" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+31" size="1" name="TAL_SFLAGCLRR31" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+32" size="1" name="TAL_SFLAGCLRR32" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+33" size="1" name="TAL_SFLAGCLRR33" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+34" size="1" name="TAL_SFLAGCLRR34" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+35" size="1" name="TAL_SFLAGCLRR35" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+36" size="1" name="TAL_SFLAGCLRR36" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+37" size="1" name="TAL_SFLAGCLRR37" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+38" size="1" name="TAL_SFLAGCLRR38" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+39" size="1" name="TAL_SFLAGCLRR39" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+40" size="1" name="TAL_SFLAGCLRR40" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+41" size="1" name="TAL_SFLAGCLRR41" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+42" size="1" name="TAL_SFLAGCLRR42" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+43" size="1" name="TAL_SFLAGCLRR43" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+44" size="1" name="TAL_SFLAGCLRR44" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+45" size="1" name="TAL_SFLAGCLRR45" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+46" size="1" name="TAL_SFLAGCLRR46" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+47" size="1" name="TAL_SFLAGCLRR47" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+48" size="1" name="TAL_SFLAGCLRR48" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+49" size="1" name="TAL_SFLAGCLRR49" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+50" size="1" name="TAL_SFLAGCLRR50" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+51" size="1" name="TAL_SFLAGCLRR51" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+52" size="1" name="TAL_SFLAGCLRR52" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+53" size="1" name="TAL_SFLAGCLRR53" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+54" size="1" name="TAL_SFLAGCLRR54" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+55" size="1" name="TAL_SFLAGCLRR55" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+56" size="1" name="TAL_SFLAGCLRR56" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+57" size="1" name="TAL_SFLAGCLRR57" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+58" size="1" name="TAL_SFLAGCLRR58" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+59" size="1" name="TAL_SFLAGCLRR59" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+60" size="1" name="TAL_SFLAGCLRR60" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+61" size="1" name="TAL_SFLAGCLRR61" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+62" size="1" name="TAL_SFLAGCLRR62" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-    <Register start="+0x300+63" size="1" name="TAL_SFLAGCLRR63" access="Read/Write" description="Inter-Process Signal Flag Bit n" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IPS" description="Inter-Process Signal n" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC0 (COUNT8)" start="0x40003800" description="Basic Timer Counter 0">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC0 (COUNT16)" start="0x40003800" description="Basic Timer Counter 0">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC0 (COUNT32)" start="0x40003800" description="Basic Timer Counter 0">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC1 (COUNT8)" start="0x40003C00" description="Basic Timer Counter 1">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC1 (COUNT16)" start="0x40003C00" description="Basic Timer Counter 1">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC1 (COUNT32)" start="0x40003C00" description="Basic Timer Counter 1">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC2 (COUNT8)" start="0x4101A000" description="Basic Timer Counter 2">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC2 (COUNT16)" start="0x4101A000" description="Basic Timer Counter 2">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC2 (COUNT32)" start="0x4101A000" description="Basic Timer Counter 2">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT8)" start="0x4101C000" description="Basic Timer Counter 3">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT16)" start="0x4101C000" description="Basic Timer Counter 3">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC3 (COUNT32)" start="0x4101C000" description="Basic Timer Counter 3">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT8)" start="0x42001400" description="Basic Timer Counter 4">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT16)" start="0x42001400" description="Basic Timer Counter 4">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC4 (COUNT32)" start="0x42001400" description="Basic Timer Counter 4">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT8)" start="0x42001800" description="Basic Timer Counter 5">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="1" name="TC_COUNT" access="Read/Write" description="COUNT8 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1B" size="1" name="TC_PER" access="Read/Write" description="COUNT8 Period" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x1C+0" size="1" name="TC_CC0" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+1" size="1" name="TC_CC1" access="Read/Write" description="COUNT8 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x2F" size="1" name="TC_PERBUF" access="Read/Write" description="COUNT8 Period Buffer" reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x30+0" size="1" name="TC_CCBUF0" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+1" size="1" name="TC_CCBUF1" access="Read/Write" description="COUNT8 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT16)" start="0x42001800" description="Basic Timer Counter 5">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="2" name="TC_COUNT" access="Read/Write" description="COUNT16 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="2" name="TC_CC0" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+2" size="2" name="TC_CC1" access="Read/Write" description="COUNT16 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="2" name="TC_CCBUF0" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+2" size="2" name="TC_CCBUF1" access="Read/Write" description="COUNT16 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TC5 (COUNT32)" start="0x42001800" description="Basic Timer Counter 5">
-    <Register start="+0x00" size="4" name="TC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="2" name="MODE" description="Timer Counter Mode">
-        <Enum name="COUNT16" start="0x0" description="Counter in 16-bit mode" />
-        <Enum name="COUNT8" start="0x1" description="Counter in 8-bit mode" />
-        <Enum name="COUNT32" start="0x2" description="Counter in 32-bit mode" />
-      </BitField>
-      <BitField start="4" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization">
-        <Enum name="GCLK" start="0x0" description="Reload or reset the counter on next generic clock" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset the counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset the counter on next generic clock and reset the prescaler counter" />
-      </BitField>
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run during Standby" />
-      <BitField start="7" size="1" name="ONDEMAND" description="Clock On Demand" />
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="Prescaler: GCLK_TC" />
-        <Enum name="DIV2" start="0x1" description="Prescaler: GCLK_TC/2" />
-        <Enum name="DIV4" start="0x2" description="Prescaler: GCLK_TC/4" />
-        <Enum name="DIV8" start="0x3" description="Prescaler: GCLK_TC/8" />
-        <Enum name="DIV16" start="0x4" description="Prescaler: GCLK_TC/16" />
-        <Enum name="DIV64" start="0x5" description="Prescaler: GCLK_TC/64" />
-        <Enum name="DIV256" start="0x6" description="Prescaler: GCLK_TC/256" />
-        <Enum name="DIV1024" start="0x7" description="Prescaler: GCLK_TC/1024" />
-      </BitField>
-      <BitField start="11" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="16" size="1" name="CAPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="17" size="1" name="CAPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="20" size="1" name="COPEN0" description="Capture On Pin 0 Enable" />
-      <BitField start="21" size="1" name="COPEN1" description="Capture On Pin 1 Enable" />
-      <BitField start="24" size="2" name="CAPTMODE0" description="Capture Mode Channel 0">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-      <BitField start="27" size="2" name="CAPTMODE1" description="Capture mode Channel 1">
-        <Enum name="DEFAULT" start="0x0" description="Default capture" />
-        <Enum name="CAPTMIN" start="0x1" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x2" description="Maximum capture" />
-      </BitField>
-    </Register>
-    <Register start="+0x04" size="1" name="TC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot on Counter" />
-      <BitField start="5" size="3" name="CMD" description="Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Force a start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force a stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update of double-buffered register" />
-        <Enum name="READSYNC" start="0x4" description="Force a read synchronization of COUNT" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x06" size="2" name="TC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT" description="Event Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or retrigger TC on event" />
-        <Enum name="COUNT" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start TC on event" />
-        <Enum name="STAMP" start="0x4" description="Time stamp capture" />
-        <Enum name="PPW" start="0x5" description="Period catured in CC0, pulse width in CC1" />
-        <Enum name="PWP" start="0x6" description="Period catured in CC1, pulse width in CC0" />
-        <Enum name="PW" start="0x7" description="Pulse width capture" />
-      </BitField>
-      <BitField start="4" size="1" name="TCINV" description="TC Event Input Polarity" />
-      <BitField start="5" size="1" name="TCEI" description="TC Event Enable" />
-      <BitField start="8" size="1" name="OVFEO" description="Event Output Enable" />
-      <BitField start="12" size="1" name="MCEO0" description="MC Event Output Enable 0" />
-      <BitField start="13" size="1" name="MCEO1" description="MC Event Output Enable 1" />
-    </Register>
-    <Register start="+0x08" size="1" name="TC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Disable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Disable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Disable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Disable 1" />
-    </Register>
-    <Register start="+0x09" size="1" name="TC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Enable" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Enable" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Enable 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Enable 1" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="OVF Interrupt Flag" />
-      <BitField start="1" size="1" name="ERR" description="ERR Interrupt Flag" />
-      <BitField start="4" size="1" name="MC0" description="MC Interrupt Flag 0" />
-      <BitField start="5" size="1" name="MC1" description="MC Interrupt Flag 1" />
-    </Register>
-    <Register start="+0x0B" size="1" name="TC_STATUS" access="Read/Write" description="Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop Status Flag" />
-      <BitField start="1" size="1" name="SLAVE" description="Slave Status Flag" />
-      <BitField start="3" size="1" name="PERBUFV" description="Synchronization Busy Status" />
-      <BitField start="4" size="1" name="CCBUFV0" description="Compare channel buffer 0 valid" />
-      <BitField start="5" size="1" name="CCBUFV1" description="Compare channel buffer 1 valid" />
-    </Register>
-    <Register start="+0x0C" size="1" name="TC_WAVE" access="Read/Write" description="Waveform Generation Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WAVEGEN" description="Waveform Generation Mode">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="MPWM" start="0x3" description="Match PWM" />
-      </BitField>
-    </Register>
-    <Register start="+0x0D" size="1" name="TC_DRVCTRL" access="Read/Write" description="Control C" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INVEN0" description="Output Waveform Invert Enable 0" />
-      <BitField start="1" size="1" name="INVEN1" description="Output Waveform Invert Enable 1" />
-    </Register>
-    <Register start="+0x0F" size="1" name="TC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Run During Debug" />
-    </Register>
-    <Register start="+0x10" size="4" name="TC_SYNCBUSY" access="ReadOnly" description="Synchronization Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="swrst" />
-      <BitField start="1" size="1" name="ENABLE" description="enable" />
-      <BitField start="2" size="1" name="CTRLB" description="CTRLB" />
-      <BitField start="3" size="1" name="STATUS" description="STATUS" />
-      <BitField start="4" size="1" name="COUNT" description="Counter" />
-      <BitField start="5" size="1" name="PER" description="Period" />
-      <BitField start="6" size="1" name="CC0" description="Compare Channel 0" />
-      <BitField start="7" size="1" name="CC1" description="Compare Channel 1" />
-    </Register>
-    <Register start="+0x14" size="4" name="TC_COUNT" access="Read/Write" description="COUNT32 Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x1C+0" size="4" name="TC_CC0" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x1C+4" size="4" name="TC_CC1" access="Read/Write" description="COUNT32 Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CC" description="Counter/Compare Value" />
-    </Register>
-    <Register start="+0x30+0" size="4" name="TC_CCBUF0" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-    <Register start="+0x30+4" size="4" name="TC_CCBUF1" access="Read/Write" description="COUNT32 Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CCBUF" description="Counter/Compare Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC0" start="0x41016000" description="Timer Counter Control 0">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC1" start="0x41018000" description="Timer Counter Control 1">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC2" start="0x42000C00" description="Timer Counter Control 2">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC3" start="0x42001000" description="Timer Counter Control 3">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TCC4" start="0x43001000" description="Timer Counter Control 4">
-    <Register start="+0x00" size="4" name="TCC_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="5" size="2" name="RESOLUTION" description="Enhanced Resolution">
-        <Enum name="NONE" start="0x0" description="Dithering is disabled" />
-        <Enum name="DITH4" start="0x1" description="Dithering is done every 16 PWM frames" />
-        <Enum name="DITH5" start="0x2" description="Dithering is done every 32 PWM frames" />
-        <Enum name="DITH6" start="0x3" description="Dithering is done every 64 PWM frames" />
-      </BitField>
-      <BitField start="8" size="3" name="PRESCALER" description="Prescaler">
-        <Enum name="DIV1" start="0x0" description="No division" />
-        <Enum name="DIV2" start="0x1" description="Divide by 2" />
-        <Enum name="DIV4" start="0x2" description="Divide by 4" />
-        <Enum name="DIV8" start="0x3" description="Divide by 8" />
-        <Enum name="DIV16" start="0x4" description="Divide by 16" />
-        <Enum name="DIV64" start="0x5" description="Divide by 64" />
-        <Enum name="DIV256" start="0x6" description="Divide by 256" />
-        <Enum name="DIV1024" start="0x7" description="Divide by 1024" />
-      </BitField>
-      <BitField start="11" size="1" name="RUNSTDBY" description="Run in Standby" />
-      <BitField start="12" size="2" name="PRESCSYNC" description="Prescaler and Counter Synchronization Selection">
-        <Enum name="GCLK" start="0x0" description="Reload or reset counter on next GCLK" />
-        <Enum name="PRESC" start="0x1" description="Reload or reset counter on next prescaler clock" />
-        <Enum name="RESYNC" start="0x2" description="Reload or reset counter on next GCLK and reset prescaler counter" />
-      </BitField>
-      <BitField start="14" size="1" name="ALOCK" description="Auto Lock" />
-      <BitField start="15" size="1" name="MSYNC" description="Master Synchronization (only for TCC Slave Instance)" />
-      <BitField start="23" size="1" name="DMAOS" description="DMA One-shot Trigger Mode" />
-      <BitField start="24" size="1" name="CPTEN0" description="Capture Channel 0 Enable" />
-      <BitField start="25" size="1" name="CPTEN1" description="Capture Channel 1 Enable" />
-      <BitField start="26" size="1" name="CPTEN2" description="Capture Channel 2 Enable" />
-      <BitField start="27" size="1" name="CPTEN3" description="Capture Channel 3 Enable" />
-      <BitField start="28" size="1" name="CPTEN4" description="Capture Channel 4 Enable" />
-      <BitField start="29" size="1" name="CPTEN5" description="Capture Channel 5 Enable" />
-    </Register>
-    <Register start="+0x04" size="1" name="TCC_CTRLBCLR" access="Read/Write" description="Control B Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x05" size="1" name="TCC_CTRLBSET" access="Read/Write" description="Control B Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Counter Direction" />
-      <BitField start="1" size="1" name="LUPD" description="Lock Update" />
-      <BitField start="2" size="1" name="ONESHOT" description="One-Shot" />
-      <BitField start="3" size="2" name="IDXCMD" description="Ramp Index Command">
-        <Enum name="DISABLE" start="0x0" description="Command disabled: Index toggles between cycles A and B" />
-        <Enum name="SET" start="0x1" description="Set index: cycle B will be forced in the next cycle" />
-        <Enum name="CLEAR" start="0x2" description="Clear index: cycle A will be forced in the next cycle" />
-        <Enum name="HOLD" start="0x3" description="Hold index: the next cycle will be the same as the current cycle" />
-      </BitField>
-      <BitField start="5" size="3" name="CMD" description="TCC Command">
-        <Enum name="NONE" start="0x0" description="No action" />
-        <Enum name="RETRIGGER" start="0x1" description="Clear start, restart or retrigger" />
-        <Enum name="STOP" start="0x2" description="Force stop" />
-        <Enum name="UPDATE" start="0x3" description="Force update or double buffered registers" />
-        <Enum name="READSYNC" start="0x4" description="Force COUNT read synchronization" />
-        <Enum name="DMAOS" start="0x5" description="One-shot DMA trigger" />
-      </BitField>
-    </Register>
-    <Register start="+0x08" size="4" name="TCC_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Swrst Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Busy" />
-      <BitField start="2" size="1" name="CTRLB" description="Ctrlb Busy" />
-      <BitField start="3" size="1" name="STATUS" description="Status Busy" />
-      <BitField start="4" size="1" name="COUNT" description="Count Busy" />
-      <BitField start="5" size="1" name="PATT" description="Pattern Busy" />
-      <BitField start="6" size="1" name="WAVE" description="Wave Busy" />
-      <BitField start="7" size="1" name="PER" description="Period Busy" />
-      <BitField start="8" size="1" name="CC0" description="Compare Channel 0 Busy" />
-      <BitField start="9" size="1" name="CC1" description="Compare Channel 1 Busy" />
-      <BitField start="10" size="1" name="CC2" description="Compare Channel 2 Busy" />
-      <BitField start="11" size="1" name="CC3" description="Compare Channel 3 Busy" />
-      <BitField start="12" size="1" name="CC4" description="Compare Channel 4 Busy" />
-      <BitField start="13" size="1" name="CC5" description="Compare Channel 5 Busy" />
-    </Register>
-    <Register start="+0x0C" size="4" name="TCC_FCTRLA" access="Read/Write" description="Recoverable Fault A Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault A Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault A Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault A Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault A Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault A Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault A Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault A Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault A Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault A Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault A Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault A Filter Value" />
-    </Register>
-    <Register start="+0x10" size="4" name="TCC_FCTRLB" access="Read/Write" description="Recoverable Fault B Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SRC" description="Fault B Source">
-        <Enum name="DISABLE" start="0x0" description="Fault input disabled" />
-        <Enum name="ENABLE" start="0x1" description="MCEx (x=0,1) event input" />
-        <Enum name="INVERT" start="0x2" description="Inverted MCEx (x=0,1) event input" />
-        <Enum name="ALTFAULT" start="0x3" description="Alternate fault (A or B) state at the end of the previous period" />
-      </BitField>
-      <BitField start="3" size="1" name="KEEP" description="Fault B Keeper" />
-      <BitField start="4" size="1" name="QUAL" description="Fault B Qualification" />
-      <BitField start="5" size="2" name="BLANK" description="Fault B Blanking Mode">
-        <Enum name="START" start="0x0" description="Blanking applied from start of the ramp" />
-        <Enum name="RISE" start="0x1" description="Blanking applied from rising edge of the output waveform" />
-        <Enum name="FALL" start="0x2" description="Blanking applied from falling edge of the output waveform" />
-        <Enum name="BOTH" start="0x3" description="Blanking applied from each toggle of the output waveform" />
-      </BitField>
-      <BitField start="7" size="1" name="RESTART" description="Fault B Restart" />
-      <BitField start="8" size="2" name="HALT" description="Fault B Halt Mode">
-        <Enum name="DISABLE" start="0x0" description="Halt action disabled" />
-        <Enum name="HW" start="0x1" description="Hardware halt action" />
-        <Enum name="SW" start="0x2" description="Software halt action" />
-        <Enum name="NR" start="0x3" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="10" size="2" name="CHSEL" description="Fault B Capture Channel">
-        <Enum name="CC0" start="0x0" description="Capture value stored in channel 0" />
-        <Enum name="CC1" start="0x1" description="Capture value stored in channel 1" />
-        <Enum name="CC2" start="0x2" description="Capture value stored in channel 2" />
-        <Enum name="CC3" start="0x3" description="Capture value stored in channel 3" />
-      </BitField>
-      <BitField start="12" size="3" name="CAPTURE" description="Fault B Capture Action">
-        <Enum name="DISABLE" start="0x0" description="No capture" />
-        <Enum name="CAPT" start="0x1" description="Capture on fault" />
-        <Enum name="CAPTMIN" start="0x2" description="Minimum capture" />
-        <Enum name="CAPTMAX" start="0x3" description="Maximum capture" />
-        <Enum name="LOCMIN" start="0x4" description="Minimum local detection" />
-        <Enum name="LOCMAX" start="0x5" description="Maximum local detection" />
-        <Enum name="DERIV0" start="0x6" description="Minimum and maximum local detection" />
-        <Enum name="CAPTMARK" start="0x7" description="Capture with ramp index as MSB value" />
-      </BitField>
-      <BitField start="15" size="1" name="BLANKPRESC" description="Fault B Blanking Prescaler" />
-      <BitField start="16" size="8" name="BLANKVAL" description="Fault B Blanking Time" />
-      <BitField start="24" size="4" name="FILTERVAL" description="Fault B Filter Value" />
-    </Register>
-    <Register start="+0x14" size="4" name="TCC_WEXCTRL" access="Read/Write" description="Waveform Extension Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="OTMX" description="Output Matrix" />
-      <BitField start="8" size="1" name="DTIEN0" description="Dead-time Insertion Generator 0 Enable" />
-      <BitField start="9" size="1" name="DTIEN1" description="Dead-time Insertion Generator 1 Enable" />
-      <BitField start="10" size="1" name="DTIEN2" description="Dead-time Insertion Generator 2 Enable" />
-      <BitField start="11" size="1" name="DTIEN3" description="Dead-time Insertion Generator 3 Enable" />
-      <BitField start="16" size="8" name="DTLS" description="Dead-time Low Side Outputs Value" />
-      <BitField start="24" size="8" name="DTHS" description="Dead-time High Side Outputs Value" />
-    </Register>
-    <Register start="+0x18" size="4" name="TCC_DRVCTRL" access="Read/Write" description="Driver Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NRE0" description="Non-Recoverable State 0 Output Enable" />
-      <BitField start="1" size="1" name="NRE1" description="Non-Recoverable State 1 Output Enable" />
-      <BitField start="2" size="1" name="NRE2" description="Non-Recoverable State 2 Output Enable" />
-      <BitField start="3" size="1" name="NRE3" description="Non-Recoverable State 3 Output Enable" />
-      <BitField start="4" size="1" name="NRE4" description="Non-Recoverable State 4 Output Enable" />
-      <BitField start="5" size="1" name="NRE5" description="Non-Recoverable State 5 Output Enable" />
-      <BitField start="6" size="1" name="NRE6" description="Non-Recoverable State 6 Output Enable" />
-      <BitField start="7" size="1" name="NRE7" description="Non-Recoverable State 7 Output Enable" />
-      <BitField start="8" size="1" name="NRV0" description="Non-Recoverable State 0 Output Value" />
-      <BitField start="9" size="1" name="NRV1" description="Non-Recoverable State 1 Output Value" />
-      <BitField start="10" size="1" name="NRV2" description="Non-Recoverable State 2 Output Value" />
-      <BitField start="11" size="1" name="NRV3" description="Non-Recoverable State 3 Output Value" />
-      <BitField start="12" size="1" name="NRV4" description="Non-Recoverable State 4 Output Value" />
-      <BitField start="13" size="1" name="NRV5" description="Non-Recoverable State 5 Output Value" />
-      <BitField start="14" size="1" name="NRV6" description="Non-Recoverable State 6 Output Value" />
-      <BitField start="15" size="1" name="NRV7" description="Non-Recoverable State 7 Output Value" />
-      <BitField start="16" size="1" name="INVEN0" description="Output Waveform 0 Inversion" />
-      <BitField start="17" size="1" name="INVEN1" description="Output Waveform 1 Inversion" />
-      <BitField start="18" size="1" name="INVEN2" description="Output Waveform 2 Inversion" />
-      <BitField start="19" size="1" name="INVEN3" description="Output Waveform 3 Inversion" />
-      <BitField start="20" size="1" name="INVEN4" description="Output Waveform 4 Inversion" />
-      <BitField start="21" size="1" name="INVEN5" description="Output Waveform 5 Inversion" />
-      <BitField start="22" size="1" name="INVEN6" description="Output Waveform 6 Inversion" />
-      <BitField start="23" size="1" name="INVEN7" description="Output Waveform 7 Inversion" />
-      <BitField start="24" size="4" name="FILTERVAL0" description="Non-Recoverable Fault Input 0 Filter Value" />
-      <BitField start="28" size="4" name="FILTERVAL1" description="Non-Recoverable Fault Input 1 Filter Value" />
-    </Register>
-    <Register start="+0x1E" size="1" name="TCC_DBGCTRL" access="Read/Write" description="Debug Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DBGRUN" description="Debug Running Mode" />
-      <BitField start="2" size="1" name="FDDBD" description="Fault Detection on Debug Break Detection" />
-    </Register>
-    <Register start="+0x20" size="4" name="TCC_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EVACT0" description="Timer/counter Input Event0 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Start, restart or re-trigger counter on event" />
-        <Enum name="COUNTEV" start="0x2" description="Count on event" />
-        <Enum name="START" start="0x3" description="Start counter on event" />
-        <Enum name="INC" start="0x4" description="Increment counter on event" />
-        <Enum name="COUNT" start="0x5" description="Count on active state of asynchronous event" />
-        <Enum name="STAMP" start="0x6" description="Stamp capture" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="3" size="3" name="EVACT1" description="Timer/counter Input Event1 Action">
-        <Enum name="OFF" start="0x0" description="Event action disabled" />
-        <Enum name="RETRIGGER" start="0x1" description="Re-trigger counter on event" />
-        <Enum name="DIR" start="0x2" description="Direction control" />
-        <Enum name="STOP" start="0x3" description="Stop counter on event" />
-        <Enum name="DEC" start="0x4" description="Decrement counter on event" />
-        <Enum name="PPW" start="0x5" description="Period capture value in CC0 register, pulse width capture value in CC1 register" />
-        <Enum name="PWP" start="0x6" description="Period capture value in CC1 register, pulse width capture value in CC0 register" />
-        <Enum name="FAULT" start="0x7" description="Non-recoverable fault" />
-      </BitField>
-      <BitField start="6" size="2" name="CNTSEL" description="Timer/counter Output Event Mode">
-        <Enum name="START" start="0x0" description="An interrupt/event is generated when a new counter cycle starts" />
-        <Enum name="END" start="0x1" description="An interrupt/event is generated when a counter cycle ends" />
-        <Enum name="BETWEEN" start="0x2" description="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" />
-        <Enum name="BOUNDARY" start="0x3" description="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" />
-      </BitField>
-      <BitField start="8" size="1" name="OVFEO" description="Overflow/Underflow Output Event Enable" />
-      <BitField start="9" size="1" name="TRGEO" description="Retrigger Output Event Enable" />
-      <BitField start="10" size="1" name="CNTEO" description="Timer/counter Output Event Enable" />
-      <BitField start="12" size="1" name="TCINV0" description="Inverted Event 0 Input Enable" />
-      <BitField start="13" size="1" name="TCINV1" description="Inverted Event 1 Input Enable" />
-      <BitField start="14" size="1" name="TCEI0" description="Timer/counter Event 0 Input Enable" />
-      <BitField start="15" size="1" name="TCEI1" description="Timer/counter Event 1 Input Enable" />
-      <BitField start="16" size="1" name="MCEI0" description="Match or Capture Channel 0 Event Input Enable" />
-      <BitField start="17" size="1" name="MCEI1" description="Match or Capture Channel 1 Event Input Enable" />
-      <BitField start="18" size="1" name="MCEI2" description="Match or Capture Channel 2 Event Input Enable" />
-      <BitField start="19" size="1" name="MCEI3" description="Match or Capture Channel 3 Event Input Enable" />
-      <BitField start="20" size="1" name="MCEI4" description="Match or Capture Channel 4 Event Input Enable" />
-      <BitField start="21" size="1" name="MCEI5" description="Match or Capture Channel 5 Event Input Enable" />
-      <BitField start="24" size="1" name="MCEO0" description="Match or Capture Channel 0 Event Output Enable" />
-      <BitField start="25" size="1" name="MCEO1" description="Match or Capture Channel 1 Event Output Enable" />
-      <BitField start="26" size="1" name="MCEO2" description="Match or Capture Channel 2 Event Output Enable" />
-      <BitField start="27" size="1" name="MCEO3" description="Match or Capture Channel 3 Event Output Enable" />
-      <BitField start="28" size="1" name="MCEO4" description="Match or Capture Channel 4 Event Output Enable" />
-      <BitField start="29" size="1" name="MCEO5" description="Match or Capture Channel 5 Event Output Enable" />
-    </Register>
-    <Register start="+0x24" size="4" name="TCC_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x28" size="4" name="TCC_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow Interrupt Enable" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger Interrupt Enable" />
-      <BitField start="2" size="1" name="CNT" description="Counter Interrupt Enable" />
-      <BitField start="3" size="1" name="ERR" description="Error Interrupt Enable" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault Interrupt Enable" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault Interrupt Enable" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A Interrupt Enable" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B Interrupt Enable" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 Interrupt Enable" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 Interrupt Enable" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture Channel 0 Interrupt Enable" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture Channel 1 Interrupt Enable" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture Channel 2 Interrupt Enable" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture Channel 3 Interrupt Enable" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture Channel 4 Interrupt Enable" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture Channel 5 Interrupt Enable" />
-    </Register>
-    <Register start="+0x2C" size="4" name="TCC_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="OVF" description="Overflow" />
-      <BitField start="1" size="1" name="TRG" description="Retrigger" />
-      <BitField start="2" size="1" name="CNT" description="Counter" />
-      <BitField start="3" size="1" name="ERR" description="Error" />
-      <BitField start="10" size="1" name="UFS" description="Non-Recoverable Update Fault" />
-      <BitField start="11" size="1" name="DFS" description="Non-Recoverable Debug Fault" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1" />
-      <BitField start="16" size="1" name="MC0" description="Match or Capture 0" />
-      <BitField start="17" size="1" name="MC1" description="Match or Capture 1" />
-      <BitField start="18" size="1" name="MC2" description="Match or Capture 2" />
-      <BitField start="19" size="1" name="MC3" description="Match or Capture 3" />
-      <BitField start="20" size="1" name="MC4" description="Match or Capture 4" />
-      <BitField start="21" size="1" name="MC5" description="Match or Capture 5" />
-    </Register>
-    <Register start="+0x30" size="4" name="TCC_STATUS" access="Read/Write" description="Status" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STOP" description="Stop" />
-      <BitField start="1" size="1" name="IDX" description="Ramp" />
-      <BitField start="2" size="1" name="UFS" description="Non-recoverable Update Fault State" />
-      <BitField start="3" size="1" name="DFS" description="Non-Recoverable Debug Fault State" />
-      <BitField start="4" size="1" name="SLAVE" description="Slave" />
-      <BitField start="5" size="1" name="PATTBUFV" description="Pattern Buffer Valid" />
-      <BitField start="7" size="1" name="PERBUFV" description="Period Buffer Valid" />
-      <BitField start="8" size="1" name="FAULTAIN" description="Recoverable Fault A Input" />
-      <BitField start="9" size="1" name="FAULTBIN" description="Recoverable Fault B Input" />
-      <BitField start="10" size="1" name="FAULT0IN" description="Non-Recoverable Fault0 Input" />
-      <BitField start="11" size="1" name="FAULT1IN" description="Non-Recoverable Fault1 Input" />
-      <BitField start="12" size="1" name="FAULTA" description="Recoverable Fault A State" />
-      <BitField start="13" size="1" name="FAULTB" description="Recoverable Fault B State" />
-      <BitField start="14" size="1" name="FAULT0" description="Non-Recoverable Fault 0 State" />
-      <BitField start="15" size="1" name="FAULT1" description="Non-Recoverable Fault 1 State" />
-      <BitField start="16" size="1" name="CCBUFV0" description="Compare Channel 0 Buffer Valid" />
-      <BitField start="17" size="1" name="CCBUFV1" description="Compare Channel 1 Buffer Valid" />
-      <BitField start="18" size="1" name="CCBUFV2" description="Compare Channel 2 Buffer Valid" />
-      <BitField start="19" size="1" name="CCBUFV3" description="Compare Channel 3 Buffer Valid" />
-      <BitField start="20" size="1" name="CCBUFV4" description="Compare Channel 4 Buffer Valid" />
-      <BitField start="21" size="1" name="CCBUFV5" description="Compare Channel 5 Buffer Valid" />
-      <BitField start="24" size="1" name="CMP0" description="Compare Channel 0 Value" />
-      <BitField start="25" size="1" name="CMP1" description="Compare Channel 1 Value" />
-      <BitField start="26" size="1" name="CMP2" description="Compare Channel 2 Value" />
-      <BitField start="27" size="1" name="CMP3" description="Compare Channel 3 Value" />
-      <BitField start="28" size="1" name="CMP4" description="Compare Channel 4 Value" />
-      <BitField start="29" size="1" name="CMP5" description="Compare Channel 5 Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH4" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="4" size="20" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH5" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="5" size="19" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x34" size="4" name="TCC_COUNT_DITH6" access="Read/Write" description="Count" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="6" size="18" name="COUNT" description="Counter Value" />
-    </Register>
-    <Register start="+0x38" size="2" name="TCC_PATT" access="Read/Write" description="Pattern" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGE0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="1" size="1" name="PGE1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="2" size="1" name="PGE2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="3" size="1" name="PGE3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="4" size="1" name="PGE4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="5" size="1" name="PGE5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="6" size="1" name="PGE6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="7" size="1" name="PGE7" description="Pattern Generator 7 Output Enable" />
-      <BitField start="8" size="1" name="PGV0" description="Pattern Generator 0 Output Value" />
-      <BitField start="9" size="1" name="PGV1" description="Pattern Generator 1 Output Value" />
-      <BitField start="10" size="1" name="PGV2" description="Pattern Generator 2 Output Value" />
-      <BitField start="11" size="1" name="PGV3" description="Pattern Generator 3 Output Value" />
-      <BitField start="12" size="1" name="PGV4" description="Pattern Generator 4 Output Value" />
-      <BitField start="13" size="1" name="PGV5" description="Pattern Generator 5 Output Value" />
-      <BitField start="14" size="1" name="PGV6" description="Pattern Generator 6 Output Value" />
-      <BitField start="15" size="1" name="PGV7" description="Pattern Generator 7 Output Value" />
-    </Register>
-    <Register start="+0x3C" size="4" name="TCC_WAVE" access="Read/Write" description="Waveform Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="WAVEGEN" description="Waveform Generation">
-        <Enum name="NFRQ" start="0x0" description="Normal frequency" />
-        <Enum name="MFRQ" start="0x1" description="Match frequency" />
-        <Enum name="NPWM" start="0x2" description="Normal PWM" />
-        <Enum name="DSCRITICAL" start="0x4" description="Dual-slope critical" />
-        <Enum name="DSBOTTOM" start="0x5" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO" />
-        <Enum name="DSBOTH" start="0x6" description="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" />
-        <Enum name="DSTOP" start="0x7" description="Dual-slope with interrupt/event condition when COUNT reaches TOP" />
-      </BitField>
-      <BitField start="4" size="2" name="RAMP" description="Ramp Mode">
-        <Enum name="RAMP1" start="0x0" description="RAMP1 operation" />
-        <Enum name="RAMP2A" start="0x1" description="Alternative RAMP2 operation" />
-        <Enum name="RAMP2" start="0x2" description="RAMP2 operation" />
-        <Enum name="RAMP2C" start="0x3" description="Critical RAMP2 operation" />
-      </BitField>
-      <BitField start="7" size="1" name="CIPEREN" description="Circular period Enable" />
-      <BitField start="8" size="1" name="CICCEN0" description="Circular Channel 0 Enable" />
-      <BitField start="9" size="1" name="CICCEN1" description="Circular Channel 1 Enable" />
-      <BitField start="10" size="1" name="CICCEN2" description="Circular Channel 2 Enable" />
-      <BitField start="11" size="1" name="CICCEN3" description="Circular Channel 3 Enable" />
-      <BitField start="16" size="1" name="POL0" description="Channel 0 Polarity" />
-      <BitField start="17" size="1" name="POL1" description="Channel 1 Polarity" />
-      <BitField start="18" size="1" name="POL2" description="Channel 2 Polarity" />
-      <BitField start="19" size="1" name="POL3" description="Channel 3 Polarity" />
-      <BitField start="20" size="1" name="POL4" description="Channel 4 Polarity" />
-      <BitField start="21" size="1" name="POL5" description="Channel 5 Polarity" />
-      <BitField start="24" size="1" name="SWAP0" description="Swap DTI Output Pair 0" />
-      <BitField start="25" size="1" name="SWAP1" description="Swap DTI Output Pair 1" />
-      <BitField start="26" size="1" name="SWAP2" description="Swap DTI Output Pair 2" />
-      <BitField start="27" size="1" name="SWAP3" description="Swap DTI Output Pair 3" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH4" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH5" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x40" size="4" name="TCC_PER_DITH6" access="Read/Write" description="Period" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="PER" description="Period Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH4" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="4" size="20" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH5" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="5" size="19" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+0" size="4" name="TCC_CC0_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+4" size="4" name="TCC_CC1_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+8" size="4" name="TCC_CC2_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+12" size="4" name="TCC_CC3_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+16" size="4" name="TCC_CC4_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x44+20" size="4" name="TCC_CC5_DITH6" access="Read/Write" description="Compare and Capture" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHER" description="Dithering Cycle Number" />
-      <BitField start="6" size="18" name="CC" description="Channel Compare/Capture Value" />
-    </Register>
-    <Register start="+0x64" size="2" name="TCC_PATTBUF" access="Read/Write" description="Pattern Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PGEB0" description="Pattern Generator 0 Output Enable Buffer" />
-      <BitField start="1" size="1" name="PGEB1" description="Pattern Generator 1 Output Enable Buffer" />
-      <BitField start="2" size="1" name="PGEB2" description="Pattern Generator 2 Output Enable Buffer" />
-      <BitField start="3" size="1" name="PGEB3" description="Pattern Generator 3 Output Enable Buffer" />
-      <BitField start="4" size="1" name="PGEB4" description="Pattern Generator 4 Output Enable Buffer" />
-      <BitField start="5" size="1" name="PGEB5" description="Pattern Generator 5 Output Enable Buffer" />
-      <BitField start="6" size="1" name="PGEB6" description="Pattern Generator 6 Output Enable Buffer" />
-      <BitField start="7" size="1" name="PGEB7" description="Pattern Generator 7 Output Enable Buffer" />
-      <BitField start="8" size="1" name="PGVB0" description="Pattern Generator 0 Output Enable" />
-      <BitField start="9" size="1" name="PGVB1" description="Pattern Generator 1 Output Enable" />
-      <BitField start="10" size="1" name="PGVB2" description="Pattern Generator 2 Output Enable" />
-      <BitField start="11" size="1" name="PGVB3" description="Pattern Generator 3 Output Enable" />
-      <BitField start="12" size="1" name="PGVB4" description="Pattern Generator 4 Output Enable" />
-      <BitField start="13" size="1" name="PGVB5" description="Pattern Generator 5 Output Enable" />
-      <BitField start="14" size="1" name="PGVB6" description="Pattern Generator 6 Output Enable" />
-      <BitField start="15" size="1" name="PGVB7" description="Pattern Generator 7 Output Enable" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH4" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="4" size="20" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH5" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x6C" size="4" name="TCC_PERBUF_DITH6" access="Read/Write" description="Period Buffer" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="PERBUF" description="Period Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH4" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-      <BitField start="4" size="20" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH5" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="5" size="19" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+0" size="4" name="TCC_CCBUF0_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+4" size="4" name="TCC_CCBUF1_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+8" size="4" name="TCC_CCBUF2_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+12" size="4" name="TCC_CCBUF3_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+16" size="4" name="TCC_CCBUF4_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-    <Register start="+0x70+20" size="4" name="TCC_CCBUF5_DITH6" access="Read/Write" description="Compare and Capture Buffer" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="DITHERBUF" description="Dithering Buffer Cycle Number" />
-      <BitField start="6" size="18" name="CCBUF" description="Channel Compare/Capture Buffer Value" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TRNG" start="0x42002800" description="True Random Generator">
-    <Register start="+0x00" size="1" name="TRNG_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="6" size="1" name="RUNSTDBY" description="Run in Standby" />
-    </Register>
-    <Register start="+0x04" size="1" name="TRNG_EVCTRL" access="Read/Write" description="Event Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDYEO" description="Data Ready Event Output" />
-    </Register>
-    <Register start="+0x08" size="1" name="TRNG_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Data Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x09" size="1" name="TRNG_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Data Ready Interrupt Enable" />
-    </Register>
-    <Register start="+0x0A" size="1" name="TRNG_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATARDY" description="Data Ready Interrupt Flag" />
-    </Register>
-    <Register start="+0x20" size="4" name="TRNG_DATA" access="ReadOnly" description="Output Data" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Output Data" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (DEVICE)" start="0x41000000" description="Universal Serial Bus">
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x0F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service" />
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service" />
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="DEVICE Control B" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DETACH" description="Detach" />
-      <BitField start="1" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration">
-        <Enum name="FS" start="0x0" description="FS : Full Speed" />
-        <Enum name="LS" start="0x1" description="LS : Low Speed" />
-        <Enum name="HS" start="0x2" description="HS : High Speed capable" />
-        <Enum name="HSTM" start="0x3" description="HSTM: High Speed Test Mode (force high-speed mode for test mode)" />
-      </BitField>
-      <BitField start="4" size="1" name="NREPLY" description="No Reply" />
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="7" size="1" name="TSTPCKT" description="Test packet mode" />
-      <BitField start="8" size="1" name="OPMODE2" description="Specific Operational Mode" />
-      <BitField start="9" size="1" name="GNAK" description="Global NAK" />
-      <BitField start="10" size="2" name="LPMHDSK" description="Link Power Management Handshake">
-        <Enum name="NO" start="0x0" description="No handshake. LPM is not supported" />
-        <Enum name="ACK" start="0x1" description="ACK" />
-        <Enum name="NYET" start="0x2" description="NYET" />
-        <Enum name="STALL" start="0x3" description="STALL" />
-      </BitField>
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_DADD" access="Read/Write" description="DEVICE Device Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="DADD" description="Device Address" />
-      <BitField start="7" size="1" name="ADDEN" description="Device Address Enable" />
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="ReadOnly" description="DEVICE Status" reset_value="0x40" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status">
-        <Enum name="FS" start="0x0" description="Full-speed mode" />
-        <Enum name="LS" start="0x1" description="Low-speed mode" />
-        <Enum name="HS" start="0x2" description="High-speed mode" />
-      </BitField>
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status">
-        <Enum name="0" start="0x0" description="SE0/RESET" />
-        <Enum name="1" start="0x1" description="FS-J or LS-K State" />
-        <Enum name="2" start="0x2" description="FS-K or LS-J State" />
-      </BitField>
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="ReadOnly" description="DEVICE Device Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-      <BitField start="15" size="1" name="FNCERR" description="Frame Number CRC Error" />
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="DEVICE Device Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="DEVICE Device Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend Interrupt Enable" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame Interrupt Enable in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet Interrupt Enable" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="DEVICE Device Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SUSPEND" description="Suspend" />
-      <BitField start="1" size="1" name="MSOF" description="Micro Start of Frame in High Speed Mode" />
-      <BitField start="2" size="1" name="SOF" description="Start Of Frame" />
-      <BitField start="3" size="1" name="EORST" description="End of Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="EORSM" description="End Of Resume" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="LPMNYET" description="Link Power Management Not Yet" />
-      <BitField start="9" size="1" name="LPMSUSP" description="Link Power Management Suspend" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_EPINTSMRY" access="ReadOnly" description="DEVICE End Point Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="End Point 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="End Point 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="End Point 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="End Point 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="End Point 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="End Point 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="End Point 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="End Point 7 Interrupt" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_EPCFG0" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_EPCFG1" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_EPCFG2" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_EPCFG3" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_EPCFG4" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_EPCFG5" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_EPCFG6" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_EPCFG7" access="Read/Write" description="DEVICE End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="EPTYPE0" description="End Point Type0" />
-      <BitField start="4" size="3" name="EPTYPE1" description="End Point Type1" />
-      <BitField start="7" size="1" name="NYETDIS" description="NYET Token Disable" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_EPSTATUSCLR0" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_EPSTATUSCLR1" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_EPSTATUSCLR2" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_EPSTATUSCLR3" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_EPSTATUSCLR4" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_EPSTATUSCLR5" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_EPSTATUSCLR6" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_EPSTATUSCLR7" access="WriteOnly" description="DEVICE End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Clear" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Clear" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Clear" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Clear" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_EPSTATUSSET0" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_EPSTATUSSET1" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_EPSTATUSSET2" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_EPSTATUSSET3" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_EPSTATUSSET4" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_EPSTATUSSET5" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_EPSTATUSSET6" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_EPSTATUSSET7" access="WriteOnly" description="DEVICE End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle OUT Set" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle IN Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request Set" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_EPSTATUS0" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_EPSTATUS1" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_EPSTATUS2" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_EPSTATUS3" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_EPSTATUS4" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_EPSTATUS5" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_EPSTATUS6" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_EPSTATUS7" access="ReadOnly" description="DEVICE End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGLOUT" description="Data Toggle Out" />
-      <BitField start="1" size="1" name="DTGLIN" description="Data Toggle In" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="STALLRQ0" description="Stall 0 Request" />
-      <BitField start="5" size="1" name="STALLRQ1" description="Stall 1 Request" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_EPINTFLAG0" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_EPINTFLAG1" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_EPINTFLAG2" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_EPINTFLAG3" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_EPINTFLAG4" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_EPINTFLAG5" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_EPINTFLAG6" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_EPINTFLAG7" access="Read/Write" description="DEVICE End Point Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_EPINTENCLR0" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_EPINTENCLR1" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_EPINTENCLR2" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_EPINTENCLR3" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_EPINTENCLR4" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_EPINTENCLR5" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_EPINTENCLR6" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_EPINTENCLR7" access="Read/Write" description="DEVICE End Point Interrupt Clear Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Disable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Disable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Disable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/Out Interrupt Disable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/Out Interrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_EPINTENSET0" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_EPINTENSET1" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_EPINTENSET2" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_EPINTENSET3" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_EPINTENSET4" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_EPINTENSET5" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_EPINTENSET6" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_EPINTENSET7" access="Read/Write" description="DEVICE End Point Interrupt Set Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL0" description="Error Flow 0 Interrupt Enable" />
-      <BitField start="3" size="1" name="TRFAIL1" description="Error Flow 1 Interrupt Enable" />
-      <BitField start="4" size="1" name="RXSTP" description="Received Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL0" description="Stall 0 In/out Interrupt enable" />
-      <BitField start="6" size="1" name="STALL1" description="Stall 1 In/out Interrupt enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB (HOST)" start="0x41000000" description="Universal Serial Bus">
-    <Register start="+0x000" size="1" name="USB_CTRLA" access="Read/Write" description="Control A" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="RUNSTDBY" description="Run in Standby Mode" />
-      <BitField start="7" size="1" name="MODE" description="Operating Mode">
-        <Enum name="DEVICE" start="0x0" description="Device Mode" />
-        <Enum name="HOST" start="0x1" description="Host Mode" />
-      </BitField>
-    </Register>
-    <Register start="+0x002" size="1" name="USB_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWRST" description="Software Reset Synchronization Busy" />
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-    </Register>
-    <Register start="+0x003" size="1" name="USB_QOSCTRL" access="Read/Write" description="USB Quality Of Service" reset_value="0x0F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CQOS" description="Configuration Quality of Service" />
-      <BitField start="2" size="2" name="DQOS" description="Data Quality of Service" />
-    </Register>
-    <Register start="+0x008" size="2" name="USB_CTRLB" access="Read/Write" description="HOST Control B" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="RESUME" description="Send USB Resume" />
-      <BitField start="2" size="2" name="SPDCONF" description="Speed Configuration for Host">
-        <Enum name="NORMAL" start="0x0" description="Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." />
-        <Enum name="FS" start="0x3" description="Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." />
-      </BitField>
-      <BitField start="4" size="1" name="AUTORESUME" description="Auto Resume Enable" />
-      <BitField start="5" size="1" name="TSTJ" description="Test mode J" />
-      <BitField start="6" size="1" name="TSTK" description="Test mode K" />
-      <BitField start="8" size="1" name="SOFE" description="Start of Frame Generation Enable" />
-      <BitField start="9" size="1" name="BUSRESET" description="Send USB Reset" />
-      <BitField start="10" size="1" name="VBUSOK" description="VBUS is OK" />
-      <BitField start="11" size="1" name="L1RESUME" description="Send L1 Resume" />
-    </Register>
-    <Register start="+0x00A" size="1" name="USB_HSOFC" access="Read/Write" description="HOST Host Start Of Frame Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FLENC" description="Frame Length Control" />
-      <BitField start="7" size="1" name="FLENCE" description="Frame Length Control Enable" />
-    </Register>
-    <Register start="+0x00C" size="1" name="USB_STATUS" access="Read/Write" description="HOST Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="2" name="SPEED" description="Speed Status" />
-      <BitField start="6" size="2" name="LINESTATE" description="USB Line State Status" />
-    </Register>
-    <Register start="+0x00D" size="1" name="USB_FSMSTATUS" access="ReadOnly" description="Finite State Machine Status" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="FSMSTATE" description="Fine State Machine Status">
-        <Enum name="OFF" start="0x1" description="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" />
-        <Enum name="ON" start="0x2" description="ON (L0). It corresponds to the Idle and Active states" />
-        <Enum name="SUSPEND" start="0x4" description="SUSPEND (L2)" />
-        <Enum name="SLEEP" start="0x8" description="SLEEP (L1)" />
-        <Enum name="DNRESUME" start="0x10" description="DNRESUME. Down Stream Resume." />
-        <Enum name="UPRESUME" start="0x20" description="UPRESUME. Up Stream Resume." />
-        <Enum name="RESET" start="0x40" description="RESET. USB lines Reset." />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="2" name="USB_FNUM" access="Read/Write" description="HOST Host Frame Number" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MFNUM" description="Micro Frame Number" />
-      <BitField start="3" size="11" name="FNUM" description="Frame Number" />
-    </Register>
-    <Register start="+0x012" size="1" name="USB_FLENHIGH" access="ReadOnly" description="HOST Host Frame Length" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="FLENHIGH" description="Frame Length" />
-    </Register>
-    <Register start="+0x014" size="2" name="USB_INTENCLR" access="Read/Write" description="HOST Host Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Disable" />
-      <BitField start="3" size="1" name="RST" description="BUS Reset Interrupt Disable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Disable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to Device Interrupt Disable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from Device Interrupt Disable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Disable" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection Interrupt Disable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Disable" />
-    </Register>
-    <Register start="+0x018" size="2" name="USB_INTENSET" access="Read/Write" description="HOST Host Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame Interrupt Enable" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset Interrupt Enable" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up Interrupt Enable" />
-      <BitField start="5" size="1" name="DNRSM" description="DownStream to the Device Interrupt Enable" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume fromthe device Interrupt Enable" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access Interrupt Enable" />
-      <BitField start="8" size="1" name="DCONN" description="Link Power Management Interrupt Enable" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection Interrupt Enable" />
-    </Register>
-    <Register start="+0x01C" size="2" name="USB_INTFLAG" access="Read/Write" description="HOST Host Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="2" size="1" name="HSOF" description="Host Start Of Frame" />
-      <BitField start="3" size="1" name="RST" description="Bus Reset" />
-      <BitField start="4" size="1" name="WAKEUP" description="Wake Up" />
-      <BitField start="5" size="1" name="DNRSM" description="Downstream" />
-      <BitField start="6" size="1" name="UPRSM" description="Upstream Resume from the Device" />
-      <BitField start="7" size="1" name="RAMACER" description="Ram Access" />
-      <BitField start="8" size="1" name="DCONN" description="Device Connection" />
-      <BitField start="9" size="1" name="DDISC" description="Device Disconnection" />
-    </Register>
-    <Register start="+0x020" size="2" name="USB_PINTSMRY" access="ReadOnly" description="HOST Pipe Interrupt Summary" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPINT0" description="Pipe 0 Interrupt" />
-      <BitField start="1" size="1" name="EPINT1" description="Pipe 1 Interrupt" />
-      <BitField start="2" size="1" name="EPINT2" description="Pipe 2 Interrupt" />
-      <BitField start="3" size="1" name="EPINT3" description="Pipe 3 Interrupt" />
-      <BitField start="4" size="1" name="EPINT4" description="Pipe 4 Interrupt" />
-      <BitField start="5" size="1" name="EPINT5" description="Pipe 5 Interrupt" />
-      <BitField start="6" size="1" name="EPINT6" description="Pipe 6 Interrupt" />
-      <BitField start="7" size="1" name="EPINT7" description="Pipe 7 Interrupt" />
-    </Register>
-    <Register start="+0x024" size="4" name="USB_DESCADD" access="Read/Write" description="Descriptor Address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESCADD" description="Descriptor Address Value" />
-    </Register>
-    <Register start="+0x028" size="2" name="USB_PADCAL" access="Read/Write" description="USB PAD Calibration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRANSP" description="USB Pad Transp calibration" />
-      <BitField start="6" size="5" name="TRANSN" description="USB Pad Transn calibration" />
-      <BitField start="12" size="3" name="TRIM" description="USB Pad Trim calibration" />
-    </Register>
-    <Register start="+0x100+0" size="1" name="USB_PCFG0" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+32" size="1" name="USB_PCFG1" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+64" size="1" name="USB_PCFG2" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+96" size="1" name="USB_PCFG3" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+128" size="1" name="USB_PCFG4" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+160" size="1" name="USB_PCFG5" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+192" size="1" name="USB_PCFG6" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x100+224" size="1" name="USB_PCFG7" access="Read/Write" description="HOST End Point Configuration" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PTOKEN" description="Pipe Token" />
-      <BitField start="2" size="1" name="BK" description="Pipe Bank" />
-      <BitField start="3" size="3" name="PTYPE" description="Pipe Type" />
-    </Register>
-    <Register start="+0x103+0" size="1" name="USB_BINTERVAL0" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+32" size="1" name="USB_BINTERVAL1" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+64" size="1" name="USB_BINTERVAL2" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+96" size="1" name="USB_BINTERVAL3" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+128" size="1" name="USB_BINTERVAL4" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+160" size="1" name="USB_BINTERVAL5" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+192" size="1" name="USB_BINTERVAL6" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x103+224" size="1" name="USB_BINTERVAL7" access="Read/Write" description="HOST Bus Access Period of Pipe" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="BITINTERVAL" description="Bit Interval" />
-    </Register>
-    <Register start="+0x104+0" size="1" name="USB_PSTATUSCLR0" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+32" size="1" name="USB_PSTATUSCLR1" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+64" size="1" name="USB_PSTATUSCLR2" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+96" size="1" name="USB_PSTATUSCLR3" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+128" size="1" name="USB_PSTATUSCLR4" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+160" size="1" name="USB_PSTATUSCLR5" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+192" size="1" name="USB_PSTATUSCLR6" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x104+224" size="1" name="USB_PSTATUSCLR7" access="WriteOnly" description="HOST End Point Pipe Status Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle clear" />
-      <BitField start="2" size="1" name="CURBK" description="Curren Bank clear" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Clear" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Clear" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Clear" />
-    </Register>
-    <Register start="+0x105+0" size="1" name="USB_PSTATUSSET0" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+32" size="1" name="USB_PSTATUSSET1" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+64" size="1" name="USB_PSTATUSSET2" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+96" size="1" name="USB_PSTATUSSET3" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+128" size="1" name="USB_PSTATUSSET4" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+160" size="1" name="USB_PSTATUSSET5" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+192" size="1" name="USB_PSTATUSSET6" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x105+224" size="1" name="USB_PSTATUSSET7" access="WriteOnly" description="HOST End Point Pipe Status Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle Set" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank Set" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze Set" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 Ready Set" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 Ready Set" />
-    </Register>
-    <Register start="+0x106+0" size="1" name="USB_PSTATUS0" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+32" size="1" name="USB_PSTATUS1" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+64" size="1" name="USB_PSTATUS2" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+96" size="1" name="USB_PSTATUS3" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+128" size="1" name="USB_PSTATUS4" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+160" size="1" name="USB_PSTATUS5" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+192" size="1" name="USB_PSTATUS6" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x106+224" size="1" name="USB_PSTATUS7" access="ReadOnly" description="HOST End Point Pipe Status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTGL" description="Data Toggle" />
-      <BitField start="2" size="1" name="CURBK" description="Current Bank" />
-      <BitField start="4" size="1" name="PFREEZE" description="Pipe Freeze" />
-      <BitField start="6" size="1" name="BK0RDY" description="Bank 0 ready" />
-      <BitField start="7" size="1" name="BK1RDY" description="Bank 1 ready" />
-    </Register>
-    <Register start="+0x107+0" size="1" name="USB_PINTFLAG0" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+32" size="1" name="USB_PINTFLAG1" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+64" size="1" name="USB_PINTFLAG2" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+96" size="1" name="USB_PINTFLAG3" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+128" size="1" name="USB_PINTFLAG4" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+160" size="1" name="USB_PINTFLAG5" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+192" size="1" name="USB_PINTFLAG6" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x107+224" size="1" name="USB_PINTFLAG7" access="Read/Write" description="HOST Pipe Interrupt Flag" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Flag" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Flag" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Flag" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Flag" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Flag" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Flag" />
-    </Register>
-    <Register start="+0x108+0" size="1" name="USB_PINTENCLR0" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+32" size="1" name="USB_PINTENCLR1" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+64" size="1" name="USB_PINTENCLR2" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+96" size="1" name="USB_PINTENCLR3" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+128" size="1" name="USB_PINTENCLR4" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+160" size="1" name="USB_PINTENCLR5" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+192" size="1" name="USB_PINTENCLR6" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x108+224" size="1" name="USB_PINTENCLR7" access="Read/Write" description="HOST Pipe Interrupt Flag Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Disable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Disable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Disable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Disable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit Setup Interrupt Disable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Inetrrupt Disable" />
-    </Register>
-    <Register start="+0x109+0" size="1" name="USB_PINTENSET0" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+32" size="1" name="USB_PINTENSET1" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+64" size="1" name="USB_PINTENSET2" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+96" size="1" name="USB_PINTENSET3" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+128" size="1" name="USB_PINTENSET4" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+160" size="1" name="USB_PINTENSET5" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+192" size="1" name="USB_PINTENSET6" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-    <Register start="+0x109+224" size="1" name="USB_PINTENSET7" access="Read/Write" description="HOST Pipe Interrupt Flag Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TRCPT0" description="Transfer Complete 0 Interrupt Enable" />
-      <BitField start="1" size="1" name="TRCPT1" description="Transfer Complete 1 Interrupt Enable" />
-      <BitField start="2" size="1" name="TRFAIL" description="Error Flow Interrupt Enable" />
-      <BitField start="3" size="1" name="PERR" description="Pipe Error Interrupt Enable" />
-      <BitField start="4" size="1" name="TXSTP" description="Transmit  Setup Interrupt Enable" />
-      <BitField start="5" size="1" name="STALL" description="Stall Interrupt Enable" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WDT" start="0x40002000" description="Watchdog Timer">
-    <Register start="+0x0" size="1" name="WDT_CTRLA" access="Read/Write" description="Control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable" />
-      <BitField start="2" size="1" name="WEN" description="Watchdog Timer Window Mode Enable" />
-      <BitField start="7" size="1" name="ALWAYSON" description="Always-On" />
-    </Register>
-    <Register start="+0x1" size="1" name="WDT_CONFIG" access="Read/Write" description="Configuration" reset_value="0xBB" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="PER" description="Time-Out Period">
-        <Enum name="CYC8" start="0x0" description="8 clock cycles" />
-        <Enum name="CYC16" start="0x1" description="16 clock cycles" />
-        <Enum name="CYC32" start="0x2" description="32 clock cycles" />
-        <Enum name="CYC64" start="0x3" description="64 clock cycles" />
-        <Enum name="CYC128" start="0x4" description="128 clock cycles" />
-        <Enum name="CYC256" start="0x5" description="256 clock cycles" />
-        <Enum name="CYC512" start="0x6" description="512 clock cycles" />
-        <Enum name="CYC1024" start="0x7" description="1024 clock cycles" />
-        <Enum name="CYC2048" start="0x8" description="2048 clock cycles" />
-        <Enum name="CYC4096" start="0x9" description="4096 clock cycles" />
-        <Enum name="CYC8192" start="0xa" description="8192 clock cycles" />
-        <Enum name="CYC16384" start="0xb" description="16384 clock cycles" />
-      </BitField>
-      <BitField start="4" size="4" name="WINDOW" description="Window Mode Time-Out Period">
-        <Enum name="CYC8" start="0x0" description="8 clock cycles" />
-        <Enum name="CYC16" start="0x1" description="16 clock cycles" />
-        <Enum name="CYC32" start="0x2" description="32 clock cycles" />
-        <Enum name="CYC64" start="0x3" description="64 clock cycles" />
-        <Enum name="CYC128" start="0x4" description="128 clock cycles" />
-        <Enum name="CYC256" start="0x5" description="256 clock cycles" />
-        <Enum name="CYC512" start="0x6" description="512 clock cycles" />
-        <Enum name="CYC1024" start="0x7" description="1024 clock cycles" />
-        <Enum name="CYC2048" start="0x8" description="2048 clock cycles" />
-        <Enum name="CYC4096" start="0x9" description="4096 clock cycles" />
-        <Enum name="CYC8192" start="0xa" description="8192 clock cycles" />
-        <Enum name="CYC16384" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x2" size="1" name="WDT_EWCTRL" access="Read/Write" description="Early Warning Interrupt Control" reset_value="0x0B" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="EWOFFSET" description="Early Warning Interrupt Time Offset">
-        <Enum name="CYC8" start="0x0" description="8 clock cycles" />
-        <Enum name="CYC16" start="0x1" description="16 clock cycles" />
-        <Enum name="CYC32" start="0x2" description="32 clock cycles" />
-        <Enum name="CYC64" start="0x3" description="64 clock cycles" />
-        <Enum name="CYC128" start="0x4" description="128 clock cycles" />
-        <Enum name="CYC256" start="0x5" description="256 clock cycles" />
-        <Enum name="CYC512" start="0x6" description="512 clock cycles" />
-        <Enum name="CYC1024" start="0x7" description="1024 clock cycles" />
-        <Enum name="CYC2048" start="0x8" description="2048 clock cycles" />
-        <Enum name="CYC4096" start="0x9" description="4096 clock cycles" />
-        <Enum name="CYC8192" start="0xa" description="8192 clock cycles" />
-        <Enum name="CYC16384" start="0xb" description="16384 clock cycles" />
-      </BitField>
-    </Register>
-    <Register start="+0x4" size="1" name="WDT_INTENCLR" access="Read/Write" description="Interrupt Enable Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x5" size="1" name="WDT_INTENSET" access="Read/Write" description="Interrupt Enable Set" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning Interrupt Enable" />
-    </Register>
-    <Register start="+0x6" size="1" name="WDT_INTFLAG" access="Read/Write" description="Interrupt Flag Status and Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EW" description="Early Warning" />
-    </Register>
-    <Register start="+0x8" size="4" name="WDT_SYNCBUSY" access="ReadOnly" description="Synchronization Busy" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="1" size="1" name="ENABLE" description="Enable Synchronization Busy" />
-      <BitField start="2" size="1" name="WEN" description="Window Enable Synchronization Busy" />
-      <BitField start="3" size="1" name="ALWAYSON" description="Always-On Synchronization Busy" />
-      <BitField start="4" size="1" name="CLEAR" description="Clear Synchronization Busy" />
-    </Register>
-    <Register start="+0xC" size="1" name="WDT_CLEAR" access="WriteOnly" description="Clear" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLEAR" description="Watchdog Clear">
-        <Enum name="KEY" start="0xa5" description="Clear Key" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000E000" name="SCB">
-    <Register start="0xE000E004" name="ICTR" aka="Interrupt_Control_Type" access="ReadOnly" description="Interrupt Controller Type Register">
-      <BitField size="5" start="0" name="INTLINESNUM" description="Total number of interrupt lines in groups">
-        <Enum name="0...32" start="0x0" />
-        <Enum name="33...64" start="0x1" />
-        <Enum name="65...96" start="0x2" />
-        <Enum name="97...128" start="0x3" />
-        <Enum name="129...160" start="0x4" />
-        <Enum name="161...192" start="0x5" />
-        <Enum name="193...224" start="0x6" />
-        <Enum name="225...256" start="0x7" />
-      </BitField>
-    </Register>
-    <Register start="0xE000E008" name="ACTLR" description="Auxiliary Control Register">
-      <BitField size="1" start="0" name="DISMCYCINT" description="Disable load/store multiple" />
-      <BitField size="1" start="1" name="DISDEFWBUF" description="Disable write buffer" />
-      <BitField size="1" start="2" name="DISFOLD" description="Disable IT folding" />
-      <BitField size="1" start="8" name="DISFPCA" description="Disable FPCA update" />
-      <BitField size="1" start="9" name="DISOOFP" description="Disable out of order FP execution" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000E010" name="SysTick" description="24Bit System Tick Timer for use in RTOS">
-    <Register start="0xE000E010" name="SYST_CSR" aka="SysTick_Control_And_Status" description="SysTick Control and Status Register">
-      <BitField size="1" name="COUNTFLAG" start="16" description="Counter Flag" />
-      <BitField size="1" name="CLKSOURCE" start="2" description="Timer Clock Source" />
-      <BitField size="1" name="TICKINT" start="1" description="Tick Interrupt Enable" />
-      <BitField size="1" name="ENABLE" start="0" description="Enable SysTick Timer" />
-    </Register>
-    <Register start="0xE000E014" name="SYST_RVR" aka="SysTick_Reload_Value" description="SysTick Reload Value Register">
-      <BitField size="24" name="RELOAD" start="0" description="Value to auto reload SysTick after reaching zero" />
-    </Register>
-    <Register start="0xE000E018" name="SYST_CVR" aka="SysTick_Current_Value" description="SysTick Current Value Register">
-      <BitField size="24" name="CURRENT" start="0" description="Current value" />
-    </Register>
-    <Register start="0xE000E01C" name="SYST_CALIB" aka="SysTick_Calibration_Value" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField size="1" name="NOREF" start="31" description="No Ref" />
-      <BitField size="1" name="SKEW" start="30" description="Clock Skew" />
-      <BitField size="24" name="TENMS" start="0" description="Reload value to use for 10ms timing" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000E100" name="NVIC" description="Nested Vectored Interrupt Controller">
-    <Register start="0xE000E100" name="NVIC_ISER0" aka="Irq_0_to_31_Set_Enable" description="Interrupt Set-Enable Register 0" />
-    <Register start="0xE000E104" name="NVIC_ISER1" aka="Irq_32_to_63_Set_Enable" description="Interrupt Set-Enable Register 1" />
-    <Register start="0xE000E108" name="NVIC_ISER2" aka="Irq_64_to_95_Set_Enable" description="Interrupt Set-Enable Register 2" />
-    <Register start="0xE000E10C" name="NVIC_ISER3" aka="Irq_96_to_127_Set_Enable" description="Interrupt Set-Enable Register 3" />
-    <Register start="0xE000E110" name="NVIC_ISER4" aka="Irq_128_to_159_Set_Enable" description="Interrupt Set-Enable Register 4" />
-    <Register start="0xE000E180" name="NVIC_ICER0" aka="Irq_0_to_31_Clear_Enable" description="Interrupt Clear-Enable Register 0" />
-    <Register start="0xE000E184" name="NVIC_ICER1" aka="Irq_32_to_63_Clear_Enable" description="Interrupt Clear-Enable Register 1" />
-    <Register start="0xE000E188" name="NVIC_ICER2" aka="Irq_64_to_95_Clear_Enable" description="Interrupt Clear-Enable Register 2" />
-    <Register start="0xE000E18C" name="NVIC_ICER3" aka="Irq_96_to_127_Clear_Enable" description="Interrupt Clear-Enable Register 3" />
-    <Register start="0xE000E190" name="NVIC_ICER4" aka="Irq_128_to_159_Clear_Enable" description="Interrupt Clear-Enable Register 4" />
-    <Register start="0xE000E200" name="NVIC_ISPR0" aka="Irq_0_to_31_Set_Pending" description="Interrupt Set-Pending Register 0" />
-    <Register start="0xE000E204" name="NVIC_ISPR1" aka="Irq_32_to_63_Set_Pending" description="Interrupt Set-Pending Register 1" />
-    <Register start="0xE000E208" name="NVIC_ISPR2" aka="Irq_64_to_95_Set_Pending" description="Interrupt Set-Pending Register 2" />
-    <Register start="0xE000E20C" name="NVIC_ISPR3" aka="Irq_96_to_127_Set_Pending" description="Interrupt Set-Pending Register 3" />
-    <Register start="0xE000E210" name="NVIC_ISPR4" aka="Irq_128_to_159_Set_Pending" description="Interrupt Set-Pending Register 4" />
-    <Register start="0xE000E280" name="NVIC_ICPR0" aka="Irq_0_to_31_Clear_Pending" description="Interrupt Clear-Pending Register 0" />
-    <Register start="0xE000E284" name="NVIC_ICPR1" aka="Irq_32_to_63_Clear_Pending" description="Interrupt Clear-Pending Register 1" />
-    <Register start="0xE000E288" name="NVIC_ICPR2" aka="Irq_64_to_95_Clear_Pending" description="Interrupt Clear-Pending Register 2" />
-    <Register start="0xE000E28C" name="NVIC_ICPR3" aka="Irq_96_to_127_Clear_Pending" description="Interrupt Clear-Pending Register 3" />
-    <Register start="0xE000E290" name="NVIC_ICPR4" aka="Irq_128_to_159_Clear_Pending" description="Interrupt Clear-Pending Register 4" />
-    <Register start="0xE000E300" name="NVIC_IABR0" aka="Irq_0_to_31_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 0" />
-    <Register start="0xE000E304" name="NVIC_IABR1" aka="Irq_32_to_63_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 1" />
-    <Register start="0xE000E308" name="NVIC_IABR2" aka="Irq_64_to_95_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 2" />
-    <Register start="0xE000E30C" name="NVIC_IABR3" aka="Irq_96_to_127_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 3" />
-    <Register start="0xE000E310" name="NVIC_IABR4" aka="Irq_128_to_159_Active_Bit" access="ReadOnly" description="Interrupt Active Bit Register 4" />
-    <Register start="0xE000E400" name="NVIC_IPR0" aka="Irq_0_to_3_Priority" description="Interrupt Priority Register 0">
-      <BitField size="3" name="PRI_0" start="5" />
-      <BitField size="3" name="PRI_1" start="13" />
-      <BitField size="3" name="PRI_2" start="21" />
-      <BitField size="3" name="PRI_3" start="29" />
-    </Register>
-    <Register start="0xE000E404" name="NVIC_IPR1" aka="Irq_4_to_7_Priority" description="Interrupt Priority Register 1">
-      <BitField size="3" name="PRI_4" start="5" />
-      <BitField size="3" name="PRI_5" start="13" />
-      <BitField size="3" name="PRI_6" start="21" />
-      <BitField size="3" name="PRI_7" start="29" />
-    </Register>
-    <Register start="0xE000E408" name="NVIC_IPR2" aka="Irq_8_to_11_Priority" description="Interrupt Priority Register 2">
-      <BitField size="3" name="PRI_8" start="5" />
-      <BitField size="3" name="PRI_9" start="13" />
-      <BitField size="3" name="PRI_10" start="21" />
-      <BitField size="3" name="PRI_11" start="29" />
-    </Register>
-    <Register start="0xE000E40C" name="NVIC_IPR3" aka="Irq_12_to_15_Priority" description="Interrupt Priority Register 3">
-      <BitField size="3" name="PRI_12" start="5" />
-      <BitField size="3" name="PRI_13" start="13" />
-      <BitField size="3" name="PRI_14" start="21" />
-      <BitField size="3" name="PRI_15" start="29" />
-    </Register>
-    <Register start="0xE000E410" name="NVIC_IPR4" aka="Irq_16_to_19_Priority" description="Interrupt Priority Register 4">
-      <BitField size="3" name="PRI_16" start="5" />
-      <BitField size="3" name="PRI_17" start="13" />
-      <BitField size="3" name="PRI_18" start="21" />
-      <BitField size="3" name="PRI_19" start="29" />
-    </Register>
-    <Register start="0xE000E414" name="NVIC_IPR5" aka="Irq_20_to_23_Priority" description="Interrupt Priority Register 5">
-      <BitField size="3" name="PRI_20" start="5" />
-      <BitField size="3" name="PRI_21" start="13" />
-      <BitField size="3" name="PRI_22" start="21" />
-      <BitField size="3" name="PRI_23" start="29" />
-    </Register>
-    <Register start="0xE000E418" name="NVIC_IPR6" aka="Irq_24_to_27_Priority" description="Interrupt Priority Register 6">
-      <BitField size="3" name="PRI_24" start="5" />
-      <BitField size="3" name="PRI_25" start="13" />
-      <BitField size="3" name="PRI_26" start="21" />
-      <BitField size="3" name="PRI_27" start="29" />
-    </Register>
-    <Register start="0xE000E41C" name="NVIC_IPR7" aka="Irq_28_to_31_Priority" description="Interrupt Priority Register 7">
-      <BitField size="3" name="PRI_28" start="5" />
-      <BitField size="3" name="PRI_29" start="13" />
-      <BitField size="3" name="PRI_30" start="21" />
-      <BitField size="3" name="PRI_31" start="29" />
-    </Register>
-    <Register start="0xE000E420" name="NVIC_IPR8" aka="Irq_32_to_35_Priority" description="Interrupt Priority Register 8">
-      <BitField size="3" name="PRI_32" start="5" />
-      <BitField size="3" name="PRI_33" start="13" />
-      <BitField size="3" name="PRI_34" start="21" />
-      <BitField size="3" name="PRI_35" start="29" />
-    </Register>
-    <Register start="0xE000E424" name="NVIC_IPR9" aka="Irq_36_to_39_Priority" description="Interrupt Priority Register 9">
-      <BitField size="3" name="PRI_36" start="5" />
-      <BitField size="3" name="PRI_37" start="13" />
-      <BitField size="3" name="PRI_38" start="21" />
-      <BitField size="3" name="PRI_39" start="29" />
-    </Register>
-    <Register start="0xE000E428" name="NVIC_IPR10" aka="Irq_40_to_43_Priority" description="Interrupt Priority Register 10">
-      <BitField size="3" name="PRI_40" start="5" />
-      <BitField size="3" name="PRI_41" start="13" />
-      <BitField size="3" name="PRI_42" start="21" />
-      <BitField size="3" name="PRI_43" start="29" />
-    </Register>
-    <Register start="0xE000E42C" name="NVIC_IPR11" aka="Irq_44_to_47_Priority" description="Interrupt Priority Register 11">
-      <BitField size="3" name="PRI_44" start="5" />
-      <BitField size="3" name="PRI_45" start="13" />
-      <BitField size="3" name="PRI_46" start="21" />
-      <BitField size="3" name="PRI_47" start="29" />
-    </Register>
-    <Register start="0xE000E430" name="NVIC_IPR12" aka="Irq_48_to_51_Priority" description="Interrupt Priority Register 12">
-      <BitField size="3" name="PRI_48" start="5" />
-      <BitField size="3" name="PRI_49" start="13" />
-      <BitField size="3" name="PRI_50" start="21" />
-      <BitField size="3" name="PRI_51" start="29" />
-    </Register>
-    <Register start="0xE000E434" name="NVIC_IPR13" aka="Irq_52_to_55_Priority" description="Interrupt Priority Register 13">
-      <BitField size="3" name="PRI_52" start="5" />
-      <BitField size="3" name="PRI_53" start="13" />
-      <BitField size="3" name="PRI_54" start="21" />
-      <BitField size="3" name="PRI_55" start="29" />
-    </Register>
-    <Register start="0xE000E438" name="NVIC_IPR14" aka="Irq_56_to_59_Priority" description="Interrupt Priority Register 14">
-      <BitField size="3" name="PRI_56" start="5" />
-      <BitField size="3" name="PRI_57" start="13" />
-      <BitField size="3" name="PRI_58" start="21" />
-      <BitField size="3" name="PRI_59" start="29" />
-    </Register>
-    <Register start="0xE000E43C" name="NVIC_IPR15" aka="Irq_60_to_63_Priority" description="Interrupt Priority Register 15">
-      <BitField size="3" name="PRI_60" start="5" />
-      <BitField size="3" name="PRI_61" start="13" />
-      <BitField size="3" name="PRI_62" start="21" />
-      <BitField size="3" name="PRI_63" start="29" />
-    </Register>
-    <Register start="0xE000E440" name="NVIC_IPR16" aka="Irq_64_to_67_Priority" description="Interrupt Priority Register 16">
-      <BitField size="3" name="PRI_64" start="5" />
-      <BitField size="3" name="PRI_65" start="13" />
-      <BitField size="3" name="PRI_66" start="21" />
-      <BitField size="3" name="PRI_67" start="29" />
-    </Register>
-    <Register start="0xE000E444" name="NVIC_IPR17" aka="Irq_68_to_71_Priority" description="Interrupt Priority Register 17">
-      <BitField size="3" name="PRI_68" start="5" />
-      <BitField size="3" name="PRI_69" start="13" />
-      <BitField size="3" name="PRI_70" start="21" />
-      <BitField size="3" name="PRI_71" start="29" />
-    </Register>
-    <Register start="0xE000E448" name="NVIC_IPR18" aka="Irq_72_to_75_Priority" description="Interrupt Priority Register 18">
-      <BitField size="3" name="PRI_72" start="5" />
-      <BitField size="3" name="PRI_73" start="13" />
-      <BitField size="3" name="PRI_74" start="21" />
-      <BitField size="3" name="PRI_75" start="29" />
-    </Register>
-    <Register start="0xE000E44C" name="NVIC_IPR19" aka="Irq_76_to_79_Priority" description="Interrupt Priority Register 19">
-      <BitField size="3" name="PRI_76" start="5" />
-      <BitField size="3" name="PRI_77" start="13" />
-      <BitField size="3" name="PRI_78" start="21" />
-      <BitField size="3" name="PRI_79" start="29" />
-    </Register>
-    <Register start="0xE000E450" name="NVIC_IPR20" aka="Irq_80_to_83_Priority" description="Interrupt Priority Register 20">
-      <BitField size="3" name="PRI_80" start="5" />
-      <BitField size="3" name="PRI_81" start="13" />
-      <BitField size="3" name="PRI_82" start="21" />
-      <BitField size="3" name="PRI_83" start="29" />
-    </Register>
-    <Register start="0xE000E454" name="NVIC_IPR21" aka="Irq_84_to_87_Priority" description="Interrupt Priority Register 21">
-      <BitField size="3" name="PRI_84" start="5" />
-      <BitField size="3" name="PRI_85" start="13" />
-      <BitField size="3" name="PRI_86" start="21" />
-      <BitField size="3" name="PRI_87" start="29" />
-    </Register>
-    <Register start="0xE000E458" name="NVIC_IPR22" aka="Irq_88_to_91_Priority" description="Interrupt Priority Register 22">
-      <BitField size="3" name="PRI_88" start="5" />
-      <BitField size="3" name="PRI_89" start="13" />
-      <BitField size="3" name="PRI_90" start="21" />
-      <BitField size="3" name="PRI_91" start="29" />
-    </Register>
-    <Register start="0xE000E45C" name="NVIC_IPR23" aka="Irq_92_to_95_Priority" description="Interrupt Priority Register 23">
-      <BitField size="3" name="PRI_92" start="5" />
-      <BitField size="3" name="PRI_93" start="13" />
-      <BitField size="3" name="PRI_94" start="21" />
-      <BitField size="3" name="PRI_95" start="29" />
-    </Register>
-    <Register start="0xE000E460" name="NVIC_IPR24" aka="Irq_96_to_99_Priority" description="Interrupt Priority Register 24">
-      <BitField size="3" name="PRI_96" start="5" />
-      <BitField size="3" name="PRI_97" start="13" />
-      <BitField size="3" name="PRI_98" start="21" />
-      <BitField size="3" name="PRI_99" start="29" />
-    </Register>
-    <Register start="0xE000E464" name="NVIC_IPR25" aka="Irq_100_to_103_Priority" description="Interrupt Priority Register 25">
-      <BitField size="3" name="PRI_100" start="5" />
-      <BitField size="3" name="PRI_101" start="13" />
-      <BitField size="3" name="PRI_102" start="21" />
-      <BitField size="3" name="PRI_103" start="29" />
-    </Register>
-    <Register start="0xE000E468" name="NVIC_IPR26" aka="Irq_104_to_107_Priority" description="Interrupt Priority Register 26">
-      <BitField size="3" name="PRI_104" start="5" />
-      <BitField size="3" name="PRI_105" start="13" />
-      <BitField size="3" name="PRI_106" start="21" />
-      <BitField size="3" name="PRI_107" start="29" />
-    </Register>
-    <Register start="0xE000E46C" name="NVIC_IPR27" aka="Irq_108_to_111_Priority" description="Interrupt Priority Register 27">
-      <BitField size="3" name="PRI_108" start="5" />
-      <BitField size="3" name="PRI_109" start="13" />
-      <BitField size="3" name="PRI_110" start="21" />
-      <BitField size="3" name="PRI_111" start="29" />
-    </Register>
-    <Register start="0xE000E470" name="NVIC_IPR28" aka="Irq_112_to_115_Priority" description="Interrupt Priority Register 28">
-      <BitField size="3" name="PRI_112" start="5" />
-      <BitField size="3" name="PRI_113" start="13" />
-      <BitField size="3" name="PRI_114" start="21" />
-      <BitField size="3" name="PRI_115" start="29" />
-    </Register>
-    <Register start="0xE000E474" name="NVIC_IPR29" aka="Irq_116_to_119_Priority" description="Interrupt Priority Register 29">
-      <BitField size="3" name="PRI_116" start="5" />
-      <BitField size="3" name="PRI_117" start="13" />
-      <BitField size="3" name="PRI_118" start="21" />
-      <BitField size="3" name="PRI_119" start="29" />
-    </Register>
-    <Register start="0xE000E478" name="NVIC_IPR30" aka="Irq_120_to_123_Priority" description="Interrupt Priority Register 30">
-      <BitField size="3" name="PRI_120" start="5" />
-      <BitField size="3" name="PRI_121" start="13" />
-      <BitField size="3" name="PRI_122" start="21" />
-      <BitField size="3" name="PRI_123" start="29" />
-    </Register>
-    <Register start="0xE000E47C" name="NVIC_IPR31" aka="Irq_124_to_127_Priority" description="Interrupt Priority Register 31">
-      <BitField size="3" name="PRI_124" start="5" />
-      <BitField size="3" name="PRI_125" start="13" />
-      <BitField size="3" name="PRI_126" start="21" />
-      <BitField size="3" name="PRI_127" start="29" />
-    </Register>
-    <Register start="0xE000E480" name="NVIC_IPR32" aka="Irq_128_to_131_Priority" description="Interrupt Priority Register 32">
-      <BitField size="3" name="PRI_128" start="5" />
-      <BitField size="3" name="PRI_129" start="13" />
-      <BitField size="3" name="PRI_130" start="21" />
-      <BitField size="3" name="PRI_131" start="29" />
-    </Register>
-    <Register start="0xE000E484" name="NVIC_IPR33" aka="Irq_132_to_135_Priority" description="Interrupt Priority Register 33">
-      <BitField size="3" name="PRI_132" start="5" />
-      <BitField size="3" name="PRI_133" start="13" />
-      <BitField size="3" name="PRI_134" start="21" />
-      <BitField size="3" name="PRI_135" start="29" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000ED00" name="SCB">
-    <Register start="0xE000ED04" name="ICSR" aka="Interrupt_Control_State" description="Interrupt Control and State Register">
-      <BitField size="1" name="NMIPENDSET" start="31" description="NMI set-pending bit" />
-      <BitField size="1" name="PENDSVSET" start="28" description="PendSV Set-Pending Bit" />
-      <BitField size="1" name="PENDSVCLR" start="27" description="PendSV Clear-Pending Bit" />
-      <BitField size="1" name="PENDSTSET" start="26" description="SysTick Exception Set-Pending Bit" />
-      <BitField size="1" name="PENDSTCLR" start="25" description="SysTick Exception Clear-Pending Bit" />
-      <BitField size="1" name="ISRPREEMPT" start="23" />
-      <BitField size="1" name="ISRPENDING" start="22" description="Interrupt Pending Flag" />
-      <BitField size="9" name="VECTPENDING" start="12" description="Vector Pending" />
-      <BitField size="1" name="RETTOBASE" start="11" description="Return to Base" />
-      <BitField size="9" name="VECTACTIVE" start="0" description="Active Exception Number" />
-    </Register>
-    <Register start="0xE000ED08" name="VTOR" aka="Vector_Table_Offset" description="Vector Table Offset Register">
-      <BitField size="1" name="TBLBASE" start="29" />
-      <BitField size="25" name="TBLOFF" start="7" />
-    </Register>
-    <Register start="0xE000ED0C" name="AIRCR" aka="Application_Interrupt_and_Reset_Control" description="Application Interrupt and Reset Control Register">
-      <BitField size="16" name="VECTKEY" start="16" description="Register Key" />
-      <BitField size="1" name="ENDIANESS" start="15" description="Data Endianness Bit" />
-      <BitField size="3" name="PRIGROUP" start="8" description="Interrupt Priority Grouping Field" />
-      <BitField size="1" name="SYSRESETREQ" start="2" description="System Reset Request" />
-      <BitField size="1" name="VECTCLRACTIVE" start="1" />
-      <BitField size="1" name="VECTRESET" start="0" />
-    </Register>
-    <Register start="0xE000ED10" name="SCR" aka="System_Control" description="System Control Register">
-      <BitField size="1" name="SEVONPEND" start="4" description="Send Event on Pending" />
-      <BitField size="1" name="SLEEPDEEP" start="2" description="Sleep or Deep Sleep" />
-      <BitField size="1" name="SLEEPONEXIT" start="1" description="Sleep on Exit" />
-    </Register>
-    <Register start="0xE000ED14" name="CCR" aka="Configuration_Control" description="Configuration and Control Register">
-      <BitField size="1" name="STKALIGN" start="9" description="Stack Alignment" />
-      <BitField size="1" name="BFHFNMIGN" start="8" description="Bus Fault Hard Fault and NMI Ignore" />
-      <BitField size="1" name="DIV_0_TRP" start="4" description="Divide by Zero Trap Enable" />
-      <BitField size="1" name="UNALIGN_TRP" start="3" description="Unaligned Access Trap Enable" />
-      <BitField size="1" name="USERSETMPEND" start="1" description="User Set Pending Enable" />
-      <BitField size="1" name="NONBASETHRDENA" start="0" description="Non Base Thread Mode Enable" />
-    </Register>
-    <Register start="0xE000ED18" name="SHPR1" aka="System_Handlers_4_7_Priority" description="System Handler Priority Register 1">
-      <BitField size="3" name="PRI_4(MemManage)" start="8-3" description="Priority of system handler 4, MemManage" />
-      <BitField size="3" name="PRI_5(BusFault)" start="16-3" description="Priority of system handler 5, BusFault" />
-      <BitField size="3" name="PRI_6(UsageFault)" start="24-3" description="Priority of system handler 6, UsageFault" />
-      <BitField size="3" name="PRI_7" start="32-3" />
-    </Register>
-    <Register start="0xE000ED1C" name="SHPR2" aka="System_Handlers_8_11_Priority" description="System Handler Priority Register 2">
-      <BitField size="3" name="PRI_8" start="8-3" />
-      <BitField size="3" name="PRI_9" start="16-3" />
-      <BitField size="3" name="PRI_10" start="24-3" />
-      <BitField size="3" name="PRI_11(SVCall)" start="32-3" description="Priority of system handler 11, SVCall" />
-    </Register>
-    <Register start="0xE000ED20" name="SHPR3" aka="System_Handlers_12_15_Priority" description="System Handler Priority Register 3">
-      <BitField size="3" name="PRI_12(DebugMonitor)" start="8-3" />
-      <BitField size="3" name="PRI_13" start="16-3" />
-      <BitField size="3" name="PRI_14(PendSV)" start="24-3" />
-      <BitField size="3" name="PRI_15(SysTick)" start="32-3" />
-    </Register>
-    <Register start="0xE000ED24" name="SHCSR" aka="System_Handler_Control_and_State" description="System Handler Control and State Register">
-      <BitField size="1" name="USGFAULTENA" start="18" description="UsageFault Enable Bit" />
-      <BitField size="1" name="BUSFAULTENA" start="17" description="BusFault Enable Bit" />
-      <BitField size="1" name="MEMFAULTENA" start="16" description="MemManage Enable Bit" />
-      <BitField size="1" name="SVCALLPENDED" start="15" description="SVCall Pending Bit" />
-      <BitField size="1" name="BUSFAULTPENDED" start="14" description="BusFault Exception Pending Bit" />
-      <BitField size="1" name="MEMFAULTPENDED" start="13" description="MemManage Exception Pending Bit" />
-      <BitField size="1" name="USGFAULTPENDED" start="12" description="UsageFault Exception Pending Bit" />
-      <BitField size="1" name="SYSTICKACT" start="11" description="SysTick Exception Active Bit" />
-      <BitField size="1" name="PENDSVACT" start="10" description="PendSV Exception Active Bit" />
-      <BitField size="1" name="MONITORACT" start="8" description="Debug Monitor Active Bit" />
-      <BitField size="1" name="SVCALLACT" start="7" description="SVCall Active Bit" />
-      <BitField size="1" name="USGFAULTACT" start="3" description="UsageFault Exception Active Bit" />
-      <BitField size="1" name="BUSFAULTACT" start="1" description="BusFault Exception Active Bit" />
-      <BitField size="1" name="MEMFAULTACT" start="0" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register start="0xE000ED28" size="1" name="MMFSR" aka="Memory_Manage_Fault_Status">
-      <BitField size="1" name="MMARVALID" start="7" />
-      <BitField size="1" name="MLSPERR" start="5" />
-      <BitField size="1" name="MSTKERR" start="4" />
-      <BitField size="1" name="MUNSTKERR" start="3" />
-      <BitField size="1" name="DACCVIOL" start="1" />
-      <BitField size="1" name="IACCVIOL" start="0" />
-    </Register>
-    <Register start="0xE000ED29" size="1" name="BFSR" aka="Bus_Fault_Status">
-      <BitField size="1" name="BFARVALID" start="7" />
-      <BitField size="1" name="LSPERR" start="5" />
-      <BitField size="1" name="STKERR" start="4" />
-      <BitField size="1" name="UNSTKERR" start="3" />
-      <BitField size="1" name="IMPRECISERR" start="2" />
-      <BitField size="1" name="PRECISERR" start="1" />
-      <BitField size="1" name="IBUSERR" start="0" />
-    </Register>
-    <Register start="0xE000ED2A" size="2" name="UFSR" aka="Usage_Fault_Status">
-      <BitField size="1" name="DIVBYZERO" start="9" />
-      <BitField size="1" name="UNALIGNED" start="8" />
-      <BitField size="1" name="NOCP" start="3" />
-      <BitField size="1" name="INVPC" start="2" />
-      <BitField size="1" name="INVSTATE" start="1" />
-      <BitField size="1" name="UNDEFINSTR" start="0" />
-    </Register>
-    <Register start="0xE000ED2C" name="HFSR" aka="Hard_Fault_Status">
-      <BitField size="1" name="DEBUGEVT" start="31" />
-      <BitField size="1" name="FORCED" start="30" />
-      <BitField size="1" name="VECTTBL" start="1" />
-    </Register>
-    <Register start="0xE000ED30" name="DFSR" aka="Debug_Fault_Status">
-      <BitField size="1" name="EXTERNAL" start="4" />
-      <BitField size="1" name="VCATCH" start="3" />
-      <BitField size="1" name="DWTTRAP" start="2" />
-      <BitField size="1" name="BKPT" start="1" />
-      <BitField size="1" name="HALTED" start="0" />
-    </Register>
-    <Register start="0xE000ED34" name="MMFAR" aka="Memory_Manage_Fault_Address" />
-    <Register start="0xE000ED38" name="BFAR" aka="Bus_Fault_Address" />
-    <Register start="0xE000ED3C" name="AFSR" aka="Auxillary_Fault_Address" />
-    <Register start="0xE000ED88" name="CPACR" description="Coprocessor Access Control Register">
-      <BitField size="2" name="CP0" start="0" />
-      <BitField size="2" name="CP1" start="2" />
-      <BitField size="2" name="CP2" start="4" />
-      <BitField size="2" name="CP3" start="6" />
-      <BitField size="2" name="CP4" start="8" />
-      <BitField size="2" name="CP5" start="10" />
-      <BitField size="2" name="CP6" start="12" />
-      <BitField size="2" name="CP7" start="14" />
-      <BitField size="2" name="CP10" start="20" />
-      <BitField size="2" name="CP11" start="22" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000ED00" name="CPUID">
-    <Register start="0xE000ED00" name="CPUID" aka="CPUID_Base" access="ReadOnly" description="CPUID Base Register">
-      <BitField size="8" name="IMPLEMENTER" start="24" description="Implementer Code" />
-      <BitField size="4" name="VARIANT" start="20" description="Variant Number" />
-      <BitField size="12" name="PARTNO" start="4" description="Part Number" />
-      <BitField size="4" name="REVISION" start="0" description="Revision Number" />
-    </Register>
-    <Register start="0xE000ED40" name="ID_PFR0" aka="PFR0" access="ReadOnly" />
-    <Register start="0xE000ED44" name="ID_PFR1" aka="PFR1" access="ReadOnly" />
-    <Register start="0xE000ED48" name="ID_DFR0" aka="DFR0" access="ReadOnly" />
-    <Register start="0xE000ED4C" name="ID_AFR0" aka="AFR0" access="ReadOnly" />
-    <Register start="0xE000ED50" name="ID_MMFR0" aka="MMFR0" access="ReadOnly" />
-    <Register start="0xE000ED54" name="ID_MMFR1" aka="MMFR1" access="ReadOnly" />
-    <Register start="0xE000ED58" name="ID_MMFR2" aka="MMFR2" access="ReadOnly" />
-    <Register start="0xE000ED5C" name="ID_MMFR3" aka="MMFR3" access="ReadOnly" />
-    <Register start="0xE000ED60" name="ID_ISAR0" aka="ISAR0" access="ReadOnly" />
-    <Register start="0xE000ED64" name="ID_ISAR1" aka="ISAR1" access="ReadOnly" />
-    <Register start="0xE000ED68" name="ID_ISAR2" aka="ISAR2" access="ReadOnly" />
-    <Register start="0xE000ED6C" name="ID_ISAR3" aka="ISAR3" access="ReadOnly" />
-    <Register start="0xE000ED70" name="ID_ISAR4" aka="ISAR4" access="ReadOnly" />
-  </RegisterGroup>
-  <RegisterGroup start="0xE000ED90" name="MPU">
-    <Register start="0xE000ED90" name="MPU_TYPE" aka="MPU_Type" access="ReadOnly" description="MPU Type Register">
-      <BitField size="8" name="IREGION" start="16" description="Number of supported MPU instruction regions" />
-      <BitField size="8" name="DREGION" start="8" description="Number of supported MPU data regions" />
-      <BitField size="8" name="SEPARATE" start="0" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register start="0xE000ED94" name="MPU_CTRL" aka="MPU_Control" description="MPU Control Register">
-      <BitField size="1" name="PRIVDEFENA" start="2" description="Enables privileged software access to the default memory map" />
-      <BitField size="1" name="HFNMIENA" start="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField size="1" name="ENABLE" start="0" description="Enable MPU" />
-    </Register>
-    <Register start="0xE000ED98" name="MPU_RNR" aka="MPU_Region_Number" description="MPU Region Number Register">
-      <BitField size="8" name="REGION" start="0" />
-    </Register>
-    <Register start="0xE000ED9C" name="MPU_RBAR" aka="MPU_Region_Base_Address" description="MPU Region Base Address Register">
-      <BitField size="27" name="ADDR" start="5" description="Region base address field" />
-      <BitField size="1" name="VALID" start="4" description="MPU Region Number valid bit" />
-      <BitField size="4" name="REGION" start="0" description="MPU region field" />
-    </Register>
-    <Register start="0xE000EDA0" name="MPU_RASR" aka="MPU_Attribute_and_Size" description="MPU Region Attribute and Size Register">
-      <BitField size="1" name="XN" start="28" description="Instruction access disable bit" />
-      <BitField size="3" name="AP" start="24" description="Access permission field" />
-      <BitField size="3" name="TEX" start="19" description="Memory access attribute" />
-      <BitField size="1" name="S" start="18" description="Shareable bit" />
-      <BitField size="1" name="C" start="17" description="Memory access attribute" />
-      <BitField size="1" name="B" start="16" description="Memory access attribute" />
-      <BitField size="8" name="SRD" start="8" description="Subregion disable bits" />
-      <BitField size="5" name="SIZE" start="1" description="MPU protection region size" />
-      <BitField size="1" name="ENABLE" start="0" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EDF0" name="CoreDebug">
-    <Register start="0xE000EDF0" name="DHCSR" />
-    <Register start="0xE000EDF4" name="DCRSR" />
-    <Register start="0xE000EDF8" name="DCRDR" />
-    <Register start="0xE000EDFC" name="DEMCR" />
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EF00" name="SCB">
-    <Register start="0xE000EF00" name="STIR" aka="SCB_SW_TRIG" access="WriteOnly" description="Software Trigger Interrupt Register">
-      <BitField size="10" name="INTID" start="0" description="ID of the interrupt to trigger" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EF34" name="SCB_FP">
-    <Register start="0xE000EF34" name="FPCCR" description="Floating-point Context Control Register">
-      <BitField size="1" name="ASPEN" start="31" description="Automatic State Preservation" />
-      <BitField size="1" name="LSPEN" start="30" description="Lazy State Preservation Enabled" />
-      <BitField size="1" name="MONRDY" start="8" description="Monitor Ready" />
-      <BitField size="1" name="BFRDY" start="6" description="BusFault Ready" />
-      <BitField size="1" name="MMRDY" start="5" description="MemManage Ready" />
-      <BitField size="1" name="HFRDY" start="4" description="HardFault Ready" />
-      <BitField size="1" name="THREAD" start="3" description="Thread Mode Allocated Stack Frame" />
-      <BitField size="1" name="USER" start="1" description="User Allocated Stack Frame" />
-      <BitField size="1" name="LSPACT" start="0" description="Lazy State Preservation Active" />
-    </Register>
-    <Register start="0xE000EF38" name="FPCAR" description="Floating-point Context Address Register" />
-    <Register start="0xE000EF3C" name="FPDSCR" description="Floating-point Default Status Control Register">
-      <BitField size="1" name="AHP" start="26" description="Default value for FPSCR.AHP" />
-      <BitField size="1" name="DN" start="25" description="Default value for FPSCR.DN" />
-      <BitField size="1" name="FZ" start="24" description="Default value for FPSCR.FZ" />
-      <BitField size="2" name="RMode" start="22" description="Default value for FPSCR.RMode" />
-    </Register>
-    <Register start="0xE000EF40" name="MVFR0" />
-    <Register start="0xE000EF44" name="MVFR1" />
-  </RegisterGroup>
-  <RegisterGroup start="0xE000EFD0" name="ID_space">
-    <Register start="0xE000EFD0" size="1" name="PID4" access="ReadOnly" />
-    <Register start="0xE000EFD4" size="1" name="PID5" access="ReadOnly" />
-    <Register start="0xE000EFD8" size="1" name="PID6" access="ReadOnly" />
-    <Register start="0xE000EFDC" size="1" name="PID7" access="ReadOnly" />
-    <Register start="0xE000EFE0" size="1" name="PID0" access="ReadOnly" />
-    <Register start="0xE000EFE4" size="1" name="PID1" access="ReadOnly" />
-    <Register start="0xE000EFE8" size="1" name="PID2" access="ReadOnly" />
-    <Register start="0xE000EFEC" size="1" name="PID3" access="ReadOnly" />
-    <Register start="0xE000EFF0" size="1" name="CID0" access="ReadOnly" />
-    <Register start="0xE000EFF4" size="1" name="CID1" access="ReadOnly" />
-    <Register start="0xE000EFF8" size="1" name="CID2" access="ReadOnly" />
-    <Register start="0xE000EFFC" size="1" name="CID3" access="ReadOnly" />
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_Vectors.s b/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_Vectors.s
deleted file mode 100644
index 6369de86..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/ATSAMD51J19A_Vectors.s
+++ /dev/null
@@ -1,1227 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * STARTUP_FROM_RESET                                                        *
- *                                                                           *
- *   If defined, the program will startup from power-on/reset. If not        *
- *   defined the program will just loop endlessly from power-on/reset.       *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-#ifndef STARTUP_FROM_RESET
-
-  .thumb_func
-  .weak Reset_Wait
-Reset_Wait:
-  b .
-
-#endif
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak PM_Handler
-  .thumb_set PM_Handler,Dummy_Handler
-
-  .weak MCLK_Handler
-  .thumb_set MCLK_Handler,Dummy_Handler
-
-  .weak OSCCTRL_0_Handler
-  .thumb_set OSCCTRL_0_Handler,Dummy_Handler
-
-  .weak OSCCTRL_1_Handler
-  .thumb_set OSCCTRL_1_Handler,Dummy_Handler
-
-  .weak OSCCTRL_2_Handler
-  .thumb_set OSCCTRL_2_Handler,Dummy_Handler
-
-  .weak OSCCTRL_3_Handler
-  .thumb_set OSCCTRL_3_Handler,Dummy_Handler
-
-  .weak OSCCTRL_4_Handler
-  .thumb_set OSCCTRL_4_Handler,Dummy_Handler
-
-  .weak OSC32KCTRL_Handler
-  .thumb_set OSC32KCTRL_Handler,Dummy_Handler
-
-  .weak SUPC_0_Handler
-  .thumb_set SUPC_0_Handler,Dummy_Handler
-
-  .weak SUPC_1_Handler
-  .thumb_set SUPC_1_Handler,Dummy_Handler
-
-  .weak WDT_Handler
-  .thumb_set WDT_Handler,Dummy_Handler
-
-  .weak RTC_Handler
-  .thumb_set RTC_Handler,Dummy_Handler
-
-  .weak EIC_0_Handler
-  .thumb_set EIC_0_Handler,Dummy_Handler
-
-  .weak EIC_1_Handler
-  .thumb_set EIC_1_Handler,Dummy_Handler
-
-  .weak EIC_2_Handler
-  .thumb_set EIC_2_Handler,Dummy_Handler
-
-  .weak EIC_3_Handler
-  .thumb_set EIC_3_Handler,Dummy_Handler
-
-  .weak EIC_4_Handler
-  .thumb_set EIC_4_Handler,Dummy_Handler
-
-  .weak EIC_5_Handler
-  .thumb_set EIC_5_Handler,Dummy_Handler
-
-  .weak EIC_6_Handler
-  .thumb_set EIC_6_Handler,Dummy_Handler
-
-  .weak EIC_7_Handler
-  .thumb_set EIC_7_Handler,Dummy_Handler
-
-  .weak EIC_8_Handler
-  .thumb_set EIC_8_Handler,Dummy_Handler
-
-  .weak EIC_9_Handler
-  .thumb_set EIC_9_Handler,Dummy_Handler
-
-  .weak EIC_10_Handler
-  .thumb_set EIC_10_Handler,Dummy_Handler
-
-  .weak EIC_11_Handler
-  .thumb_set EIC_11_Handler,Dummy_Handler
-
-  .weak EIC_12_Handler
-  .thumb_set EIC_12_Handler,Dummy_Handler
-
-  .weak EIC_13_Handler
-  .thumb_set EIC_13_Handler,Dummy_Handler
-
-  .weak EIC_14_Handler
-  .thumb_set EIC_14_Handler,Dummy_Handler
-
-  .weak EIC_15_Handler
-  .thumb_set EIC_15_Handler,Dummy_Handler
-
-  .weak FREQM_Handler
-  .thumb_set FREQM_Handler,Dummy_Handler
-
-  .weak NVMCTRL_0_Handler
-  .thumb_set NVMCTRL_0_Handler,Dummy_Handler
-
-  .weak NVMCTRL_1_Handler
-  .thumb_set NVMCTRL_1_Handler,Dummy_Handler
-
-  .weak DMAC_0_Handler
-  .thumb_set DMAC_0_Handler,Dummy_Handler
-
-  .weak DMAC_1_Handler
-  .thumb_set DMAC_1_Handler,Dummy_Handler
-
-  .weak DMAC_2_Handler
-  .thumb_set DMAC_2_Handler,Dummy_Handler
-
-  .weak DMAC_3_Handler
-  .thumb_set DMAC_3_Handler,Dummy_Handler
-
-  .weak DMAC_4_Handler
-  .thumb_set DMAC_4_Handler,Dummy_Handler
-
-  .weak EVSYS_0_Handler
-  .thumb_set EVSYS_0_Handler,Dummy_Handler
-
-  .weak EVSYS_1_Handler
-  .thumb_set EVSYS_1_Handler,Dummy_Handler
-
-  .weak EVSYS_2_Handler
-  .thumb_set EVSYS_2_Handler,Dummy_Handler
-
-  .weak EVSYS_3_Handler
-  .thumb_set EVSYS_3_Handler,Dummy_Handler
-
-  .weak EVSYS_4_Handler
-  .thumb_set EVSYS_4_Handler,Dummy_Handler
-
-  .weak PAC_Handler
-  .thumb_set PAC_Handler,Dummy_Handler
-
-  .weak TAL_0_Handler
-  .thumb_set TAL_0_Handler,Dummy_Handler
-
-  .weak TAL_1_Handler
-  .thumb_set TAL_1_Handler,Dummy_Handler
-
-  .weak RAMECC_Handler
-  .thumb_set RAMECC_Handler,Dummy_Handler
-
-  .weak SERCOM0_0_Handler
-  .thumb_set SERCOM0_0_Handler,Dummy_Handler
-
-  .weak SERCOM0_1_Handler
-  .thumb_set SERCOM0_1_Handler,Dummy_Handler
-
-  .weak SERCOM0_2_Handler
-  .thumb_set SERCOM0_2_Handler,Dummy_Handler
-
-  .weak SERCOM0_3_Handler
-  .thumb_set SERCOM0_3_Handler,Dummy_Handler
-
-  .weak SERCOM1_0_Handler
-  .thumb_set SERCOM1_0_Handler,Dummy_Handler
-
-  .weak SERCOM1_1_Handler
-  .thumb_set SERCOM1_1_Handler,Dummy_Handler
-
-  .weak SERCOM1_2_Handler
-  .thumb_set SERCOM1_2_Handler,Dummy_Handler
-
-  .weak SERCOM1_3_Handler
-  .thumb_set SERCOM1_3_Handler,Dummy_Handler
-
-  .weak SERCOM2_0_Handler
-  .thumb_set SERCOM2_0_Handler,Dummy_Handler
-
-  .weak SERCOM2_1_Handler
-  .thumb_set SERCOM2_1_Handler,Dummy_Handler
-
-  .weak SERCOM2_2_Handler
-  .thumb_set SERCOM2_2_Handler,Dummy_Handler
-
-  .weak SERCOM2_3_Handler
-  .thumb_set SERCOM2_3_Handler,Dummy_Handler
-
-  .weak SERCOM3_0_Handler
-  .thumb_set SERCOM3_0_Handler,Dummy_Handler
-
-  .weak SERCOM3_1_Handler
-  .thumb_set SERCOM3_1_Handler,Dummy_Handler
-
-  .weak SERCOM3_2_Handler
-  .thumb_set SERCOM3_2_Handler,Dummy_Handler
-
-  .weak SERCOM3_3_Handler
-  .thumb_set SERCOM3_3_Handler,Dummy_Handler
-
-  .weak SERCOM4_0_Handler
-  .thumb_set SERCOM4_0_Handler,Dummy_Handler
-
-  .weak SERCOM4_1_Handler
-  .thumb_set SERCOM4_1_Handler,Dummy_Handler
-
-  .weak SERCOM4_2_Handler
-  .thumb_set SERCOM4_2_Handler,Dummy_Handler
-
-  .weak SERCOM4_3_Handler
-  .thumb_set SERCOM4_3_Handler,Dummy_Handler
-
-  .weak SERCOM5_0_Handler
-  .thumb_set SERCOM5_0_Handler,Dummy_Handler
-
-  .weak SERCOM5_1_Handler
-  .thumb_set SERCOM5_1_Handler,Dummy_Handler
-
-  .weak SERCOM5_2_Handler
-  .thumb_set SERCOM5_2_Handler,Dummy_Handler
-
-  .weak SERCOM5_3_Handler
-  .thumb_set SERCOM5_3_Handler,Dummy_Handler
-
-  .weak USB_0_Handler
-  .thumb_set USB_0_Handler,Dummy_Handler
-
-  .weak USB_1_Handler
-  .thumb_set USB_1_Handler,Dummy_Handler
-
-  .weak USB_2_Handler
-  .thumb_set USB_2_Handler,Dummy_Handler
-
-  .weak USB_3_Handler
-  .thumb_set USB_3_Handler,Dummy_Handler
-
-  .weak TCC0_0_Handler
-  .thumb_set TCC0_0_Handler,Dummy_Handler
-
-  .weak TCC0_1_Handler
-  .thumb_set TCC0_1_Handler,Dummy_Handler
-
-  .weak TCC0_2_Handler
-  .thumb_set TCC0_2_Handler,Dummy_Handler
-
-  .weak TCC0_3_Handler
-  .thumb_set TCC0_3_Handler,Dummy_Handler
-
-  .weak TCC0_4_Handler
-  .thumb_set TCC0_4_Handler,Dummy_Handler
-
-  .weak TCC0_5_Handler
-  .thumb_set TCC0_5_Handler,Dummy_Handler
-
-  .weak TCC0_6_Handler
-  .thumb_set TCC0_6_Handler,Dummy_Handler
-
-  .weak TCC1_0_Handler
-  .thumb_set TCC1_0_Handler,Dummy_Handler
-
-  .weak TCC1_1_Handler
-  .thumb_set TCC1_1_Handler,Dummy_Handler
-
-  .weak TCC1_2_Handler
-  .thumb_set TCC1_2_Handler,Dummy_Handler
-
-  .weak TCC1_3_Handler
-  .thumb_set TCC1_3_Handler,Dummy_Handler
-
-  .weak TCC1_4_Handler
-  .thumb_set TCC1_4_Handler,Dummy_Handler
-
-  .weak TCC2_0_Handler
-  .thumb_set TCC2_0_Handler,Dummy_Handler
-
-  .weak TCC2_1_Handler
-  .thumb_set TCC2_1_Handler,Dummy_Handler
-
-  .weak TCC2_2_Handler
-  .thumb_set TCC2_2_Handler,Dummy_Handler
-
-  .weak TCC2_3_Handler
-  .thumb_set TCC2_3_Handler,Dummy_Handler
-
-  .weak TCC3_0_Handler
-  .thumb_set TCC3_0_Handler,Dummy_Handler
-
-  .weak TCC3_1_Handler
-  .thumb_set TCC3_1_Handler,Dummy_Handler
-
-  .weak TCC3_2_Handler
-  .thumb_set TCC3_2_Handler,Dummy_Handler
-
-  .weak TCC4_0_Handler
-  .thumb_set TCC4_0_Handler,Dummy_Handler
-
-  .weak TCC4_1_Handler
-  .thumb_set TCC4_1_Handler,Dummy_Handler
-
-  .weak TCC4_2_Handler
-  .thumb_set TCC4_2_Handler,Dummy_Handler
-
-  .weak TC0_Handler
-  .thumb_set TC0_Handler,Dummy_Handler
-
-  .weak TC1_Handler
-  .thumb_set TC1_Handler,Dummy_Handler
-
-  .weak TC2_Handler
-  .thumb_set TC2_Handler,Dummy_Handler
-
-  .weak TC3_Handler
-  .thumb_set TC3_Handler,Dummy_Handler
-
-  .weak TC4_Handler
-  .thumb_set TC4_Handler,Dummy_Handler
-
-  .weak TC5_Handler
-  .thumb_set TC5_Handler,Dummy_Handler
-
-  .weak PDEC_0_Handler
-  .thumb_set PDEC_0_Handler,Dummy_Handler
-
-  .weak PDEC_1_Handler
-  .thumb_set PDEC_1_Handler,Dummy_Handler
-
-  .weak PDEC_2_Handler
-  .thumb_set PDEC_2_Handler,Dummy_Handler
-
-  .weak ADC0_0_Handler
-  .thumb_set ADC0_0_Handler,Dummy_Handler
-
-  .weak ADC0_1_Handler
-  .thumb_set ADC0_1_Handler,Dummy_Handler
-
-  .weak ADC1_0_Handler
-  .thumb_set ADC1_0_Handler,Dummy_Handler
-
-  .weak ADC1_1_Handler
-  .thumb_set ADC1_1_Handler,Dummy_Handler
-
-  .weak AC_Handler
-  .thumb_set AC_Handler,Dummy_Handler
-
-  .weak DAC_0_Handler
-  .thumb_set DAC_0_Handler,Dummy_Handler
-
-  .weak DAC_1_Handler
-  .thumb_set DAC_1_Handler,Dummy_Handler
-
-  .weak DAC_2_Handler
-  .thumb_set DAC_2_Handler,Dummy_Handler
-
-  .weak DAC_3_Handler
-  .thumb_set DAC_3_Handler,Dummy_Handler
-
-  .weak DAC_4_Handler
-  .thumb_set DAC_4_Handler,Dummy_Handler
-
-  .weak I2S_Handler
-  .thumb_set I2S_Handler,Dummy_Handler
-
-  .weak PCC_Handler
-  .thumb_set PCC_Handler,Dummy_Handler
-
-  .weak AES_Handler
-  .thumb_set AES_Handler,Dummy_Handler
-
-  .weak TRNG_Handler
-  .thumb_set TRNG_Handler,Dummy_Handler
-
-  .weak ICM_Handler
-  .thumb_set ICM_Handler,Dummy_Handler
-
-  .weak QSPI_Handler
-  .thumb_set QSPI_Handler,Dummy_Handler
-
-  .weak SDHC0_Handler
-  .thumb_set SDHC0_Handler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak PM_Handler
-PM_Handler:
-  b .
-
-  .thumb_func
-  .weak MCLK_Handler
-MCLK_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_0_Handler
-OSCCTRL_0_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_1_Handler
-OSCCTRL_1_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_2_Handler
-OSCCTRL_2_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_3_Handler
-OSCCTRL_3_Handler:
-  b .
-
-  .thumb_func
-  .weak OSCCTRL_4_Handler
-OSCCTRL_4_Handler:
-  b .
-
-  .thumb_func
-  .weak OSC32KCTRL_Handler
-OSC32KCTRL_Handler:
-  b .
-
-  .thumb_func
-  .weak SUPC_0_Handler
-SUPC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SUPC_1_Handler
-SUPC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak WDT_Handler
-WDT_Handler:
-  b .
-
-  .thumb_func
-  .weak RTC_Handler
-RTC_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_0_Handler
-EIC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_1_Handler
-EIC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_2_Handler
-EIC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_3_Handler
-EIC_3_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_4_Handler
-EIC_4_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_5_Handler
-EIC_5_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_6_Handler
-EIC_6_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_7_Handler
-EIC_7_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_8_Handler
-EIC_8_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_9_Handler
-EIC_9_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_10_Handler
-EIC_10_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_11_Handler
-EIC_11_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_12_Handler
-EIC_12_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_13_Handler
-EIC_13_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_14_Handler
-EIC_14_Handler:
-  b .
-
-  .thumb_func
-  .weak EIC_15_Handler
-EIC_15_Handler:
-  b .
-
-  .thumb_func
-  .weak FREQM_Handler
-FREQM_Handler:
-  b .
-
-  .thumb_func
-  .weak NVMCTRL_0_Handler
-NVMCTRL_0_Handler:
-  b .
-
-  .thumb_func
-  .weak NVMCTRL_1_Handler
-NVMCTRL_1_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_0_Handler
-DMAC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_1_Handler
-DMAC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_2_Handler
-DMAC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_3_Handler
-DMAC_3_Handler:
-  b .
-
-  .thumb_func
-  .weak DMAC_4_Handler
-DMAC_4_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_0_Handler
-EVSYS_0_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_1_Handler
-EVSYS_1_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_2_Handler
-EVSYS_2_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_3_Handler
-EVSYS_3_Handler:
-  b .
-
-  .thumb_func
-  .weak EVSYS_4_Handler
-EVSYS_4_Handler:
-  b .
-
-  .thumb_func
-  .weak PAC_Handler
-PAC_Handler:
-  b .
-
-  .thumb_func
-  .weak TAL_0_Handler
-TAL_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TAL_1_Handler
-TAL_1_Handler:
-  b .
-
-  .thumb_func
-  .weak RAMECC_Handler
-RAMECC_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_0_Handler
-SERCOM0_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_1_Handler
-SERCOM0_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_2_Handler
-SERCOM0_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM0_3_Handler
-SERCOM0_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_0_Handler
-SERCOM1_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_1_Handler
-SERCOM1_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_2_Handler
-SERCOM1_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM1_3_Handler
-SERCOM1_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_0_Handler
-SERCOM2_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_1_Handler
-SERCOM2_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_2_Handler
-SERCOM2_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM2_3_Handler
-SERCOM2_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_0_Handler
-SERCOM3_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_1_Handler
-SERCOM3_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_2_Handler
-SERCOM3_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM3_3_Handler
-SERCOM3_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_0_Handler
-SERCOM4_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_1_Handler
-SERCOM4_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_2_Handler
-SERCOM4_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM4_3_Handler
-SERCOM4_3_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_0_Handler
-SERCOM5_0_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_1_Handler
-SERCOM5_1_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_2_Handler
-SERCOM5_2_Handler:
-  b .
-
-  .thumb_func
-  .weak SERCOM5_3_Handler
-SERCOM5_3_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_0_Handler
-USB_0_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_1_Handler
-USB_1_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_2_Handler
-USB_2_Handler:
-  b .
-
-  .thumb_func
-  .weak USB_3_Handler
-USB_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_0_Handler
-TCC0_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_1_Handler
-TCC0_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_2_Handler
-TCC0_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_3_Handler
-TCC0_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_4_Handler
-TCC0_4_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_5_Handler
-TCC0_5_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC0_6_Handler
-TCC0_6_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_0_Handler
-TCC1_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_1_Handler
-TCC1_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_2_Handler
-TCC1_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_3_Handler
-TCC1_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC1_4_Handler
-TCC1_4_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_0_Handler
-TCC2_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_1_Handler
-TCC2_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_2_Handler
-TCC2_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC2_3_Handler
-TCC2_3_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC3_0_Handler
-TCC3_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC3_1_Handler
-TCC3_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC3_2_Handler
-TCC3_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC4_0_Handler
-TCC4_0_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC4_1_Handler
-TCC4_1_Handler:
-  b .
-
-  .thumb_func
-  .weak TCC4_2_Handler
-TCC4_2_Handler:
-  b .
-
-  .thumb_func
-  .weak TC0_Handler
-TC0_Handler:
-  b .
-
-  .thumb_func
-  .weak TC1_Handler
-TC1_Handler:
-  b .
-
-  .thumb_func
-  .weak TC2_Handler
-TC2_Handler:
-  b .
-
-  .thumb_func
-  .weak TC3_Handler
-TC3_Handler:
-  b .
-
-  .thumb_func
-  .weak TC4_Handler
-TC4_Handler:
-  b .
-
-  .thumb_func
-  .weak TC5_Handler
-TC5_Handler:
-  b .
-
-  .thumb_func
-  .weak PDEC_0_Handler
-PDEC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak PDEC_1_Handler
-PDEC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak PDEC_2_Handler
-PDEC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC0_0_Handler
-ADC0_0_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC0_1_Handler
-ADC0_1_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC1_0_Handler
-ADC1_0_Handler:
-  b .
-
-  .thumb_func
-  .weak ADC1_1_Handler
-ADC1_1_Handler:
-  b .
-
-  .thumb_func
-  .weak AC_Handler
-AC_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_0_Handler
-DAC_0_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_1_Handler
-DAC_1_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_2_Handler
-DAC_2_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_3_Handler
-DAC_3_Handler:
-  b .
-
-  .thumb_func
-  .weak DAC_4_Handler
-DAC_4_Handler:
-  b .
-
-  .thumb_func
-  .weak I2S_Handler
-I2S_Handler:
-  b .
-
-  .thumb_func
-  .weak PCC_Handler
-PCC_Handler:
-  b .
-
-  .thumb_func
-  .weak AES_Handler
-AES_Handler:
-  b .
-
-  .thumb_func
-  .weak TRNG_Handler
-TRNG_Handler:
-  b .
-
-  .thumb_func
-  .weak ICM_Handler
-ICM_Handler:
-  b .
-
-  .thumb_func
-  .weak QSPI_Handler
-QSPI_Handler:
-  b .
-
-  .thumb_func
-  .weak SDHC0_Handler
-SDHC0_Handler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-#ifdef STARTUP_FROM_RESET
-  .extern Reset_Handler
-#endif
-
-_vectors:
-  .word __stack_end__
-#ifdef STARTUP_FROM_RESET
-  .word Reset_Handler
-#else
-  .word Reset_Wait
-#endif
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word PM_Handler
-  .word MCLK_Handler
-  .word OSCCTRL_0_Handler
-  .word OSCCTRL_1_Handler
-  .word OSCCTRL_2_Handler
-  .word OSCCTRL_3_Handler
-  .word OSCCTRL_4_Handler
-  .word OSC32KCTRL_Handler
-  .word SUPC_0_Handler
-  .word SUPC_1_Handler
-  .word WDT_Handler
-  .word RTC_Handler
-  .word EIC_0_Handler
-  .word EIC_1_Handler
-  .word EIC_2_Handler
-  .word EIC_3_Handler
-  .word EIC_4_Handler
-  .word EIC_5_Handler
-  .word EIC_6_Handler
-  .word EIC_7_Handler
-  .word EIC_8_Handler
-  .word EIC_9_Handler
-  .word EIC_10_Handler
-  .word EIC_11_Handler
-  .word EIC_12_Handler
-  .word EIC_13_Handler
-  .word EIC_14_Handler
-  .word EIC_15_Handler
-  .word FREQM_Handler
-  .word NVMCTRL_0_Handler
-  .word NVMCTRL_1_Handler
-  .word DMAC_0_Handler
-  .word DMAC_1_Handler
-  .word DMAC_2_Handler
-  .word DMAC_3_Handler
-  .word DMAC_4_Handler
-  .word EVSYS_0_Handler
-  .word EVSYS_1_Handler
-  .word EVSYS_2_Handler
-  .word EVSYS_3_Handler
-  .word EVSYS_4_Handler
-  .word PAC_Handler
-  .word TAL_0_Handler
-  .word TAL_1_Handler
-  .word Dummy_Handler /* Reserved */
-  .word RAMECC_Handler
-  .word SERCOM0_0_Handler
-  .word SERCOM0_1_Handler
-  .word SERCOM0_2_Handler
-  .word SERCOM0_3_Handler
-  .word SERCOM1_0_Handler
-  .word SERCOM1_1_Handler
-  .word SERCOM1_2_Handler
-  .word SERCOM1_3_Handler
-  .word SERCOM2_0_Handler
-  .word SERCOM2_1_Handler
-  .word SERCOM2_2_Handler
-  .word SERCOM2_3_Handler
-  .word SERCOM3_0_Handler
-  .word SERCOM3_1_Handler
-  .word SERCOM3_2_Handler
-  .word SERCOM3_3_Handler
-  .word SERCOM4_0_Handler
-  .word SERCOM4_1_Handler
-  .word SERCOM4_2_Handler
-  .word SERCOM4_3_Handler
-  .word SERCOM5_0_Handler
-  .word SERCOM5_1_Handler
-  .word SERCOM5_2_Handler
-  .word SERCOM5_3_Handler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word USB_0_Handler
-  .word USB_1_Handler
-  .word USB_2_Handler
-  .word USB_3_Handler
-  .word Dummy_Handler /* Reserved */
-  .word TCC0_0_Handler
-  .word TCC0_1_Handler
-  .word TCC0_2_Handler
-  .word TCC0_3_Handler
-  .word TCC0_4_Handler
-  .word TCC0_5_Handler
-  .word TCC0_6_Handler
-  .word TCC1_0_Handler
-  .word TCC1_1_Handler
-  .word TCC1_2_Handler
-  .word TCC1_3_Handler
-  .word TCC1_4_Handler
-  .word TCC2_0_Handler
-  .word TCC2_1_Handler
-  .word TCC2_2_Handler
-  .word TCC2_3_Handler
-  .word TCC3_0_Handler
-  .word TCC3_1_Handler
-  .word TCC3_2_Handler
-  .word TCC4_0_Handler
-  .word TCC4_1_Handler
-  .word TCC4_2_Handler
-  .word TC0_Handler
-  .word TC1_Handler
-  .word TC2_Handler
-  .word TC3_Handler
-  .word TC4_Handler
-  .word TC5_Handler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word PDEC_0_Handler
-  .word PDEC_1_Handler
-  .word PDEC_2_Handler
-  .word ADC0_0_Handler
-  .word ADC0_1_Handler
-  .word ADC1_0_Handler
-  .word ADC1_1_Handler
-  .word AC_Handler
-  .word DAC_0_Handler
-  .word DAC_1_Handler
-  .word DAC_2_Handler
-  .word DAC_3_Handler
-  .word DAC_4_Handler
-  .word I2S_Handler
-  .word PCC_Handler
-  .word AES_Handler
-  .word TRNG_Handler
-  .word ICM_Handler
-  .word Dummy_Handler /* Reserved */
-  .word QSPI_Handler
-  .word SDHC0_Handler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/SAMD51_Startup.s b/examples/device/cdc_msc_freertos/ses/samd51/SAMD51_Startup.s
deleted file mode 100644
index 03bf54de..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/SAMD51_Startup.s
+++ /dev/null
@@ -1,128 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/SAMD51_Target.js b/examples/device/cdc_msc_freertos/ses/samd51/SAMD51_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/SAMD51_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/flash_placement.xml b/examples/device/cdc_msc_freertos/ses/samd51/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/samd51.emProject b/examples/device/cdc_msc_freertos/ses/samd51/samd51.emProject
deleted file mode 100644
index 77ff38b6..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/samd51.emProject
+++ /dev/null
@@ -1,146 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="samd51" target="8" version="2">
-  <project Name="samd51">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="nRF52840_xxAA"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 20000000,00030000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="ATSAMD51J19"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="__SAMD51_FAMILY;__SAMD51J19A__;ARM_MATH_CM4;FLASH_PLACEMENT=1;USE_SIMPLE_ASSERT;BOARD_METRO_M4_EXPRESS;CFG_TUSB_MCU=OPT_MCU_SAMD51"
-      c_user_include_directories="./;../../src;$(rootDir)/hw;$(rootDir)/src;$(asf4Dir);$(asf4Dir)/CMSIS/Include;$(asf4Dir)/include;$(asf4Dir)/config;$(asf4Dir)/hri;$(asf4Dir)/hal/include;$(asf4Dir)/hal/utils/include;$(asf4Dir)/hpl/port;$(asf4Dir)/hpl/gclk;$(freertosDir)/Source/include;$(freertosDir)/Source/portable/GCC/ARM_CM4F"
-      debug_register_definition_file="ATSAMD51J19A_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="ATSAMD51J19A_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x20000000 0x00030000"
-      macros="DeviceFamily=SAMD51;Target=ATSAMD51J19A;Placement=Flash;rootDir=../../../../..;asf4Dir=../../../../../hw/mcu/microchip/asf4/samd51;freertosDir=../../../../../lib/FreeRTOS"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/SAMD51_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="metro_m4_express">
-          <file file_name="../../../../../hw/bsp/metro_m4_express/board_metro_m4_express.c" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="microchip">
-          <folder Name="samd">
-            <folder Name="asf4">
-              <folder Name="samd51">
-                <folder Name="gcc">
-                  <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/gcc/system_samd51.c" />
-                </folder>
-                <folder Name="hpl">
-                  <folder Name="core">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/core/hpl_init.c" />
-                  </folder>
-                  <folder Name="osc32kctrl">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c" />
-                  </folder>
-                  <folder Name="oscctrl">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c" />
-                  </folder>
-                  <folder Name="mclk">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/mclk/hpl_mclk.c" />
-                  </folder>
-                  <folder Name="gclk">
-                    <file file_name="../../../../../hw/mcu/microchip/asf4/samd51/hpl/gclk/hpl_gclk.c" />
-                  </folder>
-                </folder>
-              </folder>
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="ATSAMD51J19A_MemoryMap.xml" />
-      <file file_name="ATSAMD51J19A_Registers.xml" />
-      <file file_name="ATSAMD51J19A_Vectors.s" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="SAMD51_Startup.s" />
-      <file file_name="SAMD51_Target.js" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder
-      Name="segger_rtt"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../lib/segger_rtt"
-      recurse="No" />
-    <folder Name="lib">
-      <folder Name="FreeRTOS">
-        <folder Name="Source">
-          <folder Name="include">
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/croutine.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/deprecated_definitions.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/event_groups.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/FreeRTOS.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/list.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/message_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_prototypes.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/mpu_wrappers.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/portable.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/projdefs.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/queue.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/semphr.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stack_macros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/StackMacros.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/stream_buffer.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/task.h" />
-            <file file_name="../../../../../lib/FreeRTOS-Kernel/include/timers.h" />
-          </folder>
-          <folder Name="portable">
-            <folder Name="GCC">
-              <folder Name="ARM_CM4F">
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c" />
-                <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/GCC/ARM_CM4F/portmacro.h" />
-              </folder>
-            </folder>
-            <folder Name="MemMang">
-              <file file_name="../../../../../lib/FreeRTOS-Kernel/portable/MemMang/heap_4.c" />
-            </folder>
-          </folder>
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/list.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/queue.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/tasks.c" />
-          <file file_name="../../../../../lib/FreeRTOS-Kernel/timers.c" />
-        </folder>
-        <file file_name="../../../../../lib/FreeRTOS/freertos_hook.c" />
-      </folder>
-    </folder>
-  </project>
-  <configuration Name="Metro M4 Express" />
-</solution>
diff --git a/examples/device/cdc_msc_freertos/ses/samd51/thumb_crt0.s b/examples/device/cdc_msc_freertos/ses/samd51/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/device/cdc_msc_freertos/ses/samd51/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/host/cdc_msc_hid/ses/cdc_msc_hid.emProject b/examples/host/cdc_msc_hid/ses/cdc_msc_hid.emProject
deleted file mode 100644
index 208ea66e..00000000
--- a/examples/host/cdc_msc_hid/ses/cdc_msc_hid.emProject
+++ /dev/null
@@ -1,9 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="cdc_msc_hid" target="8" version="2">
-  <import file_name="samd21/samd21.emProject" />
-  <import file_name="samd51/samd51.emProject" />
-  <import file_name="lpc175x_6x/lpc175x_6x.emProject" />
-  <import file_name="lpc18xx/lpc18xx.emProject" />
-  <import file_name="lpc40xx/lpc40xx.emProject" />
-  <import file_name="lpc43xx/lpc43xx.emProject" />  
-</solution>
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Startup.s b/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Startup.s
deleted file mode 100644
index f039ad93..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Startup.s
+++ /dev/null
@@ -1,109 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Target.js b/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Target.js
deleted file mode 100644
index 7f945a3d..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1700_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml b/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml
deleted file mode 100644
index d9c07aea..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC1769_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC1769">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x2007C000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Registers.xml b/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Registers.xml
deleted file mode 100644
index fd38966b..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Registers.xml
+++ /dev/null
@@ -1,11058 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC176x5x" description="LPC176x/LPC175x M3">
-  <RegisterGroup name="WDT" start="0x40000000" description="Watchdog Timer (WDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="STOP" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
-        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, cleared by software." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag.  Cleared by software." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="Count" description="Watchdog time-out interval." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="Count" description="Counter timer value." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLKSEL" description="Selects source of WDT clock">
-        <Enum name="IRC" start="0x0" description="IRC" />
-        <Enum name="PCLK" start="0x1" description="Peripheral clock" />
-        <Enum name="RTCOSC" start="0x2" description="RTC oscillator" />
-      </BitField>
-      <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.">
-        <Enum name="UNLOCKED" start="0" description="This bit is set to 0 on any reset. It cannot be cleared by software." />
-        <Enum name="LOCKED" start="1" description="Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;cannot be modified." />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40004000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40008000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40010000" description="UART1  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
-        <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
-        <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="MODEM" start="0x0" description="4   - Modem Interrupt." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="VALID" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM1) ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI" start="0x40020000" description="SPI ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
-        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
-      </BitField>
-      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
-        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
-        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
-      </BitField>
-      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
-        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
-        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
-      </BitField>
-      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
-        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
-        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
-      </BitField>
-      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
-        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
-        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
-      </BitField>
-      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
-        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
-        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
-      </BitField>
-      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
-        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
-        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
-        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
-        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
-        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
-        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
-        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
-        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
-        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
-      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC)  ">
-    <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
-        <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-        <Enum name="NO_EFFECT_" start="0" description="No effect." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
-        <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-      </BitField>
-    </Register>
-    <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
-    <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0INT" description="Port 0 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="P2INT" description="Port 2 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PINCONNECT" start="0x4002C000" description="Pin connect block">
-    <Register start="+0x000" size="4" name="PINSEL0" access="Read/Write" description="Pin function select register 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_0" description="Pin function select P0.0.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.0" />
-        <Enum name="RD1" start="0x1" description="RD1" />
-        <Enum name="TXD3" start="0x2" description="TXD3" />
-        <Enum name="SDA1" start="0x3" description="SDA1" />
-      </BitField>
-      <BitField start="2" size="2" name="P0_1" description="Pin function select P0.1.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.1" />
-        <Enum name="TD1" start="0x1" description="TD1" />
-        <Enum name="RXD3" start="0x2" description="RXD3" />
-        <Enum name="SCL1" start="0x3" description="SCL1" />
-      </BitField>
-      <BitField start="4" size="2" name="P0_2" description="Pin function select P0.2.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.2" />
-        <Enum name="TXD0" start="0x1" description="TXD0" />
-        <Enum name="AD0" start="0x2" description="AD0.7" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="P0_3" description="Pin function select P0.3.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.3." />
-        <Enum name="RXD0" start="0x1" description="RXD0" />
-        <Enum name="AD0" start="0x2" description="AD0.6" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_4" description="Pin function select P0.4.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.4." />
-        <Enum name="I2SRX_CLK" start="0x1" description="I2SRX_CLK" />
-        <Enum name="RD2" start="0x2" description="RD2" />
-        <Enum name="CAP2" start="0x3" description="CAP2.0" />
-      </BitField>
-      <BitField start="10" size="2" name="P0_5" description="Pin function select P0.5.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.5." />
-        <Enum name="I2SRX_WS" start="0x1" description="I2SRX_WS" />
-        <Enum name="TD2" start="0x2" description="TD2" />
-        <Enum name="CAP2" start="0x3" description="CAP2.1" />
-      </BitField>
-      <BitField start="12" size="2" name="P0_6" description="Pin function select P0.6.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.6." />
-        <Enum name="I2SRX_SDA" start="0x1" description="I2SRX_SDA" />
-        <Enum name="SSEL1" start="0x2" description="SSEL1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.0" />
-      </BitField>
-      <BitField start="14" size="2" name="P0_7" description="Pin function select P0.7.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.7." />
-        <Enum name="I2STX_CLK" start="0x1" description="I2STX_CLK" />
-        <Enum name="SCK1" start="0x2" description="SCK1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.1" />
-      </BitField>
-      <BitField start="16" size="2" name="P0_8" description="Pin function select P0.8.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.8." />
-        <Enum name="I2STX_WS" start="0x1" description="I2STX_WS" />
-        <Enum name="MISO1" start="0x2" description="MISO1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.2" />
-      </BitField>
-      <BitField start="18" size="2" name="P0_9" description="Pin function select P0.9.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.9" />
-        <Enum name="I2STX_SDA" start="0x1" description="I2STX_SDA" />
-        <Enum name="MOSI1" start="0x2" description="MOSI1" />
-        <Enum name="MAT2" start="0x3" description="MAT2.3" />
-      </BitField>
-      <BitField start="20" size="2" name="P0_10" description="Pin function select P0.10.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.10" />
-        <Enum name="TXD2" start="0x1" description="TXD2" />
-        <Enum name="SDA2" start="0x2" description="SDA2" />
-        <Enum name="MAT3" start="0x3" description="MAT3.0" />
-      </BitField>
-      <BitField start="22" size="2" name="P0_11" description="Pin function select P0.11.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.11" />
-        <Enum name="RXD2" start="0x1" description="RXD2" />
-        <Enum name="SCL2" start="0x2" description="SCL2" />
-        <Enum name="MAT3" start="0x3" description="MAT3.1" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P0_15" description="Pin function select P0.15.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.15" />
-        <Enum name="TXD1" start="0x1" description="TXD1" />
-        <Enum name="SCK0" start="0x2" description="SCK0" />
-        <Enum name="SCK" start="0x3" description="SCK" />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="PINSEL1" access="Read/Write" description="Pin function select register 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_16" description="Pin function select P0.16.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.16" />
-        <Enum name="RXD1" start="0x1" description="RXD1" />
-        <Enum name="SSEL0" start="0x2" description="SSEL0" />
-        <Enum name="SSEL" start="0x3" description="SSEL" />
-      </BitField>
-      <BitField start="2" size="2" name="P0_17" description="Pin function select P0.17.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.17" />
-        <Enum name="CTS1" start="0x1" description="CTS1" />
-        <Enum name="MISO0" start="0x2" description="MISO0" />
-        <Enum name="MISO" start="0x3" description="MISO" />
-      </BitField>
-      <BitField start="4" size="2" name="P0_18" description="Pin function select P0.18.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.18" />
-        <Enum name="DCD1" start="0x1" description="DCD1" />
-        <Enum name="MOSI0" start="0x2" description="MOSI0" />
-        <Enum name="MOSI" start="0x3" description="MOSI" />
-      </BitField>
-      <BitField start="6" size="2" name="P0_19" description="Pin function select P019.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.19." />
-        <Enum name="DSR1" start="0x1" description="DSR1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="SDA1" start="0x3" description="SDA1" />
-      </BitField>
-      <BitField start="8" size="2" name="P0_20" description="Pin function select P0.20.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.20." />
-        <Enum name="DTR1" start="0x1" description="DTR1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="SCL1" start="0x3" description="SCL1" />
-      </BitField>
-      <BitField start="10" size="2" name="P0_21" description="Pin function select P0.21.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0.21." />
-        <Enum name="RI1" start="0x1" description="RI1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RD1" start="0x3" description="RD1" />
-      </BitField>
-      <BitField start="12" size="2" name="P0_22" description="Pin function select P022">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.22." />
-        <Enum name="RTS1" start="0x1" description="RTS1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="TD1" start="0x3" description="TD1" />
-      </BitField>
-      <BitField start="14" size="2" name="P0_23" description="Pin function select P023.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.23." />
-        <Enum name="AD0" start="0x1" description="AD0.0" />
-        <Enum name="I2SRX_CLK" start="0x2" description="I2SRX_CLK" />
-        <Enum name="CAP3" start="0x3" description="CAP3.0" />
-      </BitField>
-      <BitField start="16" size="2" name="P0_24" description="Pin function select P0.24.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.24." />
-        <Enum name="AD0" start="0x1" description="AD0.1" />
-        <Enum name="I2SRX_WS" start="0x2" description="I2SRX_WS" />
-        <Enum name="CAP3" start="0x3" description="CAP3.1" />
-      </BitField>
-      <BitField start="18" size="2" name="P0_25" description="Pin function select P0.25.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.25" />
-        <Enum name="AD0" start="0x1" description="AD0.2" />
-        <Enum name="I2SRX_SDA" start="0x2" description="I2SRX_SDA" />
-        <Enum name="TXD3" start="0x3" description="TXD3" />
-      </BitField>
-      <BitField start="20" size="2" name="P0_26" description="Pin function select P0.26.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.26" />
-        <Enum name="AD0" start="0x1" description="AD0.3" />
-        <Enum name="AOUT" start="0x2" description="AOUT" />
-        <Enum name="RXD3" start="0x3" description="RXD3" />
-      </BitField>
-      <BitField start="22" size="2" name="P0_27" description="Pin function select P0.27.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.27" />
-        <Enum name="SDA0" start="0x1" description="SDA0" />
-        <Enum name="USB_SDA" start="0x2" description="USB_SDA" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="2" name="P0_28" description="Pin function select P0.28.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.28" />
-        <Enum name="SCL0" start="0x1" description="SCL0" />
-        <Enum name="USB_SCL" start="0x2" description="USB_SCL" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="26" size="2" name="P0_29" description="Pin function select P0.29">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.29" />
-        <Enum name="USB_DP" start="0x1" description="USB_D+" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="28" size="2" name="P0_30" description="Pin function select P0.30.">
-        <Enum name="GPIO_P0" start="0x0" description="GPIO P0.30" />
-        <Enum name="USB_DM" start="0x1" description="USB_D-" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="PINSEL2" access="Read/Write" description="Pin function select register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_0" description="Pin function select P1.0.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.0" />
-        <Enum name="ENET_TXD0" start="0x1" description="ENET_TXD0" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P1_1" description="Pin function select P1.1.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.1" />
-        <Enum name="ENET_TXD1" start="0x1" description="ENET_TXD1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="P1_4" description="Pin function select P1.4.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.4." />
-        <Enum name="ENET_TX_EN" start="0x1" description="ENET_TX_EN" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="2" name="P1_8" description="Pin function select P1.8.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.8." />
-        <Enum name="ENET_CRS" start="0x1" description="ENET_CRS" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="18" size="2" name="P1_9" description="Pin function select P1.9.">
-        <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.9" />
-        <Enum name="ENET_RXD0" start="0x1" description="ENET_RXD0" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="20" size="2" name="P1_10" description="Pin function select P1.10.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.10" />
-        <Enum name="ENET_RXD1" start="0x1" description="ENET_RXD1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="2" name="P1_14" description="Pin function select P1.14.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.14" />
-        <Enum name="ENET_RX_ER" start="0x1" description="ENET_RX_ER" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P1_15" description="Pin function select P1.15.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.15" />
-        <Enum name="ENET_REF_CLK" start="0x1" description="ENET_REF_CLK" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-    </Register>
-    <Register start="+0x00C" size="4" name="PINSEL3" access="Read/Write" description="Pin function select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_16" description="Pin function select P1.16.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.16" />
-        <Enum name="ENET_MDC" start="0x1" description="ENET_MDC" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P1_17" description="Pin function select P1.17.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.17" />
-        <Enum name="ENET_MDIO" start="0x1" description="ENET_MDIO" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="P1_18" description="Pin function select P1.18.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.18" />
-        <Enum name="USB_UP_LED" start="0x1" description="USB_UP_LED" />
-        <Enum name="PWM1" start="0x2" description="PWM1.1" />
-        <Enum name="CAP1" start="0x3" description="CAP1.0" />
-      </BitField>
-      <BitField start="6" size="2" name="P1_19" description="Pin function select P1.19.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.19." />
-        <Enum name="MCOA0" start="0x1" description="MCOA0" />
-        <Enum name="USB_PPWR" start="0x2" description="USB_PPWR" />
-        <Enum name="CAP1" start="0x3" description="CAP1.1" />
-      </BitField>
-      <BitField start="8" size="2" name="P1_20" description="Pin function select P1.20.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.20." />
-        <Enum name="MCI0" start="0x1" description="MCI0" />
-        <Enum name="PWM1" start="0x2" description="PWM1.2" />
-        <Enum name="SCK0" start="0x3" description="SCK0" />
-      </BitField>
-      <BitField start="10" size="2" name="P1_21" description="Pin function select P1.21.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.21." />
-        <Enum name="MCABORT" start="0x1" description="MCABORT" />
-        <Enum name="PWM1" start="0x2" description="PWM1.3" />
-        <Enum name="SSEL0" start="0x3" description="SSEL0" />
-      </BitField>
-      <BitField start="12" size="2" name="P1_22" description="Pin function select P1.22">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.22." />
-        <Enum name="MCOB0" start="0x1" description="MCOB0" />
-        <Enum name="USB_PWRD" start="0x2" description="USB_PWRD" />
-        <Enum name="MAT1" start="0x3" description="MAT1.0" />
-      </BitField>
-      <BitField start="14" size="2" name="P1_23" description="Pin function select P1.23.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.23." />
-        <Enum name="MCI1" start="0x1" description="MCI1" />
-        <Enum name="PWM1" start="0x2" description="PWM1.4" />
-        <Enum name="MISO0" start="0x3" description="MISO0" />
-      </BitField>
-      <BitField start="16" size="2" name="P1_24" description="Pin function select P1.24.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.24." />
-        <Enum name="MCI2" start="0x1" description="MCI2" />
-        <Enum name="PWM1" start="0x2" description="PWM1.5" />
-        <Enum name="MOSI0" start="0x3" description="MOSI0" />
-      </BitField>
-      <BitField start="18" size="2" name="P1_25" description="Pin function select P1.25.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.25" />
-        <Enum name="MCOA1" start="0x1" description="MCOA1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="MAT1" start="0x3" description="MAT1.1" />
-      </BitField>
-      <BitField start="20" size="2" name="P1_26" description="Pin function select P1.26.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.26" />
-        <Enum name="MCOB1" start="0x1" description="MCOB1" />
-        <Enum name="PWM1" start="0x2" description="PWM1.6" />
-        <Enum name="CAP0" start="0x3" description="CAP0.0" />
-      </BitField>
-      <BitField start="22" size="2" name="P1_27" description="Pin function select P1.27.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.27" />
-        <Enum name="CLKOUT" start="0x1" description="CLKOUT" />
-        <Enum name="USB_OVRCR" start="0x2" description="USB_OVRCR" />
-        <Enum name="CAP0" start="0x3" description="CAP0.1" />
-      </BitField>
-      <BitField start="24" size="2" name="P1_28" description="Pin function select P1.28.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.28" />
-        <Enum name="MCOA2" start="0x1" description="MCOA2" />
-        <Enum name="PCAP1" start="0x2" description="PCAP1.0" />
-        <Enum name="MAT0" start="0x3" description="MAT0.0" />
-      </BitField>
-      <BitField start="26" size="2" name="P1_29" description="Pin function select P1.29">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.29" />
-        <Enum name="MCOB2" start="0x1" description="MCOB2" />
-        <Enum name="PCAP1" start="0x2" description="PCAP1.1" />
-        <Enum name="MAT0" start="0x3" description="MAT0.1" />
-      </BitField>
-      <BitField start="28" size="2" name="P1_30" description="Pin function select P1.30.">
-        <Enum name="GPIO_P1" start="0x0" description="GPIO P1.30" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="VBUS" start="0x2" description="VBUS" />
-        <Enum name="AD0" start="0x3" description="AD0.4" />
-      </BitField>
-      <BitField start="30" size="2" name="P1_31" description="Pin function select P1.31.">
-        <Enum name="GPIO_PORT_1" start="0x0" description="GPIO Port 1.31" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SCK1" start="0x2" description="SCK1" />
-        <Enum name="AD0" start="0x3" description="AD0.5" />
-      </BitField>
-    </Register>
-    <Register start="+0x010" size="4" name="PINSEL4" access="Read/Write" description="Pin function select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P2_0" description="Pin function select P2.0.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.0" />
-        <Enum name="PWM1" start="0x1" description="PWM1.1" />
-        <Enum name="TXD1" start="0x2" description="TXD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="2" name="P2_1" description="Pin function select P2.1.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.1" />
-        <Enum name="PWM1" start="0x1" description="PWM1.2" />
-        <Enum name="RXD1" start="0x2" description="RXD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="P2_2" description="Pin function select P2.2.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.2" />
-        <Enum name="PWM1" start="0x1" description="PWM1.3" />
-        <Enum name="CTS1" start="0x2" description="CTS1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="P2_3" description="Pin function select P2.3.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.3." />
-        <Enum name="PWM1" start="0x1" description="PWM1.4" />
-        <Enum name="DCD1" start="0x2" description="DCD1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="8" size="2" name="P2_4" description="Pin function select P2.4.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.4." />
-        <Enum name="PWM1" start="0x1" description="PWM1.5" />
-        <Enum name="DSR1" start="0x2" description="DSR1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="10" size="2" name="P2_5" description="Pin function select P2.5.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.5." />
-        <Enum name="PWM1" start="0x1" description="PWM1.6" />
-        <Enum name="DTR1" start="0x2" description="DTR1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="12" size="2" name="P2_6" description="Pin function select P2.6.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.6." />
-        <Enum name="PCAP1" start="0x1" description="PCAP1.0" />
-        <Enum name="RI1" start="0x2" description="RI1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="14" size="2" name="P2_7" description="Pin function select P2.7.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.7." />
-        <Enum name="RD2" start="0x1" description="RD2" />
-        <Enum name="RTS1" start="0x2" description="RTS1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="16" size="2" name="P2_8" description="Pin function select P2.8.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.8." />
-        <Enum name="TD2" start="0x1" description="TD2" />
-        <Enum name="TXD2" start="0x2" description="TXD2" />
-        <Enum name="ENET_MDC" start="0x3" description="ENET_MDC" />
-      </BitField>
-      <BitField start="18" size="2" name="P2_9" description="Pin function select P2.9.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.9" />
-        <Enum name="USB_CONNECT" start="0x1" description="USB_CONNECT" />
-        <Enum name="RXD2" start="0x2" description="RXD2" />
-        <Enum name="ENET_MDIO" start="0x3" description="ENET_MDIO" />
-      </BitField>
-      <BitField start="20" size="2" name="P2_10" description="Pin function select P2.10.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.10" />
-        <Enum name="EINT0" start="0x1" description="EINT0" />
-        <Enum name="NMI" start="0x2" description="NMI" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="22" size="2" name="P2_11" description="Pin function select P2.11.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.11" />
-        <Enum name="EINT1" start="0x1" description="EINT1" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_CLK" start="0x3" description="I2STX_CLK" />
-      </BitField>
-      <BitField start="24" size="2" name="P2_12" description="Pin function select P2.12.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.12" />
-        <Enum name="EINT2" start="0x1" description="EINT2" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_WS" start="0x3" description="I2STX_WS" />
-      </BitField>
-      <BitField start="26" size="2" name="P2_13" description="Pin function select P2.13.">
-        <Enum name="GPIO_P2" start="0x0" description="GPIO P2.13" />
-        <Enum name="EINT3" start="0x1" description="EINT3" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="I2STX_SDA" start="0x3" description="I2STX_SDA" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PINSEL7" access="Read/Write" description="Pin function select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="18" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="2" name="P3_25" description="Pin function select P3.25.">
-        <Enum name="GPIO_P3" start="0x0" description="GPIO P3.25" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="MAT0" start="0x2" description="MAT0.0" />
-        <Enum name="PWM1" start="0x3" description="PWM1.2" />
-      </BitField>
-      <BitField start="20" size="2" name="P3_26" description="Pin function select P3.26.">
-        <Enum name="GPIO_P3" start="0x0" description="GPIO P3.26" />
-        <Enum name="STCLK" start="0x1" description="STCLK" />
-        <Enum name="MAT0" start="0x2" description="MAT0.1" />
-        <Enum name="PWM1" start="0x3" description="PWM1.3" />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="PINSEL9" access="Read/Write" description="Pin function select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="2" name="P4_28" description="Pin function select P4.28.">
-        <Enum name="GPIO_P4" start="0x0" description="GPIO P4.28" />
-        <Enum name="RX_MCLK" start="0x1" description="RX_MCLK" />
-        <Enum name="MAT2" start="0x2" description="MAT2.0" />
-        <Enum name="TXD3" start="0x3" description="TXD3" />
-      </BitField>
-      <BitField start="26" size="2" name="P4_29" description="Pin function select P4.29.">
-        <Enum name="GPIO_P4" start="0x0" description="GPIO P4.29" />
-        <Enum name="TX_MCLK" start="0x1" description="TX_MCLK" />
-        <Enum name="MAT2" start="0x2" description="MAT2.1" />
-        <Enum name="RXD3" start="0x3" description="RXD3" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x028" size="4" name="PINSEL10" access="Read/Write" description="Pin function select register 10" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
-      <BitField start="3" size="1" name="TPIUCTRL" description="TPIU interface pins control.">
-        <Enum name="DISABLED" start="0" description="Disabled. TPIU interface is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Software should not write 1 to these bits." />
-    </Register>
-    <Register start="+0x040" size="4" name="PINMODE0" access="Read/Write" description="Pin mode select register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_00MODE" description="Port 0 pin 0 on-chip pull-up/down resistor control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P0_01MODE" description="Port 0 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P0_02MODE" description="Port 0 pin 2 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.2 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.2 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.2 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.2 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P0_03MODE" description="Port 0 pin 3 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.3 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.3 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.3 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.3 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_04MODE" description="Port 0 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P0_05MODE" description="Port 0 pin 5 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.5 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.5 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.5 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.5 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P0_06MODE" description="Port 0 pin 6 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.6 pin has a pull-up resistor enabled." />
-        <Enum name="DISABLED" start="0x1" description="Disabled. Repeater. P0.6 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.6 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.6 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P0_07MODE" description="Port 0 pin 7 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.7 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.7 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.7 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.7 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P0_08MODE" description="Port 0 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P0_09MODE" description="Port 0 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P0_10MODE" description="Port 0 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P0_11MODE" description="Port 0 pin 11 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.11 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.11 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.11 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.11 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="P0_15MODE" description="Port 0 pin 15 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.15 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.15 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.15 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.15 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x044" size="4" name="PINMODE1" access="Read/Write" description="Pin mode select register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P0_16MODE" description="Port 1 pin 16 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.16 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.16 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.16 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.16 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P0_17MODE" description="Port 1 pin 17 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.17 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.17 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.17 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.17 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P0_18MODE" description="Port 1 pin 18 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.18 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.18 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.18 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.18 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P0_19MODE" description="Port 1 pin 19 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.19 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.19 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.19 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.19 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P0_20MODE" description="Port 1 pin 20 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.20 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.20 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.20 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.20 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P0_21MODE" description="Port 1 pin 21 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.21 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.21 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.21 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.21 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P0_22MODE" description="Port 1 pin 22 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.22 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.22 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.22 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.22 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P0_23MODE" description="Port 1 pin 23 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.23 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.23 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.23 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.23 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P0_24MODE" description="Port 1 pin 24 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.24 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.24 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.24 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.24 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P0_25MODE" description="Port 1 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P0_26MODE" description="Port 1 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P0.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P0.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P0.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P0.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="PINMODE2" access="Read/Write" description="Pin mode select register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_00MODE" description="Port 1 pin 0 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P1_01MODE" description="Port 1 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="2" name="P1_04MODE" description="Port 1 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="2" name="P1_08MODE" description="Port 1 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P1_09MODE" description="Port 1 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P1_10MODE" description="Port 1 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="2" name="P1_14MODE" description="Port 1 pin 14 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.14 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.14 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.14 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.14 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="30" size="2" name="P1_15MODE" description="Port 1 pin 15 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.15 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.15 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.15 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.15 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x04C" size="4" name="PINMODE3" access="Read/Write" description="Pin mode select register 3." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P1_16MODE" description="Port 1 pin 16 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.16 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.16 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.16 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.16 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P1_17MODE" description="Port 1 pin 17 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.17 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.17 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.17 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.17 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P1_18MODE" description="Port 1 pin 18 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.18 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.18 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.18 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.18 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P1_19MODE" description="Port 1 pin 19 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.19 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.19 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.19 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.19 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P1_20MODE" description="Port 1 pin 20 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.20 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.20 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.20 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.20 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P1_21MODE" description="Port 1 pin 21 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.21 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.21 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.21 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.21 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P1_22MODE" description="Port 1 pin 22 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.22 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.22 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.22 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.22 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P1_23MODE" description="Port 1 pin 23 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.23 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.23 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.23 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.23 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P1_24MODE" description="Port 1 pin 24 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.24 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.24 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.24 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.24 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P1_25MODE" description="Port 1 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P1_26MODE" description="Port 1 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P1_27MODE" description="Port 1 pin 27 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.27 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.27 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.27 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.27 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="2" name="P1_28MODE" description="Port 1 pin 28 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.28 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.28 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.28 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.28 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P1_29MODE" description="Port 1 pin 29 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.29 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.29 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.29 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.29 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="2" name="P1_30MODE" description="Port 1 pin 30 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.30 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.30 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.30 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.30 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="30" size="2" name="P1_31MODE" description="Port 1 pin 31 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P1.31 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P1.31 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P1.31 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P1.31 has a pull-down resistor enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x050" size="4" name="PINMODE4" access="Read/Write" description="Pin mode select register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="P2_00MODE" description="Port 2 pin 0 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.0 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.0 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.0 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.0 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="2" size="2" name="P2_01MODE" description="Port 2 pin 1 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.1 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.1 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.1 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.1 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="4" size="2" name="P2_02MODE" description="Port 2 pin 2 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.2 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.2 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.2 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.2 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="6" size="2" name="P2_03MODE" description="Port 2 pin 3 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.3 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.3 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.3 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.3 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="8" size="2" name="P2_04MODE" description="Port 2 pin 4 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.4 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.4 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.4 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.4 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="10" size="2" name="P2_05MODE" description="Port 2 pin 5 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.5 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.5 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.5 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.5 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="12" size="2" name="P2_06MODE" description="Port 2 pin 6 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.6 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.6 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.6 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.6 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="14" size="2" name="P2_07MODE" description="Port 2 pin 7 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.7 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.7 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.7 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.7 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="16" size="2" name="P2_08MODE" description="Port 2 pin 8 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.8 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.8 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.8 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.8 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="18" size="2" name="P2_09MODE" description="Port 2 pin 9 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.9 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.9 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.9 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.9 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P2_10MODE" description="Port 2 pin 10 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.10 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.10 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.10 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.10 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="2" name="P2_11MODE" description="Port 2 pin 11 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.11 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.11 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.11 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.11 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="24" size="2" name="P2_12MODE" description="Port 2 pin 12 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.12 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.12 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.12 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.12 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P2_13MODE" description="Port 2 pin 13 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P2.13 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P2.13 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P2.13 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P2.13 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="PINMODE7" access="Read/Write" description="Pin mode select register 7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="P3_25MODE" description="Port 3 pin 25 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.25 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P3.25 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P3.25 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.25 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="20" size="2" name="P3_26MODE" description="Port 3 pin 26 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P3.26 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P3.26 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P3.26 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P3.26 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x064" size="4" name="PINMODE9" access="Read/Write" description="Pin mode select register 9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="2" name="P4_28MODE" description="Port 4 pin 28 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.28 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P4.28 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P4.28 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.28 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="26" size="2" name="P4_29MODE" description="Port 4 pin 29 control.">
-        <Enum name="PULL_UP" start="0x0" description="Pull-up. P4.29 pin has a pull-up resistor enabled." />
-        <Enum name="REPEATER" start="0x1" description="Repeater. P4.29 pin has repeater mode enabled." />
-        <Enum name="DISABLED" start="0x2" description="Disabled. P4.29 pin has neither pull-up nor pull-down." />
-        <Enum name="PULL_DOWN" start="0x3" description="Pull-down. P4.29 has a pull-down resistor enabled." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="PINMODE_OD0" access="Read/Write" description="Open drain mode control register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_00OD" description="Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P0_01OD" description="Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.1 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="1" name="P0_02OD" description="Port 0 pin 2 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.2 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.2 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="3" size="1" name="P0_03OD" description="Port 0 pin 3 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.3 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.3 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="4" size="1" name="P0_04OD" description="Port 0 pin 4 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="1" name="P0_05OD" description="Port 0 pin 5 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.5 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.5 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="6" size="1" name="P0_06OD" description="Port 0 pin 6 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.6 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.6 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="7" size="1" name="P0_07OD" description="Port 0 pin 7 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.7 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.7 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="8" size="1" name="P0_08OD" description="Port 0 pin 8 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P0_09OD" description="Port 0 pin 9 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P0_10OD" description="Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="1" name="P0_11OD" description="Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.11 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.11 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="P0_15OD" description="Port 0 pin 15 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.15 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.15 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="16" size="1" name="P0_16OD" description="Port 0 pin 16 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.16 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.16 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="17" size="1" name="P0_17OD" description="Port 0 pin 17 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.17 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.17 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="18" size="1" name="P0_18OD" description="Port 0 pin 18 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.18 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.18 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="19" size="1" name="P0_19OD" description="Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.19 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.19 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="20" size="1" name="P0_20OD" description="Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.">
-        <Enum name="NORMAL" start="0" description="Normal. P0.20 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.20 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="21" size="1" name="P0_21OD" description="Port 0 pin 21 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.21 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.21 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="22" size="1" name="P0_22OD" description="Port 0 pin 22 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.22 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.22 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="23" size="1" name="P0_23OD" description="Port 0 pin 23 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="24" size="1" name="P0_24OD" description="Port 0 pin 24open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="25" size="1" name="P0_25OD" description="Port 0 pin 25 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P0_26OD" description="Port 0 pin 26 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.26 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.26 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="27" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="P0_29OD" description="Port 0 pin 29 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.29 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.29 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="30" size="1" name="P0_30OD" description="Port 0 pin 30 open drain mode control">
-        <Enum name="NORMAL" start="0" description="Normal. P0.30 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P0.30 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="PINMODE_OD1" access="Read/Write" description="Open drain mode control register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P1_00OD" description="Port 1 pin 0 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P1.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P1_01OD" description="Port 1 pin 1 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.1 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="P1_04OD" description="Port 1 pin 4 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="P1_08OD" description="Port 1 pin 8 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P1_09OD" description="Port 1 pin 9 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P1_10OD" description="Port 1 pin 10 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="P1_14OD" description="Port 1 pin 14 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.14 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.14 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="15" size="1" name="P1_15OD" description="Port 1 pin 15 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.15 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.15 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="16" size="1" name="P1_16OD" description="Port 1 pin 16 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.16 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.16 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="17" size="1" name="P1_17OD" description="Port 1 pin 17 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.17 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.17 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="18" size="1" name="P1_18OD" description="Port 1 pin 18 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.18 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.18 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="19" size="1" name="P1_19OD" description="Port 1 pin 19 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.19 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.19 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="20" size="1" name="P1_20OD" description="Port 1 pin 20open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.20 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.20 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="21" size="1" name="P1_21OD" description="Port 1 pin 21 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.21 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.21 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="22" size="1" name="P1_22OD" description="Port 1 pin 22 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.22 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.22 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="23" size="1" name="P1_23OD" description="Port 1 pin 23 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.23 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.23 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="24" size="1" name="P1_24OD" description="Port 1 pin 24open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.24 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.24 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="25" size="1" name="P1_25OD" description="Port 1 pin 25 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P1_26OD" description="Port 1 pin 26 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.26 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.26 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="27" size="1" name="P1_27OD" description="Port 1 pin 27 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.27 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.27 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="28" size="1" name="P1_28OD" description="Port 1 pin 28 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.28 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.28 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="29" size="1" name="P1_29OD" description="Port 1 pin 29 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.29 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.29 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="30" size="1" name="P1_30OD" description="Port 1 pin 30 open drain mode control, see P1.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P1.30 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.30 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="31" size="1" name="P1_31OD" description="Port 1 pin 31 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P1.31 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P1.31 pin is in the open drain mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x070" size="4" name="PINMODE_OD2" access="Read/Write" description="Open drain mode control register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_00OD" description="Port 2 pin 0 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P2.0 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.0 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="1" size="1" name="P2_01OD" description="Port 2 pin 1 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.1 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.1p in is in the open drain mode." />
-      </BitField>
-      <BitField start="2" size="1" name="P2_02OD" description="Port 2 pin 2 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.2 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.2 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="3" size="1" name="P2_03OD" description="Port 2 pin 3 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.3 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.3 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="4" size="1" name="P2_04OD" description="Port 2 pin 4 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.4 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.4 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="5" size="1" name="P2_05OD" description="Port 2 pin 5 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.5 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.5 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="6" size="1" name="P2_06OD" description="Port 2 pin 6 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.6 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.6 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="7" size="1" name="P2_07OD" description="Port 2 pin 7 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.7 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.7 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="8" size="1" name="P2_08OD" description="Port 2 pin 8 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.8 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.8 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="9" size="1" name="P2_09OD" description="Port 2 pin 9 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.9 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.9 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="10" size="1" name="P2_10OD" description="Port 2 pin 10 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.10 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.10 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="11" size="1" name="P2_11OD" description="Port 2 pin 11 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.11 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.11 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="12" size="1" name="P2_12OD" description="Port 2 pin 12 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.12 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.12 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="13" size="1" name="P2_13OD" description="Port 2 pin 13 open drain mode control, see P2.00OD">
-        <Enum name="NORMAL" start="0" description="Normal. P2.13 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P2.13 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x074" size="4" name="PINMODE_OD3" access="Read/Write" description="Open drain mode control register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="25" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="1" name="P3_25OD" description="Port 3 pin 25 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P3.25 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P3.25 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="26" size="1" name="P3_26OD" description="Port 3 pin 26 open drain mode control, see P3.25OD" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x078" size="4" name="PINMODE_OD4" access="Read/Write" description="Open drain mode control register 4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="28" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="P4_28OD" description="Port 4 pin 28 open drain mode control.">
-        <Enum name="NORMAL" start="0" description="Normal. P4.28 pin is in the normal (not open drain) mode." />
-        <Enum name="OPEN_DRAIN" start="1" description="Open-drain. P4.28 pin is in the open drain mode." />
-      </BitField>
-      <BitField start="29" size="1" name="P4_29OD" description="Port 4 pin 29 open drain mode control, see P4.28OD" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x07C" size="4" name="I2CPADCFG" access="Read/Write" description="I2C Pin Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SDADRV0" description="Drive mode control for the SDA0 pin, P0.27.">
-        <Enum name="STANDARD" start="0" description="Standard. The SDA0 pin is in the standard drive mode." />
-        <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode." />
-      </BitField>
-      <BitField start="1" size="1" name="SDAI2C0" description="I 2C filter mode control for the SDA0 pin, P0.27.">
-        <Enum name="ENABLED" start="0" description="Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SCLDRV0" description="Drive mode control for the SCL0 pin, P0.28.">
-        <Enum name="STANDARD" start="0" description="Standard. The SCL0 pin is in the standard drive mode." />
-        <Enum name="FAST_MODE_PLUS" start="1" description="Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode." />
-      </BitField>
-      <BitField start="3" size="1" name="SCLI2C0" description="I 2C filter mode control for the SCL0 pin, P0.28.">
-        <Enum name="ENABLED" start="0" description="Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
-        <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
-      </BitField>
-      <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="21" size="1" name="PDN" description="Power down mode">
-        <Enum name="POWERED" start="1" description="The A/D converter is operational." />
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
-        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
-        <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
-        <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
-        <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
-        <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
-        <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
-        <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
-      </BitField>
-      <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
-        <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
-        <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
-      <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
-      <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
-      <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
-      <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
-      <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
-      <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
-      <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
-      <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
-      <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
-      <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
-      <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
-      <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
-      <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
-      <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
-      <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
-      <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
-    <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAF" start="0x4003C000" description=" CAN controller acceptance filter ">
-    <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
-      <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
-      <BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
-        <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
-        <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
-    </Register>
-    <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCAN" start="0x40040000" description="Central CAN controller ">
-    <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
-      <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
-      <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
-      <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
-      <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
-      <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
-      <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN1" start="0x40044000" description="CAN1 controller ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN2" start="0x40048000" description="CAN1 controller ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit&#xa;frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x4008C000" description=" Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
-        <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
-        <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
-        <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
-        <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA access">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x40090000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x40094000" description="Timer0/1/2/3  ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400B0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTER" access="Read/Write" description="Digital filter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
-      <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
-      <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
-      <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
-      <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
-      <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
-      <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
-      <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
-      <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
-      <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
-      <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
-      <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x400FC000" description="System and clock control">
-    <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0x303A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.">
-        <Enum name="1CLK" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock." />
-        <Enum name="2CLK" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock." />
-        <Enum name="3CLK" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock." />
-        <Enum name="4CLK" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock." />
-        <Enum name="5CLK" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only." />
-        <Enum name="6CLK" start="0x5" description="Flash accesses use 6 CPU clocks. This safe setting will work under any conditions." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="PLL0CON" access="Read/Write" description="PLL0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE0" description="PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register." />
-      <BitField start="1" size="1" name="PLLC0" description="PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="PLL0CFG" access="Read/Write" description="PLL0 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MSEL0" description="PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1.  Note: Not all values of M are needed, and therefore some are not supported by hardware." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="8" name="NSEL0" description="PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x088" size="4" name="PLL0STAT" access="ReadOnly" description="PLL0 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="MSEL0" description="Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="8" name="NSEL0" description="Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider." />
-      <BitField start="24" size="1" name="PLLE0_STAT" description="Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered." />
-      <BitField start="25" size="1" name="PLLC0_STAT" description="Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered." />
-      <BitField start="26" size="1" name="PLOCK0" description="Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details." />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x08C" size="4" name="PLL0FEED" access="WriteOnly" description="PLL0 Feed Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLL0FEED" description="The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0" size="4" name="PLL1CON" access="Read/Write" description="PLL1 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE1" description="PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency." />
-      <BitField start="1" size="1" name="PLLC1" description="PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A4" size="4" name="PLL1CFG" access="Read/Write" description="PLL1 Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL1" description="PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations." />
-      <BitField start="5" size="2" name="PSEL1" description="PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A8" size="4" name="PLL1STAT" access="ReadOnly" description="PLL1 Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL1" description="Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1." />
-      <BitField start="5" size="2" name="PSEL1" description="Read-back for the PLL1 Divider value. This is the value currently used by PLL1." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE1_STAT" description="Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="PLLC1_STAT" description="Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="10" size="1" name="PLOCK1" description="Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0AC" size="4" name="PLL1FEED" access="WriteOnly" description="PLL1 Feed Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLL1FEED" description="The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode." />
-      <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode." />
-      <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit." />
-      <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0C4" size="4" name="PCONP" access="Read/Write" description="Power Control for Peripherals Register" reset_value="0x03BE" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
-      <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
-      <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
-      <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
-      <BitField start="7" size="1" name="PCI2C0" description="The I2C0 interface power/clock control bit." />
-      <BitField start="8" size="1" name="PCSPI" description="The SPI interface power/clock control bit." />
-      <BitField start="9" size="1" name="PCRTC" description="The RTC power/clock control bit." />
-      <BitField start="10" size="1" name="PCSSP1" description="The SSP 1 interface power/clock control bit." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN." />
-      <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
-      <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
-      <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
-      <BitField start="16" size="1" name="PCRIT" description="Repetitive Interrupt Timer power/clock control bit." />
-      <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM" />
-      <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
-      <BitField start="19" size="1" name="PCI2C1" description="The I2C1 interface power/clock control bit." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="PCSSP0" description="The SSP0 interface power/clock control bit." />
-      <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
-      <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
-      <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
-      <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
-      <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
-      <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
-      <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
-      <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
-    </Register>
-    <Register start="+0x104" size="4" name="CCLKCFG" access="Read/Write" description="CPU Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CCLKSEL" description="Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x108" size="4" name="USBCLKCFG" access="Read/Write" description="USB Clock Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="USBSEL" description="Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output.  Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLKSRC" description="Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.">
-        <Enum name="SELECTS_THE_INTERNAL" start="0x0" description="Selects the Internal RC oscillator as the PLL0 clock source (default)." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the PLL0 clock source.  Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates &gt; 100 kBit/s." />
-        <Enum name="SELECTS_THE_RTC_OSCI" start="0x2" description="Selects the RTC oscillator as the PLL0 clock source." />
-        <Enum name="RESERVED" start="0x3" description="Reserved, do not use this setting." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
-      <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTMODE0" description="External interrupt 0 EINT0 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT0." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT0 is edge sensitive." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTMODE1" description="External interrupt 1 EINT1 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT1." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT1 is edge sensitive." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTMODE2" description="External interrupt 2 EINT2 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT2." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT2 is edge sensitive." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTMODE3" description="External interrupt 3 EINT3 mode.">
-        <Enum name="LEVEL_SENSITIVE" start="0" description="Level-sensitive. Level-sensitivity is selected for EINT3." />
-        <Enum name="EDGE_SENSITIVE" start="1" description="Edge-sensitive. EINT3 is edge sensitive." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt 0 EINT0 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0)." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt 1 EINT1 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1)." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt 2 EINT2 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2)." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt 3 EINT3 polarity.">
-        <Enum name="FALLING_EDGE" start="0" description="Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3)." />
-        <Enum name="RISING_EDGE" start="1" description="Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
-      <BitField start="1" size="1" name="EXTR" description="Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR." />
-      <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
-      <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System control and status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="OSCRANGE" description="Main oscillator range select.">
-        <Enum name="LOW" start="0" description="Low. The frequency range of the main oscillator is 1 MHz to 20 MHz." />
-        <Enum name="HIGH" start="1" description="High. The frequency range of the main oscillator is 15 MHz to 25 MHz." />
-      </BitField>
-      <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. The main oscillator is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
-      </BitField>
-      <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
-        <Enum name="NOT_READY" start="0" description="Not ready. The main oscillator is not ready to be used as a clock source." />
-        <Enum name="READY" start="1" description="Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="PCLKSEL0" access="Read/Write" description="Peripheral Clock Selection register 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PCLK_WDT" description="Peripheral clock selection for WDT.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="2" size="2" name="PCLK_TIMER0" description="Peripheral clock selection for TIMER0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="4" size="2" name="PCLK_TIMER1" description="Peripheral clock selection for TIMER1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="6" size="2" name="PCLK_UART0" description="Peripheral clock selection for UART0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="8" size="2" name="PCLK_UART1" description="Peripheral clock selection for UART1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="2" name="PCLK_PWM1" description="Peripheral clock selection for PWM1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="14" size="2" name="PCLK_I2C0" description="Peripheral clock selection for I2C0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="16" size="2" name="PCLK_SPI" description="Peripheral clock selection for SPI.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="18" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="20" size="2" name="PCLK_SSP1" description="Peripheral clock selection for SSP1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="22" size="2" name="PCLK_DAC" description="Peripheral clock selection for DAC.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="24" size="2" name="PCLK_ADC" description="Peripheral clock selection for ADC.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="26" size="2" name="PCLK_CAN1" description="Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6." />
-      </BitField>
-      <BitField start="28" size="2" name="PCLK_CAN2" description="Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6," />
-      </BitField>
-      <BitField start="30" size="2" name="PCLK_ACF" description="Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_6" start="0x3" description="CCLK div 6. PCLK_peripheral = CCLK/6" />
-      </BitField>
-    </Register>
-    <Register start="+0x1AC" size="4" name="PCLKSEL1" access="Read/Write" description="Peripheral Clock Selection register 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PCLK_QEI" description="Peripheral clock selection for the Quadrature Encoder Interface.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="2" size="2" name="PCLK_GPIOINT" description="Peripheral clock selection for GPIO interrupts.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="4" size="2" name="PCLK_PCB" description="Peripheral clock selection for the Pin Connect block.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="6" size="2" name="PCLK_I2C1" description="Peripheral clock selection for I2C1.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="8" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="2" name="PCLK_SSP0" description="Peripheral clock selection for SSP0.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="12" size="2" name="PCLK_TIMER2" description="Peripheral clock selection for TIMER2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="14" size="2" name="PCLK_TIMER3" description="Peripheral clock selection for TIMER3.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="16" size="2" name="PCLK_UART2" description="Peripheral clock selection for UART2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="18" size="2" name="PCLK_UART3" description="Peripheral clock selection for UART3.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="20" size="2" name="PCLK_I2C2" description="Peripheral clock selection for I2C2.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="22" size="2" name="PCLK_I2S" description="Peripheral clock selection for I2S.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="24" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="26" size="2" name="PCLK_RIT" description="Peripheral clock selection for Repetitive Interrupt Timer.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="28" size="2" name="PCLK_SYSCON" description="Peripheral clock selection for the System Control block.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-      <BitField start="30" size="2" name="PCLK_MC" description="Peripheral clock selection for the Motor Control PWM.">
-        <Enum name="CCLK_DIV_4" start="0x0" description="CCLK div 4. PCLK_peripheral = CCLK/4" />
-        <Enum name="CCLK" start="0x1" description="CCLK. PCLK_peripheral = CCLK" />
-        <Enum name="CCLK_DIV_2" start="0x2" description="CCLK div 2. PCLK_peripheral = CCLK/2" />
-        <Enum name="CCLK_DIV_8" start="0x3" description="CCLK div 8. PCLK_peripheral = CCLK/8" />
-      </BitField>
-    </Register>
-    <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
-      <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
-      <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
-      <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
-      <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
-      <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
-      <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
-      <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMASEL08" description="Selects the DMA request for GPDMA input 8: 0 - uart0 tx  1 - Timer 0 match 0 is selected." />
-      <BitField start="1" size="1" name="DMASEL09" description="Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected." />
-      <BitField start="2" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - uart1 tx  is selected. 1 - Timer 1 match 0 is selected." />
-      <BitField start="3" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - uart1 rx  is selected. 1 - Timer 1 match 1 is selected." />
-      <BitField start="4" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - uart2 tx  is selected. 1 - Timer 2 match 0 is selected." />
-      <BitField start="5" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - uart2 rx  is selected. 1 - Timer 2 match 1 is selected." />
-      <BitField start="6" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - uart3 tx  is selected. 1 - I2S channel 0 is selected." />
-      <BitField start="7" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.">
-        <Enum name="SELECTS_THE_CPU_CLOC" start="0x0" description="Selects the CPU clock as the CLKOUT source." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="0x1" description="Selects the main oscillator as the CLKOUT source." />
-        <Enum name="SELECTS_THE_INTERNAL" start="0x2" description="Selects the Internal RC oscillator as the CLKOUT source." />
-        <Enum name="SELECTS_THE_USB_CLOC" start="0x3" description="Selects the USB clock as the CLKOUT source." />
-        <Enum name="SELECTS_THE_RTC_OSCI" start="0x4" description="Selects the RTC oscillator as the CLKOUT source." />
-      </BitField>
-      <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16." />
-      <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
-      <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMAC" start="0x50000000" description="Ethernet">
-    <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
-      <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
-      <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
-      <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
-      <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
-      <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
-      <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
-      <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
-      <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
-      <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
-      <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
-      <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
-      <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
-      <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
-      <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
-      <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
-      <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
-      <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
-      <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
-      <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
-      <BitField start="3" size="29" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
-      <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
-      <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
-      <BitField start="6" size="9" name="RESERVED" description="Unused" />
-      <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
-      <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
-      <BitField start="13" size="19" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
-      <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
-      <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
-      <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
-      <BitField start="4" size="28" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
-      <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
-      <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
-      <BitField start="2" size="1" name="RESERVED" description="Unused" />
-      <BitField start="3" size="1" name="REGRESET" description="When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
-      <BitField start="4" size="1" name="TXRESET" description="When a  1  is written, the transmit datapath is reset." />
-      <BitField start="5" size="1" name="RXRESET" description="When a  1  is written, the receive datapath is reset." />
-      <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
-      <BitField start="7" size="1" name="PASSRXFILTER" description="When set to  1 , disables receive filtering i.e. all frames received are written to memory." />
-      <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
-      <BitField start="9" size="1" name="RMII" description="When set to  1 , RMII mode is selected; if 0, MII mode is selected." />
-      <BitField start="10" size="1" name="FULLDUPLEX" description="When set to  1 , indicates full duplex operation." />
-      <BitField start="11" size="21" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
-      <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
-    </Register>
-    <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
-      <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
-    </Register>
-    <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
-    </Register>
-    <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
-    </Register>
-    <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
-      <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
-      <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
-      <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
-      <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
-      <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
-      <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
-      <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
-      <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
-      <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
-      <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
-      <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
-      <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
-      <BitField start="20" size="12" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
-      <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
-      <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
-      <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
-      <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
-      <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
-      <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
-      <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
-      <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
-      <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
-      <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-      <BitField start="31" size="1" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
-      <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
-    </Register>
-    <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
-      <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
-      <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
-      <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
-      <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
-      <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
-      <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
-      <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
-      <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
-      <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
-      <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
-      <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
-      <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
-      <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
-      <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
-      <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
-      <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
-      <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="RESERVED" description="Unused" />
-      <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x50004000" description="General purpose DMA controller">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
-      <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x50008000" description="USB device/host/OTG controller">
-    <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR" description="Timer time-out." />
-      <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
-      <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
-      <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="INTCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="STCTRL" access="Read/Write" description="OTG Status and Control and USB port select" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PORT_FUNC" description="Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
-      <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
-      <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
-      <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
-      <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
-    </Register>
-    <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
-      <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
-      <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
-      <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
-      <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
-      <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
-      <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
-        <Enum name="READ" start="0x02" description="Read" />
-        <Enum name="WRITE" start="0x01" description="Write" />
-        <Enum name="COMMAND" start="0x05" description="Command" />
-      </BitField>
-      <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RX_DATA" description="Data received." />
-    </Register>
-    <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
-    </Register>
-    <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
-        <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
-        <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
-      </BitField>
-      <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
-        <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
-        <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-    </Register>
-    <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-    </Register>
-    <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-    </Register>
-    <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-    </Register>
-    <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-    </Register>
-    <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-    </Register>
-    <Register start="+0x248" size="4" name="EPIND" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 &lt;=  xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-    </Register>
-    <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
-      <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
-    </Register>
-    <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-    </Register>
-    <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RXDATA" description="Receive data." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_WO" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="TXDATA" description="Transmit data." />
-      <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
-      <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
-        <Enum name="NOT_COMPLETE" start="0" description="Transaction has not completed." />
-        <Enum name="COMPLETE" start="1" description="Transaction completed." />
-      </BitField>
-      <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
-        <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
-        <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
-      </BitField>
-      <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="ACKNOWLEDGE_RCVD" start="0" description="Last transmission received an acknowledge." />
-        <Enum name="NO_ACKNOWLEDGE_RCVD" start="1" description="Last transmission did not receive an acknowledge." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="BUSY" start="0" description="Master transmitter does not need data." />
-        <Enum name="NEED_DATA" start="1" description="Master transmitter needs data." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
-        <Enum name="BUSY" start="0" description="Slave transmitter does not need data." />
-        <Enum name="NEED_DATA" start="1" description="Slave transmitter needs data." />
-      </BitField>
-      <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
-      <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
-      <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
-      <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
-        <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
-        <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
-      </BitField>
-      <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
-        <Enum name="DATA" start="0" description="RX FIFO contains data." />
-        <Enum name="EMPTY" start="1" description="RX FIFO is empty" />
-      </BitField>
-      <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
-        <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
-        <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
-      </BitField>
-      <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
-        <Enum name="VALID_DATA" start="0" description="TX FIFO contains valid data." />
-        <Enum name="EMPTY" start="1" description="TX FIFO is empty" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
-        <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
-        <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
-        <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
-        <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
-      </BitField>
-      <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
-        <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
-        <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
-        <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
-        <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
-        <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
-        <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
-        <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
-        <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
-      </BitField>
-      <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
-        <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
-        <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
-      </BitField>
-      <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
-        <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
-        <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
-      </BitField>
-      <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
-        <Enum name="NO_RESET" start="0" description="No reset." />
-        <Enum name="RESET" start="1" description="Reset the I2C to idle state. Self clearing." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="USBCLKCTRL" access="Read/Write" description="USB Clock Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable.   Enables the usbclk input to the device controller" />
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PORTSEL_CLK_EN" description="Port select register clock enable." />
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB clock enable" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="OTGCLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
-        <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
-        <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
-        <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
-        <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
-        <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
-        <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
-        <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
-        <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
-        <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
-        <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="USBCLKST" access="ReadOnly" description="USB Clock Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock on. The usbclk input to the device controller is active&#x9;." />
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PORTSEL_CLK_ON" description="Port select register clock on." />
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB clock on." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="OTGCLKST" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
-        <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
-        <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
-        <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
-        <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
-        <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
-        <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
-        <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
-        <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
-        <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
-        <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO" start="0x2009C000" description="General Purpose I/O ">
-    <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PINDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PINDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PINDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PINDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PINDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PINDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PINDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PINDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PINDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PINDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PINDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PINDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PINDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PINDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PINDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PINDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PINDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PINDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PINDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PINDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PINDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PINDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PINDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PINDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PINDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PINDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PINDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PINDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PINDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PINDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PINDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PINMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PINMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PINMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PINMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PINMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PINMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PINMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PINMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PINMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PINMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PINMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PINMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PINMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PINMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PINMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PINMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PINMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PINMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PINMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PINMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PINMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PINMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PINMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PINMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PINMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PINMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PINMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PINMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PINMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PINMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PINMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINVAL0" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINVAL1" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINVAL2" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINVAL3" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINVAL4" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINVAL5" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINVAL6" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINVAL7" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINVAL8" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINVAL9" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINVAL10" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINVAL11" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINVAL12" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINVAL13" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINVAL14" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINVAL15" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINVAL16" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINVAL17" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINVAL18" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINVAL19" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINVAL20" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINVAL21" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINVAL22" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINVAL23" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINVAL24" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINVAL25" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINVAL26" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINVAL27" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINVAL28" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINVAL29" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINVAL30" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINVAL31" description="Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINSET0" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PINSET1" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PINSET2" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PINSET3" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PINSET4" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PINSET5" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PINSET6" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PINSET7" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PINSET8" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PINSET9" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PINSET10" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PINSET11" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PINSET12" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PINSET13" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PINSET14" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PINSET15" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PINSET16" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PINSET17" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PINSET18" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PINSET19" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PINSET20" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PINSET21" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PINSET22" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PINSET23" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PINSET24" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PINSET25" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PINSET26" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PINSET27" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PINSET28" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PINSET29" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PINSET30" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PINSET31" description="Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using FIOMASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PINCLR0" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PINCLR1" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PINCLR2" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PINCLR3" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PINCLR4" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PINCLR5" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PINCLR6" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PINCLR7" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PINCLR8" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PINCLR9" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PINCLR10" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PINCLR11" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PINCLR12" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PINCLR13" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PINCLR14" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PINCLR15" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PINCLR16" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PINCLR17" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PINCLR18" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PINCLR19" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PINCLR20" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PINCLR21" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PINCLR22" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PINCLR23" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PINCLR24" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PINCLR25" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PINCLR26" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PINCLR27" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PINCLR28" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PINCLR29" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PINCLR30" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PINCLR31" description="Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="WDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SPI" start="13" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="PLL0" start="16" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="DMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ENET" start="28" size="1" />
-      <BitField name="RIT" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PLL1" start="0" size="1" />
-      <BitField name="USBActivity" start="1" size="1" />
-      <BitField name="CANActivity" start="2" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="WDT" start="4" size="4" />
-      <BitField name="TIMER0" start="12" size="4" />
-      <BitField name="TIMER1" start="20" size="4" />
-      <BitField name="TIMER2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="TIMER3" start="4" size="4" />
-      <BitField name="UART0" start="12" size="4" />
-      <BitField name="UART1" start="20" size="4" />
-      <BitField name="UART2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="UART3" start="4" size="4" />
-      <BitField name="PWM1" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="I2C2" start="4" size="4" />
-      <BitField name="SPI" start="12" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="PLL0" start="4" size="4" />
-      <BitField name="RTC" start="12" size="4" />
-      <BitField name="EINT0" start="20" size="4" />
-      <BitField name="EINT1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="EINT2" start="4" size="4" />
-      <BitField name="EINT3" start="12" size="4" />
-      <BitField name="ADC" start="20" size="4" />
-      <BitField name="BOD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USB" start="4" size="4" />
-      <BitField name="CAN" start="12" size="4" />
-      <BitField name="DMA" start="20" size="4" />
-      <BitField name="I2S" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="ENET" start="4" size="4" />
-      <BitField name="RIT" start="12" size="4" />
-      <BitField name="MCPWM" start="20" size="4" />
-      <BitField name="QEI" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PLL1" start="4" size="4" />
-      <BitField name="USBActivity" start="12" size="4" />
-      <BitField name="CANActivity" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYS_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYS_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYS_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYS_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Vectors.s b/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Vectors.s
deleted file mode 100644
index c5fae131..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/LPC176x5x_Vectors.s
+++ /dev/null
@@ -1,418 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2015 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak WDT_IRQHandler
-  .thumb_set WDT_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak UART0_IRQHandler
-  .thumb_set UART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak UART2_IRQHandler
-  .thumb_set UART2_IRQHandler,Dummy_Handler
-
-  .weak UART3_IRQHandler
-  .thumb_set UART3_IRQHandler,Dummy_Handler
-
-  .weak PWM1_IRQHandler
-  .thumb_set PWM1_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Dummy_Handler
-
-  .weak SPI_IRQHandler
-  .thumb_set SPI_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak PLL0_IRQHandler
-  .thumb_set PLL0_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak EINT0_IRQHandler
-  .thumb_set EINT0_IRQHandler,Dummy_Handler
-
-  .weak EINT1_IRQHandler
-  .thumb_set EINT1_IRQHandler,Dummy_Handler
-
-  .weak EINT2_IRQHandler
-  .thumb_set EINT2_IRQHandler,Dummy_Handler
-
-  .weak EINT3_IRQHandler
-  .thumb_set EINT3_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak BOD_IRQHandler
-  .thumb_set BOD_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak CAN_IRQHandler
-  .thumb_set CAN_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak I2S_IRQHandler
-  .thumb_set I2S_IRQHandler,Dummy_Handler
-
-  .weak ENET_IRQHandler
-  .thumb_set ENET_IRQHandler,Dummy_Handler
-
-  .weak RIT_IRQHandler
-  .thumb_set RIT_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-  .weak PLL1_IRQHandler
-  .thumb_set PLL1_IRQHandler,Dummy_Handler
-
-  .weak USBActivity_IRQHandler
-  .thumb_set USBActivity_IRQHandler,Dummy_Handler
-
-  .weak CANActivity_IRQHandler
-  .thumb_set CANActivity_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak WDT_IRQHandler
-WDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART0_IRQHandler
-UART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART2_IRQHandler
-UART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART3_IRQHandler
-UART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM1_IRQHandler
-PWM1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_IRQHandler
-I2C2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI_IRQHandler
-SPI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PLL0_IRQHandler
-PLL0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT0_IRQHandler
-EINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT1_IRQHandler
-EINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT2_IRQHandler
-EINT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT3_IRQHandler
-EINT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_IRQHandler
-BOD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN_IRQHandler
-CAN_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S_IRQHandler
-I2S_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ENET_IRQHandler
-ENET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RIT_IRQHandler
-RIT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PLL1_IRQHandler
-PLL1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USBActivity_IRQHandler
-USBActivity_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CANActivity_IRQHandler
-CANActivity_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WDT_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word UART0_IRQHandler
-  .word UART1_IRQHandler
-  .word UART2_IRQHandler
-  .word UART3_IRQHandler
-  .word PWM1_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word SPI_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word PLL0_IRQHandler
-  .word RTC_IRQHandler
-  .word EINT0_IRQHandler
-  .word EINT1_IRQHandler
-  .word EINT2_IRQHandler
-  .word EINT3_IRQHandler
-  .word ADC_IRQHandler
-  .word BOD_IRQHandler
-  .word USB_IRQHandler
-  .word CAN_IRQHandler
-  .word DMA_IRQHandler
-  .word I2S_IRQHandler
-  .word ENET_IRQHandler
-  .word RIT_IRQHandler
-  .word MCPWM_IRQHandler
-  .word QEI_IRQHandler
-  .word PLL1_IRQHandler
-  .word USBActivity_IRQHandler
-  .word CANActivity_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/flash_placement.xml b/examples/host/cdc_msc_hid/ses/lpc175x_6x/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject b/examples/host/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject
deleted file mode 100644
index 8a2c3639..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/lpc175x_6x.emProject
+++ /dev/null
@@ -1,119 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc175x_6x" target="8" version="2">
-  <project Name="lpc175x_6x">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4357 Cortex-M4"
-      arm_architecture="v7M"
-      arm_core_type="Cortex-M3"
-      arm_endian="Little"
-      arm_fp_abi="Soft"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 00000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC1769"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="Yes"
-      c_preprocessor_definitions="LPC175x_6x;__LPC1700_FAMILY;__LPC176x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1769;CFG_TUSB_MCU=OPT_MCU_LPC175X_6X;CFG_TUSB_DEBUG=2;LOGGER_RTT"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc;$(rootDir)/lib/SEGGER_RTT/RTT"
-      debug_register_definition_file="LPC176x5x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="LPC1769_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x00000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC1700;DeviceSubFamily=LPC176x;Target=LPC1769;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/LPC1700_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="lpcxpresso1769">
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/lpcxpresso1769.c" />
-        </folder>
-        <file file_name="../../../../../hw/bsp/board.c" />
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_chip_175x_6x">
-            <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip_lpc175x_6x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip_lpc177x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/chip_lpc407x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/clock_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/cmsis_175x_6x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/core_cm3.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/gpio_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/gpioint_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/iocon_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/lpc_types.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/sys_config.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/sysctl_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/inc/uart_17xx_40xx.h" />
-            </folder>
-            <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/chip_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/clock_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/gpio_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/iocon_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/sysctl_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/sysinit_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x/src/uart_17xx_40xx.c" />
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC1700_Startup.s" />
-      <file file_name="LPC1700_Target.js" />
-      <file file_name="LPC1769_MemoryMap.xml" />
-      <file file_name="LPC176x5x_Registers.xml" />
-      <file file_name="LPC176x5x_Vectors.s" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder Name="lib">
-      <folder Name="SEGGER_RTT">
-        <folder Name="RTT">
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.c" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.h" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c" />
-        </folder>
-        <folder Name="Syscalls">
-          <file file_name="../../../../../lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c" />
-        </folder>
-      </folder>
-    </folder>
-  </project>
-  <configuration Name="LPCXpresso 1769" />
-</solution>
diff --git a/examples/host/cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s b/examples/host/cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc175x_6x/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s b/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s
deleted file mode 100644
index e17b6050..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s
+++ /dev/null
@@ -1,110 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js b/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml b/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml
deleted file mode 100644
index 4ded8a9f..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC1857">
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00010000" access="Read/Write" />
-</root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml b/examples/host/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml
deleted file mode 100644
index 5e68d4c0..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml
+++ /dev/null
@@ -1,30452 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC18xx" description="Register cmsis file for LPC18xx parts">
-  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
-        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
-      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
-      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
-      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
-      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
-      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
-      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
-        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
-      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
-      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
-      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
-        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
-        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
-        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
-        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
-      </BitField>
-      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
-        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
-        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
-      </BitField>
-      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
-        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
-        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
-        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
-        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
-      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
-        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
-        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
-      </BitField>
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRESS" description="Address." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
-    </Register>
-    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Input or output data" />
-    </Register>
-    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
-      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
-      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
-      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
-      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
-      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
-      </BitField>
-      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
-      </BitField>
-      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
-        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
-        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
-        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
-        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
-      </BitField>
-      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
-      </BitField>
-      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
-      </BitField>
-      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
-        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
-      </BitField>
-      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
-        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
-      </BitField>
-      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
-      </BitField>
-      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
-        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
-        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
-      </BitField>
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
-      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
-      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
-      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
-        <Enum name="NONE" start="0" description="None. No response expected from card" />
-        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
-      </BitField>
-      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
-        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
-        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
-      </BitField>
-      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
-        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
-        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
-      </BitField>
-      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
-        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
-        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
-      </BitField>
-      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
-        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
-        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
-      </BitField>
-      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
-        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
-      </BitField>
-      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
-        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
-        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
-      </BitField>
-      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
-        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
-        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
-      </BitField>
-      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
-        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
-        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
-      </BitField>
-      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
-        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
-        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
-      </BitField>
-      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
-      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
-        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
-      </BitField>
-      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
-        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-      </BitField>
-      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
-      </BitField>
-      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
-      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
-        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
-        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
-      </BitField>
-      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
-        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
-        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
-      </BitField>
-      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
-    </Register>
-    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
-    </Register>
-    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
-    </Register>
-    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
-    </Register>
-    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
-    </Register>
-    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
-      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
-      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
-      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
-      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
-      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
-      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
-      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
-      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
-      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
-      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
-      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
-    </Register>
-    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
-      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
-    </Register>
-    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
-    </Register>
-    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
-      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
-      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
-      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
-      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
-    </Register>
-    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
-    </Register>
-    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
-      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
-      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
-      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
-    </Register>
-    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
-        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
-        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
-        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode.">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
-        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
-        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy.">
-        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
-        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
-        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
-        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
-        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
-      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
-      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
-      </BitField>
-      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
-      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
-      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
-        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
-        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
-      </BitField>
-      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
-      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
-      </BitField>
-      <BitField start="8" size="1" name="ID" description="USB ID">
-        <Enum name="A_DEVICE" start="0" description="A-device" />
-        <Enum name="B_DEVICE" start="1" description="B-device" />
-      </BitField>
-      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
-      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
-      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
-      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
-      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
-      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
-      <BitField start="15" size="1" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
-      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
-      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
-      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
-      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
-      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
-      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
-      <BitField start="23" size="1" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="reserved" />
-      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
-      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
-      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
-      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
-      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
-        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
-        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
-      </BitField>
-      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
-        <Enum name="READ" start="0" description="Read" />
-        <Enum name="WRITE" start="1" description="Write" />
-      </BitField>
-      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
-      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
-    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
-      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
-      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
-    </Register>
-    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="WriteOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSTATSET" access="WriteOnly" description="EEPROM interrupt status set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_ST" description="Set program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
-    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
-      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
-      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
-      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
-      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
-      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
-      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
-      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
-      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
-      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
-      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
-      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
-      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
-      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
-      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
-      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
-      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
-      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
-      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
-      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
-    </Register>
-    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
-      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
-      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M3_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M3_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
-      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
-      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
-      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
-      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
-      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
-      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
-    </Register>
-    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
-      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
-      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
-      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
-      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
-      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
-      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
-      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
-      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
-    </Register>
-    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
-      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
-      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
-      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
-      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
-      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
-    </Register>
-    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="MO" description="Always 1" />
-    </Register>
-    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-    </Register>
-    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
-      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
-      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
-      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
-      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
-      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
-      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
-      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
-      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
-      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
-      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
-      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
-      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
-      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
-      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
-    </Register>
-    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
-    </Register>
-    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
-      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
-    </Register>
-    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
-    </Register>
-    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
-      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
-    </Register>
-    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
-    </Register>
-    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
-    </Register>
-    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
-      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
-      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
-      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
-      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
-      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
-      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
-      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
-      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
-      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
-      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
-      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
-      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
-      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
-    </Register>
-    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
-    </Register>
-    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
-      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
-      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
-      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
-      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
-      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
-      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
-      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
-      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
-      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
-      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
-      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
-      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
-      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
-      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
-      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
-      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
-      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
-      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
-      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
-      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
-      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
-      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
-      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
-      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
-      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
-      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
-      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
-      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
-      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
-      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
-      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
-      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
-      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
-      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
-      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
-    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
-    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
-    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M3 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
-    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
-        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
-        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
-        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
-        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
-        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
-        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
-      </BitField>
-      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
-        <Enum name="POWERED" start="0" description="Powered." />
-        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
-        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
-        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
-      </BitField>
-      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
-        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
-        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INACTIVE" start="0x3" description="Inactive." />
-      </BitField>
-      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the  data sheet for the trip values.">
-        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
-        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
-        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
-        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
-      </BitField>
-      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the  data sheet for the trip values.">
-        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
-        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
-        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
-        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
-      </BitField>
-      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
-        <Enum name="RESERVED" start="0x0" description="Reserved" />
-        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
-      </BitField>
-      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="M3MEMMAP" access="Read/Write" description="ARM Cortex-M3 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M3MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="M3TAPSEL" description="JTAG debug disable for M3 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
-        <Enum name="SPIFI" start="0x0" description="SPIFI" />
-        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
-      </BitField>
-      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
-        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
-        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
-        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
-        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
-      </BitField>
-      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
-        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
-        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
-        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
-        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
-        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
-        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
-        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
-        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
-      </BitField>
-      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
-        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
-        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
-        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
-        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-      </BitField>
-      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
-        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
-        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-      </BitField>
-      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
-        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
-        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-      </BitField>
-      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
-        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
-        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-      </BitField>
-      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
-        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
-        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-      </BitField>
-      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
-        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
-        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
-      </BitField>
-      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
-        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
-        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
-      </BitField>
-      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
-        <Enum name="ADC0" start="0x0" description="ADC0" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
-      </BitField>
-      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
-        <Enum name="ADC1" start="0x0" description="ADC1" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
-      </BitField>
-      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
-        <Enum name="DAC" start="0x0" description="DAC" />
-        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
-        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
-        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
-        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
-        <Enum name="MII" start="0x0" description="MII" />
-        <Enum name="RMII" start="0x4" description="RMII" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
-        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
-        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
-      </BitField>
-      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
-        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
-        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5284 E02B or 0x6284 E02B = LPC1850/30/20/10&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;(flashless parts)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;0x4284 E02B = LPC1857/53 (parts with on-chip flash)" />
-    </Register>
-    <Register start="+0x500" size="4" name="USB0FLADJ" access="None" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
-    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
-      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
-      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
-      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
-      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
-      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
-      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
-      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
-      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
-      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
-      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
-      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
-      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
-      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
-      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
-      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
-      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
-      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
-    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
-        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
-        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
-        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
-        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
-        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
-        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
-        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
-        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
-        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
-        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
-        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
-    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
-      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
-      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
-        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
-        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
-      </BitField>
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
-        <Enum name="IRC" start="0x01" description="IRC" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="RESERVED" start="0x0B" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="ENABLE" start="0" description="Enable" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
-        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
-      </BitField>
-      <BitField start="2" size="1" name="HF" description="Select frequency range">
-        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
-      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
-      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
-      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
-        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
-        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
-      </BitField>
-      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
-        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
-      </BitField>
-      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL1 power down">
-        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
-        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
-        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
-      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
-        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
-        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="PEQ2" start="0x1" description="2 (default)" />
-        <Enum name="PEQ4" start="0x2" description="4" />
-        <Enum name="8" start="0x3" description="8" />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="NEQ2" start="0x1" description="2" />
-        <Enum name="NEQ3" start="0x2" description="3 (default)" />
-        <Enum name="4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="RESERVED" start="0x09" description="Reserved" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
-        <Enum name="DIV1" start="0x0" description="1 (default)" />
-        <Enum name="DIV2" start="0x1" description="2" />
-        <Enum name="DIV3" start="0x2" description="3" />
-        <Enum name="DIV4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="BASE_M3_CLK" access="Read/Write" description="Output stage BASE_M3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_M3_BUS_CFG" access="Read/Write" description="CLK_M3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0408" size="4" name="CLK_M3_SPIFI_CFG" access="Read/Write" description="CLK_M3_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0410" size="4" name="CLK_M3_GPIO_CFG" access="Read/Write" description="CLK_M3_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0418" size="4" name="CLK_M3_LCD_CFG" access="Read/Write" description="CLK_M3_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0420" size="4" name="CLK_M3_ETHERNET_CFG" access="Read/Write" description="CLK_M3_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0428" size="4" name="CLK_M3_USB0_CFG" access="Read/Write" description="CLK_M3_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0430" size="4" name="CLK_M3_EMC_CFG" access="Read/Write" description="CLK_M3_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0438" size="4" name="CLK_M3_SDIO_CFG" access="Read/Write" description="CLK_M3_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0440" size="4" name="CLK_M3_DMA_CFG" access="Read/Write" description="CLK_M3_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0448" size="4" name="CLK_M3_M3CORE_CFG" access="Read/Write" description="CLK_M3_M3CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0468" size="4" name="CLK_M3_SCT_CFG" access="Read/Write" description="CLK_M3_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0470" size="4" name="CLK_M3_USB1_CFG" access="Read/Write" description="CLK_M3_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0478" size="4" name="CLK_M3_EMCDIV_CFG" access="Read/Write" description="CLK_M3_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0480" size="4" name="CLK_M3_FLASHA_CFG" access="Read/Write" description="CLK_M3_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0488" size="4" name="CLK_M3_FLASHB_CFG" access="Read/Write" description="CLK_M3_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A0" size="4" name="CLK_M3_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_M3_WWDT_CFG" access="Read/Write" description="CLK_M3_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0508" size="4" name="CLK_M3_USART0_CFG" access="Read/Write" description="CLK_M3_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0510" size="4" name="CLK_M3_UART1_CFG" access="Read/Write" description="CLK_M3_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0518" size="4" name="CLK_M3_SSP0_CFG" access="Read/Write" description="CLK_M3_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0520" size="4" name="CLK_M3_TIMER0_CFG" access="Read/Write" description="CLK_M3_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0528" size="4" name="CLK_M3_TIMER1_CFG" access="Read/Write" description="CLK_M3_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0530" size="4" name="CLK_M3_SCU_CFG" access="Read/Write" description="CLK_M3_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0538" size="4" name="CLK_M3_CREG_CFG" access="Read/Write" description="CLK_M3_CREG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_M3_RITIMER_CFG" access="Read/Write" description="CLK_M3_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0608" size="4" name="CLK_M3_USART2_CFG" access="Read/Write" description="CLK_M3_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0610" size="4" name="CLK_M3_USART3_CFG" access="Read/Write" description="CLK_M3_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0618" size="4" name="CLK_M3_TIMER2_CFG" access="Read/Write" description="CLK_M3_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0620" size="4" name="CLK_M3_TIMER3_CFG" access="Read/Write" description="CLK_M3_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0628" size="4" name="CLK_M3_SSP1_CFG" access="Read/Write" description="CLK_M3_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0630" size="4" name="CLK_M3_QEI_CFG" access="Read/Write" description="CLK_M3_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x404" size="4" name="CLK_M3_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040C" size="4" name="CLK_M3_SPIFI_STAT" access="ReadOnly" description="CLK_M3_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0414" size="4" name="CLK_M3_GPIO_STAT" access="ReadOnly" description="CLK_M3_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x041C" size="4" name="CLK_M3_LCD_STAT" access="ReadOnly" description="CLK_M3_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0424" size="4" name="CLK_M3_ETHERNET_STAT" access="ReadOnly" description="CLK_M3_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x042C" size="4" name="CLK_M3_USB0_STAT" access="ReadOnly" description="CLK_M3_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0434" size="4" name="CLK_M3_EMC_STAT" access="ReadOnly" description="CLK_M3_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x043C" size="4" name="CLK_M3_SDIO_STAT" access="ReadOnly" description="CLK_M3_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0444" size="4" name="CLK_M3_DMA_STAT" access="ReadOnly" description="CLK_M3_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044C" size="4" name="CLK_M3_M3CORE_STAT" access="ReadOnly" description="CLK_M3_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x046C" size="4" name="CLK_M3_SCT_STAT" access="ReadOnly" description="CLK_M3_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0474" size="4" name="CLK_M3_USB1_STAT" access="ReadOnly" description="CLK_M3_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x047C" size="4" name="CLK_M3_EMCDIV_STAT" access="ReadOnly" description="CLK_M3_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0484" size="4" name="CLK_M3_FLASHA_STAT" access="ReadOnly" description="CLK_M3_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048C" size="4" name="CLK_M3_FLASHB_STAT" access="ReadOnly" description="CLK_M3_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A4" size="4" name="CLK_M3_EEPROM_STAT" access="ReadOnly" description="CLK_M3_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504" size="4" name="CLK_M3_WWDT_STAT" access="ReadOnly" description="CLK_M3_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050C" size="4" name="CLK_M3_USART0_STAT" access="ReadOnly" description="CLK_M3_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0514" size="4" name="CLK_M3_UART1_STAT" access="ReadOnly" description="CLK_M3_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x051C" size="4" name="CLK_M3_SSP0_STAT" access="ReadOnly" description="CLK_M3_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0524" size="4" name="CLK_M3_TIMER0_STAT" access="ReadOnly" description="CLK_M3_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x052C" size="4" name="CLK_M3_TIMER1_STAT" access="ReadOnly" description="CLK_M3_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0534" size="4" name="CLK_M3_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x053C" size="4" name="CLK_M3_CREG_STAT" access="ReadOnly" description="CLK_M3_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x604" size="4" name="CLK_M3_RITIMER_STAT" access="ReadOnly" description="CLK_M3_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060C" size="4" name="CLK_M3_USART2_STAT" access="ReadOnly" description="CLK_M3_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0614" size="4" name="CLK_M3_USART3_STAT" access="ReadOnly" description="CLK_M3_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x061C" size="4" name="CLK_M3_TIMER2_STAT" access="ReadOnly" description="CLK_M3_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0624" size="4" name="CLK_M3_TIMER3_STAT" access="ReadOnly" description="CLK_M3_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x062C" size="4" name="CLK_M3_SSP1_STAT" access="ReadOnly" description="CLK_M3_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0634" size="4" name="CLK_M3_QEI_STAT" access="ReadOnly" description="CLK_M3_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
-    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
-      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="13" size="1" name="M3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="M3_RST" description="Status of the M3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-    </Register>
-    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="M3_RST" description="Current status of the M3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="25" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
-        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
-        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
-        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
-        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
-        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
-        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
-    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
-        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
-        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
-      </BitField>
-      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
-        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
-        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
-      </BitField>
-      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
-        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
-        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
-        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
-        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
-      </BitField>
-      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
-        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
-        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
-      </BitField>
-      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
-      </BitField>
-    </Register>
-    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
-      </BitField>
-      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
-      </BitField>
-      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DAC" description="Select DAC">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
-        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
-      </BitField>
-      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
-      <BitField start="20" size="12" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
-      <BitField start="1" size="31" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
-    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
-        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
-        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
-        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
-        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
-        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
-        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
-        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
-        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
-        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
-        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
-        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
-        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
-        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
-        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time">
-        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
-        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
-        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
-        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
-        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
-        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
-        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
-        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
-        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
-        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="DAC" start="4" size="4" />
-      <BitField name="DMA" start="20" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="FLASH" start="4" size="4" />
-      <BitField name="ETHERNET" start="12" size="4" />
-      <BitField name="SDIO" start="20" size="4" />
-      <BitField name="LCD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="USB0" start="4" size="4" />
-      <BitField name="USB1" start="12" size="4" />
-      <BitField name="SCT" start="20" size="4" />
-      <BitField name="RITIMER" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TIMER0" start="4" size="4" />
-      <BitField name="TIMER1" start="12" size="4" />
-      <BitField name="TIMER2" start="20" size="4" />
-      <BitField name="TIMER3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="MCPWM" start="4" size="4" />
-      <BitField name="ADC0" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="ADC1" start="12" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USART0" start="4" size="4" />
-      <BitField name="UART1" start="12" size="4" />
-      <BitField name="USART2" start="20" size="4" />
-      <BitField name="USART3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="I2S0" start="4" size="4" />
-      <BitField name="I2S1" start="12" size="4" />
-      <BitField name="SPIFI" start="20" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PIN_INT0" start="4" size="4" />
-      <BitField name="PIN_INT1" start="12" size="4" />
-      <BitField name="PIN_INT2" start="20" size="4" />
-      <BitField name="PIN_INT3" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="PIN_INT4" start="4" size="4" />
-      <BitField name="PIN_INT5" start="12" size="4" />
-      <BitField name="PIN_INT6" start="20" size="4" />
-      <BitField name="PIN_INT7" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="GINT0" start="4" size="4" />
-      <BitField name="GINT1" start="12" size="4" />
-      <BitField name="EVENTROUTER" start="20" size="4" />
-      <BitField name="C_CAN1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="ATIMER" start="20" size="4" />
-      <BitField name="RTC" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
-      <BitField name="WWDT" start="12" size="4" />
-      <BitField name="C_CAN0" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
-      <BitField name="QEI" start="4" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s b/examples/host/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s
deleted file mode 100644
index 8f9a39e4..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s
+++ /dev/null
@@ -1,516 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak USB0_IRQHandler
-  .thumb_set USB0_IRQHandler,Dummy_Handler
-
-  .weak USB1_IRQHandler
-  .thumb_set USB1_IRQHandler,Dummy_Handler
-
-  .weak SCT_IRQHandler
-  .thumb_set SCT_IRQHandler,Dummy_Handler
-
-  .weak RITIMER_IRQHandler
-  .thumb_set RITIMER_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak ADC0_IRQHandler
-  .thumb_set ADC0_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak USART0_IRQHandler
-  .thumb_set USART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Dummy_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Dummy_Handler
-
-  .weak I2S0_IRQHandler
-  .thumb_set I2S0_IRQHandler,Dummy_Handler
-
-  .weak I2S1_IRQHandler
-  .thumb_set I2S1_IRQHandler,Dummy_Handler
-
-  .weak SPIFI_IRQHandler
-  .thumb_set SPIFI_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak EVENTROUTER_IRQHandler
-  .thumb_set EVENTROUTER_IRQHandler,Dummy_Handler
-
-  .weak C_CAN1_IRQHandler
-  .thumb_set C_CAN1_IRQHandler,Dummy_Handler
-
-  .weak ATIMER_IRQHandler
-  .thumb_set ATIMER_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak C_CAN0_IRQHandler
-  .thumb_set C_CAN0_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak DAC_IRQHandler
-DAC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDIO_IRQHandler
-SDIO_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB0_IRQHandler
-USB0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB1_IRQHandler
-USB1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SCT_IRQHandler
-SCT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RITIMER_IRQHandler
-RITIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC0_IRQHandler
-ADC0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC1_IRQHandler
-ADC1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART0_IRQHandler
-USART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_IRQHandler
-USART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART3_IRQHandler
-USART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S0_IRQHandler
-I2S0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S1_IRQHandler
-I2S1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPIFI_IRQHandler
-SPIFI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EVENTROUTER_IRQHandler
-EVENTROUTER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN1_IRQHandler
-C_CAN1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ATIMER_IRQHandler
-ATIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN0_IRQHandler
-C_CAN0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word DAC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word DMA_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word FLASH_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDIO_IRQHandler
-  .word LCD_IRQHandler
-  .word USB0_IRQHandler
-  .word USB1_IRQHandler
-  .word SCT_IRQHandler
-  .word RITIMER_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word MCPWM_IRQHandler
-  .word ADC0_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word ADC1_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word USART0_IRQHandler
-  .word UART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word I2S0_IRQHandler
-  .word I2S1_IRQHandler
-  .word SPIFI_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word EVENTROUTER_IRQHandler
-  .word C_CAN1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word Dummy_Handler /* Reserved */
-  .word ATIMER_IRQHandler
-  .word RTC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word WWDT_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word C_CAN0_IRQHandler
-  .word QEI_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/flash_placement.xml b/examples/host/cdc_msc_hid/ses/lpc18xx/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject b/examples/host/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject
deleted file mode 100644
index 271076b5..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject
+++ /dev/null
@@ -1,139 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc18xx" target="8" version="2">
-  <project Name="lpc18xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC1857"
-      arm_architecture="v7M"
-      arm_core_type="Cortex-M3"
-      arm_endian="Little"
-      arm_fpu_type="None"
-      arm_interwork="No"
-      arm_linker_heap_size="256"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00008000;ROM;0x1A000000;0x00080000;ROM;0x1B000000;0x00080000;RAM;0x20000000;0x00010000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC1857"
-      arm_target_interface_type="SWD"
-      c_preprocessor_definitions="LPC18xx;__LPC1800_FAMILY;__LPC185x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_MCB1800;CFG_TUSB_MCU=OPT_MCU_LPC18XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)));CFG_TUSB_DEBUG=2"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)//inc;$(lpcDir)//inc/config_18xx;$(rootDir)/lib/SEGGER_RTT/RTT"
-      debug_register_definition_file="$(ProjectDir)/LPC18xx_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml"
-      linker_printf_width_precision_supported="Yes"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx"
-      package_dependencies="LPC1800"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC1800_Startup.s" />
-      <file file_name="LPC18xx_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="LPC1857_MemoryMap.xml" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC1800_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-    </folder>
-    <configuration
-      Name="Debug"
-      link_use_linker_script_file="No"
-      linker_section_placement_file="flash_placement.xml" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="mcb1800">
-          <file file_name="../../../../../hw/bsp/mcb1800/mcb1800.c" />
-        </folder>
-        <file file_name="../../../../../hw/bsp/board.c" />
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_chip_18xx">
-            <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/arm_common_tables.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/arm_math.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cguccu_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip_clocks.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip_lpc18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/chip_lpc43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/clock_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_43xx_m0app.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/cmsis_43xx_m0sub.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm0.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm0plus.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm3.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm4.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cm4_simd.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_sc000.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/core_sc300.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/creg_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/gpio_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/lpc_types.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/uart_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/usbhs_18xx_43xx.h" />
-              <folder Name="config_18xx">
-                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/config_18xx/cmsis_18xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/inc/config_18xx/sys_config.h" />
-              </folder>
-            </folder>
-            <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/chip_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/clock_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/gpio_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/sysinit_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx/src/uart_18xx_43xx.c" />
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="lib">
-      <folder Name="SEGGER_RTT">
-        <folder Name="RTT">
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.c" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c" />
-        </folder>
-        <folder Name="Syscalls">
-          <file file_name="../../../../../lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c" />
-        </folder>
-      </folder>
-    </folder>
-    <configuration
-      Name="MCB1800"
-      arm_target_interface_type="JTAG"
-      speed="12000" />
-  </project>
-  <configuration
-    Name="MCB1800"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/host/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s b/examples/host/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s b/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s
deleted file mode 100644
index 03bf54de..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s
+++ /dev/null
@@ -1,128 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  bic r0, #0x7
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-  .pushsection .init_array, "aw", %init_array
-  .word SystemCoreClockUpdate
-  .popsection
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js b/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml b/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
deleted file mode 100644
index 9b8f2d9b..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC4088FBD208">
-  <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM" start="0x10000000" size="0x00010000" access="Read/Write" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00008000" access="Read/Write" />
-</root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml b/examples/host/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml
deleted file mode 100644
index 4a4c0817..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml
+++ /dev/null
@@ -1,18992 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC408x_7x" description="LPC408x/7x M4">
-  <RegisterGroup name="FLASHCTRL" start="0x00200000" description="EEPROM/flash">
-    <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." />
-      <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation.">
-        <Enum name="STOP" start="0" description="Signature generation is stopped" />
-        <Enum name="START" start="1" description="Initiate signature generation" />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="128-bit signature Word 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." />
-    </Register>
-    <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="128-bit signature Word 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." />
-    </Register>
-    <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="128-bit signature Word 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." />
-    </Register>
-    <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="128-bit signature Word 3" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." />
-    </Register>
-    <Register start="+0x080" size="4" name="EECMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved" />
-      <BitField start="3" size="1" name="RDPREFETCH" description="Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x084" size="4" name="EEADDR" access="Read/Write" description="EEPROM address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="ADDR" description="EEPROM Address.  Lower 6 bits are don't care." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x088" size="4" name="EEWDATA" access="WriteOnly" description="EEPROM write data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="WDATA" description="Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data." />
-    </Register>
-    <Register start="+0x08C" size="4" name="EERDATA" access="ReadOnly" description="EEPROM read data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="RDATA" description="Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data." />
-    </Register>
-    <Register start="+0x090" size="4" name="EEWSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x094" size="4" name="EECLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x098" size="4" name="EEPWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down)." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." />
-      <BitField start="3" size="23" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="1" name="END_OF_RDWR" description="EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="28" size="1" name="END_OF_PROG1" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="26" size="1" name="EE_RW_DONE" description="EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="28" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="STATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." />
-      <BitField start="3" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="26" size="1" name="RDWR_CLR_ST" description="Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="28" size="1" name="PROG1_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="ENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="26" size="1" name="RDWR_CLR_EN" description="Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="28" size="1" name="PROG1_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="ENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="26" size="1" name="RDWR_SET_EN" description="Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="28" size="1" name="PROG1_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x20080000" description="General Purpose DMA controller Modification">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
-      <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
-      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
-      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
-      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
-      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
-      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
-      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
-    </Register>
-    <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
-      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x20084000" description="Ethernet">
-    <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
-      <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
-      <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
-      <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
-      <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
-      <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
-      <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
-      <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
-      <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
-      <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
-      <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
-      <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
-      <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
-      <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
-      <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
-      <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
-      <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
-      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
-      <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
-      <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Unused" />
-      <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
-      <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
-      <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
-      <BitField start="3" size="29" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
-      <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
-      <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
-      <BitField start="6" size="9" name="RESERVED" description="Unused" />
-      <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
-      <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
-      <BitField start="5" size="3" name="RESERVED" description="Unused" />
-      <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
-      <BitField start="13" size="19" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
-      <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
-      <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
-      <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
-      <BitField start="4" size="28" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
-      <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
-      <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
-      <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
-      <BitField start="2" size="1" name="RESERVED" description="Unused" />
-      <BitField start="3" size="1" name="REGRESET" description="When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
-      <BitField start="4" size="1" name="TXRESET" description="When a  1  is written, the transmit datapath is reset." />
-      <BitField start="5" size="1" name="RXRESET" description="When a  1  is written, the receive datapath is reset." />
-      <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
-      <BitField start="7" size="1" name="PASSRXFILTER" description="When set to  1 , disables receive filtering i.e. all frames received are written to memory." />
-      <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
-      <BitField start="9" size="1" name="RMII" description="When set to  1 , RMII mode is selected; if 0, MII mode is selected." />
-      <BitField start="10" size="1" name="FULLDUPLEX" description="When set to  1 , indicates full duplex operation." />
-      <BitField start="11" size="21" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
-      <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
-      <BitField start="2" size="30" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
-    </Register>
-    <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
-      <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
-    </Register>
-    <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
-    </Register>
-    <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
-      <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
-    </Register>
-    <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
-      <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
-      <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
-      <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
-      <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
-      <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
-      <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
-      <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
-      <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
-      <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
-      <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
-      <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
-      <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
-      <BitField start="20" size="12" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
-      <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
-      <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
-      <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
-      <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
-      <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
-      <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
-      <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
-      <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
-      <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
-      <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
-      <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
-      <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
-      <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
-      <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
-      <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
-      <BitField start="31" size="1" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
-      <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
-    </Register>
-    <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
-      <BitField start="16" size="16" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
-      <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
-      <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
-      <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
-      <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
-      <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
-      <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
-      <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
-      <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
-      <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
-      <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
-      <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="6" size="1" name="RESERVED" description="Unused" />
-      <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
-      <BitField start="9" size="23" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
-      <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
-      <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
-      <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
-      <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
-      <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
-      <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
-      <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
-      <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
-      <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
-      <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="8" size="4" name="RESERVED" description="Unused" />
-      <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
-      <BitField start="14" size="18" name="RESERVED" description="Unused" />
-    </Register>
-    <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="RESERVED" description="Unused" />
-      <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x20088000" description="LCD controller Modification ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the input clock, LCD_DCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCD_DCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal. 0 = LCD_FP pin is active HIGH and inactive LOW. 1 = LCD_FP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal. 0 = LCD_LP pin is active HIGH and inactive LOW. 1 = LCD_LP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state. 0 = LCD_ENAB_M output pin is active HIGH in TFT mode. 1 = LCD_ENAB_M output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the LCD_TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are low. 1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel. Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the LCD_CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the LCD_INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the VCompIM bit in the LCD_INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the LCD_INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRON" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRSIZE" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB" start="0x2008C000" description=" USB device controller ">
-    <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR" description="Timer time-out." />
-      <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
-      <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
-      <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="INCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="PORTSEL" access="Read/Write" description="USB Port Select. The USBPortSel register is identical to the OTGStCtrl register (see Section 15.8.6). In device-only operations only bits 0 and 1 of this register are used to control the routing of USB pins to Port 1 or Port 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="PORTSEL" description="Selects which USB port the device controller signals are mapped to. Other values are reserved.">
-        <Enum name="PORTU1" start="0x0" description="The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1." />
-        <Enum name="PORTU2" start="0x3" description="The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
-      </BitField>
-      <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
-      <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
-      <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
-      <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
-      <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
-      <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
-      <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
-      <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
-      <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
-      <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
-      <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
-        <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
-        <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
-        <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-      <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
-    </Register>
-    <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-      <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
-    </Register>
-    <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-      <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
-    </Register>
-    <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-      <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
-    </Register>
-    <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-      <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
-    </Register>
-    <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-      <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
-    </Register>
-    <Register start="+0x248" size="4" name="EPIN" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RX_DATA" description="Data received." />
-    </Register>
-    <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
-        <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
-        <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
-      </BitField>
-      <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
-    </Register>
-    <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
-        <Enum name="READ" start="0x02" description="Read" />
-        <Enum name="WRITE" start="0x01" description="Write" />
-        <Enum name="COMMAND" start="0x05" description="Command" />
-      </BitField>
-      <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 &lt;=  xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-      <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
-    </Register>
-    <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
-      <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
-      <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-      <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
-    </Register>
-    <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
-      <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
-    </Register>
-    <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-      <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
-    </Register>
-    <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
-      <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
-      <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
-      <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-      <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
-    </Register>
-    <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
-        <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
-        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-      <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
-    </Register>
-    <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-      <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
-    </Register>
-    <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-      <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
-    </Register>
-    <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-      <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RX_DATA" description="Receive data." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x300" size="4" name="I2C_TX" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="TXDATA" description="Transmit data." />
-      <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
-      <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
-        <Enum name="TRANSACTION_HAS_NOT_" start="0" description="Transaction has not completed." />
-        <Enum name="TRANSACTION_COMPLETE" start="1" description="Transaction completed." />
-      </BitField>
-      <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
-        <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
-        <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
-      </BitField>
-      <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="LAST_TRANSMISSION_RE" start="0" description="Last transmission received an acknowledge." />
-        <Enum name="LAST_TRANSMISSION_DI" start="1" description="Last transmission did not receive an acknowledge." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
-        <Enum name="MASTER_TRANSMITTER_D" start="0" description="Master transmitter does not need data." />
-        <Enum name="MASTER_TRANSMITTER_N" start="1" description="Master transmitter needs data." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
-        <Enum name="SLAVE_TRANSMITTER_DO" start="0" description="Slave transmitter does not need data." />
-        <Enum name="SLAVE_TRANSMITTER_NE" start="1" description="Slave transmitter needs data." />
-      </BitField>
-      <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
-      <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
-      <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
-      <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
-        <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
-        <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
-      </BitField>
-      <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
-        <Enum name="RX_FIFO_CONTAINS_DAT" start="0" description="RX FIFO contains data." />
-        <Enum name="RX_FIFO_IS_EMPTY" start="1" description="RX FIFO is empty" />
-      </BitField>
-      <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
-        <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
-        <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
-      </BitField>
-      <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
-        <Enum name="TX_FIFO_CONTAINS_VAL" start="0" description="TX FIFO contains valid data." />
-        <Enum name="TX_FIFO_IS_EMPTY" start="1" description="TX FIFO is empty" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
-        <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
-        <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
-        <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
-        <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
-      </BitField>
-      <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
-        <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
-        <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
-      </BitField>
-      <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
-        <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
-        <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
-        <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
-        <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
-        <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
-        <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
-      </BitField>
-      <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
-        <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
-        <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
-      </BitField>
-      <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
-        <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
-        <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
-      </BitField>
-      <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
-        <Enum name="SEE_THE_TEXT_" start="0" description="See the text." />
-        <Enum name="RESET_THE_I2C_TO_IDL" start="1" description="Reset the I2C to idle state. Self clearing." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF4" size="4" name="CLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
-        <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
-        <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
-        <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
-        <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
-        <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
-        <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
-        <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
-        <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
-        <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
-        <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFF8" size="4" name="OTGClkSt" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
-        <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
-        <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
-        <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
-        <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
-      </BitField>
-      <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
-        <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
-        <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
-      </BitField>
-      <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
-        <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
-        <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
-      </BitField>
-      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
-        <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
-        <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CRC" start="0x20090000" description="CRC engine ">
-    <Register start="+0x000" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CRC_POLY" description="Select CRC polynomial">
-        <Enum name="CRC_CCITT_POLYNOMIAL" start="0x0" description="CRC-CCITT polynomial" />
-        <Enum name="CRC_16_POLYNOMIAL" start="0x1" description="CRC-16 polynomial" />
-        <Enum name="CRC_32_POLYNOMIAL" start="0x2" description="CRC-32 polynomial" />
-      </BitField>
-      <BitField start="2" size="1" name="BIT_RVS_WR" description="Select bit order for CRC_WR_DATA">
-        <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_WR_DATA (per byte)" />
-        <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_WR_DATA (per byte)" />
-      </BitField>
-      <BitField start="3" size="1" name="CMPL_WR" description="Select one's complement for CRC_WR_DATA">
-        <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_WR_DATA" />
-        <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_WR_DATA" />
-      </BitField>
-      <BitField start="4" size="1" name="BIT_RVS_SUM" description="Select bit order revers for CRC_SUM">
-        <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_SUM" />
-        <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_SUM" />
-      </BitField>
-      <BitField start="5" size="1" name="CMPL_SUM" description="Select one's complement for CRC_SUM">
-        <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_SUM" />
-        <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_SUM" />
-      </BitField>
-      <BitField start="6" size="26" name="Reserved" description="Always 0 when read" />
-    </Register>
-    <Register start="+0x004" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." />
-    </Register>
-    <Register start="+0x008" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." />
-    </Register>
-    <Register start="+0x008" size="4" name="DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO" start="0x20098000" description="GPIO">
-    <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="DIR5" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x010+160" size="4" name="MASK5" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x014+160" size="4" name="PIN5" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x018+160" size="4" name="SET5" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
-    </Register>
-    <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-    <Register start="+0x01C+160" size="4" name="CLR5" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x2009C000" description="External Memory Controller (EMC)">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled:">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled&#xa;(POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map:">
-        <Enum name="NORMAL" start="0" description="Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset memory map. Static memory EMC_CS1 is&#xa;mirrored onto EMC_CS0 and EMC_DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode:">
-        <Enum name="WARMRESET" start="0" description="Normal mode (warm&#xa;reset value)." />
-        <Enum name="LOWPOWER" start="1" description="Low-power&#xa;mode. Entering low-power mode reduces memory controller power consumption.&#xa;Dynamic memory is refreshed as necessary. The memory controller&#xa;returns to normal functional mode by clearing the low-power mode&#xa;bit (L), or by POR. This bit must only be modified when the EMC&#xa;is in idle state.[1]" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not.">
-        <Enum name="IDLE" start="0" description="EMC&#xa;is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="EMC&#xa;is busy performing memory transactions, commands, auto-refresh cycles,&#xa;or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status.This bit enables the EMC to enter low-power mode or disabled mode cleanly.">
-        <Enum name="EMPTY" start="0" description="Write buffers&#xa;empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Write&#xa;buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC.">
-        <Enum name="NORMAL" start="0" description="Normal mode" />
-        <Enum name="SELFREFRESH" start="1" description="Self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes.">
-        <Enum name="LITTLEENDIAN" start="0" description="Little-endian&#xa;mode (POR reset value)." />
-        <Enum name="BIGENDIAN" start="1" description="Big-endian&#xa;mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CLKR" description="CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC.">
-        <Enum name="PORRESET" start="0" description="1:1(POR reset value)" />
-        <Enum name="DONOTUSE" start="1" description="1:2 (this option is not available on the LPC178x/177x)" />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="POWERSAVE" start="0" description="Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="HIGH" start="1" description="All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE_" start="0" description="Normal mode." />
-        <Enum name="ENTER_SELF_REFRESH_M" start="1" description="Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="CLKOUT_ENABLED_POR_" start="0" description="CLKOUT enabled (POR reset value)." />
-        <Enum name="CLKOUT_DISABLED" start="1" description="CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures dynamic memory read strategy." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy">
-        <Enum name="CLOCK_OUT_DELAYED_ST" start="0x0" description="Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value." />
-        <Enum name="COMMAND_DELAYED_STRA" start="0x1" description="Command delayed strategy, using EMCCLKDELAY (command delayed, clock out not delayed)." />
-        <Enum name="COMMAND_DELAYED_STRA" start="0x2" description="Command delayed strategy plus one clock cycle, using EMCCLKDELAY (command delayed, clock out not delayed)." />
-        <Enum name="COMMAND_DELAYED_STRA" start="0x3" description="Command delayed strategy plus two clock cycles, using EMCCLKDELAY (command delayed, clock out not delayed)." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Precharge command period." reset_value="0x0F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Time for exit self-refresh to active command." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Latency for active bank A to active bank B." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Time for load mode register to active command." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Time for long static memory read and write transfers." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
-        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
-        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT_" start="0x1" description="16 bit." />
-        <Enum name="32_BIT_" start="0x2" description="32 bit." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
-        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
-        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
-        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
-        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
-        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
-        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
-        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect">
-        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
-        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40000000" description=" Windowed Watchdog Timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="STOP" start="0" description="The watchdog timer is stopped." />
-        <Enum name="RUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
-        <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
-        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section  WDTOF." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section  WDINT." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only. See Section  WDPROTECT.">
-        <Enum name="CHANGE" start="0" description="The watchdog reload value (WDTC) can be changed at any time." />
-        <Enum name="CHANGE_W_CNT" start="1" description="The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Watchdog time-out interval." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40004000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40008000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40010000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
-        <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
-        <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="3   - THRE Interrupt." />
-        <Enum name="MODEM" start="0x0" description="4   - Modem Interrupt." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
-        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
-        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
-        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="VALID" start="0" description="THR contains valid data." />
-        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
-        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
-        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM0" start="0x40014000" description="Pulse Width Modulators (PWM0/1)">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM0/1)">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
-      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
-      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
-      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
-      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
-      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
-      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
-      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Counter Enable">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
-        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CR" description="Counter Reset">
-        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
-        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
-        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
-        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
-      </BitField>
-      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
-        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
-        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
-      </BitField>
-      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
-      </BitField>
-      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
-      </BitField>
-      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
-      </BitField>
-      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
-      </BitField>
-      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
-        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
-        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
-        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
-        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
-        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
-      </BitField>
-      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
-    </Register>
-    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
-      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
-      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
-      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
-      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
-      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
-      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
-        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
-        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
-        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
-        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="COMPARATOR" start="0x40020000" description="Comparators">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Comparator block control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMP_PD_IREF" description="Controls the current source used by the comparators. These bits must be set when either comparator is used.">
-        <Enum name="DISABLED" start="0x0" description="The comparator current source is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator current source is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The comparator current source is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The comparator current source is powered up." />
-      </BitField>
-      <BitField start="2" size="2" name="CMP_PD_VBG" description="Controls the bandgap reference source that is used by the comparators. These bits must be set when either comparator is used.">
-        <Enum name="DISABLED" start="0x0" description="The comparator bandgap reference is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator bandgap reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The comparator bandgap reference is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The comparator bandgap reference is powered up." />
-      </BitField>
-      <BitField start="4" size="2" name="CMP_VTEMP" description="Controls the voltage reference of the temperature sensor. These bits must be set when the temperature sensor is used.">
-        <Enum name="DISABLED" start="0x0" description="The temperature sensor voltage reference is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor voltage reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor voltage reference is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The temperature sensor voltage reference is powered up." />
-      </BitField>
-      <BitField start="6" size="2" name="CMP_TEMPSEN" description="Enables the temperature sensor. These bits must be set when the temperature sensor is used.">
-        <Enum name="DISABLED" start="0x0" description="Temperature sensor is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor is disabled in Power-down mode and restored automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="Temperature sensor is enabled." />
-      </BitField>
-      <BitField start="8" size="1" name="CMP_ROSCCTL" description="Selects the inputs for the flip/flops that provide the CMP_ROSC output.">
-        <Enum name="CMP1" start="0" description="The CMP_ROSC output is set by CMP1 and reset by CMP0." />
-        <Enum name="CMP0" start="1" description="The CMP_ROSC output is set by CMP0 and reset by CMP1." />
-      </BitField>
-      <BitField start="9" size="1" name="CMP_EXT_RESET" description="Selects the reset source for the CMP_ROSC output.">
-        <Enum name="INTRESET" start="0" description="The CMP_ROSC output is reset by the internal chip reset." />
-        <Enum name="CMP_RESETIN" start="1" description="The CMP_ROSC output is reset by the CMP_RESET input." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="CMP_T0CAP2" description="Selects the input for Timer 0 capture input 2.">
-        <Enum name="COMP0" start="0" description="T0CAP2 is connected to comparator 0 level output." />
-        <Enum name="COMP1" start="1" description="T0CAP2 is connected to comparator 1 level output." />
-      </BitField>
-      <BitField start="13" size="1" name="CMP_T0CAP3" description="Selects the input for Timer 0 capture input 3.">
-        <Enum name="COMP0" start="0" description="T0CAP3 is connected to comparator 0 edge output." />
-        <Enum name="COMP1" start="1" description="T0CAP3 is connected to comparator 1 edge output." />
-      </BitField>
-      <BitField start="14" size="1" name="CMP_T1CAP2" description="Selects the input for Timer 1 capture input 2.">
-        <Enum name="COMP1" start="0" description="T1CAP2 is connected to comparator 1 edge output." />
-        <Enum name="COMP0" start="1" description="T1CAP2 is connected to comparator 0 level output." />
-      </BitField>
-      <BitField start="15" size="1" name="CMP_T1CAP3" description="Selects the input for Timer 1 capture input 3.">
-        <Enum name="COMP1" start="0" description="T1CAP3 is connected to comparator 1 level output." />
-        <Enum name="COMP0" start="1" description="T1CAP3 is connected to comparator 0 edge output." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL0" access="Read/Write" description="Comparator 0 control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMP0_EN" description="Comparator 0 enable control.">
-        <Enum name="DISABLED" start="0x0" description="Comparator 0 disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 0 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 0 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="Comparator 0 is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CMP0_OE" description="Comparator 0 output enable.">
-        <Enum name="DISABLED" start="0" description="Comparator 0 output is disabled." />
-        <Enum name="ENABLED" start="1" description="Comparator 0 output is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CMP0_STAT" description="Comparator 0 status. This bit reflects the comparator 0 output, and is not affected by CMP0_OE." />
-      <BitField start="4" size="3" name="CMP0_VM" description="Comparator 0 VM input select.">
-        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
-        <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." />
-        <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." />
-        <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." />
-        <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." />
-        <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="3" name="CMP0_VP" description="Comparator 0 VP input select.">
-        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
-        <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." />
-        <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." />
-        <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." />
-        <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." />
-        <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="CMP0_SYNC" description="Comparator 0 output synchronization control.">
-        <Enum name="DIRECT" start="0" description="The comparator 0 output is used directly." />
-        <Enum name="SYNCH" start="1" description="The comparator 0 output is synchronized with the internal bus clock for output to other peripherals." />
-      </BitField>
-      <BitField start="13" size="2" name="CMP0_HYS" description="Comparator 0 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.">
-        <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." />
-        <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." />
-        <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." />
-        <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." />
-      </BitField>
-      <BitField start="15" size="1" name="CMP0_INTPOL" description="Selects the polarity of the CMP0 output for purposes of generating level interrupts. See Table 412.">
-        <Enum name="NOTINVERTED" start="0" description="The CMP0 output is used as-is for generating interrupts." />
-        <Enum name="INVERTED" start="1" description="The CMP0 output is used inverted for generating interrupts." />
-      </BitField>
-      <BitField start="16" size="1" name="CMP0_INTTYPE" description="Select comparator 0 interrupt type. See Table 412.">
-        <Enum name="EDGE" start="0" description="Comparator 0 interrupt is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Comparator 0 interrupt is level triggered." />
-      </BitField>
-      <BitField start="17" size="2" name="CMP0_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP0_IntType = 0. See Table 412.">
-        <Enum name="FALLING" start="0x0" description="Comparator 0 interrupt is active on falling edges." />
-        <Enum name="RISING" start="0x1" description="Comparator 0 interrupt is active on rising edges." />
-        <Enum name="DUALEDGE" start="0x2" description="Comparator 0 Interrupt is active on both edges." />
-      </BitField>
-      <BitField start="19" size="1" name="CMP0_INTFLAG" description="Comparator 0 interrupt flag.">
-        <Enum name="NOTPENDING" start="0" description="The Comparator 0 interrupt is not pending." />
-        <Enum name="PENDING" start="1" description="The Comparator 0 interrupt is pending. Writing a 1 to this bit clears the flag." />
-      </BitField>
-      <BitField start="20" size="2" name="CMP0_VLADEN" description="Voltage ladder enable for comparator 0.">
-        <Enum name="DISABLED" start="0x0" description="The Comparator 0 voltage ladder is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 0 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 0 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The Comparator 0 voltage ladder is enabled." />
-      </BitField>
-      <BitField start="22" size="1" name="CMP0_VLADREF" description="Voltage reference select for comparator 0 voltage ladder.">
-        <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." />
-        <Enum name="VDDA_PIN_" start="1" description="VDDA pin." />
-      </BitField>
-      <BitField start="23" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="5" name="CMP0_VSEL" description="Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of CMP0_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x  Vref0 / 31. 00010 = 2 x Vref0 / 31. ... 11111 = Vref0" />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL1" access="Read/Write" description="Comparator 1 control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CMP1_EN" description="Comparator 1 enable control.">
-        <Enum name="DISABLED" start="0x0" description="Comparator 1 disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 1 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 1 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="Comparator 1 is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CMP1_OE" description="Comparator 1 output enable.">
-        <Enum name="DISABLED" start="0" description="Comparator 1 output is disabled." />
-        <Enum name="ENABLED" start="1" description="Comparator 1 output is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CMP1_STAT" description="Comparator 1 status. This bit reflects the comparator 1 output, and is not affected by CMP1_OE." />
-      <BitField start="4" size="3" name="CMP1_VM" description="Comparator 1 VM input select.">
-        <Enum name="VREF_DIVIDER_1_" start="0x0" description="Vref divider 1." />
-        <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." />
-        <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." />
-        <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." />
-        <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." />
-        <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="3" name="CMP1_VP" description="Comparator 1 VP input select.">
-        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
-        <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." />
-        <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." />
-        <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." />
-        <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." />
-        <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." />
-        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
-        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
-      </BitField>
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="CMP1_SYNC" description="Comparator 1 output synchronization control.">
-        <Enum name="DIRECT" start="0" description="The comparator 1 output is used directly." />
-        <Enum name="SYNCH" start="1" description="The comparator 1 output is synchronized with the internal bus clock for output to other peripherals." />
-      </BitField>
-      <BitField start="13" size="2" name="CMP1_HYS" description="Comparator 1 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.">
-        <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." />
-        <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." />
-        <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." />
-        <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." />
-      </BitField>
-      <BitField start="15" size="1" name="CMP1_INTPOL" description="Selects the polarity of the CMP1 output for purposes of generating level interrupts. See Table 412.">
-        <Enum name="NOTINVERTED" start="0" description="The CMP1 output is used as-is for generating interrupts." />
-        <Enum name="INVERTED" start="1" description="The CMP1 output is used inverted for generating interrupts." />
-      </BitField>
-      <BitField start="16" size="1" name="CMP1_INTTYPE" description="Select comparator 1 interrupt type. See Table 412.">
-        <Enum name="EDGE" start="0" description="Comparator 1 interrupt is edge triggered." />
-        <Enum name="LEVEL" start="1" description="Comparator 1 interrupt is level triggered." />
-      </BitField>
-      <BitField start="17" size="2" name="CMP1_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP1_IntType = 0. See Table 412.">
-        <Enum name="FALLING" start="0x0" description="Comparator 1 interrupt is active on falling edges." />
-        <Enum name="RISING" start="0x1" description="Comparator 1 interrupt is active on rising edges." />
-        <Enum name="DUALEDGE" start="0x2" description="Comparator 1 Interrupt is active on both edges." />
-      </BitField>
-      <BitField start="19" size="1" name="CMP1_INTFLAG" description="Comparator 1 interrupt flag.">
-        <Enum name="NOTPENDING" start="0" description="The Comparator 1 interrupt is not pending." />
-        <Enum name="PENDING" start="1" description="The Comparator 1 interrupt is pending. Writing a 1 to this bit clears the flag." />
-      </BitField>
-      <BitField start="20" size="2" name="CMP1_VLADEN" description="Voltage ladder enable for comparator 1.">
-        <Enum name="DISABLED" start="0x0" description="The Comparator 1 voltage ladder is disabled." />
-        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 1 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
-        <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 1 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
-        <Enum name="ENABLED" start="0x3" description="The Comparator 1 voltage ladder is enabled." />
-      </BitField>
-      <BitField start="22" size="1" name="CMP1_VLADREF" description="Voltage reference select for comparator 1 voltage ladder.">
-        <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." />
-        <Enum name="VDDA_PIN_" start="1" description="VDDA pin." />
-      </BitField>
-      <BitField start="23" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="5" name="CMP1_VSel" description="Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of CMP1_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref1 / 31. 00010 = 2 x Vref1 / 31. ... 11111 = Vref1." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) ">
-    <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
-        <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-        <Enum name="NO_EFFECT_" start="0" description="No effect." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
-        <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-      </BitField>
-    </Register>
-    <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="GP" description="General purpose storage." />
-    </Register>
-    <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTROL" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wakeup enable for channel 0.">
-        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 0." />
-        <Enum name="AN_EVENT_IN_CHANNEL_" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="NOGPREG" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="CLRGPREG" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin RTC_EV0.">
-        <Enum name="NEG" start="0" description="A channel 0 event is defined as a negative edge on RTC_EV0." />
-        <Enum name="POS" start="1" description="A channel 0 event is defined as a positive edge on RTC_EV0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0.[1]">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wakeup enable for channel 1.">
-        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 1." />
-        <Enum name="WAKEUP" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="NOGPREG" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="CLRGPREG" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin RTC_EV1.">
-        <Enum name="NEG" start="0" description="A channel 1 event is defined as a negative edge on RTC_EV1." />
-        <Enum name="POS" start="1" description="A channel 1 event is defined as a positive edge on RTC_EV1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1.[1]">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wakeup enable for channel 2.">
-        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 2." />
-        <Enum name="WAKEUP" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="NOGPREG" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="CLRGPREG" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin RTC_EV2.">
-        <Enum name="NEG" start="0" description="A channel 2 event is defined as a negative edge on RTC_EV2." />
-        <Enum name="POS" start="1" description="A channel 2 event is defined as a positive edge on RTC_EV2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2.[1]">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2]">
-        <Enum name="DISABLED" start="0x0" description="Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="ENABLE_EVENT_MONITOR16HZ" start="0x1" description="Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="ENABLE_EVENT_MONITOR64HZ" start="0x2" description="Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="ENABLE_EVENT_MONITOR1KHZ" start="0x3" description="Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Event flag for channel 0 (RTC_EV0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 0." />
-        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Event flag for channel 1 (RTC_EV1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 1." />
-        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Event flag for channel 2 (RTC_EV2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 2." />
-        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOGPCLR" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="GPCLR" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wakeup request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_INTERRUPTWAKEUP_" start="0" description="No interrupt/wakeup request is pending" />
-        <Enum name="INTWAKEUP_PEND" start="1" description="An interrupt/wakeup request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
-    <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0Int" description="Port 0 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="P2Int" description="Port 2 GPIO interrupt pending.">
-        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
-        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="P0_31REI" description="Status of Rising Edge Interrupt for P0[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-    </Register>
-    <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="P0_31FEI" description="Status of Falling Edge Interrupt for P0[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="P0_31CI" description="Clear GPIO port Interrupts for P0[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-    </Register>
-    <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="P0_31ER" description="Enable rising edge interrupt for P0[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="P0_31EF" description="Enable falling edge interrupt for P0[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-    </Register>
-    <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="14" size="1" name="P2_14REI" description="Status of Rising Edge Interrupt for P2[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="15" size="1" name="P2_15REI" description="Status of Rising Edge Interrupt for P2[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="16" size="1" name="P2_16REI" description="Status of Rising Edge Interrupt for P2[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="17" size="1" name="P2_17REI" description="Status of Rising Edge Interrupt for P2[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="18" size="1" name="P2_18REI" description="Status of Rising Edge Interrupt for P2[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="19" size="1" name="P2_19REI" description="Status of Rising Edge Interrupt for P2[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="20" size="1" name="P2_20REI" description="Status of Rising Edge Interrupt for P2[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="21" size="1" name="P2_21REI" description="Status of Rising Edge Interrupt for P2[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="22" size="1" name="P2_22REI" description="Status of Rising Edge Interrupt for P2[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="23" size="1" name="P2_23REI" description="Status of Rising Edge Interrupt for P2[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="24" size="1" name="P2_24REI" description="Status of Rising Edge Interrupt for P2[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="25" size="1" name="P2_25REI" description="Status of Rising Edge Interrupt for P2[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="26" size="1" name="P2_26REI" description="Status of Rising Edge Interrupt for P2[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="27" size="1" name="P2_27REI" description="Status of Rising Edge Interrupt for P2[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="28" size="1" name="P2_28REI" description="Status of Rising Edge Interrupt for P2[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="29" size="1" name="P2_29REI" description="Status of Rising Edge Interrupt for P2[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="30" size="1" name="P2_30REI" description="Status of Rising Edge Interrupt for P2[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-      <BitField start="31" size="1" name="P2_31REI" description="Status of Rising Edge Interrupt for P2[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
-    </Register>
-    <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="14" size="1" name="P2_14FEI" description="Status of Falling Edge Interrupt for P2[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="15" size="1" name="P2_15FEI" description="Status of Falling Edge Interrupt for P2[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="16" size="1" name="P2_16FEI" description="Status of Falling Edge Interrupt for P2[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="17" size="1" name="P2_17FEI" description="Status of Falling Edge Interrupt for P2[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="18" size="1" name="P2_18FEI" description="Status of Falling Edge Interrupt for P2[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="19" size="1" name="P2_19FEI" description="Status of Falling Edge Interrupt for P2[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="20" size="1" name="P2_20FEI" description="Status of Falling Edge Interrupt for P2[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="21" size="1" name="P2_21FEI" description="Status of Falling Edge Interrupt for P2[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="22" size="1" name="P2_22FEI" description="Status of Falling Edge Interrupt for P2[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="23" size="1" name="P2_23FEI" description="Status of Falling Edge Interrupt for P2[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="24" size="1" name="P2_24FEI" description="Status of Falling Edge Interrupt for P2[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="25" size="1" name="P2_25FEI" description="Status of Falling Edge Interrupt for P2[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="26" size="1" name="P2_26FEI" description="Status of Falling Edge Interrupt for P2[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="27" size="1" name="P2_27FEI" description="Status of Falling Edge Interrupt for P2[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="28" size="1" name="P2_28FEI" description="Status of Falling Edge Interrupt for P2[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="29" size="1" name="P2_29FEI" description="Status of Falling Edge Interrupt for P2[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="30" size="1" name="P2_30FEI" description="Status of Falling Edge Interrupt for P2[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-      <BitField start="31" size="1" name="P2_31FEI" description="Status of Falling Edge Interrupt for P2[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="14" size="1" name="P2_14CI" description="Clear GPIO port Interrupts for P2[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="15" size="1" name="P2_15CI" description="Clear GPIO port Interrupts for P2[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="16" size="1" name="P2_16CI" description="Clear GPIO port Interrupts for P2[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="17" size="1" name="P2_17CI" description="Clear GPIO port Interrupts for P2[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="18" size="1" name="P2_18CI" description="Clear GPIO port Interrupts for P2[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="19" size="1" name="P2_19CI" description="Clear GPIO port Interrupts for P2[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="20" size="1" name="P2_20CI" description="Clear GPIO port Interrupts for P2[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="21" size="1" name="P2_21CI" description="Clear GPIO port Interrupts for P2[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="22" size="1" name="P2_22CI" description="Clear GPIO port Interrupts for P2[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="23" size="1" name="P2_23CI" description="Clear GPIO port Interrupts for P2[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="24" size="1" name="P2_24CI" description="Clear GPIO port Interrupts for P2[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="25" size="1" name="P2_25CI" description="Clear GPIO port Interrupts for P2[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="26" size="1" name="P2_26CI" description="Clear GPIO port Interrupts for P2[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="27" size="1" name="P2_27CI" description="Clear GPIO port Interrupts for P2[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="28" size="1" name="P2_28CI" description="Clear GPIO port Interrupts for P2[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="29" size="1" name="P2_29CI" description="Clear GPIO port Interrupts for P2[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="30" size="1" name="P2_30CI" description="Clear GPIO port Interrupts for P2[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-      <BitField start="31" size="1" name="P2_31CI" description="Clear GPIO port Interrupts for P2[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
-    </Register>
-    <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="14" size="1" name="P2_14ER" description="Enable rising edge interrupt for P2[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="15" size="1" name="P2_15ER" description="Enable rising edge interrupt for P2[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="16" size="1" name="P2_16ER" description="Enable rising edge interrupt for P2[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="17" size="1" name="P2_17ER" description="Enable rising edge interrupt for P2[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="18" size="1" name="P2_18ER" description="Enable rising edge interrupt for P2[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="19" size="1" name="P2_19ER" description="Enable rising edge interrupt for P2[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="20" size="1" name="P2_20ER" description="Enable rising edge interrupt for P2[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="21" size="1" name="P2_21ER" description="Enable rising edge interrupt for P2[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="22" size="1" name="P2_22ER" description="Enable rising edge interrupt for P2[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="23" size="1" name="P2_23ER" description="Enable rising edge interrupt for P2[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="24" size="1" name="P2_24ER" description="Enable rising edge interrupt for P2[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="25" size="1" name="P2_25ER" description="Enable rising edge interrupt for P2[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="26" size="1" name="P2_26ER" description="Enable rising edge interrupt for P2[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="27" size="1" name="P2_27ER" description="Enable rising edge interrupt for P2[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="28" size="1" name="P2_28ER" description="Enable rising edge interrupt for P2[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="29" size="1" name="P2_29ER" description="Enable rising edge interrupt for P2[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="30" size="1" name="P2_30ER" description="Enable rising edge interrupt for P2[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-      <BitField start="31" size="1" name="P2_31ER" description="Enable rising edge interrupt for P2[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
-    </Register>
-    <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="14" size="1" name="P2_14EF" description="Enable falling edge interrupt for P2[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="15" size="1" name="P2_15EF" description="Enable falling edge interrupt for P2[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="16" size="1" name="P2_16EF" description="Enable falling edge interrupt for P2[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="17" size="1" name="P2_17EF" description="Enable falling edge interrupt for P2[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="18" size="1" name="P2_18EF" description="Enable falling edge interrupt for P2[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="19" size="1" name="P2_19EF" description="Enable falling edge interrupt for P2[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="20" size="1" name="P2_20EF" description="Enable falling edge interrupt for P2[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="21" size="1" name="P2_21EF" description="Enable falling edge interrupt for P2[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="22" size="1" name="P2_22EF" description="Enable falling edge interrupt for P2[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="23" size="1" name="P2_23EF" description="Enable falling edge interrupt for P2[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="24" size="1" name="P2_24EF" description="Enable falling edge interrupt for P2[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="25" size="1" name="P2_25EF" description="Enable falling edge interrupt for P2[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="26" size="1" name="P2_26EF" description="Enable falling edge interrupt for P2[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="27" size="1" name="P2_27EF" description="Enable falling edge interrupt for P2[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="28" size="1" name="P2_28EF" description="Enable falling edge interrupt for P2[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="29" size="1" name="P2_29EF" description="Enable falling edge interrupt for P2[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="30" size="1" name="P2_30EF" description="Enable falling edge interrupt for P2[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-      <BitField start="31" size="1" name="P2_31EF" description="Enable falling edge interrupt for P2[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="IOCON" start="0x4002C000" description="IOCON pin configuration">
-    <Register start="+0x0" size="4" name="P0_0" access="Read/Write" description="I/O configuration register for pin P0[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[0]">
-        <Enum name="P0_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_RD1" start="0x1" description="CAN1 receiver input." />
-        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
-        <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="U0_TXD" start="0x4" description="Transmitter output for UART0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x4" size="4" name="P0_1" access="Read/Write" description="I/O configuration register for pin P0[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[1]">
-        <Enum name="P0_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_TD1" start="0x1" description="CAN1 transmitter output." />
-        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
-        <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="U0_RXD" start="0x4" description="Receiver input for UART0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x8" size="4" name="P0_2" access="Read/Write" description="I/O configuration register for pin P0[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[2]">
-        <Enum name="P0_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U0_TXD" start="0x1" description="Transmitter output for UART0." />
-        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC" size="4" name="P0_3" access="Read/Write" description="I/O configuration register for pin P0[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[3]">
-        <Enum name="P0_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U0_RXD" start="0x1" description="Receiver input for UART0." />
-        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x10" size="4" name="P0_4" access="Read/Write" description="I/O configuration register for pin P0[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[4]">
-        <Enum name="P0_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_RX_SCK" start="0x1" description="I2S Receive clock. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="CAN_RD2" start="0x2" description="CAN2 receiver input." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-        <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer                                 applications." />
-        <Enum name="LCD_VD_0" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x14" size="4" name="P0_5" access="Read/Write" description="I/O configuration register for pin P0[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[5]">
-        <Enum name="P0_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_RX_WS" start="0x1" description="I2S Receive word select. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="CAN_TD2" start="0x2" description="CAN2 transmitter output." />
-        <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." />
-        <Enum name="CMP_RESET" start="0x5" description="Comparator reset." />
-        <Enum name="LCD_VD_1" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x18" size="4" name="P0_6" access="Read/Write" description="I/O configuration register for pin P0[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[6]">
-        <Enum name="P0_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_RX_SDA" start="0x1" description="I2S Receive data. It is driven                                     by the transmitter and read by the receiver. Corresponds to the                                     signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." />
-        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
-        <Enum name="U1_RTS" start="0x4" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer                                 applications." />
-        <Enum name="LCD_VD_8" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C" size="4" name="P0_7" access="Read/Write" description="I/O configuration register for pin P0[7] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[7] ">
-        <Enum name="P0_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_TX_SCK" start="0x1" description="I2S transmit clock. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." />
-        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
-        <Enum name="RTC_EV0" start="0x4" description="Event input 0 to Event Monitor/Recorder." />
-        <Enum name="CMP_VREF" start="0x5" description="Comparator reference voltage." />
-        <Enum name="LCD_VD_9" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
-        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
-        <Enum name="DISABLED" start="1" description="No input filtering is done." />
-      </BitField>
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x20" size="4" name="P0_8" access="Read/Write" description="I/O configuration register for pin P0[8] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[8] ">
-        <Enum name="P0_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_TX_WS" start="0x1" description="I2S Transmit word select. It                                     is driven by the master and received by the slave. Corresponds                                     to the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." />
-        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
-        <Enum name="RTC_EV1" start="0x4" description="Event input 1 to Event Monitor/Recorder." />
-        <Enum name="CMP1_IN_3" start="0x5" description="Comparator 1, input 3." />
-        <Enum name="LCD_VD_16" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
-        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
-        <Enum name="DISABLED" start="1" description="No input filtering is done." />
-      </BitField>
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x24" size="4" name="P0_9" access="Read/Write" description="I/O configuration register for pin P0[9]" reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[9]">
-        <Enum name="P0_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2S_TX_SDA" start="0x1" description="I2S transmit data. It is                                     driven by the transmitter and read by the receiver. Corresponds                                     to the signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." />
-        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
-        <Enum name="RTC_EV2" start="0x4" description="Event input 2 to Event Monitor/Recorder." />
-        <Enum name="CMP1_IN_2" start="0x5" description="Comparator 1, input 2." />
-        <Enum name="LCD_VD_17" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
-        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
-        <Enum name="DISABLED" start="1" description="No input filtering is done." />
-      </BitField>
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x28" size="4" name="P0_10" access="Read/Write" description="I/O configuration register for pin P0[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[10]">
-        <Enum name="P0_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U2_TXD" start="0x1" description="Transmitter output for UART2." />
-        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
-        <Enum name="LCD_VD_5" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x2C" size="4" name="P0_11" access="Read/Write" description="I/O configuration register for pin P0[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[11]">
-        <Enum name="P0_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U2_RXD" start="0x1" description="Receiver input for UART2." />
-        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
-        <Enum name="LCD_VD_10" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x30" size="4" name="P0_12" access="Read/Write" description="I/O configuration register for pin P0[12]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[12]">
-        <Enum name="P0_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_PPWR2" start="0x1" description="Port Power enable signal for USB port 2." />
-        <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." />
-        <Enum name="ADC0_IN_6" start="0x3" description="A/D converter 0, input 6. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x34" size="4" name="P0_13" access="Read/Write" description="I/O configuration register for pin P0[13]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[13]">
-        <Enum name="P0_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_UP_LED2" start="0x1" description="USB port 2 GoodLink LED indicator. It is LOW when the                                     device is configured (non-control endpoints enabled), or when                                     the host is enabled and has detected a device on the bus. It is                                     HIGH when the device is not configured, or when host is enabled                                     and has not detected a device on the bus, or during global                                     suspend. It transitions between LOW and HIGH (flashes) when the                                     host is enabled and detects activity on the bus." />
-        <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." />
-        <Enum name="ADC0_IN_7" start="0x3" description="A/D converter 0, input 7. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x38" size="4" name="P0_14" access="Read/Write" description="I/O configuration register for pin P0[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[14]">
-        <Enum name="P0_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_HSTEN2" start="0x1" description="Host Enabled status for USB port 2." />
-        <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." />
-        <Enum name="USB_CONNECT2" start="0x3" description="SoftConnect control for USB port 2. Signal used to switch                                     an external 1.5 kW resistor under                                     software control. Used with the SoftConnect USB                                     feature." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x3C" size="4" name="P0_15" access="Read/Write" description="I/O configuration register for pin P0[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[15]">
-        <Enum name="P0_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_TXD" start="0x1" description="Transmitter output for UART1." />
-        <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." />
-        <Enum name="SPIFI_IO_2" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x40" size="4" name="P0_16" access="Read/Write" description="I/O configuration register for pin P0[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[16]">
-        <Enum name="P0_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_RXD" start="0x1" description="Receiver input for UART1." />
-        <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." />
-        <Enum name="SPIFI_IO_3" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x44" size="4" name="P0_17" access="Read/Write" description="I/O configuration register for pin P0[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[17]">
-        <Enum name="P0_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_CTS" start="0x1" description="Clear to Send input for UART1." />
-        <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." />
-        <Enum name="SPIFI_IO_1" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x48" size="4" name="P0_18" access="Read/Write" description="I/O configuration register for pin P0[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[18]">
-        <Enum name="P0_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_DCD" start="0x1" description="Data Carrier Detect input for UART1." />
-        <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." />
-        <Enum name="SPIFI_IO_0" start="0x5" description="Data bit 0 for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x4C" size="4" name="P0_19" access="Read/Write" description="I/O configuration register for pin P0[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[19]">
-        <Enum name="P0_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_DSR" start="0x1" description="Data Set Ready input for UART1." />
-        <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." />
-        <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="LCD_VD_13" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x50" size="4" name="P0_20" access="Read/Write" description="I/O configuration register for pin P0[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[20]">
-        <Enum name="P0_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_DTR" start="0x1" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." />
-        <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="LCD_VD_14" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x54" size="4" name="P0_21" access="Read/Write" description="I/O configuration register for pin P0[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[21]">
-        <Enum name="P0_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_RI" start="0x1" description="Ring Indicator input for UART1." />
-        <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power                                     supply." />
-        <Enum name="U4_OE" start="0x3" description="RS-485/EIA-485 output enable signal for                                     UART4." />
-        <Enum name="CAN_RD1" start="0x4" description="CAN1 receiver input." />
-        <Enum name="U4_SCLK" start="0x5" description="USART 4 clock input or output in synchronous                                     mode." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x58" size="4" name="P0_22" access="Read/Write" description="I/O configuration register for pin P0[22]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[22]">
-        <Enum name="P0_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U1_RTS" start="0x1" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." />
-        <Enum name="U4_TXD" start="0x3" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
-        <Enum name="CAN_TD1" start="0x4" description="CAN1 transmitter output." />
-        <Enum name="SPIFI_CLK" start="0x5" description="Clock output for SPIFI." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x5C" size="4" name="P0_23" access="Read/Write" description="I/O configuration register for pin P0[23]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[23]">
-        <Enum name="P0_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_0" start="0x1" description="A/D converter 0, input 0. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2S_RX_SCK" start="0x2" description="Receive Clock. It is driven by the master and received by                                     the slave. Corresponds to the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
-      </BitField>
-    </Register>
-    <Register start="+0x60" size="4" name="P0_24" access="Read/Write" description="I/O configuration register for pin P0[24]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[24]">
-        <Enum name="P0_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_1" start="0x1" description="A/D converter 0, input 1. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2S_RX_WS" start="0x2" description="Receive Word Select. It is driven by the master and                                     received by the slave. Corresponds to the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x64" size="4" name="P0_25" access="Read/Write" description="I/O configuration register for pin P0[25]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[25]">
-        <Enum name="P0_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_2" start="0x1" description="A/D converter 0, input 2. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2S_RX_SDA" start="0x2" description="Receive data. It is driven by the transmitter and read by                                     the receiver. Corresponds to the signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="U3_TXD" start="0x3" description="Transmitter output for UART3." />
-      </BitField>
-    </Register>
-    <Register start="+0x68" size="4" name="P0_26" access="Read/Write" description="I/O configuration register for pin P0[26]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[26]">
-        <Enum name="P0_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ADC0_IN_3" start="0x1" description="A/D converter 0, input 3. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="DAC_OUT" start="0x2" description="D/A converter output. When configured as the DAC output,                                     the digital function of the pin must be disabled." />
-        <Enum name="U3_RXD" start="0x3" description="Receiver input for UART3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="DACEN" description="DAC output enable.">
-        <Enum name="DISABLE" start="0" description="DAC disable." />
-        <Enum name="ENABLE" start="1" description="DAC enable." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x6C" size="4" name="P0_27" access="Read/Write" description="I/O configuration register for pin P0[27]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[27]">
-        <Enum name="P0_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2C0_SDA" start="0x1" description="I2C0 data input/output. (This                                     pin uses a specialized I2C pad)." />
-        <Enum name="USB_SDA1" start="0x2" description="I2C serial data for communication with an external USB                                     transceiver." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x70" size="4" name="P0_28" access="Read/Write" description="I/O configuration register for pin P0[28]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[28]">
-        <Enum name="P0_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="I2C0_SCL" start="0x1" description="I2C0 clock input/output (this                                     pin uses a specialized I2C pad." />
-        <Enum name="USB_SCL1" start="0x2" description="I2C serial clock for communication with an external USB                                     transceiver." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x74" size="4" name="P0_29" access="Read/Write" description="I/O configuration register for pin P0[29]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[29]">
-        <Enum name="P0_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_DP1" start="0x1" description="USB port 1 bidirectional D+ line." />
-        <Enum name="EINT0" start="0x2" description="External interrupt 0 input." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x78" size="4" name="P0_30" access="Read/Write" description="I/O configuration register for pin P0[30]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[30]">
-        <Enum name="P0_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_DM1" start="0x1" description="USB port 1 bidirectional D-                                     line." />
-        <Enum name="EINT1" start="0x2" description="External interrupt 1 input." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x7C" size="4" name="P0_31" access="Read/Write" description="I/O configuration register for pin P0[31]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[31]">
-        <Enum name="P0_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_DP2" start="0x1" description="USB port 2 bidirectional D+ line." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x80" size="4" name="P1_0" access="Read/Write" description="I/O configuration register for pin P1[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[0]">
-        <Enum name="P1_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD0" start="0x1" description="Ethernet transmit data 0 (RMII/MII                                     interface)." />
-        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
-        <Enum name="SSP2_SCK" start="0x4" description="Serial clock for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x84" size="4" name="P1_1" access="Read/Write" description="I/O configuration register for pin P1[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[1]">
-        <Enum name="P1_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD1" start="0x1" description="Ethernet transmit data 1 (RMII/MII                                     interface)." />
-        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
-        <Enum name="SSP2_MOSI" start="0x4" description="Master Out Slave In for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x88" size="4" name="P1_2" access="Read/Write" description="I/O configuration register for pin P1[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[2]">
-        <Enum name="P1_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD2" start="0x1" description="Ethernet transmit data 2 (MII interface)." />
-        <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." />
-        <Enum name="PWM0_1" start="0x3" description="Pulse Width Modulator 0, output 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x8C" size="4" name="P1_3" access="Read/Write" description="I/O configuration register for pin P1[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[3]">
-        <Enum name="P1_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TXD3" start="0x1" description="Ethernet transmit data 3 (MII interface)." />
-        <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." />
-        <Enum name="PWM0_2" start="0x3" description="Pulse Width Modulator 0, output 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x90" size="4" name="P1_4" access="Read/Write" description="I/O configuration register for pin P1[4] " reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[4] ">
-        <Enum name="P1_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TX_EN" start="0x1" description="Ethernet transmit data enable (RMII/MII                                     interface)." />
-        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
-        <Enum name="SSP2_MISO" start="0x4" description="Master In Slave Out for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x94" size="4" name="P1_5" access="Read/Write" description="I/O configuration register for pin P1[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[5]">
-        <Enum name="P1_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TX_ER" start="0x1" description="Ethernet Transmit Error (MII interface)." />
-        <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power                                     supply." />
-        <Enum name="PWM0_3" start="0x3" description="Pulse Width Modulator 0, output 3." />
-        <Enum name="CMP1_IN_1" start="0x5" description="Comparator 1, input 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x98" size="4" name="P1_6" access="Read/Write" description="I/O configuration register for pin P1[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[6]">
-        <Enum name="P1_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_TX_CLK" start="0x1" description="Ethernet Transmit Clock (MII interface)." />
-        <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." />
-        <Enum name="PWM0_4" start="0x3" description="Pulse Width Modulator 0, output 4." />
-        <Enum name="CMP0_IN_3" start="0x5" description="Comparator 0, input 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x9C" size="4" name="P1_7" access="Read/Write" description="I/O configuration register for pin P1[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[7]">
-        <Enum name="P1_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_COL" start="0x1" description="Ethernet Collision detect (MII interface)." />
-        <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." />
-        <Enum name="PWM0_5" start="0x3" description="Pulse Width Modulator 0, output 5." />
-        <Enum name="CMP1_IN_0" start="0x5" description="Comparator 1, input 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xA0" size="4" name="P1_8" access="Read/Write" description="I/O configuration register for pin P1[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[8]">
-        <Enum name="P1_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_CRS_CRS_DV" start="0x1" description="Ethernet Carrier Sense (MII interface) or Ethernet                                     Carrier Sense/Data Valid (RMII interface)." />
-        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
-        <Enum name="SSP2_SSEL" start="0x4" description="Slave Select for SSP2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xA4" size="4" name="P1_9" access="Read/Write" description="I/O configuration register for pin P1[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[9]">
-        <Enum name="P1_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD0" start="0x1" description="Ethernet receive data 0 (RMII/MII interface)." />
-        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xA8" size="4" name="P1_10" access="Read/Write" description="I/O configuration register for pin P1[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[10]">
-        <Enum name="P1_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD1" start="0x1" description="Ethernet receive data 1 (RMII/MII interface)." />
-        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xAC" size="4" name="P1_11" access="Read/Write" description="I/O configuration register for pin P1[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[11]">
-        <Enum name="P1_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD2" start="0x1" description="Ethernet Receive Data 2 (MII interface)." />
-        <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." />
-        <Enum name="PWM0_6" start="0x3" description="Pulse Width Modulator 0, output 6." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xB0" size="4" name="P1_12" access="Read/Write" description="I/O configuration register for pin P1[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[12]">
-        <Enum name="P1_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RXD3" start="0x1" description="Ethernet Receive Data (MII interface)." />
-        <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." />
-        <Enum name="PWM0_CAP0" start="0x3" description="Capture input for PWM0, channel 0." />
-        <Enum name="CMP1_OUT" start="0x5" description="Comparator 1, output." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xB4" size="4" name="P1_13" access="Read/Write" description="I/O configuration register for pin P1[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[13]">
-        <Enum name="P1_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RX_DV" start="0x1" description="Ethernet Receive Data Valid (MII interface)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xB8" size="4" name="P1_14" access="Read/Write" description="I/O configuration register for pin P1[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[14]">
-        <Enum name="P1_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RX_ER" start="0x1" description="Ethernet receive error (RMII/MII interface)." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-        <Enum name="CMP0_IN_0" start="0x5" description="Comparator 0, input 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xBC" size="4" name="P1_15" access="Read/Write" description="I/O configuration register for pin P1[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[15]">
-        <Enum name="P1_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_RX_CLK_REF_CLK" start="0x1" description="Ethernet Receive Clock (MII interface) or Ethernet                                     Reference Clock (RMII interface)." />
-        <Enum name="I2C2_SDA" start="0x3" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC0" size="4" name="P1_16" access="Read/Write" description="I/O configuration register for pin P1[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[16]">
-        <Enum name="P1_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_MDC" start="0x1" description="Ethernet MIIM clock." />
-        <Enum name="I2S_TX_MCLK" start="0x2" description="I2S transmit master clock." />
-        <Enum name="CMP0_IN_1" start="0x5" description="Comparator 0, input 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC4" size="4" name="P1_17" access="Read/Write" description="I/O configuration register for pin P1[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[17]">
-        <Enum name="P1_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="ENET_MDIO" start="0x1" description="Ethernet MIIM data input and output." />
-        <Enum name="I2S_RX_MCLK" start="0x2" description="I2S receive master clock." />
-        <Enum name="CMP0_IN_2" start="0x5" description="Comparator 0, input 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xC8" size="4" name="P1_18" access="Read/Write" description="I/O configuration register for pin P1[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[18]">
-        <Enum name="P1_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_UP_LED1" start="0x1" description="It is LOW when the device is configured (non-control                                     endpoints enabled), or when the host is enabled and has detected                                     a device on the bus. It is HIGH when the device is not                                     configured, or when host is enabled and has not detected a                                     device on the bus, or during global suspend. It transitions                                     between LOW and HIGH (flashes) when the host is enabled and                                     detects activity on the bus." />
-        <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, channel 1 output." />
-        <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." />
-        <Enum name="SSP1_MISO" start="0x5" description="Master In Slave Out for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xCC" size="4" name="P1_19" access="Read/Write" description="I/O configuration register for pin P1[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[19]">
-        <Enum name="P1_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_TX_E1" start="0x1" description="Transmit Enable signal for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="USB_PPWR1" start="0x2" description="Port Power enable signal for USB port 1." />
-        <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." />
-        <Enum name="MC_0A" start="0x4" description="Motor control PWM channel 0, output A." />
-        <Enum name="SSP1_SCK" start="0x5" description="Serial clock for SSP1." />
-        <Enum name="U2_OE" start="0x6" description="RS-485/EIA-485 output enable signal for                                     UART2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xD0" size="4" name="P1_20" access="Read/Write" description="I/O configuration register for pin P1[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[20]">
-        <Enum name="P1_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_TX_DP1" start="0x1" description="D+ transmit data for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, channel 2 output." />
-        <Enum name="QEI_PHA" start="0x3" description="Quadrature Encoder Interface PHA input." />
-        <Enum name="MC_FB0" start="0x4" description="Motor control PWM channel 0 feedback input." />
-        <Enum name="SSP0_SCK" start="0x5" description="Serial clock for SSP0." />
-        <Enum name="LCD_VD_6" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_10" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xD4" size="4" name="P1_21" access="Read/Write" description="I/O configuration register for pin P1[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[21]">
-        <Enum name="P1_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_TX_DM1" start="0x1" description="D- transmit data for USB port                                     1 (OTG transceiver)." />
-        <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, channel 3 output." />
-        <Enum name="SSP0_SSEL" start="0x3" description="Slave Select for SSP0." />
-        <Enum name="MC_ABORT" start="0x4" description="Motor control PWM, active low fast abort." />
-        <Enum name="LCD_VD_7" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_11" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xD8" size="4" name="P1_22" access="Read/Write" description="I/O configuration register for pin P1[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[22]">
-        <Enum name="P1_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_RCV1" start="0x1" description="Differential receive data for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="USB_PWRD1" start="0x2" description="Power Status for USB port 1 (host power                                     switch)." />
-        <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." />
-        <Enum name="MC_0B" start="0x4" description="Motor control PWM channel 0, output B." />
-        <Enum name="SSP1_MOSI" start="0x5" description="Master Out Slave In for SSP1." />
-        <Enum name="LCD_VD_8" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_12" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xDC" size="4" name="P1_23" access="Read/Write" description="I/O configuration register for pin P1[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[23]">
-        <Enum name="P1_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_RX_DP1" start="0x1" description="D+ receive data for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, channel 4 output." />
-        <Enum name="QEI_PHB" start="0x3" description="Quadrature Encoder Interface PHB input." />
-        <Enum name="MC_FB1" start="0x4" description="Motor control PWM channel 1 feedback input." />
-        <Enum name="SSP0_MISO" start="0x5" description="Master In Slave Out for SSP0." />
-        <Enum name="LCD_VD_9" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_13" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xE0" size="4" name="P1_24" access="Read/Write" description="I/O configuration register for pin P1[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[24]">
-        <Enum name="P1_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_RX_DM1" start="0x1" description="D- receive data for USB port 1                                     (OTG transceiver)." />
-        <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, channel 5 output." />
-        <Enum name="QEI_IDX" start="0x3" description="Quadrature Encoder Interface INDEX input." />
-        <Enum name="MC_FB2" start="0x4" description="Motor control PWM channel 2 feedback input." />
-        <Enum name="SSP0_MOSI" start="0x5" description="Master Out Slave in for SSP0." />
-        <Enum name="LCD_VD_10" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_14" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xE4" size="4" name="P1_25" access="Read/Write" description="I/O configuration register for pin P1[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[25]">
-        <Enum name="P1_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_LS1" start="0x1" description="Low Speed status for USB port 1 (OTG                                     transceiver)." />
-        <Enum name="USB_HSTEN1" start="0x2" description="Host Enabled status for USB port 1." />
-        <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." />
-        <Enum name="MC_1A" start="0x4" description="Motor control PWM channel 1, output A." />
-        <Enum name="CLKOUT" start="0x5" description="Selectable clock output." />
-        <Enum name="LCD_VD_11" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_15" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xE8" size="4" name="P1_26" access="Read/Write" description="I/O configuration register for pin P1[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[26]">
-        <Enum name="P1_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_SSPND1" start="0x1" description="USB port 1 Bus Suspend status (OTG                                     transceiver)." />
-        <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, channel 6 output." />
-        <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." />
-        <Enum name="MC_1B" start="0x4" description="Motor control PWM channel 1, output B." />
-        <Enum name="SSP1_SSEL" start="0x5" description="Slave Select for SSP1." />
-        <Enum name="LCD_VD_12" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_20" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xEC" size="4" name="P1_27" access="Read/Write" description="I/O configuration register for pin P1[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[27]">
-        <Enum name="P1_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_INT1" start="0x1" description="USB port 1 OTG transceiver interrupt (OTG                                     transceiver)." />
-        <Enum name="USB_OVRCR1" start="0x2" description="USB port 1 Over-Current status." />
-        <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." />
-        <Enum name="CLKOUT" start="0x4" description="Selectable clock output." />
-        <Enum name="LCD_VD_13" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_21" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xF0" size="4" name="P1_28" access="Read/Write" description="I/O configuration register for pin P1[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[28]">
-        <Enum name="P1_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_SCL1" start="0x1" description="USB port 1 I2C serial clock                                     (OTG transceiver)." />
-        <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." />
-        <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." />
-        <Enum name="MC_2A" start="0x4" description="Motor control PWM channel 2, output A." />
-        <Enum name="SSP0_SSEL" start="0x5" description="Slave Select for SSP0." />
-        <Enum name="LCD_VD_14" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_22" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xF4" size="4" name="P1_29" access="Read/Write" description="I/O configuration register for pin P1[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[29]">
-        <Enum name="P1_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_SDA1" start="0x1" description="USB port 1 I2C serial data                                     (OTG transceiver)." />
-        <Enum name="PWM1_CAP1" start="0x2" description="Capture input for PWM1, channel 1." />
-        <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." />
-        <Enum name="MC_2B" start="0x4" description="Motor control PWM channel 2, output B." />
-        <Enum name="U4_TXD" start="0x5" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
-        <Enum name="LCD_VD_15" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_23" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xF8" size="4" name="P1_30" access="Read/Write" description="I/O configuration register for pin P1[30]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[30]">
-        <Enum name="P1_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_PWRD2" start="0x1" description="Power Status for USB port 2." />
-        <Enum name="USB_VBUS" start="0x2" description="Monitors the presence of USB bus power.This signal must be HIGH for USB reset to                                     occur." />
-        <Enum name="ADC0_IN_4" start="0x3" description="A/D converter 0, input 4. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2C0_SDA" start="0x4" description="I2C0 data input/output (this                                     pin does not use a specialized I2C pad." />
-        <Enum name="U3_OE" start="0x5" description="RS-485/EIA-485 output enable signal for                                     UART3." />
-      </BitField>
-    </Register>
-    <Register start="+0xFC" size="4" name="P1_31" access="Read/Write" description="I/O configuration register for pin P1[31]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[31]">
-        <Enum name="P1_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_OVRCR2" start="0x1" description="Over-Current status for USB port 2." />
-        <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." />
-        <Enum name="ADC0_IN_5" start="0x3" description="A/D converter 0, input 5. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
-        <Enum name="I2C0_SCL" start="0x4" description="I2C0 clock input/output (this                                     pin does not use a specialized I2C pad." />
-      </BitField>
-    </Register>
-    <Register start="+0x100" size="4" name="P2_0" access="Read/Write" description="I/O configuration register for pin P2[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[0]">
-        <Enum name="P2_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_1" start="0x1" description="Pulse Width Modulator 1, channel 1 output." />
-        <Enum name="U1_TXD" start="0x2" description="Transmitter output for UART1." />
-        <Enum name="LCD_PWR" start="0x7" description="LCD panel power enable." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="P2_1" access="Read/Write" description="I/O configuration register for pin P2[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[1]">
-        <Enum name="P2_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_2" start="0x1" description="Pulse Width Modulator 1, channel 2 output." />
-        <Enum name="U1_RXD" start="0x2" description="Receiver input for UART1." />
-        <Enum name="LCD_LE" start="0x7" description="Line end signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x108" size="4" name="P2_2" access="Read/Write" description="I/O configuration register for pin P2[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[2]">
-        <Enum name="P2_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_3" start="0x1" description="Pulse Width Modulator 1, channel 3 output." />
-        <Enum name="U1_CTS" start="0x2" description="Clear to Send input for UART1." />
-        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
-        <Enum name="TRACEDATA_3" start="0x5" description="Trace data, bit 3." />
-        <Enum name="LCD_DCLK" start="0x7" description="LCD panel clock." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x10C" size="4" name="P2_3" access="Read/Write" description="I/O configuration register for pin P2[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[3]">
-        <Enum name="P2_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_4" start="0x1" description="Pulse Width Modulator 1, channel 4 output." />
-        <Enum name="U1_DCD" start="0x2" description="Data Carrier Detect input for UART1." />
-        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
-        <Enum name="TRACEDATA_2" start="0x5" description="Trace data, bit 2." />
-        <Enum name="LCD_FP" start="0x7" description="Frame pulse (STN). Vertical synchronization pulse                                     (TFT)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x110" size="4" name="P2_4" access="Read/Write" description="I/O configuration register for pin P2[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[4]">
-        <Enum name="P2_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_5" start="0x1" description="Pulse Width Modulator 1, channel 5 output." />
-        <Enum name="U1_DSR" start="0x2" description="Data Set Ready input for UART1." />
-        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
-        <Enum name="TRACEDATA_1" start="0x5" description="Trace data, bit 1." />
-        <Enum name="LCD_ENAB_M" start="0x7" description="STN AC bias drive or TFT data enable output." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x114" size="4" name="P2_5" access="Read/Write" description="I/O configuration register for pin P2[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[5]">
-        <Enum name="P2_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_6" start="0x1" description="Pulse Width Modulator 1, channel 6 output." />
-        <Enum name="U1_DTR" start="0x2" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
-        <Enum name="TRACEDATA_0" start="0x5" description="Trace data, bit 0." />
-        <Enum name="LCD_LP" start="0x7" description="Line synchronization pulse (STN). Horizontal                                     synchronization pulse (TFT)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x118" size="4" name="P2_6" access="Read/Write" description="I/O configuration register for pin P2[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[6]">
-        <Enum name="P2_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="PWM1_CAP0" start="0x1" description="Capture input for PWM1, channel 0." />
-        <Enum name="U1_RI" start="0x2" description="Ring Indicator input for UART1." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-        <Enum name="U2_OE" start="0x4" description="RS-485/EIA-485 output enable signal for                                     UART2." />
-        <Enum name="TRACECLK" start="0x5" description="Trace clock." />
-        <Enum name="LCD_VD_0" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_4" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="P2_7" access="Read/Write" description="I/O configuration register for pin P2[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[7]">
-        <Enum name="P2_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_RD2" start="0x1" description="CAN2 receiver input." />
-        <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="SPIFI_CS" start="0x5" description="Chip select output for SPIFI." />
-        <Enum name="LCD_VD_1" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_5" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x120" size="4" name="P2_8" access="Read/Write" description="I/O configuration register for pin P2[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[8]">
-        <Enum name="P2_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="CAN_TD2" start="0x1" description="CAN2 transmitter output." />
-        <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." />
-        <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." />
-        <Enum name="ENET_MDC" start="0x4" description="Ethernet MIIM clock." />
-        <Enum name="LCD_VD_2" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_6" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x124" size="4" name="P2_9" access="Read/Write" description="I/O configuration register for pin P2[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[9]">
-        <Enum name="P2_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="USB_CONNECT1" start="0x1" description="USB1 SoftConnect control. Signal used to switch an                                     external 1.5 kW resistor under the                                     software control. Used with the SoftConnect USB                                     feature." />
-        <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." />
-        <Enum name="U4_RXD" start="0x3" description="Receiver input for USART4." />
-        <Enum name="ENET_MDIO" start="0x4" description="Ethernet MIIM data input and output." />
-        <Enum name="LCD_VD_3" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_7" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x128" size="4" name="P2_10" access="Read/Write" description="I/O configuration register for pin P2[10]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[10]">
-        <Enum name="P2_10" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter.A LOW on this pin while RESET is LOW forces the on-chip&#xa;                                    boot loader to take over control of the part after a reset and&#xa;                                    go into ISP mode. " />
-        <Enum name="EINT0" start="0x1" description="External interrupt 0 input." />
-        <Enum name="NMI" start="0x2" description="Non-maskable interrupt input." />
-      </BitField>
-    </Register>
-    <Register start="+0x12C" size="4" name="P2_11" access="Read/Write" description="I/O configuration register for pin P2[11]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[11]">
-        <Enum name="P2_11" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
-        <Enum name="EINT1" start="0x1" description="External interrupt 1 input." />
-        <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." />
-        <Enum name="I2S_TX_SCK" start="0x3" description="Transmit Clock. It is driven by the master and received                                     by the slave. Corresponds to the signal SCK in the                                             I2S-bus                                         specification." />
-        <Enum name="LCD_CLKIN" start="0x7" description="LCD clock." />
-      </BitField>
-    </Register>
-    <Register start="+0x130" size="4" name="P2_12" access="Read/Write" description="I/O configuration register for pin P2[12]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[12]">
-        <Enum name="P2_12" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
-        <Enum name="EINT2" start="0x1" description="External interrupt 2 input." />
-        <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." />
-        <Enum name="I2S_TX_WS" start="0x3" description="Transmit Word Select. It is driven by the master and                                     received by the slave. Corresponds to the signal WS in the                                             I2S-bus                                         specification." />
-        <Enum name="LCD_VD_4" start="0x4" description="LCD data." />
-        <Enum name="LCD_VD_3" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_8" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_18" start="0x7" description="LCD data." />
-      </BitField>
-    </Register>
-    <Register start="+0x134" size="4" name="P2_13" access="Read/Write" description="I/O configuration register for pin P2[13]" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[13]">
-        <Enum name="P2_13" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
-        <Enum name="EINT3" start="0x1" description="External interrupt 3 input." />
-        <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." />
-        <Enum name="I2S_TX_SDA" start="0x3" description="Transmit data. It is driven by the transmitter and read                                     by the receiver. Corresponds to the signal SD in the                                             I2S-bus                                         specification." />
-        <Enum name="LCD_VD_5" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_9" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_19" start="0x7" description="LCD data." />
-      </BitField>
-    </Register>
-    <Register start="+0x138" size="4" name="P2_14" access="Read/Write" description="I/O configuration register for pin P2[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[14]">
-        <Enum name="P2_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS2" start="0x1" description="LOW active Chip Select 2 signal." />
-        <Enum name="I2C1_SDA" start="0x2" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x13C" size="4" name="P2_15" access="Read/Write" description="I/O configuration register for pin P2[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[15]">
-        <Enum name="P2_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS3" start="0x1" description="LOW active Chip Select 3 signal." />
-        <Enum name="I2C1_SCL" start="0x2" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140" size="4" name="P2_16" access="Read/Write" description="I/O configuration register for pin P2[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[16]">
-        <Enum name="P2_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CAS" start="0x1" description="LOW active SDRAM Column Address Strobe." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x144" size="4" name="P2_17" access="Read/Write" description="I/O configuration register for pin P2[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[17]">
-        <Enum name="P2_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_RAS" start="0x1" description="LOW active SDRAM Row Address Strobe." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="P2_18" access="Read/Write" description="I/O configuration register for pin P2[18]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[18]">
-        <Enum name="P2_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CLK_0" start="0x1" description="SDRAM clock 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x14C" size="4" name="P2_19" access="Read/Write" description="I/O configuration register for pin P2[19]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[19]">
-        <Enum name="P2_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CLK_1" start="0x1" description="SDRAM clock 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
-        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
-        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
-      </BitField>
-      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
-        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
-        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x150" size="4" name="P2_20" access="Read/Write" description="I/O configuration register for pin P2[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[20]">
-        <Enum name="P2_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS0" start="0x1" description="SDRAM chip select 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x154" size="4" name="P2_21" access="Read/Write" description="I/O configuration register for pin P2[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[21]">
-        <Enum name="P2_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS1" start="0x1" description="SDRAM chip select 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x158" size="4" name="P2_22" access="Read/Write" description="I/O configuration register for pin P2[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[22]">
-        <Enum name="P2_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS2" start="0x1" description="SDRAM chip select 2." />
-        <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." />
-        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x15C" size="4" name="P2_23" access="Read/Write" description="I/O configuration register for pin P2[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[23]">
-        <Enum name="P2_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DYCS3" start="0x1" description="SDRAM chip select 3." />
-        <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." />
-        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="P2_24" access="Read/Write" description="I/O configuration register for pin P2[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[24]">
-        <Enum name="P2_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE0" start="0x1" description="SDRAM clock enable 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="P2_25" access="Read/Write" description="I/O configuration register for pin P2[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[25]">
-        <Enum name="P2_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE1" start="0x1" description="SDRAM clock enable 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x168" size="4" name="P2_26" access="Read/Write" description="I/O configuration register for pin P2[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[26]">
-        <Enum name="P2_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE2" start="0x1" description="SDRAM clock enable 2." />
-        <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." />
-        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x16C" size="4" name="P2_27" access="Read/Write" description="I/O configuration register for pin P2[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[27]">
-        <Enum name="P2_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CKE3" start="0x1" description="SDRAM clock enable 3." />
-        <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." />
-        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x170" size="4" name="P2_28" access="Read/Write" description="I/O configuration register for pin P2[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[28]">
-        <Enum name="P2_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM0" start="0x1" description="Data mask 0 used with SDRAM and static                                     devices." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x174" size="4" name="P2_29" access="Read/Write" description="I/O configuration register for pin P2[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[29]">
-        <Enum name="P2_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM1" start="0x1" description="Data mask 1 used with SDRAM and static                                     devices." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x178" size="4" name="P2_30" access="Read/Write" description="I/O configuration register for pin P2[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[30]">
-        <Enum name="P2_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM2" start="0x1" description="Data mask 2 used with SDRAM and static                                     devices." />
-        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x17C" size="4" name="P2_31" access="Read/Write" description="I/O configuration register for pin P2[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[31]">
-        <Enum name="P2_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_DQM3" start="0x1" description="Data mask 3 used with SDRAM and static                                     devices." />
-        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x180" size="4" name="P3_0" access="Read/Write" description="I/O configuration register for pin P3[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[0]">
-        <Enum name="P3_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_0" start="0x1" description="External memory data line 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x184" size="4" name="P3_1" access="Read/Write" description="I/O configuration register for pin P3[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[1]">
-        <Enum name="P3_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_1" start="0x1" description="External memory data line 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x188" size="4" name="P3_2" access="Read/Write" description="I/O configuration register for pin P3[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[2]">
-        <Enum name="P3_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_2" start="0x1" description="External memory data line 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x18C" size="4" name="P3_3" access="Read/Write" description="I/O configuration register for pin P3[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[3]">
-        <Enum name="P3_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_3" start="0x1" description="External memory data line 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x190" size="4" name="P3_4" access="Read/Write" description="I/O configuration register for pin P3[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[4]">
-        <Enum name="P3_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_4" start="0x1" description="External memory data line 4." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x194" size="4" name="P3_5" access="Read/Write" description="I/O configuration register for pin P3[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[5]">
-        <Enum name="P3_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_5" start="0x1" description="External memory data line 5." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x198" size="4" name="P3_6" access="Read/Write" description="I/O configuration register for pin P3[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[6]">
-        <Enum name="P3_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_6" start="0x1" description="External memory data line 6." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x19C" size="4" name="P3_7" access="Read/Write" description="I/O configuration register for pin P3[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[7]">
-        <Enum name="P3_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_7" start="0x1" description="External memory data line 7." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="P3_8" access="Read/Write" description="I/O configuration register for pin P3[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[8]">
-        <Enum name="P3_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_8" start="0x1" description="External memory data line 8." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1A4" size="4" name="P3_9" access="Read/Write" description="I/O configuration register for pin P3[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[9]">
-        <Enum name="P3_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_9" start="0x1" description="External memory data line 9." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="P3_10" access="Read/Write" description="I/O configuration register for pin P3[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[10]">
-        <Enum name="P3_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_10" start="0x1" description="External memory data line 10." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1AC" size="4" name="P3_11" access="Read/Write" description="I/O configuration register for pin P3[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[11]">
-        <Enum name="P3_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_11" start="0x1" description="External memory data line 11." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1B0" size="4" name="P3_12" access="Read/Write" description="I/O configuration register for pin P3[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[12]">
-        <Enum name="P3_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_12" start="0x1" description="External memory data line 12." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1B4" size="4" name="P3_13" access="Read/Write" description="I/O configuration register for pin P3[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[13]">
-        <Enum name="P3_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_13" start="0x1" description="External memory data line 13." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1B8" size="4" name="P3_14" access="Read/Write" description="I/O configuration register for pin P3[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[14]">
-        <Enum name="P3_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_14" start="0x1" description="External memory data line 14. " />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1BC" size="4" name="P3_15" access="Read/Write" description="I/O configuration register for pin P3[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[15]">
-        <Enum name="P3_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_15" start="0x1" description="External memory data line 15. " />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C0" size="4" name="P3_16" access="Read/Write" description="I/O configuration register for pin P3[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[16]">
-        <Enum name="P3_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_16" start="0x1" description="External memory data line 16." />
-        <Enum name="PWM0_1" start="0x2" description="Pulse Width Modulator 0, output 1." />
-        <Enum name="U1_TXD" start="0x3" description="Transmitter output for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="P3_17" access="Read/Write" description="I/O configuration register for pin P3[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[17]">
-        <Enum name="P3_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_17" start="0x1" description="External memory data line 17." />
-        <Enum name="PWM0_2" start="0x2" description="Pulse Width Modulator 0, output 2." />
-        <Enum name="U1_RXD" start="0x3" description="Receiver input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="P3_18" access="Read/Write" description="I/O configuration register for pin P3[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[18]">
-        <Enum name="P3_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_18" start="0x1" description="External memory data line 18." />
-        <Enum name="PWM0_3" start="0x2" description="Pulse Width Modulator 0, output 3." />
-        <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1CC" size="4" name="P3_19" access="Read/Write" description="I/O configuration register for pin P3[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[19]">
-        <Enum name="P3_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_19" start="0x1" description="External memory data line 19." />
-        <Enum name="PWM0_4" start="0x2" description="Pulse Width Modulator 0, output 4." />
-        <Enum name="U1_DCD" start="0x3" description="Data Carrier Detect input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1D0" size="4" name="P3_20" access="Read/Write" description="I/O configuration register for pin P3[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[20]">
-        <Enum name="P3_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_20" start="0x1" description="External memory data line 20." />
-        <Enum name="PWM0_5" start="0x2" description="Pulse Width Modulator 0, output 5." />
-        <Enum name="U1_DSR" start="0x3" description="Data Set Ready input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1D4" size="4" name="P3_21" access="Read/Write" description="I/O configuration register for pin P3[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[21]">
-        <Enum name="P3_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_21" start="0x1" description="External memory data line 21." />
-        <Enum name="PWM0_6" start="0x2" description="Pulse Width Modulator 0, output 6." />
-        <Enum name="U1_DTR" start="0x3" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1D8" size="4" name="P3_22" access="Read/Write" description="I/O configuration register for pin P3[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[22]">
-        <Enum name="P3_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_22" start="0x1" description="External memory data line 22." />
-        <Enum name="PWM0_CAP0" start="0x2" description="Capture input for PWM0, channel 0." />
-        <Enum name="U1_RI" start="0x3" description="Ring Indicator input for UART1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1DC" size="4" name="P3_23" access="Read/Write" description="I/O configuration register for pin P3[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[23]">
-        <Enum name="P3_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_23" start="0x1" description="External memory data line 23." />
-        <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." />
-        <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1E0" size="4" name="P3_24" access="Read/Write" description="I/O configuration register for pin P3[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[24]">
-        <Enum name="P3_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_24" start="0x1" description="External memory data line 24." />
-        <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, output 1." />
-        <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1E4" size="4" name="P3_25" access="Read/Write" description="I/O configuration register for pin P3[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[25]">
-        <Enum name="P3_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_25" start="0x1" description="External memory data line 25." />
-        <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, output 2." />
-        <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1E8" size="4" name="P3_26" access="Read/Write" description="I/O configuration register for pin P3[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[26]">
-        <Enum name="P3_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_26" start="0x1" description="External memory data line 26." />
-        <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, output 3." />
-        <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." />
-        <Enum name="STCLK" start="0x4" description="System tick timer clock input." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1EC" size="4" name="P3_27" access="Read/Write" description="I/O configuration register for pin P3[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[27]">
-        <Enum name="P3_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_27" start="0x1" description="External memory data line 27." />
-        <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, output 4." />
-        <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1F0" size="4" name="P3_28" access="Read/Write" description="I/O configuration register for pin P3[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[28]">
-        <Enum name="P3_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_28" start="0x1" description="External memory data line 28." />
-        <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, output 5." />
-        <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1F4" size="4" name="P3_29" access="Read/Write" description="I/O configuration register for pin P3[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[29]">
-        <Enum name="P3_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_29" start="0x1" description="External memory data line 29." />
-        <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, output 6." />
-        <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1F8" size="4" name="P3_30" access="Read/Write" description="I/O configuration register for pin P3[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[30]">
-        <Enum name="P3_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_30" start="0x1" description="External memory data line 30." />
-        <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
-        <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1FC" size="4" name="P3_31" access="Read/Write" description="I/O configuration register for pin P3[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[31]">
-        <Enum name="P3_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_D_31" start="0x1" description="External memory data line 31." />
-        <Enum name="T1_MAT2" start="0x3" description="Match output for Timer 1, channel 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="P4_0" access="Read/Write" description="I/O configuration register for pin P4[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[0]">
-        <Enum name="P4_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_0" start="0x1" description="External memory address line 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x204" size="4" name="P4_1" access="Read/Write" description="I/O configuration register for pin P4[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[1]">
-        <Enum name="P4_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_1" start="0x1" description="External memory address line 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x208" size="4" name="P4_2" access="Read/Write" description="I/O configuration register for pin P4[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[2]">
-        <Enum name="P4_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_2" start="0x1" description="External memory address line 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x20C" size="4" name="P4_3" access="Read/Write" description="I/O configuration register for pin P4[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[3]">
-        <Enum name="P4_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_3" start="0x1" description="External memory address line 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x210" size="4" name="P4_4" access="Read/Write" description="I/O configuration register for pin P4[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[4]">
-        <Enum name="P4_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_4" start="0x1" description="External memory address line 4." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x214" size="4" name="P4_5" access="Read/Write" description="I/O configuration register for pin P4[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[5]">
-        <Enum name="P4_5" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_5" start="0x1" description="External memory address line 5." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x218" size="4" name="P4_6" access="Read/Write" description="I/O configuration register for pin P4[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[6]">
-        <Enum name="P4_6" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_6" start="0x1" description="External memory address line 6." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x21C" size="4" name="P4_7" access="Read/Write" description="I/O configuration register for pin P4[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[7]">
-        <Enum name="P4_7" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_7" start="0x1" description="External memory address line 7." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x220" size="4" name="P4_8" access="Read/Write" description="I/O configuration register for pin P4[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[8]">
-        <Enum name="P4_8" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_8" start="0x1" description="External memory address line 8." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x224" size="4" name="P4_9" access="Read/Write" description="I/O configuration register for pin P4[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[9]">
-        <Enum name="P4_9" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_9" start="0x1" description="External memory address line 9." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x228" size="4" name="P4_10" access="Read/Write" description="I/O configuration register for pin P4[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[10]">
-        <Enum name="P4_10" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_10" start="0x1" description="External memory address line 10." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x22C" size="4" name="P4_11" access="Read/Write" description="I/O configuration register for pin P4[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[11]">
-        <Enum name="P4_11" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_11" start="0x1" description="External memory address line 11." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x230" size="4" name="P4_12" access="Read/Write" description="I/O configuration register for pin P4[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[12]">
-        <Enum name="P4_12" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_12" start="0x1" description="External memory address line 12." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x234" size="4" name="P4_13" access="Read/Write" description="I/O configuration register for pin P4[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[13]">
-        <Enum name="P4_13" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_13" start="0x1" description="External memory address line 13." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x238" size="4" name="P4_14" access="Read/Write" description="I/O configuration register for pin P4[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[14]">
-        <Enum name="P4_14" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_14" start="0x1" description="External memory address line 14." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x23C" size="4" name="P4_15" access="Read/Write" description="I/O configuration register for pin P4[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[15]">
-        <Enum name="P4_15" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_15" start="0x1" description="External memory address line 15." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240" size="4" name="P4_16" access="Read/Write" description="I/O configuration register for pin P4[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[16]">
-        <Enum name="P4_16" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_16" start="0x1" description="External memory address line 16." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x244" size="4" name="P4_17" access="Read/Write" description="I/O configuration register for pin P4[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[17]">
-        <Enum name="P4_17" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_17" start="0x1" description="External memory address line 17." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x248" size="4" name="P4_18" access="Read/Write" description="I/O configuration register for pin P4[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[18]">
-        <Enum name="P4_18" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_18" start="0x1" description="External memory address line 18." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x24C" size="4" name="P4_19" access="Read/Write" description="I/O configuration register for pin P4[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[19]">
-        <Enum name="P4_19" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_19" start="0x1" description="External memory address line 19." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x250" size="4" name="P4_20" access="Read/Write" description="I/O configuration register for pin P4[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[20]">
-        <Enum name="P4_20" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_20" start="0x1" description="External memory address line 20." />
-        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="SSP1_SCK" start="0x3" description="Serial Clock for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x254" size="4" name="P4_21" access="Read/Write" description="I/O configuration register for pin P4[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[21]">
-        <Enum name="P4_21" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_21" start="0x1" description="External memory address line 21." />
-        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="SSP1_SSEL" start="0x3" description="Slave Select for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x258" size="4" name="P4_22" access="Read/Write" description="I/O configuration register for pin P4[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[22]">
-        <Enum name="P4_22" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_22" start="0x1" description="External memory address line 22." />
-        <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." />
-        <Enum name="SSP1_MISO" start="0x3" description="Master In Slave Out for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x25C" size="4" name="P4_23" access="Read/Write" description="I/O configuration register for pin P4[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[23]">
-        <Enum name="P4_23" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_23" start="0x1" description="External memory address line 23." />
-        <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." />
-        <Enum name="SSP1_MOSI" start="0x3" description="Master Out Slave In for SSP1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x260" size="4" name="P4_24" access="Read/Write" description="I/O configuration register for pin P4[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[24]">
-        <Enum name="P4_24" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_OE" start="0x1" description="LOW active Output Enable signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x264" size="4" name="P4_25" access="Read/Write" description="I/O configuration register for pin P4[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[25]">
-        <Enum name="P4_25" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_WE" start="0x1" description="LOW active Write Enable signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x268" size="4" name="P4_26" access="Read/Write" description="I/O configuration register for pin P4[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[26]">
-        <Enum name="P4_26" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS0" start="0x1" description="LOW active Byte Lane select signal 0." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x26C" size="4" name="P4_27" access="Read/Write" description="I/O configuration register for pin P4[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[27]">
-        <Enum name="P4_27" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS1" start="0x1" description="LOW active Byte Lane select signal 1." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x270" size="4" name="P4_28" access="Read/Write" description="I/O configuration register for pin P4[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[28]">
-        <Enum name="P4_28" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS2" start="0x1" description="LOW active Byte Lane select signal 2." />
-        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
-        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
-        <Enum name="LCD_VD_6" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_10" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_2" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x274" size="4" name="P4_29" access="Read/Write" description="I/O configuration register for pin P4[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[29]">
-        <Enum name="P4_29" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_BLS3" start="0x1" description="LOW active Byte Lane select signal 3." />
-        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
-        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
-        <Enum name="I2C2_SCL" start="0x4" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
-        <Enum name="LCD_VD_7" start="0x5" description="LCD data." />
-        <Enum name="LCD_VD_11" start="0x6" description="LCD data." />
-        <Enum name="LCD_VD_3" start="0x7" description="LCD data." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x278" size="4" name="P4_30" access="Read/Write" description="I/O configuration register for pin P4[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[30]">
-        <Enum name="P4_30" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS0" start="0x1" description="LOW active Chip Select 0 signal." />
-        <Enum name="CMP0_OUT" start="0x5" description="Comparator 0, output." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x27C" size="4" name="P4_31" access="Read/Write" description="I/O configuration register for pin P4[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[31]">
-        <Enum name="P4_31" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_CS1" start="0x1" description="LOW active Chip Select 1 signal." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x280" size="4" name="P5_0" access="Read/Write" description="I/O configuration register for pin P5[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[0]">
-        <Enum name="P5_0" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_24" start="0x1" description="External memory address line 24." />
-        <Enum name="SSP2_MOSI" start="0x2" description="Master Out Slave In for SSP2." />
-        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x284" size="4" name="P5_1" access="Read/Write" description="I/O configuration register for pin P5[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[1]">
-        <Enum name="P5_1" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="EMC_A_25" start="0x1" description="External memory address line 25." />
-        <Enum name="SSP2_MISO" start="0x2" description="Master In Slave Out for SSP2." />
-        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x288" size="4" name="P5_2" access="Read/Write" description="I/O configuration register for pin P5[2]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[2]">
-        <Enum name="P5_2" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
-        <Enum name="I2C0_SDA" start="0x5" description="I2C0 data input/output (this                                     pin uses a specialized I2C pad that                                     supports I2C Fast Mode                                     Plus)." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x28C" size="4" name="P5_3" access="Read/Write" description="I/O configuration register for pin P5[3]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[3]">
-        <Enum name="P5_3" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U4_RXD" start="0x4" description="Receiver input for USART4." />
-        <Enum name="I2C0_SCL" start="0x5" description="I2C0 clock input/output (this                                     pin uses a specialized I2C pad that                                     supports I2C Fast Mode                                     Plus." />
-      </BitField>
-      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
-        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
-        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
-        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
-        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x290" size="4" name="P5_4" access="Read/Write" description="I/O configuration register for pin P5[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[4]">
-        <Enum name="P5_4" start="0x0" description="General purpose digital input/output pin." />
-        <Enum name="U0_OE" start="0x1" description="RS-485/EIA-485 output enable signal for                                     UART0." />
-        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
-        <Enum name="U4_TXD" start="0x4" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
-      </BitField>
-      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
-        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
-        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
-        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
-        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
-      </BitField>
-      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="ENABLE_" start="1" description="Enable." />
-      </BitField>
-      <BitField start="6" size="1" name="INV" description="Invert input">
-        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
-        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
-      </BitField>
-      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
-        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
-        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
-      </BitField>
-      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
-        <Enum name="DISABLE_" start="0" description="Disable." />
-        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC)">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
-        <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
-      </BitField>
-      <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="21" size="1" name="PDN" description="Power down mode">
-        <Enum name="POWERED" start="1" description="The A/D converter is operational." />
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
-        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
-        <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
-        <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
-        <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
-        <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
-        <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
-        <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
-      </BitField>
-      <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
-      </BitField>
-      <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
-      </BitField>
-      <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
-        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
-        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
-        <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
-        <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
-      <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
-      <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
-      <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
-      <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
-      <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
-      <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
-      <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
-      <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
-      <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
-      <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
-      <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
-      <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
-      <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
-      <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
-      <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
-      <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
-    <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-    <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CANAF" start="0x4003C000" description="CAN controller">
-    <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
-      <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
-      <BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
-        <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
-        <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
-    </Register>
-    <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCAN" start="0x40040000" description=" CAN controller">
-    <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
-      <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
-      <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
-      <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
-      <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
-      <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
-      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
-      <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
-      <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN1" start="0x40044000" description="CAN controller  ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CAN2" start="0x40048000" description="CAN controller  ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RM" description="Reset Mode.">
-        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
-        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
-      </BitField>
-      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
-        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
-        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
-      </BitField>
-      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
-        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
-        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
-      </BitField>
-      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
-        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
-        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
-      </BitField>
-      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
-        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
-        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
-      </BitField>
-      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
-        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
-        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TM" description="Test Mode.">
-        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
-        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TR" description="Transmission Request.">
-        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
-      </BitField>
-      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
-        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
-        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
-      </BitField>
-      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
-        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
-        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
-      </BitField>
-      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
-        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
-        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
-      </BitField>
-      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
-        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
-        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
-      </BitField>
-      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
-      </BitField>
-      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
-      </BitField>
-      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
-        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
-        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
-        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
-        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
-      </BitField>
-      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
-        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
-        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
-      </BitField>
-      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
-        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
-        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
-        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
-        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
-      </BitField>
-      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
-        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
-      </BitField>
-      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
-        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
-        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
-      </BitField>
-      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
-        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
-        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
-      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
-        <Enum name="RESET" start="0" description="Reset" />
-        <Enum name="SET" start="1" description="Set" />
-      </BitField>
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
-      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
-        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
-        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
-      </BitField>
-      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
-        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
-        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
-        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
-        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
-      </BitField>
-      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
-    </Register>
-    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
-      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
-      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
-      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
-      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
-      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
-      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
-      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
-      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
-      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
-      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
-      <BitField start="23" size="1" name="SAM" description="Sampling">
-        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
-        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
-      </BitField>
-      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
-      </BitField>
-      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
-      </BitField>
-      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
-      </BitField>
-      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
-      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
-      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
-        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
-        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
-      </BitField>
-      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
-        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
-        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
-      </BitField>
-      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
-      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
-        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
-        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
-      </BitField>
-      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
-      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
-      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
-      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
-    </Register>
-    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
-      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
-      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
-    </Register>
-    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
-      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
-      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
-      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x4008C000" description="Digital-to-Analog Converter (DAC) Modification">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
-        <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
-        <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
-        <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
-        <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE" start="1" description="Enable" />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA access">
-        <Enum name="DISABLE" start="0" description="Disable" />
-        <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x40090000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x40094000" description=" Timer0/1/2/3 ">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
-        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
-        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
-        <Enum name="DISABLE" start="0" description="This feature is disabled." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
-        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
-        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
-        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
-        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART4" start="0x400A4000" description="UART4  ">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="The UART4 Receiver Buffer Register contains the oldest received byte in the UART4 Rx FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Writing to the UART4 Transmit Holding Register causes the data to be stored in the UART4 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="The UART4 Divisor Latch LSB Register, along with the U4DLM register, determines the baud rate of the UART4." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="The UART4 Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART4." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
-        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
-        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
-        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
-        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
-        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that U4IIR[0] is active low. The pending interrupt can be determined by evaluating U4IIR[3:1].">
-        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
-        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. U4IER[3:1] identifies an interrupt corresponding to the UART4 Rx or TX FIFO. All other combinations of U4IER[3:1] not listed below are reserved (000,100,101,111).">
-        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
-        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
-        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
-        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of U4FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
-        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
-        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
-        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
-        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select">
-        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
-        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control">
-        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
-        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
-        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
-        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
-        <Enum name="THE_UARTN_RECEIVER_F" start="0" description="The UARTn receiver FIFO is empty." />
-        <Enum name="THE_UARTN_RECEIVER_F" start="1" description="The UARTn receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
-        <Enum name="OVERRUN_ERROR_STATUS" start="0" description="Overrun error status is inactive." />
-        <Enum name="OVERRUN_ERROR_STATUS" start="1" description="Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="PARITY_ERROR_STATUS_" start="0" description="Parity error status is inactive." />
-        <Enum name="PARITY_ERROR_STATUS_" start="1" description="Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="FRAMING_ERROR_STATUS" start="0" description="Framing error status is inactive." />
-        <Enum name="FRAMING_ERROR_STATUS" start="1" description="Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
-        <Enum name="UNTHR_CONTAINS_VALID" start="0" description="UnTHR contains valid data." />
-        <Enum name="UNTHR_IS_EMPTY_" start="1" description="UnTHR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
-        <Enum name="VALID_DATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
-        <Enum name="UNRBR_CONTAINS_NO_UA" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
-        <Enum name="UARTN_RBR_CONTAINS_A" start="1" description="UARTn RBR contains at least one UARTn RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
-        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0_" start="0" description="Mode 0." />
-        <Enum name="MODE_1_" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART_" start="0" description="No restart." />
-        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
-        <Enum name="NO_IMPACT_" start="0" description="No impact." />
-        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode">
-        <Enum name="DISABLED_IRDA_MODE_" start="0" description="Disabled. IrDA mode on UART4 is disabled, UART4 acts as a standard UART." />
-        <Enum name="ENABLED_IRDA_MODE_O" start="1" description="Enabled. IrDA mode on UART4 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED_" start="0" description="Not inverted." />
-        <Enum name="INVERTED_THIS_HAS_N" start="1" description="Inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1.">
-        <Enum name="2XTPCLK" start="0x0" description="2xTPCLK" />
-        <Enum name="4XTPCLK" start="0x1" description="4xTPCLK" />
-        <Enum name="8XTPCLK" start="0x2" description="8xTPCLK" />
-        <Enum name="16XTPCLK" start="0x3" description="16xTPCLK" />
-        <Enum name="32XTPCLK" start="0x4" description="32xTPCLK" />
-        <Enum name="64XTPCLK" start="0x5" description="64xTPCLK" />
-        <Enum name="128XTPCLK" start="0x6" description="128xTPCLK" />
-        <Enum name="256XTPCLK" start="0x7" description="256xTPCLK" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud Rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART4 baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud Rate pre-scaler multiplier value. This field must be greater or equal 1 for UART4 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In smartcard mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface control register. Enables and configures the smartcard Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
-        <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="A_NACK_RESPONSE_IS_E" start="0" description="A NACK response is enabled." />
-        <Enum name="A_NACK_RESPONSE_IS_I" start="1" description="A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. See Section 20.6.18 RS-485/EIA-485 modes of operation." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED_" start="0" description="Enabled." />
-        <Enum name="DISABLED_" start="1" description="Disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLED_" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
-        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW_THE_DIRECTION_C" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH_THE_DIRECTION_" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (U4OE) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
-        <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Falling edge sampling.">
-        <Enum name="RXD_IS_SAMPLED_ON_TH" start="0" description="RxD is sampled on the rising edge of SCLK" />
-        <Enum name="RXD_IS_SAMPLED_ON_TH" start="1" description="RxD is sampled on the falling edge of SCLK" />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="THE_INPUT_CLOCK_IS_S" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="THE_INPUT_CLOCK_IS_N" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
-        <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." />
-        <Enum name="NOSTARTSTOPBIT" start="1" description="Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
-        <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI)  ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on PHA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay for PhA." />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on PHB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay for PhB." />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on IDX" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay for the index." />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width." />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
-      <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
-      <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
-      <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
-      <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
-      <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
-      <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
-      <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
-      <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
-      <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
-      <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
-      <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
-      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
-      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
-      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
-      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
-      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
-      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
-      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
-      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
-      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
-      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
-      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
-      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
-      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
-      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
-      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x400C0000" description="SD card">
-    <Register start="+0x000" size="4" name="PWR" access="Read/Write" description="Power control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTRL" description="Power control">
-        <Enum name="POWER_OFF" start="0x0" description="Power-off" />
-        <Enum name="POWER_UP" start="0x2" description="Power-up" />
-        <Enum name="POWER_ON" start="0x3" description="Power-on" />
-      </BitField>
-      <BitField start="2" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="6" size="1" name="OPENDRAIN" description="SD_CMD output control." />
-      <BitField start="7" size="1" name="ROD" description="Rod control." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x004" size="4" name="CLOCK" access="Read/Write" description="Clock control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLKDIV" description="Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)]." />
-      <BitField start="8" size="1" name="ENABLE" description="Enable SD card bus clock:">
-        <Enum name="CLOCK_DISABLED_" start="0" description="Clock disabled." />
-        <Enum name="CLOCK_ENABLED_" start="1" description="Clock enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="PWRSAVE" description="Disable SD_CLK output when bus is idle:">
-        <Enum name="ALWAYS_ENABLED_" start="0" description="Always enabled." />
-        <Enum name="CLOCK_ENABLED_WHEN_B" start="1" description="Clock enabled when bus is active." />
-      </BitField>
-      <BitField start="10" size="1" name="BYPASS" description="Enable bypass of clock divide logic:">
-        <Enum name="DISABLE_BYPASS_" start="0" description="Disable bypass." />
-        <Enum name="ENABLE_BYPASS_MCLK_" start="1" description="Enable bypass. MCLK driven to card bus output (SD_CLK)." />
-      </BitField>
-      <BitField start="11" size="1" name="WIDEBUS" description="Enable wide bus mode.">
-        <Enum name="STANDARD_BUS_MODE_O" start="0" description="Standard bus mode (only SD_DAT[0] used)." />
-        <Enum name="WIDE_BUS_MODE_SD_DA" start="1" description="Wide bus mode (SD_DAT[3:0] used)" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="ARGUMENT" access="Read/Write" description="Argument register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CmdArg" description="Command argument" />
-    </Register>
-    <Register start="+0x00C" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CmdIndex" description="Command index." />
-      <BitField start="6" size="1" name="Response" description="If set, CPSM waits for a response." />
-      <BitField start="7" size="1" name="LongRsp" description="If set, CPSM receives a 136 bit long response." />
-      <BitField start="8" size="1" name="Interrupt" description="If set, CPSM disables command timer and waits for interrupt request." />
-      <BitField start="9" size="1" name="Pending" description="If set, CPSM waits for CmdPend before it starts sending a command." />
-      <BitField start="10" size="1" name="Enable" description="If set, CPSM is enabled." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="RESPCMD" access="ReadOnly" description="Response command register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESPCMD" description="Response command index" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x014+0" size="4" name="RESPONSE0" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x014+4" size="4" name="RESPONSE1" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x014+8" size="4" name="RESPONSE2" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x014+12" size="4" name="RESPONSE3" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="STATUS" description="Card status" />
-    </Register>
-    <Register start="+0x024" size="4" name="DATATIMER" access="Read/Write" description="Data Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATATIME" description="Data timeout period." />
-    </Register>
-    <Register start="+0x028" size="4" name="DATALENGTH" access="Read/Write" description="Data length register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATALENGTH" description="Data length value" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATACTRL" access="Read/Write" description="Data control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Data transfer enable." />
-      <BitField start="1" size="1" name="DIRECTION" description="Data transfer direction">
-        <Enum name="FROM_CONTROLLER_TO_C" start="0" description="From controller to card." />
-        <Enum name="FROM_CARD_TO_CONTROL" start="1" description="From card to controller." />
-      </BitField>
-      <BitField start="2" size="1" name="MODE" description="Data transfer mode">
-        <Enum name="BLOCK_DATA_TRANSFER_" start="0" description="Block data transfer." />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAENABLE" description="Enable DMA">
-        <Enum name="DMA_DISABLED_" start="0" description="DMA disabled." />
-        <Enum name="DMA_ENABLED_" start="1" description="DMA enabled." />
-      </BitField>
-      <BitField start="4" size="4" name="BLOCKSIZE" description="Data block length" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x030" size="4" name="DATACNT" access="ReadOnly" description="Data counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATACOUNT" description="Remaining data" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x034" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CMDCRCFAIL" description="Command response received (CRC check failed)." />
-      <BitField start="1" size="1" name="DATACRCFAIL" description="Data block sent/received (CRC check failed)." />
-      <BitField start="2" size="1" name="CMDTIMEOUT" description="Command response timeout." />
-      <BitField start="3" size="1" name="DATATIMEOUT" description="Data timeout." />
-      <BitField start="4" size="1" name="TXUNDERRUN" description="Transmit FIFO underrun error." />
-      <BitField start="5" size="1" name="RXOVERRUN" description="Receive FIFO overrun error." />
-      <BitField start="6" size="1" name="CMDRESPEND" description="Command response received (CRC check passed)." />
-      <BitField start="7" size="1" name="CMDSENT" description="Command sent (no response required)." />
-      <BitField start="8" size="1" name="DATAEND" description="Data end (data counter is zero)." />
-      <BitField start="9" size="1" name="STARTBITERR" description="Start bit not detected on all data signals in wide bus mode." />
-      <BitField start="10" size="1" name="DATABLOCKEND" description="Data block sent/received (CRC check passed)." />
-      <BitField start="11" size="1" name="CMDACTIVE" description="Command transfer in progress." />
-      <BitField start="12" size="1" name="TXACTIVE" description="Data transmit in progress." />
-      <BitField start="13" size="1" name="RXACTIVE" description="Data receive in progress." />
-      <BitField start="14" size="1" name="TXFIFOHALFEMPTY" description="Transmit FIFO half empty." />
-      <BitField start="15" size="1" name="RXFIFOHALFFULL" description="Receive FIFO half full." />
-      <BitField start="16" size="1" name="TXFIFOFULL" description="Transmit FIFO full." />
-      <BitField start="17" size="1" name="RXFIFOFULL" description="Receive FIFO full." />
-      <BitField start="18" size="1" name="TXFIFOEMPTY" description="Transmit FIFO empty." />
-      <BitField start="19" size="1" name="RXFIFOEMPTY" description="Receive FIFO empty." />
-      <BitField start="20" size="1" name="TXDATAAVLBL" description="Data available in transmit FIFO." />
-      <BitField start="21" size="1" name="RXDATAAVLBL" description="Data available in receive FIFO." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="CLEAR" access="WriteOnly" description="Clear register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CMDCRCFAILCLR" description="Clears CmdCrcFail flag." />
-      <BitField start="1" size="1" name="DATACRCFAILCLR" description="Clears DataCrcFail flag." />
-      <BitField start="2" size="1" name="CMDTIMEOUTCLR" description="Clears CmdTimeOut flag." />
-      <BitField start="3" size="1" name="DATATIMEOUTCLR" description="Clears DataTimeOut flag." />
-      <BitField start="4" size="1" name="TXUNDERRUNCLR" description="Clears TxUnderrun flag." />
-      <BitField start="5" size="1" name="RXOVERRUNCLR" description="Clears RxOverrun flag." />
-      <BitField start="6" size="1" name="CMDRESPENDCLR" description="Clears CmdRespEnd flag." />
-      <BitField start="7" size="1" name="CMDSENTCLR" description="Clears CmdSent flag." />
-      <BitField start="8" size="1" name="DATAENDCLR" description="Clears DataEnd flag." />
-      <BitField start="9" size="1" name="STARTBITERRCLR" description="Clears StartBitErr flag." />
-      <BitField start="10" size="1" name="DATABLOCKENDCLR" description="Clears DataBlockEnd flag." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x03C" size="4" name="MASK0" access="Read/Write" description="Interrupt 0 mask register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASK0" description="Mask CmdCrcFail flag." />
-      <BitField start="1" size="1" name="MASK1" description="Mask DataCrcFail flag." />
-      <BitField start="2" size="1" name="MASK2" description="Mask CmdTimeOut flag." />
-      <BitField start="3" size="1" name="MASK3" description="Mask DataTimeOut flag." />
-      <BitField start="4" size="1" name="MASK4" description="Mask TxUnderrun flag." />
-      <BitField start="5" size="1" name="MASK5" description="Mask RxOverrun flag." />
-      <BitField start="6" size="1" name="MASK6" description="Mask CmdRespEnd flag." />
-      <BitField start="7" size="1" name="MASK7" description="Mask CmdSent flag." />
-      <BitField start="8" size="1" name="MASK8" description="Mask DataEnd flag." />
-      <BitField start="9" size="1" name="MASK9" description="Mask StartBitErr flag." />
-      <BitField start="10" size="1" name="MASK10" description="Mask DataBlockEnd flag." />
-      <BitField start="11" size="1" name="MASK11" description="Mask CmdActive flag." />
-      <BitField start="12" size="1" name="MASK12" description="Mask TxActive flag." />
-      <BitField start="13" size="1" name="MASK13" description="Mask RxActive flag." />
-      <BitField start="14" size="1" name="MASK14" description="Mask TxFifoHalfEmpty flag." />
-      <BitField start="15" size="1" name="MASK15" description="Mask RxFifoHalfFull flag." />
-      <BitField start="16" size="1" name="MASK16" description="Mask TxFifoFull flag." />
-      <BitField start="17" size="1" name="MASK17" description="Mask RxFifoFull flag." />
-      <BitField start="18" size="1" name="MASK18" description="Mask TxFifoEmpty flag." />
-      <BitField start="19" size="1" name="MASK19" description="Mask RxFifoEmpty flag." />
-      <BitField start="20" size="1" name="MASK20" description="Mask TxDataAvlbl flag." />
-      <BitField start="21" size="1" name="MASK21" description="Mask RxDataAvlbl flag." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x048" size="4" name="FIFOCNT" access="ReadOnly" description="FIFO Counter." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="15" name="DATACOUNT" description="Remaining data" />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x080+0" size="4" name="FIFO0" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+4" size="4" name="FIFO1" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+8" size="4" name="FIFO2" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+12" size="4" name="FIFO3" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+16" size="4" name="FIFO4" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+20" size="4" name="FIFO5" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+24" size="4" name="FIFO6" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+28" size="4" name="FIFO7" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+32" size="4" name="FIFO8" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+36" size="4" name="FIFO9" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+40" size="4" name="FIFO10" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+44" size="4" name="FIFO11" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+48" size="4" name="FIFO12" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+52" size="4" name="FIFO13" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+56" size="4" name="FIFO14" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-    <Register start="+0x080+60" size="4" name="FIFO15" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="FIFO data." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SYSCON" start="0x400FC000" description=" System and clock control ">
-    <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. All other values are reserved.">
-        <Enum name="FLASH_ACCESSES_USE_1" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_2" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_3" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_4" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost off. Use this setting for operation from 100 to 120 MHz operation with power boost on." />
-        <Enum name="FLASH_ACCESSES_USE_5" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost off." />
-        <Enum name="FLASH_ACCESSES_USE_6" start="0x5" description="Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x080+0" size="4" name="PLLCON0" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x080+32" size="4" name="PLLCON1" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x084+0" size="4" name="PLLCFG0" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value &quot;M&quot; in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." />
-      <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value &quot;P&quot; in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x084+32" size="4" name="PLLCFG1" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value &quot;M&quot; in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." />
-      <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value &quot;P&quot; in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x088+0" size="4" name="PLLSTAT0" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." />
-      <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x088+32" size="4" name="PLLSTAT1" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." />
-      <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x08C+0" size="4" name="PLLFEED0" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x08C+32" size="4" name="PLLFEED1" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details." />
-      <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details." />
-      <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection." />
-      <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x0C4" size="4" name="PCONP0" access="Read/Write" description="Power Control for Peripherals" reset_value="0x0408829E" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PCLCD" description="LCD controller power/clock control bit." />
-      <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
-      <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
-      <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
-      <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
-      <BitField start="5" size="1" name="PCPWM0" description="PWM0 power/clock control bit." />
-      <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
-      <BitField start="7" size="1" name="PCI2C0" description="I2C0 interface power/clock control bit." />
-      <BitField start="8" size="1" name="PCUART4" description="UART4 power/clock control bit." />
-      <BitField start="9" size="1" name="PCRTC" description="RTC and Event Monitor/Recorder power/clock control bit." />
-      <BitField start="10" size="1" name="PCSSP1" description="SSP 1 interface power/clock control bit." />
-      <BitField start="11" size="1" name="PCEMC" description="External Memory Controller power/clock control bit." />
-      <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before attempting to set PDN." />
-      <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
-      <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
-      <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
-      <BitField start="16" size="1" name="PCSPIFI" description="SPI Flash Interface power/clock control bit." />
-      <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM power/clock control bit." />
-      <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
-      <BitField start="19" size="1" name="PCI2C1" description="I2C1 interface power/clock control bit." />
-      <BitField start="20" size="1" name="PCSSP2" description="SSP2 interface power/clock control bit." />
-      <BitField start="21" size="1" name="PCSSP0" description="SSP0 interface power/clock control bit." />
-      <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
-      <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
-      <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
-      <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
-      <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
-      <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
-      <BitField start="28" size="1" name="PCSDC" description="SD Card interface power/clock control bit." />
-      <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
-      <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
-      <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
-    </Register>
-    <Register start="+0x0C8" size="4" name="PCONP1" access="Read/Write" description="Power Control for Peripherals" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PCCMP" description="comparator 0/1 power/clock control bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="EMCCLKSEL" access="Read/Write" description="External Memory Controller Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EMCDIV" description="Selects the EMC clock rate relative to the CPU clock.">
-        <Enum name="THE_EMC_USES_THE_SAM" start="0" description="The EMC uses the same clock as the CPU." />
-        <Enum name="THE_EMC_USES_A_CLOCK" start="1" description="The EMC uses a clock at half the rate of the CPU." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x104" size="4" name="CCLKSEL" access="Read/Write" description="CPU Clock Selection register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="5" name="CCLKDIV" description="Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. ... 31 = The input clock is divided by 31 to produce the CPU clock." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="CCLKSEL" description="Selects the input clock for the CPU clock divider.">
-        <Enum name="SYSCLK_IS_USED_AS_TH" start="0" description="Sysclk is used as the input to the CPU clock divider." />
-        <Enum name="THE_OUTPUT_OF_THE_MA" start="1" description="The output of the Main PLL is used as the input to the CPU clock divider." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x108" size="4" name="USBCLKSEL" access="Read/Write" description="USB Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="USBDIV" description="Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation.">
-        <Enum name="THE_DIVIDER_IS_TURNE" start="0x0" description="The divider is turned off, no clock will be provided to the USB subsystem." />
-        <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x4" description="PLL0 output is divided by 4. PLL0 output must be 192 MHz." />
-        <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x6" description="PLL0 output is divided by 6. PLL0 output must be 288 MHz." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="USBSEL" description="Selects the input clock for the USB clock divider.">
-        <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions." />
-        <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the USB clock divider." />
-        <Enum name="ALTPLLOOUT" start="0x2" description="The output of the Alt PLL is used as the input to the USB clock divider." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKSRC" description="Selects the clock source for sysclk and PLL0 as follows:">
-        <Enum name="SELECTS_THE_INTERNAL" start="0" description="Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default)." />
-        <Enum name="SELECTS_THE_MAIN_OSC" start="1" description="Selects the main oscillator as the sysclk and PLL0 clock source." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
-      <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTMODE0" description="Level or edge sensitivity select for EINT0.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTMODE1" description="Level or edge sensitivity select for EINT1.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTMODE2" description="Level or edge sensitivity select for EINT2.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTMODE3" description="Level or edge sensitivity select for EINT3.">
-        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
-        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt polarity for EINT0.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE0)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE0)." />
-      </BitField>
-      <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt polarity for EINT1.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE1)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE1)." />
-      </BitField>
-      <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt polarity for EINT2.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE2)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE2)." />
-      </BitField>
-      <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt polarity for EINT3.">
-        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE3)." />
-        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE3)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
-      <BitField start="1" size="1" name="EXTR" description="Assertion of the external RESET signal sets this bit. This bit is cleared only by software or POR." />
-      <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
-      <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
-      <BitField start="4" size="1" name="SYSRESET" description="This bit is set if the processor has been reset due to a system reset request. Setting the SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is cleared only by software or POR." />
-      <BitField start="5" size="1" name="LOCKUP" description="This bit is set if the processor has been reset due to a &quot;lockup&quot;. The lockup state causes a chip reset. This bit is cleared only by software or POR." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x188" size="4" name="MATRIXARB" access="Read/Write" description="Matrix arbitration register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="PRI_ICODE" description="I-Code bus priority. Should be lower than PRI_DCODE for proper operation." />
-      <BitField start="2" size="2" name="PRI_DCODE" description="D-Code bus priority." />
-      <BitField start="4" size="2" name="PRI_SYS" description="System bus priority." />
-      <BitField start="6" size="2" name="PRI_GPDMA" description="General Purpose DMA controller priority." />
-      <BitField start="8" size="2" name="PRI_ETH" description="Ethernet DMA priority." />
-      <BitField start="10" size="2" name="PRI_LCD" description="LCD DMA priority." />
-      <BitField start="12" size="2" name="PRI_USB" description="USB DMA priority." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="1" name="ROM_LAT" description="ROM latency select. Should always be 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System Control and Status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EMCSC" description="EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter.">
-        <Enum name="STATIC_MEMORY_ADDRES" start="0" description="Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift." />
-        <Enum name="STATIC_MEMORY_ADDRES" start="1" description="Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices." />
-      </BitField>
-      <BitField start="1" size="1" name="EMCRD" description="EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter.">
-        <Enum name="BOTH_EMC_RESETS_ARE_" start="0" description="Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition." />
-        <Enum name="MANY_PORTIONS_OF_THE" start="1" description="Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset." />
-      </BitField>
-      <BitField start="2" size="1" name="EMCBC" description="External Memory Controller burst control. Also see Section 9.10 in the EMC chapter.">
-        <Enum name="BURST_ENABLED_" start="0" description="Burst enabled." />
-        <Enum name="BURST_DISABLED_THIS" start="1" description="Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices." />
-      </BitField>
-      <BitField start="3" size="1" name="MCIPWRAL" description="MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR.">
-        <Enum name="SD_PWR_IS_ACTIVE_LOW" start="0" description="SD_PWR is active low (inverted output of the SD Card interface block)." />
-        <Enum name="SD_PWR_IS_ACTIVE_HIG" start="1" description="SD_PWR is active high (follows the output of the SD Card interface block)." />
-      </BitField>
-      <BitField start="4" size="1" name="OSCRS" description="Main oscillator range select.">
-        <Enum name="THE_FREQUENCY_RANGE_" start="0" description="The frequency range of the main oscillator is 1 MHz to 20 MHz." />
-        <Enum name="THE_FREQUENCY_RANGE_" start="1" description="The frequency range of the main oscillator is 15 MHz to 25 MHz." />
-      </BitField>
-      <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
-        <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is disabled." />
-        <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
-      </BitField>
-      <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
-        <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is not ready to be used as a clock source." />
-        <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1A8" size="4" name="PCLKSEL" access="Read/Write" description="Peripheral Clock Selection register" reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCLKDIV" description="Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals. 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. ... 31 = The input clock is divided by 31 to produce the APB peripheral clock." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1B0" size="4" name="PBOOST" access="Read/Write" description="Power boost register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="Boost" description="Boost control bits. 00 : Boost is off, operation must be below 100 MHz. 11 : Boost is on, operation up to 120 MHz is supported. Other values are not allowed." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1B4" size="4" name="SPIFICLKSEL" access="Read/Write" description="SPIFI Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="SPIFIDIV" description="Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. ... 31 = The input clock is divided by 31 to produce the SPIFI clock." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="2" name="SPIFISEL" description="Selects the input clock for the USB clock divider.">
-        <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the SPIFI clock divider." />
-        <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the SPIFI clock divider." />
-        <Enum name="ALTPLLOUT" start="0x2" description="The output of the Alt PLL is used as the input to the SPIFI clock divider." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1B8" size="4" name="LCD_CFG" access="Read/Write" description="LCD Clock configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="CLKDIV" description="LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
-      <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
-      <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
-      <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
-      <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
-      <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
-      <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 3.12.8 &quot;Wake-up from Reduced Power Modes&quot; for details). Also see Section 3.10.3 &quot;PLLs and Power-down mode&quot; and Section 3.3.7 &quot;Power Control for Peripherals registers&quot; for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
-      <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
-    </Register>
-    <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMASEL00" description="Selects the DMA request for GPDMA input 0: 0 - (unused) 1 - Timer 0 match 0 is selected." />
-      <BitField start="1" size="1" name="DMASEL01" description="Selects the DMA request for GPDMA input 1: 0 - SD card interface is selected. 1 - Timer 0 match 1 is selected." />
-      <BitField start="2" size="1" name="DMASEL02" description="Selects the DMA request for GPDMA input 2: 0 - SSP0 transmit is selected. 1 - Timer 1 match 0 is selected." />
-      <BitField start="3" size="1" name="DMASEL03" description="Selects the DMA request for GPDMA input 3: 0 - SSP0 receive is selected. 1 - Timer 1 match 1 is selected." />
-      <BitField start="4" size="1" name="DMASEL04" description="Selects the DMA request for GPDMA input 4: 0 - SSP1 transmit is selected. 1 - Timer 2 match 0 is selected." />
-      <BitField start="5" size="1" name="DMASEL05" description="Selects the DMA request for GPDMA input 5: 0 - SSP1 receive is selected. 1 - Timer 2 match 1 is selected." />
-      <BitField start="6" size="1" name="DMASEL06" description="Selects the DMA request for GPDMA input 6: 0 - SSP2 transmit is selected. 1 - I2S channel 0 is selected." />
-      <BitField start="7" size="1" name="DMASEL07" description="Selects the DMA request for GPDMA input 7: 0 - SSP2 receive is selected. 1 - I2S channel 1 is selected." />
-      <BitField start="8" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - UART0 transmit is selected. 1 - UART3 transmit is selected." />
-      <BitField start="11" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - UART0 receive is selected. 1 - UART3 receive is selected." />
-      <BitField start="12" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - UART1 transmit is selected. 1 - UART4 transmit is selected." />
-      <BitField start="13" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - UART1 receive is selected. 1 - UART4 receive is selected." />
-      <BitField start="14" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - UART2 transmit is selected. 1 - Timer 3 match 0 is selected." />
-      <BitField start="15" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - UART2 receive is selected. 1 - Timer 3 match 1 is selected." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. 0x0 = Selects the CPU clock as the CLKOUT source. 0x1 = Selects the main oscillator as the CLKOUT source. 0x2 = Selects the Internal RC oscillator as the CLKOUT source. 0x3 = Selects the USB clock as the CLKOUT source. 0x4 = Selects the RTC oscillator as the CLKOUT source. 0x5 = Selects the SPIFI clock as the CLKOUT source. 0x6 = Selects the Watchdog oscillator as the CLKOUT source. Other settings are reserved. Do not use." />
-      <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0x0 = Clock is divided by 1. 0x1 = Clock is divided by 2. 0x2 = Clock is divided by 3. ... 0xF = Clock is divided by 16." />
-      <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
-      <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1CC" size="4" name="RSTCON0" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RSTLCD" description="LCD controller reset control bit." />
-      <BitField start="1" size="1" name="RSTTIM0" description="Timer/Counter 0 reset control bit." />
-      <BitField start="2" size="1" name="RSTTIM1" description="Timer/Counter 1 reset control bit." />
-      <BitField start="3" size="1" name="RSTUART0" description="UART0 reset control bit." />
-      <BitField start="4" size="1" name="RSTUART1" description="UART1 reset control bit." />
-      <BitField start="5" size="1" name="RSTPWM0" description="PWM0 reset control bit." />
-      <BitField start="6" size="1" name="RSTPWM1" description="PWM1 reset control bit." />
-      <BitField start="7" size="1" name="RSTI2C0" description="The I2C0 interface reset control bit." />
-      <BitField start="8" size="1" name="RSTUART4" description="UART4 reset control bit." />
-      <BitField start="9" size="1" name="RSTRTC" description="RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see Table 626 &quot;Register overview: Real-Time Clock (base address 0x4002 4000)&quot; for details." />
-      <BitField start="10" size="1" name="RSTSSP1" description="The SSP 1 interface reset control bit." />
-      <BitField start="11" size="1" name="RSTEMC" description="External Memory Controller reset control bit." />
-      <BitField start="12" size="1" name="RSTADC" description="A/D converter (ADC) reset control bit." />
-      <BitField start="13" size="1" name="RSTCAN1" description="CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." />
-      <BitField start="14" size="1" name="RSTCAN2" description="CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." />
-      <BitField start="15" size="1" name="RSTGPIO" description="Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a separate bit in the RSTCON1 register." />
-      <BitField start="16" size="1" name="RSTSPIFI" description="SPI Flash Interface reset control bit." />
-      <BitField start="17" size="1" name="RSTMCPWM" description="Motor Control PWM reset control bit." />
-      <BitField start="18" size="1" name="RSTQEI" description="Quadrature Encoder Interface reset control bit." />
-      <BitField start="19" size="1" name="RSTI2C1" description="The I2C1 interface reset control bit." />
-      <BitField start="20" size="1" name="RSTSSP2" description="The SSP2 interface reset control bit." />
-      <BitField start="21" size="1" name="RSTSSP0" description="The SSP0 interface reset control bit." />
-      <BitField start="22" size="1" name="RSTTIM2" description="Timer 2 reset control bit." />
-      <BitField start="23" size="1" name="RSTTIM3" description="Timer 3 reset control bit." />
-      <BitField start="24" size="1" name="RSTUART2" description="UART 2 reset control bit." />
-      <BitField start="25" size="1" name="RSTUART3" description="UART 3 reset control bit." />
-      <BitField start="26" size="1" name="RSTI2C2" description="I2C interface 2 reset control bit." />
-      <BitField start="27" size="1" name="RSTI2S" description="I2S interface reset control bit." />
-      <BitField start="28" size="1" name="RSTSDC" description="SD Card interface reset control bit." />
-      <BitField start="29" size="1" name="RSTGPDMA" description="GPDMA function reset control bit." />
-      <BitField start="30" size="1" name="RSTENET" description="Ethernet block reset control bit." />
-      <BitField start="31" size="1" name="RSTUSB" description="USB interface reset control bit." />
-    </Register>
-    <Register start="+0x1D0" size="4" name="RSTCON1" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RSTIOCON" description="Reset control bit for the IOCON registers." />
-      <BitField start="1" size="1" name="RSTDAC" description="D/A converter (DAC) reset control bit." />
-      <BitField start="2" size="1" name="RSTCANACC" description="CAN acceptance filter reset control bit." />
-      <BitField start="3" size="1" name="RSTCMP" description="Comparator 0/1 reset control bit." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1DC" size="4" name="EMCDLYCTL" access="Read/Write" description="Values for the 4 programmable delays associated with SDRAM operation." reset_value="0x210" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="CMDDLY" description="Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="8" size="5" name="FBCLKDLY" description="Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="16" size="5" name="CLKOUT0DLY" description="Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet." />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="24" size="5" name="CLKOUT1DLY" description="Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x1E0" size="4" name="EMCCAL" access="Read/Write" description="Controls the calibration counter for programmable delays and returns the result value." reset_value="0x1F00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CALVALUE" description="Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the IRC oscillator. This represents the composite effect of processing variation, internal regulator supply voltage, and ambient temperature." />
-      <BitField start="8" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="14" size="1" name="START" description="Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the measurement process. This bit is cleared automatically when the measurement is complete." />
-      <BitField start="15" size="1" name="DONE" description="Measurement completion flag. this bit is set when a calibration measurement is completed. This bit is cleared automatically when the START bit is set." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="WWDT" start="0" size="1" />
-      <BitField name="TIMER0" start="1" size="1" />
-      <BitField name="TIMER1" start="2" size="1" />
-      <BitField name="TIMER2" start="3" size="1" />
-      <BitField name="TIMER3" start="4" size="1" />
-      <BitField name="UART0" start="5" size="1" />
-      <BitField name="UART1" start="6" size="1" />
-      <BitField name="UART2" start="7" size="1" />
-      <BitField name="UART3" start="8" size="1" />
-      <BitField name="PWM1" start="9" size="1" />
-      <BitField name="I2C0" start="10" size="1" />
-      <BitField name="I2C1" start="11" size="1" />
-      <BitField name="I2C2" start="12" size="1" />
-      <BitField name="SSP0" start="14" size="1" />
-      <BitField name="SSP1" start="15" size="1" />
-      <BitField name="RTC" start="17" size="1" />
-      <BitField name="EINT0" start="18" size="1" />
-      <BitField name="EINT1" start="19" size="1" />
-      <BitField name="EINT2" start="20" size="1" />
-      <BitField name="EINT3" start="21" size="1" />
-      <BitField name="ADC" start="22" size="1" />
-      <BitField name="BOD" start="23" size="1" />
-      <BitField name="USB" start="24" size="1" />
-      <BitField name="CAN" start="25" size="1" />
-      <BitField name="GPDMA" start="26" size="1" />
-      <BitField name="I2S" start="27" size="1" />
-      <BitField name="ETHERNET" start="28" size="1" />
-      <BitField name="SDMMC" start="29" size="1" />
-      <BitField name="MCPWM" start="30" size="1" />
-      <BitField name="QEI" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="USB_NEED_CLK" start="1" size="1" />
-      <BitField name="UART4" start="3" size="1" />
-      <BitField name="SSP2" start="4" size="1" />
-      <BitField name="LCD" start="5" size="1" />
-      <BitField name="GPIOINT" start="6" size="1" />
-      <BitField name="PWM0" start="7" size="1" />
-      <BitField name="EEPROM" start="8" size="1" />
-      <BitField name="CMP0" start="9" size="1" />
-      <BitField name="CMP1" start="10" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="WWDT" start="4" size="4" />
-      <BitField name="TIMER0" start="12" size="4" />
-      <BitField name="TIMER1" start="20" size="4" />
-      <BitField name="TIMER2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="TIMER3" start="4" size="4" />
-      <BitField name="UART0" start="12" size="4" />
-      <BitField name="UART1" start="20" size="4" />
-      <BitField name="UART2" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="UART3" start="4" size="4" />
-      <BitField name="PWM1" start="12" size="4" />
-      <BitField name="I2C0" start="20" size="4" />
-      <BitField name="I2C1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="I2C2" start="4" size="4" />
-      <BitField name="SSP0" start="20" size="4" />
-      <BitField name="SSP1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="RTC" start="12" size="4" />
-      <BitField name="EINT0" start="20" size="4" />
-      <BitField name="EINT1" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="EINT2" start="4" size="4" />
-      <BitField name="EINT3" start="12" size="4" />
-      <BitField name="ADC" start="20" size="4" />
-      <BitField name="BOD" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USB" start="4" size="4" />
-      <BitField name="CAN" start="12" size="4" />
-      <BitField name="GPDMA" start="20" size="4" />
-      <BitField name="I2S" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="ETHERNET" start="4" size="4" />
-      <BitField name="SDMMC" start="12" size="4" />
-      <BitField name="MCPWM" start="20" size="4" />
-      <BitField name="QEI" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="USB_NEED_CLK" start="12" size="4" />
-      <BitField name="UART4" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="SSP2" start="4" size="4" />
-      <BitField name="LCD" start="12" size="4" />
-      <BitField name="GPIOINT" start="20" size="4" />
-      <BitField name="PWM0" start="28" size="4" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="EEPROM" start="4" size="4" />
-      <BitField name="CMP0" start="12" size="4" />
-      <BitField name="CMP1" start="20" size="4" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s b/examples/host/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s
deleted file mode 100644
index 02568546..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s
+++ /dev/null
@@ -1,458 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak UART0_IRQHandler
-  .thumb_set UART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak UART2_IRQHandler
-  .thumb_set UART2_IRQHandler,Dummy_Handler
-
-  .weak UART3_IRQHandler
-  .thumb_set UART3_IRQHandler,Dummy_Handler
-
-  .weak PWM1_IRQHandler
-  .thumb_set PWM1_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak EINT0_IRQHandler
-  .thumb_set EINT0_IRQHandler,Dummy_Handler
-
-  .weak EINT1_IRQHandler
-  .thumb_set EINT1_IRQHandler,Dummy_Handler
-
-  .weak EINT2_IRQHandler
-  .thumb_set EINT2_IRQHandler,Dummy_Handler
-
-  .weak EINT3_IRQHandler
-  .thumb_set EINT3_IRQHandler,Dummy_Handler
-
-  .weak ADC_IRQHandler
-  .thumb_set ADC_IRQHandler,Dummy_Handler
-
-  .weak BOD_IRQHandler
-  .thumb_set BOD_IRQHandler,Dummy_Handler
-
-  .weak USB_IRQHandler
-  .thumb_set USB_IRQHandler,Dummy_Handler
-
-  .weak CAN_IRQHandler
-  .thumb_set CAN_IRQHandler,Dummy_Handler
-
-  .weak GPDMA_IRQHandler
-  .thumb_set GPDMA_IRQHandler,Dummy_Handler
-
-  .weak I2S_IRQHandler
-  .thumb_set I2S_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDMMC_IRQHandler
-  .thumb_set SDMMC_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-  .weak USB_NEED_CLK_IRQHandler
-  .thumb_set USB_NEED_CLK_IRQHandler,Dummy_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Dummy_Handler
-
-  .weak SSP2_IRQHandler
-  .thumb_set SSP2_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak GPIOINT_IRQHandler
-  .thumb_set GPIOINT_IRQHandler,Dummy_Handler
-
-  .weak PWM0_IRQHandler
-  .thumb_set PWM0_IRQHandler,Dummy_Handler
-
-  .weak EEPROM_IRQHandler
-  .thumb_set EEPROM_IRQHandler,Dummy_Handler
-
-  .weak CMP0_IRQHandler
-  .thumb_set CMP0_IRQHandler,Dummy_Handler
-
-  .weak CMP1_IRQHandler
-  .thumb_set CMP1_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART0_IRQHandler
-UART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART2_IRQHandler
-UART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART3_IRQHandler
-UART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM1_IRQHandler
-PWM1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C2_IRQHandler
-I2C2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT0_IRQHandler
-EINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT1_IRQHandler
-EINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT2_IRQHandler
-EINT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EINT3_IRQHandler
-EINT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC_IRQHandler
-ADC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak BOD_IRQHandler
-BOD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_IRQHandler
-USB_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CAN_IRQHandler
-CAN_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GPDMA_IRQHandler
-GPDMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S_IRQHandler
-I2S_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDMMC_IRQHandler
-SDMMC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB_NEED_CLK_IRQHandler
-USB_NEED_CLK_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART4_IRQHandler
-UART4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP2_IRQHandler
-SSP2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GPIOINT_IRQHandler
-GPIOINT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PWM0_IRQHandler
-PWM0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EEPROM_IRQHandler
-EEPROM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CMP0_IRQHandler
-CMP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak CMP1_IRQHandler
-CMP1_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDT_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word UART0_IRQHandler
-  .word UART1_IRQHandler
-  .word UART2_IRQHandler
-  .word UART3_IRQHandler
-  .word PWM1_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word RTC_IRQHandler
-  .word EINT0_IRQHandler
-  .word EINT1_IRQHandler
-  .word EINT2_IRQHandler
-  .word EINT3_IRQHandler
-  .word ADC_IRQHandler
-  .word BOD_IRQHandler
-  .word USB_IRQHandler
-  .word CAN_IRQHandler
-  .word GPDMA_IRQHandler
-  .word I2S_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDMMC_IRQHandler
-  .word MCPWM_IRQHandler
-  .word QEI_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word USB_NEED_CLK_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word UART4_IRQHandler
-  .word SSP2_IRQHandler
-  .word LCD_IRQHandler
-  .word GPIOINT_IRQHandler
-  .word PWM0_IRQHandler
-  .word EEPROM_IRQHandler
-  .word CMP0_IRQHandler
-  .word CMP1_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/flash_placement.xml b/examples/host/cdc_msc_hid/ses/lpc40xx/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject b/examples/host/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
deleted file mode 100644
index 68995f1a..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
+++ /dev/null
@@ -1,126 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc40xx" target="8" version="2">
-  <project Name="lpc40xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4088FBD208"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="256"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="256"
-      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00080000;RAM;0x10000000;0x00010000;RAM;0x20000000;0x00008000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC4088"
-      arm_target_interface_type="SWD"
-      c_preprocessor_definitions="CORE_M4;__LPC4000_FAMILY;__LPC408x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4088QS;CFG_TUSB_MCU=OPT_MCU_LPC40XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)));CFG_TUSB_DEBUG=2;LOGGER_RTT"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc;$(rootDir)/lib/SEGGER_RTT/RTT"
-      debug_register_definition_file="$(ProjectDir)/LPC408x_7x_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC4088FBD208_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceFamily=LPC4000;DeviceSubFamily=LPC408x;Target=LPC4088FBD208;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx"
-      package_dependencies="LPC4000"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC4000_Startup.s" />
-      <file file_name="LPC408x_7x_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-      <file file_name="LPC4088FBD208_MemoryMap.xml" />
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC4000_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-    </folder>
-    <configuration
-      Name="EA4088 QuickStart"
-      link_use_linker_script_file="No"
-      linker_section_placement_file="flash_placement.xml" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="ea4088qs">
-          <file file_name="../../../../../hw/bsp/ea4088qs/ea4088qs.c" />
-        </folder>
-        <file file_name="../../../../../hw/bsp/board.c" />
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_chip_40xx">
-            <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip_lpc175x_6x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip_lpc177x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/chip_lpc407x_8x.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/clock_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/cmsis_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cm4.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cm4_simd.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/gpio_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/sys_config.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/sysctl_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/uart_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/usb_17xx_40xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/inc/iocon_17xx_40xx.h" />
-            </folder>
-            <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/chip_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/clock_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/gpio_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/iocon_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/sysctl_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/sysinit_17xx_40xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx/src/uart_17xx_40xx.c" />
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="lib">
-      <folder Name="SEGGER_RTT">
-        <folder Name="RTT">
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.c" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.h" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c" />
-        </folder>
-        <folder Name="Syscalls">
-          <file file_name="../../../../../lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c" />
-        </folder>
-      </folder>
-    </folder>
-  </project>
-  <configuration
-    Name="EA4088 QuickStart"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-</solution>
diff --git a/examples/host/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s b/examples/host/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4300_Startup.s b/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4300_Startup.s
deleted file mode 100644
index 3df2ad96..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4300_Startup.s
+++ /dev/null
@@ -1,126 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  ldr r1, =0x7
-  bics r0, r1
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4300_Target.js b/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4300_Target.js
deleted file mode 100644
index 20560af4..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4300_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml b/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml
deleted file mode 100644
index eb42b7bf..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC4357 Cortex-M4_MemoryMap.xml	
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC4357 Cortex-M4">
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00010000" access="Read/Write" />
-</root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC43xx_Registers.xml b/examples/host/cdc_msc_hid/ses/lpc43xx/LPC43xx_Registers.xml
deleted file mode 100644
index 9c094646..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC43xx_Registers.xml
+++ /dev/null
@@ -1,33526 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC43xx" description="Register cmsis file for LPC43xx parts">
-  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
-        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
-      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
-      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
-      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
-      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
-      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
-      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
-        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
-      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
-      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
-      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
-        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
-        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
-        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
-        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
-      </BitField>
-      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
-        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
-        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
-      </BitField>
-      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
-        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
-        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
-        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
-        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
-      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
-        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
-        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
-      </BitField>
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRESS" description="Address." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
-    </Register>
-    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Input or output data" />
-    </Register>
-    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
-      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
-      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
-      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
-      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
-      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
-      </BitField>
-      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
-      </BitField>
-      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
-        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
-        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
-        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
-        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
-      </BitField>
-      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
-      </BitField>
-      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
-      </BitField>
-      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
-        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
-      </BitField>
-      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
-        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
-      </BitField>
-      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
-      </BitField>
-      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
-        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
-        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
-      </BitField>
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
-      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
-      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
-      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
-        <Enum name="NONE" start="0" description="None. No response expected from card" />
-        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
-      </BitField>
-      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
-        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
-        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
-      </BitField>
-      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
-        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
-        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
-      </BitField>
-      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
-        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
-        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
-      </BitField>
-      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
-        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
-        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
-      </BitField>
-      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
-        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
-      </BitField>
-      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
-        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
-        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
-      </BitField>
-      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
-        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
-        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
-      </BitField>
-      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
-        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
-        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
-      </BitField>
-      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
-        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
-        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
-      </BitField>
-      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
-      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
-        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
-      </BitField>
-      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
-        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-      </BitField>
-      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
-      </BitField>
-      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
-      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
-        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
-        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
-      </BitField>
-      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
-        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
-        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
-      </BitField>
-      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
-    </Register>
-    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
-    </Register>
-    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
-    </Register>
-    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
-    </Register>
-    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
-    </Register>
-    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
-      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
-      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
-      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
-      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
-      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
-      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
-      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
-      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
-      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
-      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
-      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
-    </Register>
-    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
-      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
-    </Register>
-    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
-    </Register>
-    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
-      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
-      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
-      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
-      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
-    </Register>
-    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
-    </Register>
-    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
-      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
-      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
-      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
-    </Register>
-    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
-        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
-        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
-        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode.">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
-        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
-        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy.">
-        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
-        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
-        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
-        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
-        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
-      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
-      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
-      </BitField>
-      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
-      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
-      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
-        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
-        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
-      </BitField>
-      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
-      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
-      </BitField>
-      <BitField start="8" size="1" name="ID" description="USB ID">
-        <Enum name="A_DEVICE" start="0" description="A-device" />
-        <Enum name="B_DEVICE" start="1" description="B-device" />
-      </BitField>
-      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
-      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
-      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
-      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
-      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
-      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
-      <BitField start="15" size="1" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
-      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
-      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
-      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
-      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
-      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
-      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
-      <BitField start="23" size="1" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="reserved" />
-      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
-      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
-      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
-      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
-      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
-        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
-        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
-      </BitField>
-      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
-        <Enum name="READ" start="0" description="Read" />
-        <Enum name="WRITE" start="1" description="Write" />
-      </BitField>
-      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
-      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
-    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
-      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
-      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
-    </Register>
-    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
-    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
-      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
-      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
-      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
-      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
-      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
-      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
-      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
-      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
-      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
-      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
-      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
-      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
-      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
-      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
-      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
-      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
-      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
-      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
-      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
-    </Register>
-    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
-      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
-      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
-      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
-      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
-      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
-      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
-      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
-      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
-    </Register>
-    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
-      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
-      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
-      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
-      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
-      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
-      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
-      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
-      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
-    </Register>
-    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
-      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
-      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
-      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
-      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
-      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
-    </Register>
-    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="MO" description="Always 1" />
-    </Register>
-    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-    </Register>
-    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
-      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
-      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
-      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
-      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
-      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
-      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
-      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
-      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
-      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
-      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
-      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
-      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
-      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
-      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
-    </Register>
-    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
-    </Register>
-    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
-      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
-    </Register>
-    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
-    </Register>
-    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
-      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
-    </Register>
-    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
-    </Register>
-    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
-    </Register>
-    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
-      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
-      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
-      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
-      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
-      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
-      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
-      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
-      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
-      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
-      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
-      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
-      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
-      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
-    </Register>
-    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
-    </Register>
-    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
-      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
-      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
-      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
-      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
-      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
-      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
-      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
-      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
-      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
-      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
-      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
-      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
-      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
-      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
-      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
-      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
-      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
-      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
-      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
-      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
-      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
-      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
-      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
-      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
-      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
-      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
-      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
-      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
-      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
-      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
-      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
-      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
-      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
-      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
-      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
-    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
-    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
-    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M4 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register." />
-      <BitField start="1" size="1" name="ENA_EVENT1" description="Writing a 1 enables the Cortex-M0 core and the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Cortex-M0 subsystem core to put the part into any of&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;the Power-down modes Deep-sleep, Power-down, or&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Deep power-down depending on the value in the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;PD0_SLEEP0_MODE register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 3CBA = Power-down mode with M0SUB SRAM maintained&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
-    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
-        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
-        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
-        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
-        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
-        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
-        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
-      </BitField>
-      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
-        <Enum name="POWERED" start="0" description="Powered." />
-        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
-        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
-        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
-      </BitField>
-      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
-        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
-        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INACTIVE" start="0x3" description="Inactive." />
-      </BitField>
-      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.">
-        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
-        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
-        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
-        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
-      </BitField>
-      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.">
-        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
-        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
-        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
-        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
-      </BitField>
-      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
-        <Enum name="RESERVED" start="0x0" description="Reserved" />
-        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
-      </BitField>
-      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="M4MEMMAP" access="Read/Write" description="ARM Cortex-M4 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M4MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="M0SUBTAPSEL" description="JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="11" size="1" name="M4TAPSEL" description="JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="12" size="1" name="M0APPTAPSEL" description="JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="13" size="19" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
-        <Enum name="SPIFI" start="0x0" description="SPIFI" />
-        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
-        <Enum name="SGPIO14" start="0x2" description="SGPIO14" />
-        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
-      </BitField>
-      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
-        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
-        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
-        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
-        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
-        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
-        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
-        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
-        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
-        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
-        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
-        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
-        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
-      </BitField>
-      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
-        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
-        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="SGPIO15" start="0x3" description="SGPIO15" />
-      </BitField>
-      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
-        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
-        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="SGPIO14" start="0x3" description="SGPIO14" />
-      </BitField>
-      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
-        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
-        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-        <Enum name="ADCHS_WRITE" start="0x3" description="ADCHS write" />
-      </BitField>
-      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
-        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
-        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-        <Enum name="ADCHS_READ" start="0x3" description="ADCHS read" />
-      </BitField>
-      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
-        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
-        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
-        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
-        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
-        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
-        <Enum name="SGPIO14" start="0x1" description="SGPIO14" />
-        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
-        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
-        <Enum name="SGPIO15" start="0x1" description="SGPIO15" />
-        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
-        <Enum name="ADC0" start="0x0" description="ADC0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
-      </BitField>
-      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
-        <Enum name="ADC1" start="0x0" description="ADC1" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
-      </BitField>
-      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
-        <Enum name="DAC" start="0x0" description="DAC" />
-        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
-        <Enum name="SGPIO15" start="0x2" description="SGPIO15" />
-        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
-        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
-        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
-        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
-        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
-        <Enum name="MII" start="0x0" description="MII" />
-        <Enum name="RMII" start="0x4" description="RMII" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
-        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
-        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
-      </BitField>
-      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
-        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
-        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x130" size="4" name="M4TXEVENT" access="Read/Write" description="Cortex-M4 TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M4 TXEV event.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)" />
-    </Register>
-    <Register start="+0x308" size="4" name="M0SUBMEMMAP" access="Read/Write" description="ARM Cortex-M0SUB memory mapping" reset_value="0x18400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M0SUBMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x314" size="4" name="M0SUBTXEVENT" access="Read/Write" description="Cortex-M0SUB TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0SUB TXEV event handling.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="M0APPTXEVENT" access="Read/Write" description="Cortex-M0APP TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0APP TXEV event handling.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="M0APPMEMMAP" access="Read/Write" description="ARM Cortex-M0APP memory mapping" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M0APPMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x500" size="4" name="USB0FLADJ" access="Read/Write" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
-    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
-      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
-      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
-      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
-      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
-      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
-      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
-      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
-      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
-      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
-      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
-      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
-      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
-      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
-      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
-      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
-      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
-      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
-    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
-        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
-        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
-        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
-        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
-        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
-        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
-        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
-        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
-        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
-        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
-        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
-    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
-      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
-      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
-        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
-        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
-      </BitField>
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
-        <Enum name="IRC" start="0x01" description="IRC" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="RESERVED" start="0x0B" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="ENABLE" start="0" description="Enable" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
-        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
-      </BitField>
-      <BitField start="2" size="1" name="HF" description="Select frequency range">
-        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
-      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
-      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
-      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
-        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
-        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
-      </BitField>
-      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
-        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
-      </BitField>
-      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL1 power down">
-        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
-        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
-        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
-      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
-        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
-        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="PEQ2" start="0x1" description="2 (default)" />
-        <Enum name="PEQ4" start="0x2" description="4" />
-        <Enum name="8" start="0x3" description="8" />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="NEQ2" start="0x1" description="2" />
-        <Enum name="NEQ3" start="0x2" description="3 (default)" />
-        <Enum name="4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="RESERVED" start="0x09" description="Reserved" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
-        <Enum name="DIV1" start="0x0" description="1 (default)" />
-        <Enum name="DIV2" start="0x1" description="2" />
-        <Enum name="DIV3" start="0x2" description="3" />
-        <Enum name="DIV4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="BASE_M4_CLK" access="Read/Write" description="Output stage BASE_M4_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="BASE_SPI_CLK" access="Read/Write" description="Output stage BASE_SPI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_M4_BUS_CFG" access="Read/Write" description="CLK_M4_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0408" size="4" name="CLK_M4_SPIFI_CFG" access="Read/Write" description="CLK_M4_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0410" size="4" name="CLK_M4_GPIO_CFG" access="Read/Write" description="CLK_M4_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0418" size="4" name="CLK_M4_LCD_CFG" access="Read/Write" description="CLK_M4_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0420" size="4" name="CLK_M4_ETHERNET_CFG" access="Read/Write" description="CLK_M4_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0428" size="4" name="CLK_M4_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0430" size="4" name="CLK_M4_EMC_CFG" access="Read/Write" description="CLK_M4_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0438" size="4" name="CLK_M4_SDIO_CFG" access="Read/Write" description="CLK_M4_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0440" size="4" name="CLK_M4_DMA_CFG" access="Read/Write" description="CLK_M4_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0448" size="4" name="CLK_M4_M4CORE_CFG" access="Read/Write" description="CLK_M4_M4CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0468" size="4" name="CLK_M4_SCT_CFG" access="Read/Write" description="CLK_M4_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0470" size="4" name="CLK_M4_USB1_CFG" access="Read/Write" description="CLK_M4_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0478" size="4" name="CLK_M4_EMCDIV_CFG" access="Read/Write" description="CLK_M4_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0480" size="4" name="CLK_M4_FLASHA_CFG" access="Read/Write" description="CLK_M4_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0488" size="4" name="CLK_M4_FLASHB_CFG" access="Read/Write" description="CLK_M4_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0490" size="4" name="CLK_M4_M0APP_CFG" access="Read/Write" description="CLK_M0APP_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0498" size="4" name="CLK_M4_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A0" size="4" name="CLK_M4_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_M4_WWDT_CFG" access="Read/Write" description="CLK_M4_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0508" size="4" name="CLK_M4_USART0_CFG" access="Read/Write" description="CLK_M4_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0510" size="4" name="CLK_M4_UART1_CFG" access="Read/Write" description="CLK_M4_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0518" size="4" name="CLK_M4_SSP0_CFG" access="Read/Write" description="CLK_M4_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0520" size="4" name="CLK_M4_TIMER0_CFG" access="Read/Write" description="CLK_M4_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0528" size="4" name="CLK_M4_TIMER1_CFG" access="Read/Write" description="CLK_M4_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0530" size="4" name="CLK_M4_SCU_CFG" access="Read/Write" description="CLK_M4_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0538" size="4" name="CLK_M4_CREG_CFG" access="Read/Write" description="CLK_M4_CREGclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_M4_RITIMER_CFG" access="Read/Write" description="CLK_M4_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0608" size="4" name="CLK_M4_USART2_CFG" access="Read/Write" description="CLK_M4_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0610" size="4" name="CLK_M4_USART3_CFG" access="Read/Write" description="CLK_M4_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0618" size="4" name="CLK_M4_TIMER2_CFG" access="Read/Write" description="CLK_M4_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0620" size="4" name="CLK_M4_TIMER3_CFG" access="Read/Write" description="CLK_M4_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0628" size="4" name="CLK_M4_SSP1_CFG" access="Read/Write" description="CLK_M4_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0630" size="4" name="CLK_M4_QEI_CFG" access="Read/Write" description="CLK_M4_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0700" size="4" name="CLK_PERIPH_BUS_CFG" access="Read/Write" description="CLK_PERIPH_BUS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0710" size="4" name="CLK_PERIPH_CORE_CFG" access="Read/Write" description="CLK_PERIPH_CORE_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0718" size="4" name="CLK_PERIPH_SGPIO_CFG" access="Read/Write" description="CLK_PERIPH_SGPIO_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xA00" size="4" name="CLK_SPI_CFG" access="Read/Write" description="CLK_SPI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xB00" size="4" name="CLK_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x404" size="4" name="CLK_M4_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040C" size="4" name="CLK_M4_SPIFI_STAT" access="ReadOnly" description="CLK_M4_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0414" size="4" name="CLK_M4_GPIO_STAT" access="ReadOnly" description="CLK_M4_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x041C" size="4" name="CLK_M4_LCD_STAT" access="ReadOnly" description="CLK_M4_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0424" size="4" name="CLK_M4_ETHERNET_STAT" access="ReadOnly" description="CLK_M4_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x042C" size="4" name="CLK_M4_USB0_STAT" access="ReadOnly" description="CLK_M4_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0434" size="4" name="CLK_M4_EMC_STAT" access="ReadOnly" description="CLK_M4_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x043C" size="4" name="CLK_M4_SDIO_STAT" access="ReadOnly" description="CLK_M4_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0444" size="4" name="CLK_M4_DMA_STAT" access="ReadOnly" description="CLK_M4_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044C" size="4" name="CLK_M4_M4CORE_STAT" access="ReadOnly" description="CLK_M4_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x046C" size="4" name="CLK_M4_SCT_STAT" access="ReadOnly" description="CLK_M4_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0474" size="4" name="CLK_M4_USB1_STAT" access="ReadOnly" description="CLK_M4_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x047C" size="4" name="CLK_M4_EMCDIV_STAT" access="ReadOnly" description="CLK_M4_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0484" size="4" name="CLK_M4_FLASHA_STAT" access="ReadOnly" description="CLK_M4_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048C" size="4" name="CLK_M4_FLASHB_STAT" access="ReadOnly" description="CLK_M4_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0494" size="4" name="CLK_M4_M0APP_STAT" access="ReadOnly" description="CLK_M4_MOAPP clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x049C" size="4" name="CLK_M4_ADCHS_STAT" access="ReadOnly" description="CLK_M4_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A4" size="4" name="CLK_M4_EEPROM_STAT" access="ReadOnly" description="CLK_M4_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504" size="4" name="CLK_M4_WWDT_STAT" access="ReadOnly" description="CLK_M4_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050C" size="4" name="CLK_M4_USART0_STAT" access="ReadOnly" description="CLK_M4_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0514" size="4" name="CLK_M4_UART1_STAT" access="ReadOnly" description="CLK_M4_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x051C" size="4" name="CLK_M4_SSP0_STAT" access="ReadOnly" description="CLK_M4_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0524" size="4" name="CLK_M4_TIMER0_STAT" access="ReadOnly" description="CLK_M4_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x052C" size="4" name="CLK_M4_TIMER1_STAT" access="ReadOnly" description="CLK_M4_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0534" size="4" name="CLK_M4_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x053C" size="4" name="CLK_M4_CREG_STAT" access="ReadOnly" description="CLK_M4_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x604" size="4" name="CLK_M4_RITIMER_STAT" access="ReadOnly" description="CLK_M4_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060C" size="4" name="CLK_M4_USART2_STAT" access="ReadOnly" description="CLK_M4_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0614" size="4" name="CLK_M4_USART3_STAT" access="ReadOnly" description="CLK_M4_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x061C" size="4" name="CLK_M4_TIMER2_STAT" access="ReadOnly" description="CLK_M4_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0624" size="4" name="CLK_M4_TIMER3_STAT" access="ReadOnly" description="CLK_M4_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x062C" size="4" name="CLK_M4_SSP1_STAT" access="ReadOnly" description="CLK_M4_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0634" size="4" name="CLK_M4_QEI_STAT" access="ReadOnly" description="CLK_M4_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_PERIPH_BUS_STAT" access="ReadOnly" description="CLK_PERIPH_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0714" size="4" name="CLK_PERIPH_CORE_STAT" access="ReadOnly" description="CLK_CORE_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x071C" size="4" name="CLK_PERIPH_SGPIO_STAT" access="ReadOnly" description="CLK_CORE_SGPIO_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xA04" size="4" name="CLK_SPI_STAT" access="ReadOnly" description="CLK_SPI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xB04" size="4" name="CLK_ADCHS_STAT" access="ReadOnly" description="CLK_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
-    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
-      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="13" size="1" name="M4_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="24" size="1" name="M0APP_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="25" size="1" name="SGPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="SPI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="1" name="ADCHS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="M4_RST" description="Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-    </Register>
-    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="M0APP_RST" description="Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SGPIO_RST" description="Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="SPI_RST" description="Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="ADCHS_RST" description="Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="M4_RST" description="Current status of the M4_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="24" size="1" name="M0APP_RST" description="Current status of the M0APP_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="25" size="1" name="SGPIO_RST" description="Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="SPI_RST" description="Current status of the SPI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="ADCHS_RST" description="Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x430" size="4" name="RESET_EXT_STAT12" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E0" size="4" name="RESET_EXT_STAT56" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E4" size="4" name="RESET_EXT_STAT57" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E8" size="4" name="RESET_EXT_STAT58" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04F0" size="4" name="RESET_EXT_STAT60" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
-        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
-        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
-        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
-        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
-        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
-        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
-    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
-        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
-        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
-      </BitField>
-      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
-        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
-        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
-      </BitField>
-      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
-        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
-        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
-        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
-        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
-      </BitField>
-      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
-        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
-        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
-      </BitField>
-      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
-      </BitField>
-    </Register>
-    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
-      </BitField>
-      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
-      </BitField>
-      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DAC" description="Select DAC">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
-        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
-      </BitField>
-      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
-      <BitField start="20" size="12" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
-      <BitField start="1" size="31" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
-    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="SGPIO3_DIV" start="0x1" description="SGPIO3_DIV" />
-        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
-        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
-        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
-        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO12_DIV" start="0x1" description="SGPIO12_DIV" />
-        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
-        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
-        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
-        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
-        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
-        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
-        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
-        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
-        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="SGPIO3_DIV" start="0x2" description="SGPIO3_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="SGPIO12" start="0x2" description="SGPIO12" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
-        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
-        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="ADCHS_TRIGGER_IN" access="Read/Write" description="ADCHS trigger input multiplexer (GIMA output 24)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0xA to 0xF are reserved.">
-        <Enum name="GPIO6_28" start="0x0" description="GPIO6[28]" />
-        <Enum name="GPIO5_3" start="0x1" description="GPIO5[3]" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO12" start="0x3" description="SGPIO12" />
-        <Enum name="RESERVED" start="0x4" description="Reserved" />
-        <Enum name="MCOB2" start="0x5" description="MCOB2" />
-        <Enum name="CTOUT_0_OR_T0_MAT0" start="0x6" description="CTOUT_0 or T0_MAT0" />
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x7" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T0_MAT0" start="0x8" description="T0_MAT0" />
-        <Enum name="T2_MAT0" start="0x9" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
-        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time">
-        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
-        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
-        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
-        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
-        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
-        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
-        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
-        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
-        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
-        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADCHS" start="0x400F0000" description="12-bit Analog-to-Digital Converter  High-Speed (ADCHS)">
-    <Register start="+0x0000" size="4" name="FLUSH" access="WriteOnly" description="Flushes FIFO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFO_FLUSH" description="1= fifo is cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="DMA_REQ" access="Read/Write" description="Set or clear DMA write request" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMA_REQ_WR" description="1 = Dma_req_wr is set (initially used to fill second table),  0 = Dma_req_wr is cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0008" size="4" name="FIFO_STS" access="ReadOnly" description="Indicates FIFO fill level status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="LEVEL" description="0 = FIFO is empty  1...15 = FIFO is partially full  16 = FIFO is full" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000C" size="4" name="FIFO_CFG" access="Read/Write" description="Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PACKED_READ" description="0 = one sample is packed in one 32-bit read cycle  1 = two samples are packed in one 32-bit read cycle" />
-      <BitField start="1" size="5" name="LEVEL" description="When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0010" size="4" name="TRIGGER" access="WriteOnly" description="Enable software trigger to start descriptor processing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SW_TRIGGER" description="Auto cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="DSCR_STS" access="Read/Write" description="Indicates active descriptor table and descriptor entry" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACT_TABLE" description="0 = table 0 is active  1 = table 1 is active." />
-      <BitField start="1" size="3" name="ACT_DESCRIPTOR" description="ID of the descriptor that is active." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="POWER_DOWN" access="Read/Write" description="Set or clear power down mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD_CTRL" description="0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set.   1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x001C" size="4" name="CONFIG" access="Read/Write" description="Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." reset_value="0x00002400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TRIGGER__MASK" description="00 = triggers off  01 = software trigger only  10 = external trigger only  11 = both triggers allowed" />
-      <BitField start="2" size="2" name="TRIGGER_MODE" description="00 = rising external trigger  01 = falling external trigger  10 = low external trigger  11 = high external trigger" />
-      <BitField start="4" size="1" name="TRIGGER_SYNC" description="0  = do not synchronize external  trigger input  1 = synchronize external  trigger input" />
-      <BitField start="5" size="1" name="CHANNEL_ID_EN" description="0 = do not add channel ID to FIFO output data  1 = add channel ID to FIFO output data" />
-      <BitField start="6" size="8" name="RECOVERY_TIME" description="ADC recovery time from power down" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0020" size="4" name="THR_A" access="Read/Write" description="Configures window comparator A levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="THR_LOW_A" description="Low Compare Threshold Register A:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="16" size="12" name="THR_HIGH_A" description="High Compare Threshold Register A:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0024" size="4" name="THR_B" access="Read/Write" description="Configures window comparator B levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="THR_LOW_B" description="Low Compare Threshold Register B:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="16" size="12" name="THR_HIGH_B" description="High Compare Threshold Register B:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0028+0" size="4" name="LAST_SAMPLE[0]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+4" size="4" name="LAST_SAMPLE[1]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+8" size="4" name="LAST_SAMPLE[2]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+12" size="4" name="LAST_SAMPLE[3]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+16" size="4" name="LAST_SAMPLE[4]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+20" size="4" name="LAST_SAMPLE[5]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0104" size="4" name="ADC_SPEED" access="Read/Write" description="ADC speed control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DGEC0" description="Speed0" />
-      <BitField start="4" size="4" name="DGEC1" description="Speed1" />
-      <BitField start="8" size="4" name="DGEC2" description="Speed2" />
-      <BitField start="12" size="4" name="DGEC3" description="Speed3" />
-      <BitField start="16" size="4" name="DGEC4" description="Speed4" />
-      <BitField start="20" size="4" name="DGEC5" description="Speed5" />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="POWER_CONTROL" access="Read/Write" description="Configures ADC power vs. speed, DC-in biasing, output format and power gating." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CRS" description="current setting for power versus speed programming" />
-      <BitField start="4" size="6" name="DCINNEG" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_neg side" />
-      <BitField start="10" size="6" name="DCINPOS" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_pos side" />
-      <BitField start="16" size="1" name="TWOS" description="Output data format selection  0 = offset binary  1 = two's complement" />
-      <BitField start="17" size="1" name="POWER_SWITCH" description="0 = ADC is powered down 1 = ADC is active" />
-      <BitField start="18" size="1" name="BGAP_SWITCH" description="0 = ADC band gap reference is powered down  1 = ADC band gap reference is active" />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0200+0" size="4" name="FIFO_OUTPUT[0]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+4" size="4" name="FIFO_OUTPUT[1]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+8" size="4" name="FIFO_OUTPUT[2]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+12" size="4" name="FIFO_OUTPUT[3]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+16" size="4" name="FIFO_OUTPUT[4]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+20" size="4" name="FIFO_OUTPUT[5]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+24" size="4" name="FIFO_OUTPUT[6]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+28" size="4" name="FIFO_OUTPUT[7]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+32" size="4" name="FIFO_OUTPUT[8]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+36" size="4" name="FIFO_OUTPUT[9]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+40" size="4" name="FIFO_OUTPUT[10]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+44" size="4" name="FIFO_OUTPUT[11]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+48" size="4" name="FIFO_OUTPUT[12]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+52" size="4" name="FIFO_OUTPUT[13]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+56" size="4" name="FIFO_OUTPUT[14]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+60" size="4" name="FIFO_OUTPUT[15]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0300+0" size="4" name="DESCRIPTOR0_[0]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+4" size="4" name="DESCRIPTOR0_[1]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+8" size="4" name="DESCRIPTOR0_[2]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+12" size="4" name="DESCRIPTOR0_[3]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+16" size="4" name="DESCRIPTOR0_[4]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+20" size="4" name="DESCRIPTOR0_[5]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+24" size="4" name="DESCRIPTOR0_[6]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+28" size="4" name="DESCRIPTOR0_[7]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+0" size="4" name="DESCRIPTOR1_[0]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+4" size="4" name="DESCRIPTOR1_[1]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+8" size="4" name="DESCRIPTOR1_[2]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+12" size="4" name="DESCRIPTOR1_[3]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+16" size="4" name="DESCRIPTOR1_[4]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+20" size="4" name="DESCRIPTOR1_[5]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+24" size="4" name="DESCRIPTOR1_[6]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+28" size="4" name="DESCRIPTOR1_[7]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0F00" size="4" name="CLR_EN0" access="WriteOnly" description="Interrupt 0 clear mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CEN0" description="Interrupt clear enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F04" size="4" name="SET_EN0" access="WriteOnly" description="Interrupt 0 set mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SEN0" description="Interrupt set enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F08" size="4" name="MASK0" access="ReadOnly" description="Interrupt 0 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="M0" description="Interrupt enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F0C" size="4" name="STATUS0" access="ReadOnly" description="Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFO_FULL" description="0: number of samples in FIFO less than or equal to FIFO_LEVEL  1: number of samples in FIFO is more than FIFO_LEVEL" />
-      <BitField start="1" size="1" name="FIFO_EMPTY" description="0: FIFO is not empty   1: FIFO is empty" />
-      <BitField start="2" size="1" name="FIFO_OVERFLOW" description="FIFO was full; conversion sample is not stored  and lost" />
-      <BitField start="3" size="1" name="DSCR_DONE" description="The descriptor INTERRUPT field was enabled and its sample is converted." />
-      <BitField start="4" size="1" name="DSCR_ERROR" description="The ADC was not fully woken up when a sample was converted and the conversion results is unreliable" />
-      <BitField start="5" size="1" name="ADC_OVF" description="Converted sample value was over range of the 12 bit output code." />
-      <BitField start="6" size="1" name="ADC_UNF" description="Converted sample value was under range of the 12 bit output code." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F10" size="4" name="CLR_STAT0" access="WriteOnly" description="Interrupt 0 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CSTAT0" description="Interrupt clear status" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F14" size="4" name="SET_STAT0" access="WriteOnly" description="Interrupt 0 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SSTAT0" description="Interrupt set status" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F20" size="4" name="CLR_EN1" access="WriteOnly" description="Interrupt 1 mask clear enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="CEN1" description="Interrupt clear enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F24" size="4" name="SET_EN1" access="WriteOnly" description="Interrupt 1 mask set enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SEN1" description="Interrupt set enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F28" size="4" name="MASK1" access="ReadOnly" description="Interrupt 1 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="M1" description="Interrupt enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F2C" size="4" name="STATUS1" access="ReadOnly" description="Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="THCMP_BRANGE0" description="Input channel 0 result below  range" />
-      <BitField start="1" size="1" name="THCMP_ARANGE0" description="Input channel 0 result above range" />
-      <BitField start="2" size="1" name="THCMP_DCROSS0" description="Input channel 0 result  downward threshold crossing detected" />
-      <BitField start="3" size="1" name="THCMP_UCROSS0" description="Input channel 0 result upward threshold crossing detected" />
-      <BitField start="4" size="1" name="OVERRUN_0" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [0]  before it has been read" />
-      <BitField start="5" size="1" name="THCMP_BRANGE1" description="Input channel 1 result below  range" />
-      <BitField start="6" size="1" name="THCMP_ARANGE1" description="Input channel 1 result above range" />
-      <BitField start="7" size="1" name="THCMP_DCROSS1" description="Input channel 1 result  downward threshold crossing detected" />
-      <BitField start="8" size="1" name="THCMP_UCROSS1" description="Input channel 1 result upward threshold crossing detected" />
-      <BitField start="9" size="1" name="OVERRUN_1" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [1]  before it has been read" />
-      <BitField start="10" size="1" name="THCMP_BRANGE2" description="Input channel 2 result below  range" />
-      <BitField start="11" size="1" name="THCMP_ARANGE2" description="Input channel 2 result above range" />
-      <BitField start="12" size="1" name="THCMP_DCROSS2" description="Input channel 2 result  downward threshold crossing detected" />
-      <BitField start="13" size="1" name="THCMP_UCROSS2" description="Input channel 2 result upward threshold crossing detected" />
-      <BitField start="14" size="1" name="OVERRUN_2" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [2]  before it has been read" />
-      <BitField start="15" size="1" name="THCMP_BRANGE3" description="Input channel 3 result below  range" />
-      <BitField start="16" size="1" name="THCMP_ARANGE3" description="Input channel 3 result above range" />
-      <BitField start="17" size="1" name="THCMP_DCROSS3" description="Input channel 3 result  downward threshold crossing detected" />
-      <BitField start="18" size="1" name="THCMP_UCROSS3" description="Input channel 3 result upward threshold crossing detected" />
-      <BitField start="19" size="1" name="OVERRUN_3" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [3]  before it has been read" />
-      <BitField start="20" size="1" name="THCMP_BRANGE4" description="Input channel 4 result below  range" />
-      <BitField start="21" size="1" name="THCMP_ARANGE4" description="Input channel 4 result above range" />
-      <BitField start="22" size="1" name="THCMP_DCROSS4" description="Input channel 4 result  downward threshold crossing detected" />
-      <BitField start="23" size="1" name="THCMP_UCROSS4" description="Input channel 4 result upward threshold crossing detected" />
-      <BitField start="24" size="1" name="OVERRUN_4" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [4]  before it has been read" />
-      <BitField start="25" size="1" name="THCMP_BRANGE5" description="Input channel 5 result below  range" />
-      <BitField start="26" size="1" name="THCMP_ARANGE5" description="Input channel 5 result above range" />
-      <BitField start="27" size="1" name="THCMP_DCROSS5" description="Input channel 5 result  downward threshold crossing detected" />
-      <BitField start="28" size="1" name="THCMP_UCROSS5" description="Input channel 5 result upward threshold crossing detected" />
-      <BitField start="29" size="1" name="OVERRUN_5" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [5]  before it has been read" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F30" size="4" name="CLR_STAT1" access="WriteOnly" description="Interrupt 1 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="CSTAT1" description="Interrupt clear status" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F34" size="4" name="SET_STAT1" access="WriteOnly" description="Interrupt 1 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SSTAT1" description="Interrupt set status" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI" start="0x40100000" description="SPI ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
-        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
-      </BitField>
-      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
-        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
-        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
-      </BitField>
-      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
-        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
-        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
-      </BitField>
-      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
-        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
-        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
-      </BitField>
-      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
-        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
-        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
-      </BitField>
-      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
-        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
-        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
-      </BitField>
-      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
-        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
-        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
-        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
-        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
-        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
-        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
-        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
-        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
-        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
-      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="TCR" access="Read/Write" description="SPI Test Control register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="7" name="TEST" description="SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="TSR" access="Read/Write" description="SPI Test Status register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SGPIO" start="0x40101000" description="Serial GPIO (SGPIO)">
-    <Register start="+0x0000+0" size="4" name="OUT_MUX_CFG[0]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+4" size="4" name="OUT_MUX_CFG[1]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+8" size="4" name="OUT_MUX_CFG[2]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+12" size="4" name="OUT_MUX_CFG[3]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+16" size="4" name="OUT_MUX_CFG[4]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+20" size="4" name="OUT_MUX_CFG[5]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+24" size="4" name="OUT_MUX_CFG[6]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+28" size="4" name="OUT_MUX_CFG[7]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+32" size="4" name="OUT_MUX_CFG[8]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+36" size="4" name="OUT_MUX_CFG[9]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+40" size="4" name="OUT_MUX_CFG[10]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+44" size="4" name="OUT_MUX_CFG[11]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+48" size="4" name="OUT_MUX_CFG[12]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+52" size="4" name="OUT_MUX_CFG[13]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+56" size="4" name="OUT_MUX_CFG[14]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+60" size="4" name="OUT_MUX_CFG[15]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040+0" size="4" name="SGPIO_MUX_CFG[0]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+4" size="4" name="SGPIO_MUX_CFG[1]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+8" size="4" name="SGPIO_MUX_CFG[2]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+12" size="4" name="SGPIO_MUX_CFG[3]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+16" size="4" name="SGPIO_MUX_CFG[4]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+20" size="4" name="SGPIO_MUX_CFG[5]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+24" size="4" name="SGPIO_MUX_CFG[6]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+28" size="4" name="SGPIO_MUX_CFG[7]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+32" size="4" name="SGPIO_MUX_CFG[8]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+36" size="4" name="SGPIO_MUX_CFG[9]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+40" size="4" name="SGPIO_MUX_CFG[10]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+44" size="4" name="SGPIO_MUX_CFG[11]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+48" size="4" name="SGPIO_MUX_CFG[12]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+52" size="4" name="SGPIO_MUX_CFG[13]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+56" size="4" name="SGPIO_MUX_CFG[14]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+60" size="4" name="SGPIO_MUX_CFG[15]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0080+0" size="4" name="SLICE_MUX_CFG[0]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+4" size="4" name="SLICE_MUX_CFG[1]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+8" size="4" name="SLICE_MUX_CFG[2]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+12" size="4" name="SLICE_MUX_CFG[3]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+16" size="4" name="SLICE_MUX_CFG[4]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+20" size="4" name="SLICE_MUX_CFG[5]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+24" size="4" name="SLICE_MUX_CFG[6]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+28" size="4" name="SLICE_MUX_CFG[7]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+32" size="4" name="SLICE_MUX_CFG[8]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+36" size="4" name="SLICE_MUX_CFG[9]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+40" size="4" name="SLICE_MUX_CFG[10]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+44" size="4" name="SLICE_MUX_CFG[11]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+48" size="4" name="SLICE_MUX_CFG[12]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+52" size="4" name="SLICE_MUX_CFG[13]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+56" size="4" name="SLICE_MUX_CFG[14]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+60" size="4" name="SLICE_MUX_CFG[15]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C0+0" size="4" name="REG[0]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+4" size="4" name="REG[1]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+8" size="4" name="REG[2]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+12" size="4" name="REG[3]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+16" size="4" name="REG[4]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+20" size="4" name="REG[5]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+24" size="4" name="REG[6]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+28" size="4" name="REG[7]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+32" size="4" name="REG[8]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+36" size="4" name="REG[9]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+40" size="4" name="REG[10]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+44" size="4" name="REG[11]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+48" size="4" name="REG[12]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+52" size="4" name="REG[13]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+56" size="4" name="REG[14]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+60" size="4" name="REG[15]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x0100+0" size="4" name="REG_SS[0]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+4" size="4" name="REG_SS[1]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+8" size="4" name="REG_SS[2]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+12" size="4" name="REG_SS[3]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+16" size="4" name="REG_SS[4]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+20" size="4" name="REG_SS[5]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+24" size="4" name="REG_SS[6]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+28" size="4" name="REG_SS[7]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+32" size="4" name="REG_SS[8]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+36" size="4" name="REG_SS[9]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+40" size="4" name="REG_SS[10]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+44" size="4" name="REG_SS[11]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+48" size="4" name="REG_SS[12]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+52" size="4" name="REG_SS[13]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+56" size="4" name="REG_SS[14]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+60" size="4" name="REG_SS[15]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0140+0" size="4" name="PRESET[0]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+4" size="4" name="PRESET[1]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+8" size="4" name="PRESET[2]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+12" size="4" name="PRESET[3]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+16" size="4" name="PRESET[4]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+20" size="4" name="PRESET[5]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+24" size="4" name="PRESET[6]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+28" size="4" name="PRESET[7]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+32" size="4" name="PRESET[8]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+36" size="4" name="PRESET[9]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+40" size="4" name="PRESET[10]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+44" size="4" name="PRESET[11]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+48" size="4" name="PRESET[12]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+52" size="4" name="PRESET[13]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+56" size="4" name="PRESET[14]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+60" size="4" name="PRESET[15]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+0" size="4" name="COUNT[0]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+4" size="4" name="COUNT[1]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+8" size="4" name="COUNT[2]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+12" size="4" name="COUNT[3]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+16" size="4" name="COUNT[4]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+20" size="4" name="COUNT[5]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+24" size="4" name="COUNT[6]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+28" size="4" name="COUNT[7]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+32" size="4" name="COUNT[8]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+36" size="4" name="COUNT[9]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+40" size="4" name="COUNT[10]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+44" size="4" name="COUNT[11]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+48" size="4" name="COUNT[12]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+52" size="4" name="COUNT[13]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+56" size="4" name="COUNT[14]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+60" size="4" name="COUNT[15]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+0" size="4" name="POS[0]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+4" size="4" name="POS[1]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+8" size="4" name="POS[2]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+12" size="4" name="POS[3]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+16" size="4" name="POS[4]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+20" size="4" name="POS[5]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+24" size="4" name="POS[6]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+28" size="4" name="POS[7]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+32" size="4" name="POS[8]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+36" size="4" name="POS[9]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+40" size="4" name="POS[10]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+44" size="4" name="POS[11]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+48" size="4" name="POS[12]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+52" size="4" name="POS[13]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+56" size="4" name="POS[14]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+60" size="4" name="POS[15]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0200" size="4" name="MASK_A" access="Read/Write" description="Mask for pattern match function of slice A" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_A" description="Mask for pattern match function of slice A  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0204" size="4" name="MASK_H" access="Read/Write" description="Mask for pattern match function of slice H" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_H" description="Mask for pattern match function of slice H  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0208" size="4" name="MASK_I" access="Read/Write" description="Mask for pattern match function of slice I" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_I" description="Mask for pattern match function of slice I  0 = No effect . 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x020C" size="4" name="MASK_P" access="Read/Write" description="Mask for pattern match function of slice P" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_P" description="Mask for pattern match function of slice P  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0210" size="4" name="GPIO_INREG" access="ReadOnly" description="GPIO input status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_INi" description="Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0214" size="4" name="GPIO_OUTREG" access="Read/Write" description="GPIO output control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_OUT" description="GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0218" size="4" name="GPIO_OENREG" access="Read/Write" description="GPIO OE control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_OE" description="Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x021C" size="4" name="CTRL_ENABLE" access="Read/Write" description="Enables the slice COUNT counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTRL_EN" description="Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0220" size="4" name="CTRL_DISABLE" access="Read/Write" description="Disables the slice POS counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTRL_DIS" description="Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F00" size="4" name="CLR_EN_0" access="WriteOnly" description="Shift clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_SCI" description="1 = Shift clock interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F04" size="4" name="SET_EN_0" access="WriteOnly" description="Shift clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_SCI" description="1 = Shift clock interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F08" size="4" name="ENABLE_0" access="ReadOnly" description="Shift clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_SCI" description="1 = Shift clock interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F0C" size="4" name="STATUS_0" access="ReadOnly" description="Shift clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_SCI" description="Shift clock interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F10" size="4" name="CLR_STATUS_0" access="WriteOnly" description="Shift clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_SCI" description="Shift clock interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F14" size="4" name="SET_STATUS_0" access="WriteOnly" description="Shift clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_SCI" description="Shift clock interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F20" size="4" name="CLR_EN_1" access="WriteOnly" description="Exchange clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN_CCI" description="1 = Exchange clock interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F24" size="4" name="SET_EN_1" access="WriteOnly" description="Exchange clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_CCI" description="1 = Exchange clock interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F28" size="4" name="ENABLE_1" access="ReadOnly" description="Exchange clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_CCI" description="Exchange clock interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F2C" size="4" name="STATUS_1" access="ReadOnly" description="Exchange clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_CCI" description="Exchange clock interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F30" size="4" name="CLR_STATUS_1" access="WriteOnly" description="Exchange clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_CCI" description="Exchange clock interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F34" size="4" name="SET_STATUS_1" access="WriteOnly" description="Exchange clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_CCI" description="Exchange clock interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F40" size="4" name="CLR_EN_2" access="WriteOnly" description="Pattern match interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN2_PMI" description="1 = Match interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F44" size="4" name="SET_EN_2" access="WriteOnly" description="Pattern match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_PMI" description="1 = Match interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F48" size="4" name="ENABLE_2" access="ReadOnly" description="Pattern match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_PMI" description="Match interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F4C" size="4" name="STATUS_2" access="ReadOnly" description="Pattern match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_PMI" description="Match interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F50" size="4" name="CLR_STATUS_2" access="WriteOnly" description="Pattern match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_PMI" description="Match interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F54" size="4" name="SET_STATUS_2" access="WriteOnly" description="Pattern match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_PMI" description="Match interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F60" size="4" name="CLR_EN_3" access="WriteOnly" description="Input interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN_INPI" description="1 = Input interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F64" size="4" name="SET_EN_3" access="WriteOnly" description="Input bit match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_INPI" description="1 = Input interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F68" size="4" name="ENABLE_3" access="ReadOnly" description="Input bit match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE3_INPI" description="Input interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F6C" size="4" name="STATUS_3" access="ReadOnly" description="Input bit match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_INPI" description="Input interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F70" size="4" name="CLR_STATUS_3" access="WriteOnly" description="Input bit match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_INPI" description="Input interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F74" size="4" name="SET_STATUS_3" access="WriteOnly" description="Input bit match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_INPI" description="Shift interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="DAC" start="5" size="3" />
-      <BitField name="DMA" start="21" size="3" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="FLASH" start="5" size="3" />
-      <BitField name="ETHERNET" start="13" size="3" />
-      <BitField name="SDIO" start="21" size="3" />
-      <BitField name="LCD" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="USB0" start="5" size="3" />
-      <BitField name="USB1" start="13" size="3" />
-      <BitField name="SCT" start="21" size="3" />
-      <BitField name="RITIMER" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TIMER0" start="5" size="3" />
-      <BitField name="TIMER1" start="13" size="3" />
-      <BitField name="TIMER2" start="21" size="3" />
-      <BitField name="TIMER3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="MCPWM" start="5" size="3" />
-      <BitField name="ADC0" start="13" size="3" />
-      <BitField name="I2C0" start="21" size="3" />
-      <BitField name="I2C1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SPI_INT" start="5" size="3" />
-      <BitField name="ADC1" start="13" size="3" />
-      <BitField name="SSP0" start="21" size="3" />
-      <BitField name="SSP1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USART0" start="5" size="3" />
-      <BitField name="UART1" start="13" size="3" />
-      <BitField name="USART2" start="21" size="3" />
-      <BitField name="USART3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="I2S0" start="5" size="3" />
-      <BitField name="I2S1" start="13" size="3" />
-      <BitField name="SPIFI" start="21" size="3" />
-      <BitField name="SGPIO_IINT" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PIN_INT0" start="5" size="3" />
-      <BitField name="PIN_INT1" start="13" size="3" />
-      <BitField name="PIN_INT2" start="21" size="3" />
-      <BitField name="PIN_INT3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="PIN_INT4" start="5" size="3" />
-      <BitField name="PIN_INT5" start="13" size="3" />
-      <BitField name="PIN_INT6" start="21" size="3" />
-      <BitField name="PIN_INT7" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="GINT0" start="5" size="3" />
-      <BitField name="GINT1" start="13" size="3" />
-      <BitField name="EVENTROUTER" start="21" size="3" />
-      <BitField name="C_CAN1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="ADCHS" start="13" size="3" />
-      <BitField name="ATIMER" start="21" size="3" />
-      <BitField name="RTC" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
-      <BitField name="WWDT" start="13" size="3" />
-      <BitField name="C_CAN0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
-      <BitField name="QEI" start="5" size="3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FPU" description="Floating Point Unit">
-    <Register name="CPACR" start="0xE000ED88" description="Coprocessor Access Control Register">
-      <BitField name="CP11" start="22" size="2" description="Access privileges for coprocessor 11" />
-      <BitField name="CP10" start="20" size="2" description="Access privileges for coprocessor 10" />
-    </Register>
-    <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register">
-      <BitField name="ASPEN" start="31" size="1" description="Automatic State Preservation" />
-      <BitField name="LSPEN" start="30" size="1" description="Lazy State Preservation Enabled" />
-      <BitField name="MONRDY" start="8" size="1" description="Monitor Ready" />
-      <BitField name="BFRDY" start="6" size="1" description="BusFault Ready" />
-      <BitField name="MMRDY" start="5" size="1" description="MemManage Ready" />
-      <BitField name="HFRDY" start="4" size="1" description="HardFault Ready" />
-      <BitField name="THREAD" start="3" size="1" description="Thread Mode Allocated Stack Frame" />
-      <BitField name="USER" start="1" size="1" description="User Allocated Stack Frame" />
-      <BitField name="LSPACT" start="0" size="1" description="Lazy State Preservation Active" />
-    </Register>
-    <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register">
-      <BitField name="ADDRESSS" start="3" size="29" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" />
-    </Register>
-    <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Status Control Register">
-      <BitField name="N" start="31" size="1" description="Negative condition code flag" />
-      <BitField name="Z" start="30" size="1" description="Zero condition code flag" />
-      <BitField name="C" start="29" size="1" description="Carry condition code flag" />
-      <BitField name="V" start="28" size="1" description="Overflow condition code flag" />
-      <BitField name="AHP" start="26" size="1" description="Alternative half-precision control bit" />
-      <BitField name="DN" start="25" size="1" description="Default NaN mode control bit" />
-      <BitField name="FZ" start="24" size="1" description="Flush-to-zero mode control bit" />
-      <BitField name="RMode" start="22" size="2" description="Rounding Mode control field" />
-      <BitField name="IDC" start="7" size="1" description="Input Denormal cumulative exception bit" />
-      <BitField name="IXC" start="4" size="1" description="Inexact cumulative exception bit" />
-      <BitField name="UFC" start="3" size="1" description="Underflow cumulative exception bit" />
-      <BitField name="OFC" start="2" size="1" description="Overflow cumulative exception bit" />
-      <BitField name="DZC" start="1" size="1" description="Division by Zero cumulative exception bit" />
-      <BitField name="IOC" start="0" size="1" description="Invalid Operation cumulative exception bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC43xx_Vectors.s b/examples/host/cdc_msc_hid/ses/lpc43xx/LPC43xx_Vectors.s
deleted file mode 100644
index ab223b8a..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/LPC43xx_Vectors.s
+++ /dev/null
@@ -1,540 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak USB0_IRQHandler
-  .thumb_set USB0_IRQHandler,Dummy_Handler
-
-  .weak USB1_IRQHandler
-  .thumb_set USB1_IRQHandler,Dummy_Handler
-
-  .weak SCT_IRQHandler
-  .thumb_set SCT_IRQHandler,Dummy_Handler
-
-  .weak RITIMER_IRQHandler
-  .thumb_set RITIMER_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak ADC0_IRQHandler
-  .thumb_set ADC0_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak SPI_INT_IRQHandler
-  .thumb_set SPI_INT_IRQHandler,Dummy_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak USART0_IRQHandler
-  .thumb_set USART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Dummy_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Dummy_Handler
-
-  .weak I2S0_IRQHandler
-  .thumb_set I2S0_IRQHandler,Dummy_Handler
-
-  .weak I2S1_IRQHandler
-  .thumb_set I2S1_IRQHandler,Dummy_Handler
-
-  .weak SPIFI_IRQHandler
-  .thumb_set SPIFI_IRQHandler,Dummy_Handler
-
-  .weak SGPIO_IINT_IRQHandler
-  .thumb_set SGPIO_IINT_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak EVENTROUTER_IRQHandler
-  .thumb_set EVENTROUTER_IRQHandler,Dummy_Handler
-
-  .weak C_CAN1_IRQHandler
-  .thumb_set C_CAN1_IRQHandler,Dummy_Handler
-
-  .weak ADCHS_IRQHandler
-  .thumb_set ADCHS_IRQHandler,Dummy_Handler
-
-  .weak ATIMER_IRQHandler
-  .thumb_set ATIMER_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak C_CAN0_IRQHandler
-  .thumb_set C_CAN0_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak DAC_IRQHandler
-DAC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDIO_IRQHandler
-SDIO_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB0_IRQHandler
-USB0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB1_IRQHandler
-USB1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SCT_IRQHandler
-SCT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RITIMER_IRQHandler
-RITIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC0_IRQHandler
-ADC0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI_INT_IRQHandler
-SPI_INT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC1_IRQHandler
-ADC1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART0_IRQHandler
-USART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_IRQHandler
-USART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART3_IRQHandler
-USART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S0_IRQHandler
-I2S0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S1_IRQHandler
-I2S1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPIFI_IRQHandler
-SPIFI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SGPIO_IINT_IRQHandler
-SGPIO_IINT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EVENTROUTER_IRQHandler
-EVENTROUTER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN1_IRQHandler
-C_CAN1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADCHS_IRQHandler
-ADCHS_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ATIMER_IRQHandler
-ATIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN0_IRQHandler
-C_CAN0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word DAC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word DMA_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word FLASH_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDIO_IRQHandler
-  .word LCD_IRQHandler
-  .word USB0_IRQHandler
-  .word USB1_IRQHandler
-  .word SCT_IRQHandler
-  .word RITIMER_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word MCPWM_IRQHandler
-  .word ADC0_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word SPI_INT_IRQHandler
-  .word ADC1_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word USART0_IRQHandler
-  .word UART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word I2S0_IRQHandler
-  .word I2S1_IRQHandler
-  .word SPIFI_IRQHandler
-  .word SGPIO_IINT_IRQHandler
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word EVENTROUTER_IRQHandler
-  .word C_CAN1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word ADCHS_IRQHandler
-  .word ATIMER_IRQHandler
-  .word RTC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word WWDT_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word C_CAN0_IRQHandler
-  .word QEI_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/flash_placement.xml b/examples/host/cdc_msc_hid/ses/lpc43xx/flash_placement.xml
deleted file mode 100644
index 79bedc53..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject b/examples/host/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject
deleted file mode 100644
index 2d99ae6c..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject
+++ /dev/null
@@ -1,137 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="lpc43xx" target="8" version="2">
-  <project Name="lpc43xx">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4357 Cortex-M4"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="1024"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="1024"
-      arm_simulator_memory_simulation_parameter="RX 1a000000,00080000,FFFFFFFF;RWX 10000000,00008000,CDCDCDCD"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC4357_M4"
-      arm_target_interface_type="SWD"
-      build_treat_warnings_as_errors="No"
-      c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4357;CFG_TUSB_MCU=OPT_MCU_LPC43XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
-      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)//inc;$(rootDir)/lib/SEGGER_RTT/RTT;$(lpcDir)//inc/config_43xx"
-      debug_register_definition_file="LPC43xx_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_enable_all_warnings="Yes"
-      gcc_entry_point="Reset_Handler"
-      link_use_linker_script_file="No"
-      linker_memory_map_file="LPC4357 Cortex-M4_MemoryMap.xml"
-      linker_section_placement_file="flash_placement.xml"
-      linker_section_placements_segments="FLASH RX 0x1a000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_script_file="$(ProjectDir)/LPC4300_Target.js"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../../src"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="ea4357">
-          <file file_name="../../../../../hw/bsp/ea4357/ea4357.c" />
-          <file file_name="../../../../../hw/bsp/ea4357/pca9532.c" />
-          <file file_name="../../../../../hw/bsp/ea4357/pca9532.h" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc_chip_43xx">
-            <folder Name="inc">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/arm_common_tables.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/arm_math.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cguccu_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip_clocks.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip_lpc18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/chip_lpc43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/clock_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_18xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_43xx_m0app.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm0.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm0plus.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm3.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm4.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cm4_simd.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cmFunc.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_cmInstr.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_sc000.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/core_sc300.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/creg_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/fpu_init.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/gpio_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/i2c_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/i2cm_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/lpc_types.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/packing.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/uart_18xx_43xx.h" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/usbhs_18xx_43xx.h" />
-              <folder Name="config_43xx">
-                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/inc/config_43xx/sys_config.h" />
-              </folder>
-            </folder>
-            <folder Name="src">
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/chip_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/clock_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/fpu_init.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/gpio_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/i2c_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/i2cm_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/sysinit_18xx_43xx.c" />
-              <file file_name="../../../../../hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx/src/uart_18xx_43xx.c" />
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration Name="Debug" build_treat_warnings_as_errors="Yes" />
-    <folder
-      Name="src"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../src"
-      recurse="Yes" />
-    <folder Name="System Files">
-      <file file_name="flash_placement.xml" />
-      <file file_name="LPC4300_Startup.s" />
-      <file file_name="LPC4300_Target.js" />
-      <file file_name="LPC4357 Cortex-M4_MemoryMap.xml" />
-      <file file_name="LPC43xx_Registers.xml" />
-      <file file_name="LPC43xx_Vectors.s" />
-      <file file_name="thumb_crt0.s" />
-    </folder>
-    <folder Name="lib">
-      <folder Name="SEGGER_RTT">
-        <folder Name="RTT">
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.c" />
-          <file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c" />
-        </folder>
-        <folder Name="Syscalls">
-          <file file_name="../../../../../lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c" />
-        </folder>
-      </folder>
-    </folder>
-  </project>
-</solution>
diff --git a/examples/host/cdc_msc_hid/ses/lpc43xx/thumb_crt0.s b/examples/host/cdc_msc_hid/ses/lpc43xx/thumb_crt0.s
deleted file mode 100644
index 17f88e0c..00000000
--- a/examples/host/cdc_msc_hid/ses/lpc43xx/thumb_crt0.s
+++ /dev/null
@@ -1,415 +0,0 @@
-// **********************************************************************
-// *                    SEGGER Microcontroller GmbH                     *
-// *                        The Embedded Experts                        *
-// **********************************************************************
-// *                                                                    *
-// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
-// *            (c) 2001 - 2018 Rowley Associates Limited               *
-// *                                                                    *
-// *           www.segger.com     Support: support@segger.com           *
-// *                                                                    *
-// **********************************************************************
-// *                                                                    *
-// * All rights reserved.                                               *
-// *                                                                    *
-// * Redistribution and use in source and binary forms, with or         *
-// * without modification, are permitted provided that the following    *
-// * conditions are met:                                                *
-// *                                                                    *
-// * - Redistributions of source code must retain the above copyright   *
-// *   notice, this list of conditions and the following disclaimer.    *
-// *                                                                    *
-// * - Neither the name of SEGGER Microcontroller GmbH                  *
-// *   nor the names of its contributors may be used to endorse or      *
-// *   promote products derived from this software without specific     *
-// *   prior written permission.                                        *
-// *                                                                    *
-// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-// * DISCLAIMED.                                                        *
-// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
-// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-// * DAMAGE.                                                            *
-// *                                                                    *
-// **********************************************************************
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .balign 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .balign 2
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-

From 143582870c8a4175706109e238f4cfa814ae90bc Mon Sep 17 00:00:00 2001
From: Rafael Silva <silvagracarafael@gmail.com>
Date: Thu, 4 Mar 2021 23:00:48 +0000
Subject: [PATCH 31/72] add efm32gg12 family

Signed-off-by: Rafael Silva <silvagracarafael@gmail.com>
---
 hw/bsp/board_mcu.h | 3 +++
 src/tusb_option.h  | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index a175197e..3c18f6d3 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -119,6 +119,9 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_RP2040
   #include "pico.h"
+  
+#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12
+  #include "em_device.h"
 
 #else
   #error "Missing MCU header"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cafe9e52..d0ed78ac 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -103,6 +103,11 @@
 // NXP Kinetis
 #define OPT_MCU_MKL25ZXX         1200 ///< NXP MKL25Zxx
 
+// Silabs
+#define OPT_MCU_EFM32GG          1300 ///< Silabs EFM32GG
+#define OPT_MCU_EFM32GG11        1301 ///< Silabs EFM32GG11
+#define OPT_MCU_EFM32GG12        1302 ///< Silabs EFM32GG12
+
 /** @} */
 
 /** \defgroup group_supported_os Supported RTOS

From fb661a99bd0668044004278cd9473e0a9e07ff04 Mon Sep 17 00:00:00 2001
From: Rafael Silva <silvagracarafael@gmail.com>
Date: Thu, 4 Mar 2021 23:20:24 +0000
Subject: [PATCH 32/72] added efm32gg12 family cmsis

Signed-off-by: Rafael Silva <silvagracarafael@gmail.com>
---
 .gitmodules                        | 3 +++
 hw/mcu/silabs/cmsis-dfp-efm32gg12b | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 hw/mcu/silabs/cmsis-dfp-efm32gg12b

diff --git a/.gitmodules b/.gitmodules
index c0e6eef0..1a5ae2c5 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -113,3 +113,6 @@
 [submodule "lib/CMSIS_5"]
 	path = lib/CMSIS_5
 	url = https://github.com/ARM-software/CMSIS_5.git
+[submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
+	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
+	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
diff --git a/hw/mcu/silabs/cmsis-dfp-efm32gg12b b/hw/mcu/silabs/cmsis-dfp-efm32gg12b
new file mode 160000
index 00000000..f1c31b78
--- /dev/null
+++ b/hw/mcu/silabs/cmsis-dfp-efm32gg12b
@@ -0,0 +1 @@
+Subproject commit f1c31b7887669cb230b3ea63f9b56769078960bc

From 2807644e7e72150b96be0f40a263f689a6de994a Mon Sep 17 00:00:00 2001
From: Rafael Silva <silvagracarafael@gmail.com>
Date: Thu, 4 Mar 2021 23:02:42 +0000
Subject: [PATCH 33/72] add efm32 driver

Signed-off-by: Rafael Silva <silvagracarafael@gmail.com>
---
 src/portable/silabs/efm32/dcd_efm32.c | 931 ++++++++++++++++++++++++++
 1 file changed, 931 insertions(+)
 create mode 100644 src/portable/silabs/efm32/dcd_efm32.c

diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c
new file mode 100644
index 00000000..bd1f32e6
--- /dev/null
+++ b/src/portable/silabs/efm32/dcd_efm32.c
@@ -0,0 +1,931 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Rafael Silva (@perigoso)
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && ( \
+  (CFG_TUSB_MCU == OPT_MCU_EFM32GG) || \
+  (CFG_TUSB_MCU == OPT_MCU_EFM32GG11) || \
+  (CFG_TUSB_MCU == OPT_MCU_EFM32GG12) )
+
+/* Silabs */
+#include "em_device.h"
+
+#include "device/dcd.h"
+
+/* 
+ * Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+ * We disable SOF for now until needed later on
+ */
+#define USE_SOF     0
+
+/* 
+ * Number of endpoints
+ * 12 software-configurable endpoints (6 IN, 6 OUT) in addition to endpoint 0
+ */
+#define EP_COUNT        7
+
+/* FIFO size in bytes */
+#define EP_FIFO_SIZE    2048
+
+/* Max number of IN EP FIFOs */
+#define EP_FIFO_NUM     7
+
+/* */
+typedef struct {
+    uint8_t *buffer;
+    uint16_t total_len;
+    uint16_t queued_len;
+    uint16_t max_size;
+    bool short_packet;
+} xfer_ctl_t;
+
+static uint32_t _setup_packet[2];
+
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+static xfer_ctl_t xfer_status[EP_COUNT][2];
+
+/* Keep count of how many FIFOs are in use */
+static uint8_t _allocated_fifos = 1; /* FIFO0 is always in use */
+
+static volatile uint32_t* tx_fifo[EP_FIFO_NUM] = {
+  USB->FIFO0D,
+  USB->FIFO1D,
+  USB->FIFO2D,
+  USB->FIFO3D,
+  USB->FIFO4D,
+  USB->FIFO5D,
+  USB->FIFO6D,
+};
+
+/* Register Helpers */
+#define DCTL_WO_BITMASK     (USB_DCTL_CGOUTNAK | USB_DCTL_SGOUTNAK | USB_DCTL_CGNPINNAK | USB_DCTL_SGNPINNAK)
+#define GUSBCFG_WO_BITMASK  (USB_GUSBCFG_CORRUPTTXPKT)
+#define DEPCTL_WO_BITMASK   (USB_DIEP_CTL_CNAK | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_SETD0PIDEF | USB_DIEP_CTL_SETD1PIDOF)
+
+/* Will either return an unused FIFO number, or 0 if all are used. */
+static uint8_t get_free_fifo(void)
+{
+  if(_allocated_fifos < EP_FIFO_NUM) return _allocated_fifos++;
+  return 0;
+}
+
+/*
+static void flush_rx_fifo(void)
+{
+  USB->GRSTCTL = USB_GRSTCTL_RXFFLSH;
+  while(USB->GRSTCTL & USB_GRSTCTL_RXFFLSH);
+} 
+*/
+
+static void flush_tx_fifo(uint8_t fifo_num)
+{
+  USB->GRSTCTL = USB_GRSTCTL_TXFFLSH | (fifo_num << _USB_GRSTCTL_TXFNUM_SHIFT);
+  while(USB->GRSTCTL & USB_GRSTCTL_TXFFLSH);
+}
+
+/* Setup the control endpoint 0. */
+static void bus_reset(void)
+{
+  USB->DOEP0CTL |= USB_DIEP_CTL_SNAK;
+  for(uint8_t i = 0; i < EP_COUNT - 1; i++)
+  {
+    USB->DOEP[i].CTL |= USB_DIEP_CTL_SNAK;
+  }
+  
+  /* reset address */
+  USB->DCFG &= ~_USB_DCFG_DEVADDR_MASK;
+
+  USB->DAINTMSK |= USB_DAINTMSK_OUTEPMSK0 | USB_DAINTMSK_INEPMSK0;
+  USB->DOEPMSK |= USB_DOEPMSK_SETUPMSK | USB_DOEPMSK_XFERCOMPLMSK;
+  USB->DIEPMSK |= USB_DIEPMSK_TIMEOUTMSK | USB_DIEPMSK_XFERCOMPLMSK;
+
+  /* 
+   * - All EP OUT shared a unique OUT FIFO which uses
+   *   * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
+   *   * 2 locations for OUT endpoint control words.
+   *   * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
+   *   * 1 location for global NAK (not required/used here).
+   *   * It is recommended to allocate 2 times the largest packet size, therefore
+   *  Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
+   */
+  flush_tx_fifo(_USB_GRSTCTL_TXFNUM_FALL);  // Flush All
+  USB->GRXFSIZ = 52;
+
+  /* Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) */
+  USB->GNPTXFSIZ = (16 << _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT) | (USB->GRXFSIZ & _USB_GNPTXFSIZ_NPTXFSTADDR_MASK);
+
+  /* Ready to receive SETUP packet */
+  USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_SUPCNT_SHIFT);
+
+  USB->GINTMSK |= USB_GINTMSK_IEPINTMSK | USB_GINTMSK_OEPINTMSK;
+}
+
+static void enum_done_processing(void)
+{
+  /* Maximum packet size for EP 0 is set for both directions by writing DIEPCTL */
+  if((USB->DSTS & _USB_DSTS_ENUMSPD_MASK) == USB_DSTS_ENUMSPD_FS)
+  { 
+    /* Full Speed (PHY on 48 MHz) */
+    USB->DOEP0CTL = (USB->DOEP0CTL & ~_USB_DOEP0CTL_MPS_MASK) | _USB_DOEP0CTL_MPS_64B; /* Maximum Packet Size 64 bytes */
+    USB->DOEP0CTL &= ~_USB_DOEP0CTL_STALL_MASK; /* clear Stall */
+    xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+    xfer_status[0][TUSB_DIR_IN].max_size = 64;
+  }
+  else
+  { 
+    /* Low Speed (PHY on 6 MHz) */
+    USB->DOEP0CTL = (USB->DOEP0CTL & ~_USB_DOEP0CTL_MPS_MASK) | _USB_DOEP0CTL_MPS_8B; /* Maximum Packet Size 64 bytes */
+    USB->DOEP0CTL &= ~_USB_DOEP0CTL_STALL_MASK; /* clear Stall */
+    xfer_status[0][TUSB_DIR_OUT].max_size = 8;
+    xfer_status[0][TUSB_DIR_IN].max_size = 8;
+  }
+}
+
+
+/*------------------------------------------------------------------*/
+/* Controller API                                                   */
+/*------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  /* Reset Core */
+  USB->PCGCCTL &= ~USB_PCGCCTL_STOPPCLK;
+  USB->PCGCCTL &= ~(USB_PCGCCTL_PWRCLMP | USB_PCGCCTL_RSTPDWNMODULE);
+
+  /* Core Soft Reset */
+  USB->GRSTCTL |= USB_GRSTCTL_CSFTRST;
+  while(USB->GRSTCTL & USB_GRSTCTL_CSFTRST);
+
+  while(!(USB->GRSTCTL & USB_GRSTCTL_AHBIDLE));
+
+  /* Enable PHY pins */
+  USB->ROUTE = USB_ROUTE_PHYPEN;
+
+  dcd_disconnect(rhport);
+
+  /* 
+   * Set device speed (Full speed PHY)
+   * Stall on non-zero len status OUT packets (ctrl transfers)
+   * periodic frame interval to 80% 
+   */
+  USB->DCFG = (USB->DCFG & ~(_USB_DCFG_DEVSPD_MASK | _USB_DCFG_PERFRINT_MASK)) | USB_DCFG_DEVSPD_FS | USB_DCFG_NZSTSOUTHSHK;
+  
+  /* Enable Global Interrupts */
+  USB->GAHBCFG = (USB->GAHBCFG & ~_USB_GAHBCFG_HBSTLEN_MASK) | USB_GAHBCFG_GLBLINTRMSK;
+
+  /* Force Device Mode */
+  USB->GUSBCFG = (USB->GUSBCFG & ~(GUSBCFG_WO_BITMASK | USB_GUSBCFG_FORCEHSTMODE)) | USB_GUSBCFG_FORCEDEVMODE;
+
+  /* No Overrides */
+  USB->GOTGCTL &= ~(USB_GOTGCTL_BVALIDOVVAL | USB_GOTGCTL_BVALIDOVEN | USB_GOTGCTL_VBVALIDOVVAL);
+
+  /* Ignore frame numbers on ISO transfers. */
+  USB->DCTL = (USB->DCTL & ~DCTL_WO_BITMASK) | USB_DCTL_IGNRFRMNUM;
+
+  /* Setting SNAKs */
+  USB->DOEP0CTL |= USB_DIEP_CTL_SNAK;
+  for(uint8_t i = 0; i < EP_COUNT - 1; i++)
+  {
+    USB->DOEP[i].CTL |= USB_DIEP_CTL_SNAK;
+  }
+
+  /* D. Interruption masking */
+  /* Disable all device interrupts */
+  USB->DIEPMSK  = 0;
+  USB->DOEPMSK  = 0;
+  USB->DAINTMSK = 0;
+  USB->DIEPEMPMSK = 0;
+  USB->GINTMSK = 0;
+  USB->GOTGINT = ~0U; /* clear OTG ints */
+  USB->GINTSTS = ~0U; /* clear pending ints */
+  USB->GINTMSK = USB_GINTMSK_MODEMISMSK  |
+              #if USE_SOF
+                 USB_GINTMSK_SOFMSK      |
+              #endif
+                 USB_GINTMSK_ERLYSUSPMSK |
+                 USB_GINTMSK_USBSUSPMSK  |
+                 USB_GINTMSK_USBRSTMSK   |
+                 USB_GINTMSK_ENUMDONEMSK |
+                 USB_GINTMSK_RESETDETMSK |
+                 USB_GINTMSK_DISCONNINTMSK;
+
+  NVIC_ClearPendingIRQ(USB_IRQn);
+
+  dcd_connect(rhport);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+
+  USB->DCFG = (USB->DCFG & ~_USB_DCFG_DEVADDR_MASK) | (dev_addr << _USB_DCFG_DEVADDR_SHIFT);
+
+  /* Response with status after changing device address */
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+
+  /* connect by enabling internal pull-up resistor on D+/D- */
+  USB->DCTL &= ~(DCTL_WO_BITMASK | USB_DCTL_SFTDISCON);
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+
+  /* disconnect by disabling internal pull-up resistor on D+/D- */
+  USB->DCTL = (USB->DCTL & ~(DCTL_WO_BITMASK)) | USB_DCTL_SFTDISCON;
+}
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint Port                                                */
+/*------------------------------------------------------------------*/
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  if(dir == TUSB_DIR_IN)
+  {
+    if(epnum == 0)
+    {
+      USB->DIEP0CTL = (USB->DIEP0CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP0CTL_SNAK | USB_DIEP0CTL_STALL;
+
+      flush_tx_fifo(_USB_GRSTCTL_TXFNUM_F0);
+    }
+    else
+    {
+      /* Only disable currently enabled non-control endpoint */
+      if(USB->DIEP[epnum - 1].CTL & USB_DIEP_CTL_EPENA) 
+      {
+        USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_EPDIS | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_STALL;
+        while(!(USB->DIEP[epnum - 1].INT & USB_DIEP_INT_EPDISBLD));
+        USB->DIEP[epnum - 1].INT |= USB_DIEP_INT_EPDISBLD;
+      }
+      else
+      {
+        USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_STALL;
+      }
+
+      /* Flush the FIFO */
+      uint8_t const fifo_num = ((USB->DIEP[epnum - 1].CTL & _USB_DIEP_CTL_TXFNUM_MASK) >> _USB_DIEP_CTL_TXFNUM_SHIFT);
+      flush_tx_fifo(fifo_num);
+    }
+  }
+  else
+  {
+    if(epnum == 0)
+    {
+      USB->DOEP0CTL = (USB->DOEP0CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP0CTL_STALL;
+    }
+    else
+    {
+      /* Only disable currently enabled non-control endpoint */
+      if(USB->DOEP[epnum - 1].CTL & USB_DIEP_CTL_EPENA) 
+      {
+        /* Asserting GONAK is required to STALL an OUT endpoint. */
+        USB->DCTL |= USB_DCTL_SGOUTNAK;
+        while(!(USB->GINTSTS & USB_GINTSTS_GOUTNAKEFF));
+        
+        /* Disable the endpoint. Note that only STALL and not SNAK is set here. */
+        USB->DOEP[epnum - 1].CTL = (USB->DOEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_EPDIS | USB_DIEP_CTL_STALL;
+        while(USB->DOEP[epnum - 1].INT & USB_DIEP_INT_EPDISBLD);
+        USB->DOEP[epnum - 1].INT |= USB_DIEP_INT_EPDISBLD;
+
+        /* Allow other OUT endpoints to keep receiving. */
+        USB->DCTL |= USB_DCTL_CGOUTNAK;
+      }
+      else
+      {
+        USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_STALL;
+      }
+    }
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  if(dir == TUSB_DIR_IN)
+  {
+    if(epnum == 0)
+    {
+      USB->DIEP0CTL &= ~(DEPCTL_WO_BITMASK | USB_DIEP0CTL_STALL);
+    }
+    else
+    {
+      USB->DIEP[epnum - 1].CTL &= ~(DEPCTL_WO_BITMASK | USB_DIEP_CTL_STALL);
+    
+      /* Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. */
+      uint8_t eptype = (USB->DIEP[epnum - 1].CTL & _USB_DIEP_CTL_EPTYPE_MASK) >> _USB_DIEP_CTL_EPTYPE_SHIFT;
+
+      if((eptype == _USB_DIEP_CTL_EPTYPE_BULK) || (eptype == _USB_DIEP_CTL_EPTYPE_INT))
+      {
+        USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_SETD0PIDEF;
+      }
+    }
+  }
+  else
+  {
+    if(epnum == 0)
+    {
+      USB->DOEP0CTL &= ~(DEPCTL_WO_BITMASK | USB_DOEP0CTL_STALL);
+    }
+    else
+    {
+      USB->DOEP[epnum - 1].CTL &= ~(DEPCTL_WO_BITMASK | USB_DOEP_CTL_STALL);
+    
+      /* Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. */
+      uint8_t eptype = (USB->DOEP[epnum - 1].CTL & _USB_DOEP_CTL_EPTYPE_MASK) >> _USB_DOEP_CTL_EPTYPE_SHIFT;
+
+      if((eptype == _USB_DOEP_CTL_EPTYPE_BULK) || (eptype == _USB_DOEP_CTL_EPTYPE_INT))
+      {
+        USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_SETD0PIDEF;
+      }
+    }
+  }
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void)rhport;
+
+  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+  TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= 64);
+  TU_ASSERT(epnum < EP_COUNT);
+  TU_ASSERT(epnum != 0);
+
+  xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = p_endpoint_desc->wMaxPacketSize.size;
+
+  if(dir == TUSB_DIR_OUT)
+  {
+    USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_USBACTEP |
+                                (p_endpoint_desc->bmAttributes.xfer << _USB_DOEP_CTL_EPTYPE_SHIFT) |
+                                (p_endpoint_desc->wMaxPacketSize.size << _USB_DOEP_CTL_MPS_SHIFT);
+    USB->DAINTMSK |= (1 << (_USB_DAINTMSK_OUTEPMSK0_SHIFT + epnum));
+  }
+  else
+  {
+    uint8_t fifo_num = get_free_fifo();
+    TU_ASSERT(fifo_num != 0);
+
+    USB->DIEP[epnum - 1].CTL &= ~(_USB_DIEP_CTL_TXFNUM_MASK | _USB_DIEP_CTL_EPTYPE_MASK | USB_DIEP_CTL_SETD0PIDEF | _USB_DIEP_CTL_MPS_MASK);
+    USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_USBACTEP |
+                                (fifo_num << _USB_DIEP_CTL_TXFNUM_SHIFT) |
+                                (p_endpoint_desc->bmAttributes.xfer << _USB_DIEP_CTL_EPTYPE_SHIFT) |
+                                ((p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) ? USB_DIEP_CTL_SETD0PIDEF : 0) |
+                                (p_endpoint_desc->wMaxPacketSize.size << 0);
+
+    USB->DAINTMSK |= (1 << epnum);
+
+    /* Both TXFD and TXSA are in unit of 32-bit words. */
+    /* IN FIFO 0 was configured during enumeration, hence the "+ 16". */
+    uint16_t const allocated_size = (USB->GRXFSIZ & _USB_GRXFSIZ_RXFDEP_MASK) + 16;
+    uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_FIFO_NUM-1);
+    uint32_t const fifo_offset = allocated_size + fifo_size*(fifo_num-1);
+
+    /* DIEPTXF starts at FIFO #1. */
+    volatile uint32_t* usb_dieptxf = &USB->DIEPTXF1;
+    usb_dieptxf[epnum - 1] = (fifo_size << _USB_DIEPTXF1_INEPNTXFDEP_SHIFT) | fifo_offset;
+  }
+  return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer       = buffer;
+  xfer->total_len    = total_bytes;
+  xfer->queued_len   = 0;
+  xfer->short_packet = false;
+
+  uint16_t num_packets = (total_bytes / xfer->max_size);
+  uint8_t short_packet_size = total_bytes % xfer->max_size;
+
+  // Zero-size packet is special case.
+  if(short_packet_size > 0 || (total_bytes == 0))
+  {
+    num_packets++;
+  }
+
+  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
+  // here.
+  if(dir == TUSB_DIR_IN)
+  {
+    if(epnum == 0)
+    {
+      // A full IN transfer (multiple packets, possibly) triggers XFRC.
+      USB->DIEP0TSIZ = (num_packets << _USB_DIEP0TSIZ_PKTCNT_SHIFT) | total_bytes;
+      USB->DIEP0CTL |= USB_DIEP0CTL_EPENA | USB_DIEP0CTL_CNAK; // Enable | CNAK
+    }
+    else
+    {
+      // A full IN transfer (multiple packets, possibly) triggers XFRC.
+      USB->DIEP[epnum - 1].TSIZ = (num_packets << _USB_DIEP_TSIZ_PKTCNT_SHIFT) | total_bytes;
+      USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_EPENA | USB_DIEP_CTL_CNAK; // Enable | CNAK
+    }
+    
+    // Enable fifo empty interrupt only if there are something to put in the fifo.
+    if(total_bytes != 0)
+    {
+      USB->DIEPEMPMSK |= (1 << epnum);
+    }
+  }
+  else
+  {
+    if(epnum == 0)
+    {
+      // A full IN transfer (multiple packets, possibly) triggers XFRC.
+      USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP0TSIZ_XFERSIZE_MASK) << _USB_DOEP0TSIZ_XFERSIZE_SHIFT);
+      USB->DOEP0CTL |= USB_DOEP0CTL_EPENA | USB_DOEP0CTL_CNAK;
+    }
+    else
+    {
+      // A full IN transfer (multiple packets, possibly) triggers XFRC.
+      USB->DOEP[epnum - 1].TSIZ |= (1 << _USB_DOEP_TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP_TSIZ_XFERSIZE_MASK) << _USB_DOEP_TSIZ_XFERSIZE_SHIFT);
+      USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_EPENA | USB_DOEP_CTL_CNAK;
+    }
+  }
+  return true;
+}
+
+/*------------------------------------------------------------------*/
+/* IRQ                                                              */
+/*------------------------------------------------------------------*/
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+
+  NVIC_DisableIRQ(USB_IRQn);
+}
+
+static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size)
+{
+  uint16_t remaining = xfer->total_len - xfer->queued_len;
+  uint16_t to_recv_size;
+
+  if(remaining <= xfer->max_size)
+  {
+    /* Avoid buffer overflow. */
+    to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
+  }
+  else
+  {
+    /* Room for full packet, choose recv_size based on what the microcontroller claims. */
+    to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
+  }
+
+  uint8_t to_recv_rem = to_recv_size % 4;
+  uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
+
+  /* Do not assume xfer buffer is aligned. */
+  uint8_t *base = (xfer->buffer + xfer->queued_len);
+
+  /* This for loop always runs at least once- skip if less than 4 bytes to collect. */
+  if(to_recv_size >= 4)
+  {
+    for(uint16_t i = 0; i < to_recv_size_aligned; i += 4)
+    {
+      uint32_t tmp = (*USB->FIFO0D);
+      base[i] = tmp & 0x000000FF;
+      base[i + 1] = (tmp & 0x0000FF00) >> 8;
+      base[i + 2] = (tmp & 0x00FF0000) >> 16;
+      base[i + 3] = (tmp & 0xFF000000) >> 24;
+    }
+  }
+
+  /* Do not read invalid bytes from RX FIFO. */
+  if(to_recv_rem != 0)
+  {
+    uint32_t tmp = (*USB->FIFO0D);
+    uint8_t *last_32b_bound = base + to_recv_size_aligned;
+
+    last_32b_bound[0] = tmp & 0x000000FF;
+    if(to_recv_rem > 1)
+    {
+      last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
+    }
+    if(to_recv_rem > 2)
+    {
+      last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
+    }
+  }
+
+  xfer->queued_len += xfer_size;
+
+  /* Per USB spec, a short OUT packet (including length 0) is always */
+  /* indicative of the end of a transfer (at least for ctl, bulk, int). */
+  xfer->short_packet = (xfer_size < xfer->max_size);
+}
+
+static void transmit_packet(xfer_ctl_t *xfer, uint8_t fifo_num)
+{
+  uint16_t remaining;
+  if(fifo_num == 0)
+  {
+    remaining = (USB->DIEP0TSIZ & 0x7FFFFU) >> _USB_DIEP0TSIZ_XFERSIZE_SHIFT;
+  }
+  else
+  {
+    remaining = (USB->DIEP[fifo_num - 1].TSIZ & 0x7FFFFU) >> _USB_DIEP_TSIZ_XFERSIZE_SHIFT;
+  }
+  xfer->queued_len = xfer->total_len - remaining;
+
+  uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
+  uint8_t to_xfer_rem = to_xfer_size % 4;
+  uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
+
+  /* Buffer might not be aligned to 32b, so we need to force alignment by copying to a temp var. */
+  uint8_t *base = (xfer->buffer + xfer->queued_len);
+
+  /* This for loop always runs at least once- skip if less than 4 bytes to send off. */
+  if(to_xfer_size >= 4)
+  {
+    for(uint16_t i = 0; i < to_xfer_size_aligned; i += 4)
+    {
+      uint32_t tmp = base[i] | (base[i + 1] << 8) | (base[i + 2] << 16) | (base[i + 3] << 24);
+      *tx_fifo[fifo_num] = tmp;
+    }
+  }
+
+  /* Do not read beyond end of buffer if not divisible by 4. */
+  if(to_xfer_rem != 0)
+  {
+    uint32_t tmp = 0;
+    uint8_t *last_32b_bound = base + to_xfer_size_aligned;
+
+    tmp |= last_32b_bound[0];
+    if(to_xfer_rem > 1)
+    {
+      tmp |= (last_32b_bound[1] << 8);
+    }
+    if(to_xfer_rem > 2)
+    {
+      tmp |= (last_32b_bound[2] << 16);
+    }
+
+    *tx_fifo[fifo_num] = tmp;
+  }
+}
+
+static void read_rx_fifo(void)
+{
+  /*
+   * Pop control word off FIFO (completed xfers will have 2 control words,
+   * we only pop one ctl word each interrupt).
+   */
+  uint32_t const ctl_word = USB->GRXSTSP;
+  uint8_t  const pktsts   = (ctl_word & _USB_GRXSTSP_PKTSTS_MASK) >> _USB_GRXSTSP_PKTSTS_SHIFT;
+  uint8_t  const epnum    = (ctl_word & _USB_GRXSTSP_CHNUM_MASK ) >> _USB_GRXSTSP_CHNUM_SHIFT;
+  uint16_t const bcnt     = (ctl_word & _USB_GRXSTSP_BCNT_MASK  ) >> _USB_GRXSTSP_BCNT_SHIFT;
+
+  switch(pktsts)
+  {
+    case 0x01: /* Global OUT NAK (Interrupt) */
+      break;
+
+    case 0x02:
+    { 
+      /* Out packet recvd */
+      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+      receive_packet(xfer, bcnt);
+    }
+    break;
+
+    case 0x03:
+      /* Out packet done (Interrupt) */
+      break;
+
+    case 0x04: 
+      /* Step 2: Setup transaction completed (Interrupt) */
+      /* After this event, OEPINT interrupt will occur with SETUP bit set */
+      if(epnum == 0)
+      {
+        USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_SUPCNT_SHIFT);
+      }
+      
+      break;
+
+    case 0x06:
+    { 
+      /* Step1: Setup data packet received */
+
+      /*
+       * We can receive up to three setup packets in succession, but
+       * only the last one is valid. Therefore we just overwrite it
+       */
+      _setup_packet[0] = (*USB->FIFO0D);
+      _setup_packet[1] = (*USB->FIFO0D);
+    }
+    break;
+
+    default: 
+      /* Invalid, breakpoint. */
+      TU_BREAKPOINT();
+      break;
+  }
+}
+
+static void handle_epout_ints(void)
+{
+  // GINTSTS will be cleared with DAINT == 0
+  // DAINT for a given EP clears when DOEPINTx is cleared.
+  // DOEPINT will be cleared when DAINT's out bits are cleared.
+
+  for(uint8_t n = 0; n < EP_COUNT; n++)
+  {
+    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+
+    if(n == 0)
+    {
+      if(USB->DAINT & (1 << (_USB_DAINT_OUTEPINT0_SHIFT + n)))
+      {
+        // SETUP packet Setup Phase done.
+        if((USB->DOEP0INT & USB_DOEP0INT_SETUP))
+        {
+          USB->DOEP0INT = USB_DOEP0INT_STUPPKTRCVD | USB_DOEP0INT_SETUP; // clear
+          dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
+        }
+
+        // OUT XFER complete (single packet).q
+        if(USB->DOEP0INT & USB_DOEP0INT_XFERCOMPL)
+        {
+          USB->DOEP0INT = USB_DOEP0INT_XFERCOMPL;
+
+          // Transfer complete if short packet or total len is transferred
+          if(xfer->short_packet || (xfer->queued_len == xfer->total_len))
+          {
+            xfer->short_packet = false;
+            dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+          }
+          else
+          {
+            // Schedule another packet to be received.
+            USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP0TSIZ_XFERSIZE_MASK) << _USB_DOEP0TSIZ_XFERSIZE_SHIFT);
+            USB->DOEP0CTL |= USB_DOEP0CTL_EPENA | USB_DOEP0CTL_CNAK;
+          }
+        }
+      }
+    }
+    else
+    {
+      if(USB->DAINT & (1 << (_USB_DAINT_OUTEPINT0_SHIFT + n)))
+      {
+        // SETUP packet Setup Phase done.
+        if((USB->DOEP[n - 1].INT & USB_DOEP_INT_SETUP))
+        {
+          USB->DOEP[n - 1].INT = USB_DOEP_INT_STUPPKTRCVD | USB_DOEP_INT_SETUP; // clear
+          dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
+        }
+
+        // OUT XFER complete (single packet).q
+        if(USB->DOEP[n - 1].INT & USB_DOEP_INT_XFERCOMPL)
+        {
+          USB->DOEP[n - 1].INT = USB_DOEP_INT_XFERCOMPL;
+
+          // Transfer complete if short packet or total len is transferred
+          if(xfer->short_packet || (xfer->queued_len == xfer->total_len))
+          {
+            xfer->short_packet = false;
+            dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+          }
+          else
+          {
+            // Schedule another packet to be received.
+            USB->DOEP[n - 1].TSIZ |= (1 << _USB_DOEP_TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP_TSIZ_XFERSIZE_MASK) << _USB_DOEP_TSIZ_XFERSIZE_SHIFT);
+            USB->DOEP[n - 1].CTL |= USB_DOEP_CTL_EPENA | USB_DOEP_CTL_CNAK;
+          }
+        }
+      }
+    }
+  }
+}
+
+static void handle_epin_ints(void)
+{
+
+  for(uint32_t n = 0; n < EP_COUNT; n++)
+  {
+    xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN];
+
+    if(n == 0)
+    {
+      if(USB->DAINT & (1 << n))
+      {
+        /* IN XFER complete (entire xfer). */
+        if(USB->DIEP0INT & USB_DIEP0INT_XFERCOMPL)
+        {
+          USB->DIEP0INT = USB_DIEP0INT_XFERCOMPL;
+          dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        }
+
+        /* XFER FIFO empty */
+        if(USB->DIEP0INT & USB_DIEP0INT_TXFEMP)
+        {
+          USB->DIEP0INT = USB_DIEP0INT_TXFEMP;
+          transmit_packet(xfer, n);
+
+          /* Turn off TXFE if all bytes are written. */
+          if(xfer->queued_len == xfer->total_len)
+          {
+            USB->DIEPEMPMSK  &= ~(1 << n);
+          }
+        }
+
+        /* XFER Timeout */
+        if(USB->DIEP0INT & USB_DIEP0INT_TIMEOUT)
+        {
+          /* Clear interrupt or enpoint will hang. */
+          USB->DIEP0INT = USB_DIEP0INT_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      if(USB->DAINT & (1 << n))
+      {
+        /* IN XFER complete (entire xfer). */
+        if(USB->DIEP[n - 1].INT & USB_DIEP_INT_XFERCOMPL)
+        {
+          USB->DIEP[n - 1].INT = USB_DIEP_INT_XFERCOMPL;
+          dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        }
+
+        /* XFER FIFO empty */
+        if(USB->DIEP[n - 1].INT & USB_DIEP_INT_TXFEMP)
+        {
+          USB->DIEP[n - 1].INT = USB_DIEP_INT_TXFEMP;
+          transmit_packet(xfer, n);
+
+          /* Turn off TXFE if all bytes are written. */
+          if(xfer->queued_len == xfer->total_len)
+          {
+            USB->DIEPEMPMSK  &= ~(1 << n);
+          }
+        }
+
+        /* XFER Timeout */
+        if(USB->DIEP[n - 1].INT & USB_DIEP_INT_TIMEOUT)
+        {
+          /* Clear interrupt or enpoint will hang. */
+          USB->DIEP[n - 1].INT = USB_DIEP_INT_TIMEOUT;
+        }
+      }
+    }
+  }
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+  (void) rhport;
+
+  const uint32_t int_status = USB->GINTSTS;
+
+  /* USB Reset */
+  if(int_status & USB_GINTSTS_USBRST)
+  {
+    /* start of reset */
+    USB->GINTSTS = USB_GINTSTS_USBRST;
+    /* FIFOs will be reassigned when the endpoints are reopen */
+    _allocated_fifos = 1;
+    bus_reset();
+  }
+
+  /* Reset detected Interrupt */
+  if(int_status & USB_GINTSTS_RESETDET)
+  {
+    USB->GINTSTS = USB_GINTSTS_RESETDET;
+    bus_reset();
+  }
+
+  /* Enumeration Done */
+  if(int_status & USB_GINTSTS_ENUMDONE)
+  {
+    /* This interrupt is considered the end of reset. */
+    USB->GINTSTS = USB_GINTSTS_ENUMDONE;
+    enum_done_processing();
+    dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+  }
+
+  /* OTG Interrupt */
+  if(int_status & USB_GINTSTS_OTGINT)
+  {
+    /* OTG INT bit is read-only */
+
+    uint32_t const otg_int = USB->GOTGINT;
+
+    if(otg_int & USB_GOTGINT_SESENDDET)
+    {
+      dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+    }
+
+    USB->GOTGINT = otg_int;
+  }
+
+  #if USE_SOF
+  if(int_status & USB_GINTSTS_SOF)
+  {
+    USB->GINTSTS = USB_GINTSTS_SOF;
+    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+  }
+  #endif
+
+  /* RxFIFO Non-Empty */
+  if(int_status & USB_GINTSTS_RXFLVL)
+  {
+    /* RXFLVL bit is read-only */
+
+    /* Mask out RXFLVL while reading data from FIFO */
+    USB->GINTMSK &= ~USB_GINTMSK_RXFLVLMSK;
+    read_rx_fifo();
+    USB->GINTMSK |= USB_GINTMSK_RXFLVLMSK;
+  }
+
+  /* OUT Endpoints Interrupt */
+  if(int_status & USB_GINTMSK_OEPINTMSK)
+  {
+    /* OEPINT is read-only */
+    handle_epout_ints();
+  }
+
+  /* IN Endpoints Interrupt */
+  if(int_status & USB_GINTMSK_IEPINTMSK)
+  {
+    /* IEPINT bit read-only */
+    handle_epin_ints();
+  }
+
+  /* unhandled */
+  USB->GINTSTS |= USB_GINTSTS_CURMOD      |
+                  USB_GINTSTS_MODEMIS     |
+                  USB_GINTSTS_OTGINT      |
+                  USB_GINTSTS_NPTXFEMP    |
+                  USB_GINTSTS_GINNAKEFF   |
+                  USB_GINTSTS_GOUTNAKEFF  |
+                  USB_GINTSTS_ERLYSUSP    |
+                  USB_GINTSTS_USBSUSP     |
+                  USB_GINTSTS_ISOOUTDROP  |
+                  USB_GINTSTS_EOPF        |
+                  USB_GINTSTS_EPMIS       |
+                  USB_GINTSTS_INCOMPISOIN |
+                  USB_GINTSTS_INCOMPLP    |
+                  USB_GINTSTS_FETSUSP     |
+                  USB_GINTSTS_PTXFEMP;
+}
+
+#endif

From 18be454011eb29652b9e740f33b5b5677d50e7b7 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 5 Mar 2021 01:38:49 +0900
Subject: [PATCH 34/72] added board files

---
 hw/bsp/gr_citrus/board.mk     |  54 +++++++++
 hw/bsp/gr_citrus/gr_citrus.c  | 217 ++++++++++++++++++++++++++++++++++
 hw/bsp/gr_citrus/hwinit.c     |  31 +++++
 hw/bsp/gr_citrus/r5f5631fd.ld | 127 ++++++++++++++++++++
 4 files changed, 429 insertions(+)
 create mode 100644 hw/bsp/gr_citrus/board.mk
 create mode 100644 hw/bsp/gr_citrus/gr_citrus.c
 create mode 100644 hw/bsp/gr_citrus/hwinit.c
 create mode 100644 hw/bsp/gr_citrus/r5f5631fd.ld

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/gr_citrus/board.mk
new file mode 100644
index 00000000..8675d853
--- /dev/null
+++ b/hw/bsp/gr_citrus/board.mk
@@ -0,0 +1,54 @@
+CFLAGS += \
+  -nostartfiles \
+  -nostdinc \
+  -ffunction-sections \
+  -fdata-sections \
+  -mcpu=rx610 \
+  -misa=v1 \
+  -mlittle-endian-data \
+  -DCFG_TUSB_MCU=OPT_MCU_RX63X
+
+# Cross Compiler for RX
+CROSS_COMPILE = rx-elf-
+
+ifeq ($(CMDEXE),1)
+OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
+else
+OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
+endif
+
+# mcu driver cause following warnings
+CFLAGS += -isystem $(OPTLIBINC)
+
+LIBS += -loptm -loptc
+
+MCU_DIR = hw/mcu/renesas/rx63n
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/$(BOARD)/r5f5631fd.ld
+
+SRC_C += \
+	$(MCU_DIR)/vects.c
+
+INC += \
+	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(MCU_DIR)
+
+SRC_S += $(MCU_DIR)/start.S
+
+# For TinyUSB port source
+VENDOR = renesas
+CHIP_FAMILY = usba
+
+# For freeRTOS port source
+FREERTOS_PORT = RX600
+
+# For flash-jlink target
+JLINK_DEVICE = R5F5631F
+JLINK_IF     = JTAG
+
+# For flash-pyocd target
+PYOCD_TARGET =
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/gr_citrus/gr_citrus.c b/hw/bsp/gr_citrus/gr_citrus.c
new file mode 100644
index 00000000..3fa568cc
--- /dev/null
+++ b/hw/bsp/gr_citrus/gr_citrus.c
@@ -0,0 +1,217 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "iodefine.h"
+#include "interrupt_handlers.h"
+
+#define IRQ_PRIORITY_CMT0     5
+#define IRQ_PRIORITY_USBI0    5
+#define IRQ_PRIORITY_SCI0     5
+
+#define SYSTEM_PRCR_PRC1      (1<<1)
+#define SYSTEM_PRCR_PRKEY     (0xA5u<<8)
+
+#define CMT_PCLK              48000000
+#define CMT_CMCR_CKS_DIV_128  2
+#define CMT_CMCR_CMIE         (1<<6)
+#define MPC_PFS_ISEL          (1<<6)
+
+#define SCI_PCLK              48000000
+#define SCI_SSR_FER           (1<<4)
+#define SCI_SSR_ORER          (1<<5)
+
+#define SCI_SCR_TEIE          (1u<<2)
+#define SCI_SCR_RE            (1u<<4)
+#define SCI_SCR_TE            (1u<<5)
+#define SCI_SCR_RIE           (1u<<6)
+#define SCI_SCR_TIE           (1u<<7)
+
+//--------------------------------------------------------------------+
+// SCI0 handling
+//--------------------------------------------------------------------+
+typedef struct {
+  uint8_t *buf;
+  uint32_t cnt;
+} sci_buf_t;
+static volatile sci_buf_t sci0_buf[2];
+
+void INT_Excep_SCI0_TXI0(void)
+{
+  uint8_t *buf = sci0_buf[0].buf;
+  uint32_t cnt = sci0_buf[0].cnt;
+  
+  if (!buf || !cnt) {
+    SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+    return;
+  }
+  SCI0.TDR = *buf;
+  if (--cnt) {
+    ++buf;
+  } else {
+    buf = NULL;
+    SCI0.SCR.BIT.TIE  = 0;
+    SCI0.SCR.BIT.TEIE = 1;
+  }
+  sci0_buf[0].buf = buf;
+  sci0_buf[0].cnt = cnt;
+}
+
+void INT_Excep_SCI0_TEI0(void)
+{
+  SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+}
+
+void INT_Excep_SCI0_RXI0(void)
+{
+  uint8_t *buf = sci0_buf[1].buf;
+  uint32_t cnt = sci0_buf[1].cnt;
+
+  if (!buf || !cnt ||
+      (SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
+    sci0_buf[1].buf = NULL;
+    SCI0.SSR.BYTE   = 0;
+    SCI0.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+    return;
+  }
+  *buf = SCI0.RDR;
+  if (--cnt) {
+    ++buf;
+  } else {
+    buf = NULL;
+    SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+  }
+  sci0_buf[1].buf = buf;
+  sci0_buf[1].cnt = cnt;
+}
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void INT_Excep_USB0_USBI0(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void)
+{
+#if CFG_TUSB_OS == OPT_OS_NONE
+  /* Enable CMT0 */
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  /* Setup 1ms tick timer */
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = CMT_PCLK / 1000 / 128;
+  CMT0.CMCR.WORD  = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+#endif
+
+  /* Unlock MPC registers */
+  MPC.PWPR.BIT.B0WI  = 0;
+  MPC.PWPR.BIT.PFSWE = 1;
+  /* LED PA0 */
+  PORTA.PMR.BIT.B0  = 0U;
+  PORTA.PODR.BIT.B0 = 0U;
+  PORTA.PDR.BIT.B0  = 1U;
+  /* UART TXD0 => P20, RXD0 => P21 */
+  PORT2.PMR.BIT.B0 = 1U;
+  PORT2.PCR.BIT.B0 = 1U;
+  MPC.P20PFS.BYTE  = 0b01010;
+  PORT2.PMR.BIT.B1 = 1U;
+  MPC.P21PFS.BYTE  = 0b01010;
+  /* USB VBUS -> P16, RXD0 => P21, TXD0 => P20 */
+  PORT1.PMR.BIT.B6 = 1U;
+  MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
+  /* Lock MPC registers */
+  MPC.PWPR.BIT.PFSWE = 0;
+  MPC.PWPR.BIT.B0WI  = 1;
+
+  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
+
+  /* Enable SCI0 */
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(SCI0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
+  IR(SCI0,  RXI0)  = 0;
+  IR(SCI0,  TXI0)  = 0;
+  IR(SCI0,  TEI0)  = 0;
+  IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
+  IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
+  IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
+  IEN(SCI0, RXI0) = 1;
+  IEN(SCI0, TXI0) = 1;
+  IEN(SCI0, TEI0) = 1;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  PORTA.PODR.BIT.B0 = state ? 1 : 0;
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  sci0_buf[1].buf = buf;
+  sci0_buf[1].cnt = len;
+  SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
+  while (SCI0.SCR.BIT.RE) ;
+  return len - sci0_buf[1].cnt;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  sci0_buf[0].buf = (uint8_t*)buf;
+  sci0_buf[0].cnt = len;
+  SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
+  while (SCI0.SCR.BIT.TE) ;
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void INT_Excep_CMT0_CMI0(void)
+{
+  ++system_ticks;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/gr_citrus/hwinit.c b/hw/bsp/gr_citrus/hwinit.c
new file mode 100644
index 00000000..8245d774
--- /dev/null
+++ b/hw/bsp/gr_citrus/hwinit.c
@@ -0,0 +1,31 @@
+/************************************************************************/
+/*    File Version: V1.00                                               */
+/*    Date Generated: 08/07/2013                                        */
+/************************************************************************/
+
+#include "iodefine.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern void HardwareSetup(void);
+#ifdef __cplusplus
+}
+#endif
+
+void HardwareSetup(void)
+{
+    SYSTEM.PRCR.WORD     = 0xA503u;
+    SYSTEM.SOSCCR.BYTE   = 0x01u;
+    SYSTEM.MOSCWTCR.BYTE = 0x0Du;
+    SYSTEM.PLLWTCR.BYTE  = 0x0Eu;
+    SYSTEM.PLLCR.WORD    = 0x0F00u;
+    SYSTEM.MOSCCR.BYTE   = 0x00u;
+    SYSTEM.PLLCR2.BYTE   = 0x00u;
+    for (unsigned i = 0; i < 2075u; ++i) __asm("nop");
+    SYSTEM.SCKCR.LONG    = 0x21021211u;
+    SYSTEM.SCKCR2.WORD   = 0x0033u;
+    SYSTEM.SCKCR3.WORD   = 0x0400u;
+    SYSTEM.SYSCR0.WORD   = 0x5A01;
+    SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
+    SYSTEM.PRCR.WORD     = 0xA500u;
+}
diff --git a/hw/bsp/gr_citrus/r5f5631fd.ld b/hw/bsp/gr_citrus/r5f5631fd.ld
new file mode 100644
index 00000000..166a9e7c
--- /dev/null
+++ b/hw/bsp/gr_citrus/r5f5631fd.ld
@@ -0,0 +1,127 @@
+__USTACK_SIZE = 0x00000200;
+__ISTACK_SIZE = 0x00000100;
+
+MEMORY
+{
+	RAM : ORIGIN = 0x4,        LENGTH = 0x3fffc
+	ROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000
+}
+SECTIONS
+{
+	.fvectors 0xFFFFFF80: AT(0xFFFFFF80)
+	{
+		KEEP(*(.fvectors))
+	} > ROM
+	.text 0xFFE00000: AT(0xFFE00000)
+	{
+		*(.text)
+		*(.text.*)
+		*(P)
+		etext = .;
+	} > ROM
+	.rvectors ALIGN(4):
+	{
+		_rvectors_start = .;
+		KEEP(*(.rvectors))
+		_rvectors_end = .;
+	} > ROM
+	.init :
+	{
+		KEEP(*(.init))
+		__preinit_array_start = .;
+		KEEP(*(.preinit_array))
+		__preinit_array_end = .;
+		__init_array_start = (. + 3) & ~ 3;
+		KEEP(*(.init_array))
+		KEEP(*(SORT(.init_array.*)))
+		__init_array_end = .;
+		__fini_array_start = .;
+		KEEP(*(.fini_array))
+		KEEP(*(SORT(.fini_array.*)))
+		__fini_array_end = .;
+	} > ROM
+	.fini :
+	{
+		KEEP(*(.fini))
+	} > ROM
+	.got :
+	{
+		*(.got)
+		*(.got.plt)
+	} > ROM
+	.rodata :
+	{
+		*(.rodata)
+		*(.rodata.*)
+		*(C_1)
+		*(C_2)
+		*(C)
+		_erodata = .;
+	} > ROM
+	.eh_frame_hdr :
+	{
+		*(.eh_frame_hdr)
+	} > ROM
+	.eh_frame :
+	{
+		*(.eh_frame)
+	} > ROM
+	.jcr :
+	{
+		*(.jcr)
+	} > ROM
+	.tors :
+	{
+		__CTOR_LIST__ = .;
+		. = ALIGN(2);
+		___ctors = .;
+		*(.ctors)
+		___ctors_end = .;
+		__CTOR_END__ = .;
+		__DTOR_LIST__ = .;
+		___dtors = .;
+		*(.dtors)
+		___dtors_end = .;
+		__DTOR_END__ = .;
+		. = ALIGN(2);
+		_mdata = .;
+	} > ROM
+	.data : AT(_mdata)
+	{
+		_data = .;
+		*(.data)
+		*(.data.*)
+		*(D)
+		*(D_1)
+		*(D_2)
+		_edata = .;
+	} > RAM
+	.gcc_exc :
+	{
+		*(.gcc_exc)
+	} > RAM
+	.bss :
+	{
+		_bss = .;
+		*(.bss)
+		*(.bss.**)
+		*(COMMON)
+		*(B)
+		*(B_1)
+		*(B_2)
+		_ebss = .;
+		_end = .;
+	} > RAM
+	.ustack (COPY) :
+	{
+		. = ALIGN(8);
+		. = . + __USTACK_SIZE;
+		PROVIDE(_ustack = .);
+	} > RAM
+	.istack (COPY) :
+	{
+		. = ALIGN(8);
+		. = . + __ISTACK_SIZE;
+		PROVIDE(_istack = .);
+	} > RAM
+}

From 13735eb21de8d21a88871e69859f69db02af93c6 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 7 Mar 2021 14:53:21 +0900
Subject: [PATCH 35/72] added dcd for Renesas USBa

---
 src/portable/renesas/usba/dcd_usba.c | 755 +++++++++++++++++++++++++++
 1 file changed, 755 insertions(+)
 create mode 100644 src/portable/renesas/usba/dcd_usba.c

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
new file mode 100644
index 00000000..b0fa1749
--- /dev/null
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -0,0 +1,755 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X )
+
+#include "device/dcd.h"
+#include "iodefine.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+#define SYSTEM_PRCR_PRC1     (1<<1)
+#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
+
+#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
+#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
+#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
+#define USB_IS0_CTSQ         ((uint16_t)(7u))
+#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
+#define USB_IS0_VALID        ((uint16_t)(1u<<3))
+#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
+#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
+#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
+#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
+#define USB_IS0_DVST         ((uint16_t)(1u<<12))
+#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
+#define USB_IS0_RESM         ((uint16_t)(1u<<14))
+#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
+#define USB_IS1_SACK         ((uint16_t)(1u<<4))
+#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
+#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
+#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
+#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
+#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
+#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
+
+#define USB_IS0_CTSQ_MSK     (7u)
+#define USB_IS0_CTSQ_SETUP   (1u)
+#define USB_IS0_DVSQ_DEF     (1u<<4)
+#define USB_IS0_DVSQ_ADDR    (2u<<4)
+#define USB_IS0_DVSQ_SUSP    (4u<<4)
+
+#define USB_PIPECTR_PID_NAK   (0u)
+#define USB_PIPECTR_PID_BUF   (1u)
+#define USB_PIPECTR_PID_STALL (2u)
+#define USB_PIPECTR_CCPL      (1u<<2)
+#define USB_PIPECTR_SQMON     (1u<<6)
+#define USB_PIPECTR_SQCLR     (1u<<8)
+#define USB_PIPECTR_ACLRM     (1u<<9)
+#define USB_PIPECTR_BSTS      (1u<<15)
+
+#define USB_FIFOCTR_DTLN     (0x1FF)
+#define USB_FIFOCTR_FRDY     (1u<<13)
+#define USB_FIFOCTR_BCLR     (1u<<14)
+#define USB_FIFOCTR_BVAL     (1u<<15)
+
+#define USB_PIPECFG_SHTNAK   (1u<<7)
+#define USB_PIPECFG_DBLB     (1u<<9)
+#define USB_PIPECFG_BULK     (1u<<14)
+#define USB_PIPECFG_ISO      (3u<<14)
+#define USB_PIPECFG_INT      (2u<<14)
+
+#define FIFO_REQ_CLR         (1u)
+#define FIFO_COMPLETE        (1u<<1)
+
+typedef struct {
+  union {
+    struct {
+      uint16_t      : 8;
+      uint16_t TRCLR: 1;
+      uint16_t TRENB: 1;
+      uint16_t      : 0;
+    };
+    uint16_t TRE;
+  };
+  uint16_t TRN;
+} reg_pipetre_t;
+
+typedef union {
+  struct {
+    volatile uint16_t u8: 8;
+    volatile uint16_t   : 0;
+  };
+  volatile uint16_t u16;
+} hw_fifo_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uintptr_t addr;
+  uint16_t  length;
+  uint16_t  remaining;
+  struct {
+    uint32_t ep  : 8;
+    uint32_t data: 1;
+    uint32_t     : 0;
+  };
+} pipe_state_t;
+
+typedef struct
+{
+  pipe_state_t pipe[9];
+  uint8_t ep[2][16]; /* index for pipe number */
+} dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+CFG_TUSB_MEM_SECTION static dcd_data_t _dcd;
+
+static uint32_t disable_interrupt(void)
+{
+  uint32_t pswi;
+  pswi = __builtin_rx_mvfc(0) & 0x010000;
+  __builtin_rx_clrpsw('I');
+  return pswi;
+}
+
+static void enable_interrupt(uint32_t pswi)
+{
+  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+}
+
+static unsigned find_pipe(unsigned xfer)
+{
+  switch (xfer) {
+  case TUSB_XFER_ISOCHRONOUS:
+    for (int i = 1; i <= 2; ++i) {
+      if (0 == _dcd.pipe[i].ep) return  i;
+    }
+    break;
+  case TUSB_XFER_BULK:
+    for (int i = 3; i <= 5; ++i) {
+      if (0 == _dcd.pipe[i].ep) return  i;
+    }
+    for (int i = 1; i <= 1; ++i) {
+      if (0 == _dcd.pipe[i].ep) return  i;
+    }
+    break;
+  case TUSB_XFER_INTERRUPT:
+    for (int i = 6; i <= 9; ++i) {
+      if (0 == _dcd.pipe[i].ep) return  i;
+    }
+    break;
+  default:
+    /* No support for control transfer */
+    break;
+  }
+  return 0;
+}
+
+static volatile uint16_t* get_pipectr(unsigned num)
+{
+  volatile uint16_t *ctr = NULL;
+  if (num) {
+    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
+    ctr += num - 1;
+  } else {
+    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+  }
+  return ctr;
+}
+
+static volatile reg_pipetre_t* get_pipetre(unsigned num)
+{
+  volatile reg_pipetre_t* tre = NULL;
+  if ((1 <= num) && (num <= 5)) {
+    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
+    tre += num - 1;
+  }
+  return tre;
+}
+
+static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
+{
+  (void)rhport;
+  volatile uint16_t *ctr = NULL;
+  const unsigned epn = ep_addr & 0xFu;
+  if (epn) {
+    const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+    const unsigned num = _dcd.ep[dir][epn];
+    if (num) {
+      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
+      ctr += num - 1;
+    }
+  } else {
+    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+  }
+  return ctr;
+}
+
+
+/* 1 less than 64 bytes were written
+ * 2 no bytes were written
+ * 0 64 bytes were written */
+static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
+{
+  unsigned rem  = pipe->remaining;
+  if (!rem) return 2;
+  unsigned len  = (rem < mps) ? rem: mps;
+
+  hw_fifo_t *reg = (hw_fifo_t*)fifo;
+  uintptr_t addr = pipe->addr + pipe->length - rem;
+  if (addr & 1u) {
+    /* addr is not 2-byte aligned */
+    reg->u8 = *(const uint8_t *)addr;
+    ++addr;
+    --len;
+  }
+  while (len >= 2) {
+    reg->u16 = *(const uint16_t *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(const uint8_t *)addr;
+    ++addr;
+  }
+  if (rem < mps) return 1;
+  return 0;
+}
+
+/* 1 if the number of bytes read is less than 64 bytes
+ * 0 otherwise */
+static int read_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size_t len)
+{
+  unsigned rem  = pipe->remaining;
+  if (!rem) return 2;
+  if (rem < len) len = rem;
+  pipe->remaining = rem - len;
+
+  hw_fifo_t *reg = (hw_fifo_t*)fifo;
+  uintptr_t addr = pipe->addr;
+  while (len--) {
+    *(uint8_t *)addr = reg->u8;
+    ++addr;
+  }
+  pipe->addr = addr;
+  if (rem < mps) return 1;
+  return 0;
+}
+
+static void process_setup_packet(uint8_t rhport)
+{
+  uint16_t setup_packet[4];
+  if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return;
+  USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  setup_packet[0] = USB0.USBREQ.WORD;
+  setup_packet[1] = USB0.USBVAL;
+  setup_packet[2] = USB0.USBINDX;
+  setup_packet[3] = USB0.USBLENG;
+  USB0.INTSTS0.WORD = ~USB_IS0_VALID;
+  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
+  //  TU_LOG1("S\r\n");
+}
+
+static void process_status_completion(uint8_t rhport)
+{
+  uint8_t ep_addr;
+  /* Check the data stage direction */
+  if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) {
+    /* IN transfer. */
+    ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
+  } else {
+    /* OUT transfer. */
+    ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
+  }
+  dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
+  //  TU_LOG1("C\r\n");
+}
+
+static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  /* set fifo direction */
+  if (ep_addr) { /* IN */
+    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16;
+    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
+  } else {       /* OUT */
+    USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
+    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
+  }
+  if (total_bytes) {
+    pipe->addr      = (uintptr_t)buffer;
+    pipe->length    = total_bytes;
+    pipe->remaining = total_bytes;
+    pipe->data      = USB0.DCPCTR.BIT.SQMON;
+    if (ep_addr) { /* IN */
+      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
+      if (write_fifo(&USB0.CFIFO.WORD, pipe, 64)) {
+        USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      }
+    }
+    USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+    //    TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
+  } else {
+    /* ZLP */
+    pipe->addr      = 0;
+    pipe->length    = 0;
+    pipe->remaining = 0;
+    pipe->data      = USB0.DCPCTR.BIT.SQMON;
+    USB0.DCPCTR.WORD   = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
+    //    TU_LOG1("Z %x\r\n", USB0.DCPCTR.WORD);
+  }
+  return true;
+}
+
+static void process_edpt0_bemp(uint8_t rhport)
+{
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  unsigned data = pipe->data;
+  if (USB0.DCPCTR.BIT.SQMON == data) {
+    TU_LOG1("W %x\r\n", USB0.DCPCTR.WORD);
+    /* retry transfer */
+    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
+    if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    return;
+  }
+  const unsigned rem = pipe->remaining;
+  if (rem > 64) {
+    pipe->remaining = rem - 64;
+    pipe->data      = data ^ 1;
+    TU_LOG1("Y %d %x\r\n", rem - 64, USB0.DCPCTR.WORD);
+    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
+    if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    return;
+  }
+  pipe->addr      = 0;
+  pipe->remaining = 0;
+  dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
+			  pipe->length, XFER_RESULT_SUCCESS, true);
+  //  TU_LOG1("c\r\n");
+}
+
+static void process_edpt0_brdy(uint8_t rhport)
+{
+  size_t len = USB0.CFIFOCTR.BIT.DTLN;
+  int cplt = read_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, len);
+  if (cplt || (len < 64)) {
+    if (2 != cplt) {
+      USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+    }
+    dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+                            _dcd.pipe[0].length - _dcd.pipe[0].remaining,
+			    XFER_RESULT_SUCCESS, true);
+    //    TU_LOG1("c\r\n");
+  }
+}
+
+static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+
+  const unsigned epn = ep_addr & 0xFu;
+  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned num = _dcd.ep[dir][epn];
+
+  TU_ASSERT(num);
+
+  pipe_state_t *pipe = &_dcd.pipe[num];
+  pipe->addr      = (uintptr_t)buffer;
+  pipe->length    = total_bytes;
+  pipe->remaining = total_bytes;
+
+  USB0.PIPESEL.WORD  = num;
+  const unsigned mps = USB0.PIPEMAXP.WORD;
+  if (dir) { /* IN */
+    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
+    while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
+    if (write_fifo(&USB0.D0FIFO.WORD, pipe, mps)) {
+      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    }
+    USB0.D0FIFOSEL.WORD = 0;
+  } else {
+    volatile reg_pipetre_t *pt = get_pipetre(num);
+    if (pt) {
+      volatile uint16_t *ctr = get_pipectr(num);
+      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
+      pt->TRE   = 1u << 8;
+      pt->TRN   = (total_bytes + mps - 1) / mps;
+      pt->TRENB = 1;
+      *ctr = USB_PIPECTR_PID_BUF;
+    }
+  }
+  TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
+  return true;
+}
+
+static void process_pipe_bemp(uint8_t rhport, unsigned num)
+{
+  pipe_state_t *pipe = &_dcd.pipe[num];
+  const unsigned rem = pipe->remaining;
+  if (rem > 64) {
+    pipe->remaining = rem - 64;
+    TU_LOG1("Y %d\r\n", rem - 64);
+    USB0.PIPESEL.WORD  = num;
+    const unsigned mps = USB0.PIPEMAXP.WORD;
+    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
+    while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
+    int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps);
+    if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    USB0.D0FIFOSEL.WORD = 0;
+    return;
+  }
+  pipe->addr      = 0;
+  pipe->remaining = 0;
+  dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
+			  XFER_RESULT_SUCCESS, true);
+  //  TU_LOG1("cE\r\n");
+}
+
+static void process_pipe_brdy(uint8_t rhport, unsigned num)
+{
+  pipe_state_t *pipe  = &_dcd.pipe[num];
+  USB0.PIPESEL.WORD   = num;
+  const unsigned mps  = USB0.PIPEMAXP.WORD;
+  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
+  while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
+  unsigned ctr;
+  do {
+    ctr = USB0.D0FIFOCTR.WORD;
+  } while (!(ctr & USB_FIFOCTR_FRDY));
+  const unsigned len  = ctr & USB_FIFOCTR_DTLN;
+  TU_LOG1(">> %d %x %x\r\n", num, USB0.D0FIFOSEL.WORD, ctr);
+  int cplt = read_fifo(&USB0.D0FIFO.WORD, pipe, mps, len);
+  if (cplt || (len < mps)) {
+    if (2 != cplt) {
+      USB0.D0FIFO.WORD = USB_FIFOCTR_BCLR;
+    }
+    USB0.D0FIFOSEL.WORD = 0;
+    dcd_event_xfer_complete(rhport, pipe->ep,
+                            pipe->length - pipe->remaining,
+			    XFER_RESULT_SUCCESS, true);
+    TU_LOG1("c\r\n");
+  } else {
+    USB0.D0FIFOSEL.WORD = 0;
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  USB0.BEMPENB.WORD   = 1;
+  USB0.BRDYENB.WORD   = 1;
+  USB0.CFIFOCTR.WORD  = USB_FIFOCTR_BCLR;
+  USB0.D0FIFOSEL.WORD = 0;
+  USB0.D1FIFOSEL.WORD = 0;
+  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD));
+  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD));
+  for (int i = 1; i <= 5; ++i) {
+    USB0.PIPESEL.WORD  = i;
+    USB0.PIPECFG.WORD  = 0;
+    *ctr = USB_PIPECTR_ACLRM;
+    *ctr = 0;
+    ++ctr;
+    *tre = (1u<<8);
+    tre += 2;
+  }
+  for (int i = 6; i <= 9; ++i) {
+    USB0.PIPESEL.WORD  = i;
+    USB0.PIPECFG.WORD  = 0;
+    *ctr = USB_PIPECTR_ACLRM;
+    *ctr = 0;
+    ++ctr;
+  }
+  tu_varclr(&_dcd);
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+  TU_LOG1("R\r\n");
+}
+
+static void process_set_address(uint8_t rhport)
+{
+  const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
+  if (!addr) return;
+  const tusb_control_request_t setup_packet = {
+    .bmRequestType = 0,
+    .bRequest      = 5,
+    .wValue        = addr,
+    .wIndex        = 0,
+    .wLength       = 0,
+  };
+  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  (void)rhport;
+  /* Enable USB0 */
+  uint32_t pswi = disable_interrupt();
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  enable_interrupt(pswi);
+  USB0.SYSCFG.BIT.SCKE = 1;
+  while (!USB0.SYSCFG.BIT.SCKE) ;
+  USB0.SYSCFG.BIT.DRPD = 0;
+  USB0.SYSCFG.BIT.DCFM = 0;
+  USB0.SYSCFG.BIT.USBE = 1;
+
+  IR(USB0, USBI0)   = 0;
+
+  /* Setup default control pipe */
+  USB0.DCPMAXP.BIT.MXPS  = 64;
+  USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT;
+  USB0.BEMPENB.WORD = 1;
+  USB0.BRDYENB.WORD = 1;
+
+  TU_LOG1("INIT\r\n");
+  if (USB0.INTSTS0.BIT.VBSTS) {
+    dcd_connect(rhport);
+  }
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  IEN(USB0, USBI0) = 1;
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  IEN(USB0, USBI0) = 0;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  (void)dev_addr;
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void)rhport;
+  /* TODO */
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void)rhport;
+  USB0.SYSCFG.BIT.DPRPU = 1;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void)rhport;
+  USB0.SYSCFG.BIT.DPRPU = 0;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void)rhport;
+
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = ep_addr & 0xFu;
+  const unsigned dir     = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned xfer    = ep_desc->bmAttributes.xfer;
+
+  const unsigned mps = ep_desc->wMaxPacketSize.size;
+  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
+    /* USBB support up to 256 bytes */
+    return false;
+  }
+
+  const unsigned num = find_pipe(xfer);
+  if (!num) return false;
+  _dcd.pipe[num].ep = ep_addr;
+  _dcd.ep[dir][epn] = num;
+
+  /* setup pipe */
+  USB0.PIPESEL.WORD  = num;
+  USB0.PIPEMAXP.WORD = mps;
+  volatile uint16_t *ctr = get_pipectr(num);
+  *ctr = USB_PIPECTR_ACLRM;
+  *ctr = 0;
+  unsigned cfg = (dir << 4) | epn;
+  if (xfer == TUSB_XFER_BULK) {
+    cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
+  } else if (xfer == TUSB_XFER_INTERRUPT) {
+    cfg |= USB_PIPECFG_INT;
+  } else {
+    cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
+  }
+  USB0.PIPECFG.WORD = cfg;
+  if (dir) {
+    USB0.BEMPENB.WORD |= 1u << num;
+    *ctr = USB_PIPECTR_PID_BUF;
+  } else {
+    USB0.BRDYENB.WORD |= 1u << num;
+    if (xfer != TUSB_XFER_BULK) {
+      *ctr = USB_PIPECTR_PID_BUF;
+    }
+  }
+  TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
+
+  return true;
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  const unsigned epn = ep_addr & 0xFu;
+  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned num = _dcd.ep[dir][epn];
+
+  USB0.BEMPENB.WORD &= ~(1u << num);
+  USB0.BRDYENB.WORD &= ~(1u << num);
+  volatile uint16_t *ctr = get_pipectr(num);
+  *ctr = 0;
+  USB0.PIPESEL.WORD = num;
+  USB0.PIPECFG.WORD = 0;
+  _dcd.pipe[num].ep = 0;
+  _dcd.ep[dir][epn] = 0;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  bool r;
+  const unsigned epn = ep_addr & 0xFu;
+  dcd_int_disable(rhport);
+  if (0 == epn) {
+    r = process_edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
+  } else {
+    r = process_pipe_xfer(rhport, ep_addr, buffer, total_bytes);
+  }
+  dcd_int_enable(rhport);
+  return r;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
+  if (!ctr) return;
+  dcd_int_disable(rhport);
+  const uint32_t pid = *ctr & 0x3;
+  *ctr = pid | USB_PIPECTR_PID_STALL;
+  *ctr = USB_PIPECTR_PID_STALL;
+  dcd_int_enable(rhport);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
+  if (!ctr) return;
+  dcd_int_disable(rhport);
+  *ctr = USB_PIPECTR_SQCLR;
+
+  if (ep_addr & TUSB_DIR_IN_MASK) {
+    *ctr = USB_PIPECTR_PID_BUF;
+  } else {
+    /* TODO */
+  }
+  dcd_int_enable(rhport);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+  (void)rhport;
+
+  unsigned is0 = USB0.INTSTS0.WORD;
+  /* clear bits except VALID */
+  USB0.INTSTS0.WORD = USB_IS0_VALID;
+  if (is0 & USB_IS0_VBINT) {
+    if (USB0.INTSTS0.BIT.VBSTS) {
+      dcd_connect(rhport);
+    } else {
+      dcd_disconnect(rhport);
+    }
+  }
+  if (is0 & USB_IS0_DVST) {
+    switch (is0 & USB_IS0_DVSQ) {
+    case USB_IS0_DVSQ_DEF:
+      process_bus_reset(rhport);
+      break;
+    case USB_IS0_DVSQ_ADDR:
+      process_set_address(rhport);
+      break;
+    default:
+      break;
+    }
+  }
+  if (is0 & USB_IS0_CTRT) {
+    if (is0 & USB_IS0_CTSQ_SETUP) {
+      /* A setup packet has been received. */
+      process_setup_packet(rhport);
+    } else if (0 == (is0 & USB_IS0_CTSQ_MSK)) {
+      /* A ZLP has been sent/received. */
+      process_status_completion(rhport);
+    }
+  }
+  if (is0 & USB_IS0_BEMP) {
+    const unsigned m = USB0.BEMPENB.WORD;
+    unsigned s       = USB0.BEMPSTS.WORD & m;
+    USB0.BEMPSTS.WORD = 0;
+    if (s & 1) {
+      process_edpt0_bemp(rhport);
+      s &= ~1;
+    }
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_bemp(rhport, num);
+      s &= ~(1<<num);
+    }
+  }
+  if (is0 & USB_IS0_BRDY) {
+    const unsigned m = USB0.BRDYENB.WORD;
+    unsigned s       = USB0.BRDYSTS.WORD & m;
+    USB0.BRDYSTS.WORD = 0;
+    if (s & 1) {
+      process_edpt0_brdy(rhport);
+      s &= ~1;
+    }
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_brdy(rhport, num);
+      s &= ~(1<<num);
+    }
+  }
+}
+
+#endif

From f8cf88f918e09179137b77fc86ded0f648209746 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 24 Mar 2021 00:53:55 +0900
Subject: [PATCH 36/72] update for gr_citurs

---
 hw/bsp/gr_citrus/board.mk            |   5 +-
 hw/bsp/gr_citrus/gr_citrus.c         |   8 +-
 src/portable/renesas/usba/dcd_usba.c | 169 +++++++++++++++++++++------
 src/tusb_option.h                    |   3 +
 4 files changed, 141 insertions(+), 44 deletions(-)

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/gr_citrus/board.mk
index 8675d853..53f85aa7 100644
--- a/hw/bsp/gr_citrus/board.mk
+++ b/hw/bsp/gr_citrus/board.mk
@@ -28,6 +28,7 @@ MCU_DIR = hw/mcu/renesas/rx63n
 LD_FILE = hw/bsp/$(BOARD)/r5f5631fd.ld
 
 SRC_C += \
+	src/portable/renesas/usba/dcd_usba.c \
 	$(MCU_DIR)/vects.c
 
 INC += \
@@ -36,10 +37,6 @@ INC += \
 
 SRC_S += $(MCU_DIR)/start.S
 
-# For TinyUSB port source
-VENDOR = renesas
-CHIP_FAMILY = usba
-
 # For freeRTOS port source
 FREERTOS_PORT = RX600
 
diff --git a/hw/bsp/gr_citrus/gr_citrus.c b/hw/bsp/gr_citrus/gr_citrus.c
index 3fa568cc..f8cf8b18 100644
--- a/hw/bsp/gr_citrus/gr_citrus.c
+++ b/hw/bsp/gr_citrus/gr_citrus.c
@@ -29,7 +29,7 @@
 #include "interrupt_handlers.h"
 
 #define IRQ_PRIORITY_CMT0     5
-#define IRQ_PRIORITY_USBI0    5
+#define IRQ_PRIORITY_USBI0    6
 #define IRQ_PRIORITY_SCI0     5
 
 #define SYSTEM_PRCR_PRC1      (1<<1)
@@ -146,13 +146,17 @@ void board_init(void)
   MPC.P20PFS.BYTE  = 0b01010;
   PORT2.PMR.BIT.B1 = 1U;
   MPC.P21PFS.BYTE  = 0b01010;
-  /* USB VBUS -> P16, RXD0 => P21, TXD0 => P20 */
+  /* USB VBUS -> P16 DPUPE -> P14 */
+  PORT1.PMR.BIT.B4 = 1U;
   PORT1.PMR.BIT.B6 = 1U;
+  MPC.P14PFS.BYTE  = 0b10001;
   MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
+  MPC.PFUSB0.BIT.PUPHZS = 1;
   /* Lock MPC registers */
   MPC.PWPR.BIT.PFSWE = 0;
   MPC.PWPR.BIT.B0WI  = 1;
 
+  IR(USB0, USBI0)  = 0;
   IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
 
   /* Enable SCI0 */
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index b0fa1749..cc25a3a8 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -72,6 +72,7 @@
 #define USB_PIPECTR_SQMON     (1u<<6)
 #define USB_PIPECTR_SQCLR     (1u<<8)
 #define USB_PIPECTR_ACLRM     (1u<<9)
+#define USB_PIPECTR_INBUFM    (1u<<14)
 #define USB_PIPECTR_BSTS      (1u<<15)
 
 #define USB_FIFOCTR_DTLN     (0x1FF)
@@ -213,13 +214,29 @@ static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
   return ctr;
 }
 
+static unsigned wait_for_pipe_ready(void)
+{
+  unsigned ctr;
+  do {
+    ctr = USB0.D0FIFOCTR.WORD;
+  } while (!(ctr & USB_FIFOCTR_FRDY));
+  return ctr;
+}
+
+static unsigned select_pipe(unsigned num, unsigned attr)
+{
+  USB0.PIPESEL.WORD  = num;
+  USB0.D0FIFOSEL.WORD = num | attr;
+  while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
+  return wait_for_pipe_ready();
+}
 
 /* 1 less than 64 bytes were written
  * 2 no bytes were written
- * 0 64 bytes were written */
-static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
+ * 0 mps bytes were written */
+static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps, unsigned ofs)
 {
-  unsigned rem  = pipe->remaining;
+  unsigned rem  = pipe->remaining - ofs;
   if (!rem) return 2;
   unsigned len  = (rem < mps) ? rem: mps;
 
@@ -243,6 +260,35 @@ static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
   if (rem < mps) return 1;
   return 0;
 }
+#if 1
+static int write_fifo2(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
+{
+  unsigned rem  = pipe->remaining;
+  if (!rem) return 2;
+  unsigned len  = (rem < mps) ? rem: mps;
+  pipe->remaining = rem - len;
+
+  hw_fifo_t *reg = (hw_fifo_t*)fifo;
+  uintptr_t addr = pipe->addr + pipe->length - rem;
+  if (addr & 1u) {
+    /* addr is not 2-byte aligned */
+    reg->u8 = *(const uint8_t *)addr;
+    ++addr;
+    --len;
+  }
+  while (len >= 2) {
+    reg->u16 = *(const uint16_t *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(const uint8_t *)addr;
+    ++addr;
+  }
+  if (rem < mps) return 1;
+  return 0;
+}
+#endif
 
 /* 1 if the number of bytes read is less than 64 bytes
  * 0 otherwise */
@@ -313,7 +359,7 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     pipe->data      = USB0.DCPCTR.BIT.SQMON;
     if (ep_addr) { /* IN */
       TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      if (write_fifo(&USB0.CFIFO.WORD, pipe, 64)) {
+      if (write_fifo(&USB0.CFIFO.WORD, pipe, 64, 0)) {
         USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
       }
     }
@@ -321,11 +367,11 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     //    TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   } else {
     /* ZLP */
-    pipe->addr      = 0;
-    pipe->length    = 0;
-    pipe->remaining = 0;
-    pipe->data      = USB0.DCPCTR.BIT.SQMON;
-    USB0.DCPCTR.WORD   = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
+    pipe->addr       = 0;
+    pipe->length     = 0;
+    pipe->remaining  = 0;
+    pipe->data       = USB0.DCPCTR.BIT.SQMON;
+    USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
     //    TU_LOG1("Z %x\r\n", USB0.DCPCTR.WORD);
   }
   return true;
@@ -338,7 +384,7 @@ static void process_edpt0_bemp(uint8_t rhport)
   if (USB0.DCPCTR.BIT.SQMON == data) {
     TU_LOG1("W %x\r\n", USB0.DCPCTR.WORD);
     /* retry transfer */
-    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
+    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, 0);
     if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
     return;
   }
@@ -347,7 +393,7 @@ static void process_edpt0_bemp(uint8_t rhport)
     pipe->remaining = rem - 64;
     pipe->data      = data ^ 1;
     TU_LOG1("Y %d %x\r\n", rem - 64, USB0.DCPCTR.WORD);
-    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
+    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, 0);
     if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
     return;
   }
@@ -393,9 +439,23 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   if (dir) { /* IN */
     USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
     while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
-    if (write_fifo(&USB0.D0FIFO.WORD, pipe, mps)) {
+#if 0
+    unsigned ofs = 0;
+    if (USB0.PIPECFG.BIT.DBLB && (total_bytes > mps)) {
+      write_fifo(&USB0.D0FIFO.WORD, pipe, mps, 0);
+    }
+    if (write_fifo(&USB0.D0FIFO.WORD, pipe, mps, ofs)) {
       USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
     }
+#else
+    if (USB0.PIPECFG.BIT.DBLB && (total_bytes > mps)) {
+      write_fifo2(&USB0.D0FIFO.WORD, pipe, mps);
+      wait_for_pipe_ready();
+    }
+    if (write_fifo2(&USB0.D0FIFO.WORD, pipe, mps)) {
+      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    }
+#endif
     USB0.D0FIFOSEL.WORD = 0;
   } else {
     volatile reg_pipetre_t *pt = get_pipetre(num);
@@ -411,43 +471,76 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   return true;
 }
-
+#if 0
 static void process_pipe_bemp(uint8_t rhport, unsigned num)
 {
   pipe_state_t *pipe = &_dcd.pipe[num];
-  const unsigned rem = pipe->remaining;
-  if (rem > 64) {
-    pipe->remaining = rem - 64;
-    TU_LOG1("Y %d\r\n", rem - 64);
-    USB0.PIPESEL.WORD  = num;
-    const unsigned mps = USB0.PIPEMAXP.WORD;
-    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
-    while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
-    int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps);
-    if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    USB0.D0FIFOSEL.WORD = 0;
+  unsigned rem = pipe->remaining;
+  USB0.PIPESEL.WORD  = num;
+  const unsigned mps = USB0.PIPEMAXP.WORD;
+
+  if (rem > mps) {
+    rem -= mps;
+    pipe->remaining = rem;
+    if (USB0.PIPECFG.BIT.DBLB) {
+      if (rem > mps) {
+	unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_16);
+	int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps, mps);
+	if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+	USB0.D0FIFOSEL.WORD = 0;
+	TU_LOG1("< %d %x %x %d\r\n", rem, ctr, *get_pipectr(num), r);
+      }
+    } else {
+      unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_16);
+      int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps, 0);
+      if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      USB0.D0FIFOSEL.WORD = 0;
+      TU_LOG1("< %d %x %x %d\r\n", rem, ctr, *get_pipectr(num), r);
+    }
     return;
   }
   pipe->addr      = 0;
   pipe->remaining = 0;
+  USB0.D0FIFOSEL.WORD = 0;
   dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
 			  XFER_RESULT_SUCCESS, true);
-  //  TU_LOG1("cE\r\n");
+  TU_LOG1("cE\r\n");
 }
+#else
+static void process_pipe_bemp(uint8_t rhport, unsigned num)
+{
+  pipe_state_t *pipe = &_dcd.pipe[num];
+  const unsigned rem = pipe->remaining;
+  if (rem) {
+    USB0.PIPESEL.WORD  = num;
+    const unsigned mps = USB0.PIPEMAXP.WORD;
+    unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_16);
+    int r = write_fifo2(&USB0.D0FIFO.WORD, pipe, mps);
+    if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    USB0.D0FIFOSEL.WORD = 0;
+    TU_LOG1("< %d %x %x %d\r\n", rem, ctr, *get_pipectr(num), r);
+    return;
+  }
+  if (*get_pipectr(num) & USB_PIPECTR_INBUFM) {
+    TU_LOG1("< SKIP\r\n");
+    return;
+  }
+  pipe->addr      = 0;
+  pipe->remaining = 0;
+  USB0.D0FIFOSEL.WORD = 0;
+  dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
+			  XFER_RESULT_SUCCESS, true);
+  TU_LOG1("cE\r\n");
+}
+#endif
 
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
-  pipe_state_t *pipe  = &_dcd.pipe[num];
-  USB0.PIPESEL.WORD   = num;
-  const unsigned mps  = USB0.PIPEMAXP.WORD;
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
-  while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
-  unsigned ctr;
-  do {
-    ctr = USB0.D0FIFOCTR.WORD;
-  } while (!(ctr & USB_FIFOCTR_FRDY));
-  const unsigned len  = ctr & USB_FIFOCTR_DTLN;
-  TU_LOG1(">> %d %x %x\r\n", num, USB0.D0FIFOSEL.WORD, ctr);
+  const unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_8);
+  const unsigned len = ctr & USB_FIFOCTR_DTLN;
+  const unsigned mps = USB0.PIPEMAXP.WORD;
+  pipe_state_t *pipe = &_dcd.pipe[num];
+  //  TU_LOG1("> %d %x %x\r\n", num, USB0.D0FIFOSEL.WORD, ctr);
   int cplt = read_fifo(&USB0.D0FIFO.WORD, pipe, mps, len);
   if (cplt || (len < mps)) {
     if (2 != cplt) {
@@ -457,7 +550,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
     dcd_event_xfer_complete(rhport, pipe->ep,
                             pipe->length - pipe->remaining,
 			    XFER_RESULT_SUCCESS, true);
-    TU_LOG1("c\r\n");
+    //    TU_LOG1("c\r\n");
   } else {
     USB0.D0FIFOSEL.WORD = 0;
   }
@@ -589,7 +682,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   const unsigned mps = ep_desc->wMaxPacketSize.size;
   if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
-    /* USBB support up to 256 bytes */
+    /* USBa supports up to 256 bytes */
     return false;
   }
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index d0ed78ac..644208ab 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -108,6 +108,9 @@
 #define OPT_MCU_EFM32GG11        1301 ///< Silabs EFM32GG11
 #define OPT_MCU_EFM32GG12        1302 ///< Silabs EFM32GG12
 
+// Renesas RX
+#define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
+
 /** @} */
 
 /** \defgroup group_supported_os Supported RTOS

From e010ea30e57e0f8561f8aa7b66afefb01a9bc42d Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Mar 2021 14:42:19 +0900
Subject: [PATCH 37/72] using BRDY interruption for handling IN transfers.

---
 src/portable/renesas/usba/dcd_usba.c | 228 ++++++++-------------------
 1 file changed, 62 insertions(+), 166 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index cc25a3a8..e7518b01 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -200,9 +200,9 @@ static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
 {
   (void)rhport;
   volatile uint16_t *ctr = NULL;
-  const unsigned epn = ep_addr & 0xFu;
+  const unsigned epn   = tu_edpt_number(ep_addr);
   if (epn) {
-    const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+    const unsigned dir = tu_edpt_dir(ep_addr);
     const unsigned num = _dcd.ep[dir][epn];
     if (num) {
       ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
@@ -234,39 +234,11 @@ static unsigned select_pipe(unsigned num, unsigned attr)
 /* 1 less than 64 bytes were written
  * 2 no bytes were written
  * 0 mps bytes were written */
-static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps, unsigned ofs)
-{
-  unsigned rem  = pipe->remaining - ofs;
-  if (!rem) return 2;
-  unsigned len  = (rem < mps) ? rem: mps;
-
-  hw_fifo_t *reg = (hw_fifo_t*)fifo;
-  uintptr_t addr = pipe->addr + pipe->length - rem;
-  if (addr & 1u) {
-    /* addr is not 2-byte aligned */
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
-    --len;
-  }
-  while (len >= 2) {
-    reg->u16 = *(const uint16_t *)addr;
-    addr += 2;
-    len  -= 2;
-  }
-  if (len) {
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
-  }
-  if (rem < mps) return 1;
-  return 0;
-}
-#if 1
-static int write_fifo2(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
+static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
 {
   unsigned rem  = pipe->remaining;
   if (!rem) return 2;
-  unsigned len  = (rem < mps) ? rem: mps;
-  pipe->remaining = rem - len;
+  unsigned len  = TU_MIN(rem, mps);
 
   hw_fifo_t *reg = (hw_fifo_t*)fifo;
   uintptr_t addr = pipe->addr + pipe->length - rem;
@@ -288,7 +260,6 @@ static int write_fifo2(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
   if (rem < mps) return 1;
   return 0;
 }
-#endif
 
 /* 1 if the number of bytes read is less than 64 bytes
  * 0 otherwise */
@@ -359,7 +330,7 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     pipe->data      = USB0.DCPCTR.BIT.SQMON;
     if (ep_addr) { /* IN */
       TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      if (write_fifo(&USB0.CFIFO.WORD, pipe, 64, 0)) {
+      if (write_fifo(&USB0.CFIFO.WORD, pipe, 64)) {
         USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
       }
     }
@@ -372,7 +343,6 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     pipe->remaining  = 0;
     pipe->data       = USB0.DCPCTR.BIT.SQMON;
     USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
-    //    TU_LOG1("Z %x\r\n", USB0.DCPCTR.WORD);
   }
   return true;
 }
@@ -382,9 +352,8 @@ static void process_edpt0_bemp(uint8_t rhport)
   pipe_state_t *pipe = &_dcd.pipe[0];
   unsigned data = pipe->data;
   if (USB0.DCPCTR.BIT.SQMON == data) {
-    TU_LOG1("W %x\r\n", USB0.DCPCTR.WORD);
     /* retry transfer */
-    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, 0);
+    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
     if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
     return;
   }
@@ -392,16 +361,14 @@ static void process_edpt0_bemp(uint8_t rhport)
   if (rem > 64) {
     pipe->remaining = rem - 64;
     pipe->data      = data ^ 1;
-    TU_LOG1("Y %d %x\r\n", rem - 64, USB0.DCPCTR.WORD);
-    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, 0);
+    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
     if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
     return;
   }
   pipe->addr      = 0;
   pipe->remaining = 0;
   dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
-			  pipe->length, XFER_RESULT_SUCCESS, true);
-  //  TU_LOG1("c\r\n");
+                          pipe->length, XFER_RESULT_SUCCESS, true);
 }
 
 static void process_edpt0_brdy(uint8_t rhport)
@@ -414,8 +381,7 @@ static void process_edpt0_brdy(uint8_t rhport)
     }
     dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
                             _dcd.pipe[0].length - _dcd.pipe[0].remaining,
-			    XFER_RESULT_SUCCESS, true);
-    //    TU_LOG1("c\r\n");
+                            XFER_RESULT_SUCCESS, true);
   }
 }
 
@@ -423,8 +389,8 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
 {
   (void)rhport;
 
-  const unsigned epn = ep_addr & 0xFu;
-  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned epn = tu_edpt_number(ep_addr);
+  const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
 
   TU_ASSERT(num);
@@ -439,120 +405,61 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   if (dir) { /* IN */
     USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
     while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
-#if 0
-    unsigned ofs = 0;
-    if (USB0.PIPECFG.BIT.DBLB && (total_bytes > mps)) {
-      write_fifo(&USB0.D0FIFO.WORD, pipe, mps, 0);
-    }
-    if (write_fifo(&USB0.D0FIFO.WORD, pipe, mps, ofs)) {
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    }
-#else
-    if (USB0.PIPECFG.BIT.DBLB && (total_bytes > mps)) {
-      write_fifo2(&USB0.D0FIFO.WORD, pipe, mps);
-      wait_for_pipe_ready();
-    }
-    if (write_fifo2(&USB0.D0FIFO.WORD, pipe, mps)) {
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    }
-#endif
+    int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps);
+    if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
     USB0.D0FIFOSEL.WORD = 0;
   } else {
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
       volatile uint16_t *ctr = get_pipectr(num);
       if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
-      pt->TRE   = 1u << 8;
+      pt->TRE   = TU_BIT(8);
       pt->TRN   = (total_bytes + mps - 1) / mps;
       pt->TRENB = 1;
       *ctr = USB_PIPECTR_PID_BUF;
     }
   }
-  TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
+  //TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   return true;
 }
-#if 0
-static void process_pipe_bemp(uint8_t rhport, unsigned num)
-{
-  pipe_state_t *pipe = &_dcd.pipe[num];
-  unsigned rem = pipe->remaining;
-  USB0.PIPESEL.WORD  = num;
-  const unsigned mps = USB0.PIPEMAXP.WORD;
-
-  if (rem > mps) {
-    rem -= mps;
-    pipe->remaining = rem;
-    if (USB0.PIPECFG.BIT.DBLB) {
-      if (rem > mps) {
-	unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_16);
-	int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps, mps);
-	if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-	USB0.D0FIFOSEL.WORD = 0;
-	TU_LOG1("< %d %x %x %d\r\n", rem, ctr, *get_pipectr(num), r);
-      }
-    } else {
-      unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_16);
-      int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps, 0);
-      if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      TU_LOG1("< %d %x %x %d\r\n", rem, ctr, *get_pipectr(num), r);
-    }
-    return;
-  }
-  pipe->addr      = 0;
-  pipe->remaining = 0;
-  USB0.D0FIFOSEL.WORD = 0;
-  dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
-			  XFER_RESULT_SUCCESS, true);
-  TU_LOG1("cE\r\n");
-}
-#else
-static void process_pipe_bemp(uint8_t rhport, unsigned num)
-{
-  pipe_state_t *pipe = &_dcd.pipe[num];
-  const unsigned rem = pipe->remaining;
-  if (rem) {
-    USB0.PIPESEL.WORD  = num;
-    const unsigned mps = USB0.PIPEMAXP.WORD;
-    unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_16);
-    int r = write_fifo2(&USB0.D0FIFO.WORD, pipe, mps);
-    if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    USB0.D0FIFOSEL.WORD = 0;
-    TU_LOG1("< %d %x %x %d\r\n", rem, ctr, *get_pipectr(num), r);
-    return;
-  }
-  if (*get_pipectr(num) & USB_PIPECTR_INBUFM) {
-    TU_LOG1("< SKIP\r\n");
-    return;
-  }
-  pipe->addr      = 0;
-  pipe->remaining = 0;
-  USB0.D0FIFOSEL.WORD = 0;
-  dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
-			  XFER_RESULT_SUCCESS, true);
-  TU_LOG1("cE\r\n");
-}
-#endif
 
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
-  const unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_8);
-  const unsigned len = ctr & USB_FIFOCTR_DTLN;
-  const unsigned mps = USB0.PIPEMAXP.WORD;
   pipe_state_t *pipe = &_dcd.pipe[num];
-  //  TU_LOG1("> %d %x %x\r\n", num, USB0.D0FIFOSEL.WORD, ctr);
-  int cplt = read_fifo(&USB0.D0FIFO.WORD, pipe, mps, len);
-  if (cplt || (len < mps)) {
-    if (2 != cplt) {
-      USB0.D0FIFO.WORD = USB_FIFOCTR_BCLR;
+  if (!tu_edpt_dir(pipe->ep)) {
+    const unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_8);
+    const unsigned len = ctr & USB_FIFOCTR_DTLN;
+    const unsigned mps = USB0.PIPEMAXP.WORD;
+    int cplt = read_fifo(&USB0.D0FIFO.WORD, pipe, mps, len);
+    if (cplt || (len < mps)) {
+      if (2 != cplt) {
+        USB0.D0FIFO.WORD = USB_FIFOCTR_BCLR;
+      }
+      USB0.D0FIFOSEL.WORD = 0;
+      dcd_event_xfer_complete(rhport, pipe->ep,
+                              pipe->length - pipe->remaining,
+                              XFER_RESULT_SUCCESS, true);
+      return;
     }
     USB0.D0FIFOSEL.WORD = 0;
-    dcd_event_xfer_complete(rhport, pipe->ep,
-                            pipe->length - pipe->remaining,
-			    XFER_RESULT_SUCCESS, true);
-    //    TU_LOG1("c\r\n");
   } else {
+    select_pipe(num, USB_FIFOSEL_MBW_16);
+    const unsigned mps = USB0.PIPEMAXP.WORD;
+    unsigned rem       = pipe->remaining;
+    rem               -= TU_MIN(rem, mps);
+    pipe->remaining    = rem;
+    if (rem) {
+      int r = 0;
+      r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps);
+      if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      USB0.D0FIFOSEL.WORD = 0;
+      return;
+    }
     USB0.D0FIFOSEL.WORD = 0;
+    pipe->addr      = 0;
+    pipe->remaining = 0;
+    dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
+                            XFER_RESULT_SUCCESS, true);
   }
 }
 
@@ -571,7 +478,7 @@ static void process_bus_reset(uint8_t rhport)
     *ctr = USB_PIPECTR_ACLRM;
     *ctr = 0;
     ++ctr;
-    *tre = (1u<<8);
+    *tre = TU_BIT(8);
     tre += 2;
   }
   for (int i = 6; i <= 9; ++i) {
@@ -583,7 +490,7 @@ static void process_bus_reset(uint8_t rhport)
   }
   tu_varclr(&_dcd);
   dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
-  TU_LOG1("R\r\n");
+  //  TU_LOG1("R\r\n");
 }
 
 static void process_set_address(uint8_t rhport)
@@ -626,7 +533,6 @@ void dcd_init(uint8_t rhport)
   USB0.BEMPENB.WORD = 1;
   USB0.BRDYENB.WORD = 1;
 
-  TU_LOG1("INIT\r\n");
   if (USB0.INTSTS0.BIT.VBSTS) {
     dcd_connect(rhport);
   }
@@ -676,8 +582,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   (void)rhport;
 
   const unsigned ep_addr = ep_desc->bEndpointAddress;
-  const unsigned epn     = ep_addr & 0xFu;
-  const unsigned dir     = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned dir     = tu_edpt_dir(ep_addr);
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
 
   const unsigned mps = ep_desc->wMaxPacketSize.size;
@@ -692,6 +598,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   _dcd.ep[dir][epn] = num;
 
   /* setup pipe */
+  dcd_int_disable(rhport);
   USB0.PIPESEL.WORD  = num;
   USB0.PIPEMAXP.WORD = mps;
   volatile uint16_t *ctr = get_pipectr(num);
@@ -705,17 +612,14 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   } else {
     cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
   }
-  USB0.PIPECFG.WORD = cfg;
-  if (dir) {
-    USB0.BEMPENB.WORD |= 1u << num;
+  USB0.PIPECFG.WORD  = cfg;
+  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
+  USB0.BRDYENB.WORD |= TU_BIT(num);
+  if (dir || (xfer != TUSB_XFER_BULK)) {
     *ctr = USB_PIPECTR_PID_BUF;
-  } else {
-    USB0.BRDYENB.WORD |= 1u << num;
-    if (xfer != TUSB_XFER_BULK) {
-      *ctr = USB_PIPECTR_PID_BUF;
-    }
   }
-  TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
+  //  TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
+  dcd_int_enable(rhport);
 
   return true;
 }
@@ -723,12 +627,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
-  const unsigned epn = ep_addr & 0xFu;
-  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned epn = tu_edpt_number(ep_addr);
+  const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
 
-  USB0.BEMPENB.WORD &= ~(1u << num);
-  USB0.BRDYENB.WORD &= ~(1u << num);
+  USB0.BRDYENB.WORD &= ~TU_BIT(num);
   volatile uint16_t *ctr = get_pipectr(num);
   *ctr = 0;
   USB0.PIPESEL.WORD = num;
@@ -740,7 +643,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   bool r;
-  const unsigned epn = ep_addr & 0xFu;
+  const unsigned epn = tu_edpt_number(ep_addr);
   dcd_int_disable(rhport);
   if (0 == epn) {
     r = process_edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
@@ -816,17 +719,10 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
   if (is0 & USB_IS0_BEMP) {
-    const unsigned m = USB0.BEMPENB.WORD;
-    unsigned s       = USB0.BEMPSTS.WORD & m;
+    const unsigned s = USB0.BEMPSTS.WORD;
     USB0.BEMPSTS.WORD = 0;
     if (s & 1) {
       process_edpt0_bemp(rhport);
-      s &= ~1;
-    }
-    while (s) {
-      const unsigned num = __builtin_ctz(s);
-      process_pipe_bemp(rhport, num);
-      s &= ~(1<<num);
     }
   }
   if (is0 & USB_IS0_BRDY) {
@@ -840,7 +736,7 @@ void dcd_int_handler(uint8_t rhport)
     while (s) {
       const unsigned num = __builtin_ctz(s);
       process_pipe_brdy(rhport, num);
-      s &= ~(1<<num);
+      s &= ~TU_BIT(num);
     }
   }
 }

From e48b2c681e9d7eaf07f3e1d4125ab24872645f32 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Mar 2021 16:00:56 +0900
Subject: [PATCH 38/72] fixed definitions for stack areas

---
 hw/bsp/gr_citrus/r5f5631fd.ld | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/gr_citrus/r5f5631fd.ld b/hw/bsp/gr_citrus/r5f5631fd.ld
index 166a9e7c..fa814293 100644
--- a/hw/bsp/gr_citrus/r5f5631fd.ld
+++ b/hw/bsp/gr_citrus/r5f5631fd.ld
@@ -1,5 +1,5 @@
 __USTACK_SIZE = 0x00000200;
-__ISTACK_SIZE = 0x00000100;
+__ISTACK_SIZE = 0x00000200;
 
 MEMORY
 {
@@ -112,13 +112,13 @@ SECTIONS
 		_ebss = .;
 		_end = .;
 	} > RAM
-	.ustack (COPY) :
+	.ustack :
 	{
 		. = ALIGN(8);
 		. = . + __USTACK_SIZE;
 		PROVIDE(_ustack = .);
 	} > RAM
-	.istack (COPY) :
+	.istack :
 	{
 		. = ALIGN(8);
 		. = . + __ISTACK_SIZE;

From a1f1941c3f965483e274993e43d18a9ede5e1f09 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Mar 2021 16:03:04 +0900
Subject: [PATCH 39/72] fixed a OUT transfer did not completed multiple of the
 max packet size

---
 src/portable/renesas/usba/dcd_usba.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index e7518b01..844fa385 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -261,7 +261,7 @@ static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
   return 0;
 }
 
-/* 1 if the number of bytes read is less than 64 bytes
+/* 1 if the number of bytes read is less than mps bytes
  * 0 otherwise */
 static int read_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size_t len)
 {
@@ -272,12 +272,14 @@ static int read_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size
 
   hw_fifo_t *reg = (hw_fifo_t*)fifo;
   uintptr_t addr = pipe->addr;
-  while (len--) {
+  unsigned  loop = len;
+  while (loop--) {
     *(uint8_t *)addr = reg->u8;
     ++addr;
   }
   pipe->addr = addr;
-  if (rem < mps) return 1;
+  if (rem < mps)  return 1;
+  if (rem == len) return 2;
   return 0;
 }
 
@@ -419,7 +421,7 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
       *ctr = USB_PIPECTR_PID_BUF;
     }
   }
-  //TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
+  //  TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   return true;
 }
 

From eab214e07c53d84d33a74c5a73fe40c152e3b987 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Mar 2021 19:12:34 +0900
Subject: [PATCH 40/72] added settings for LWIP and FreeRTOS

---
 hw/bsp/gr_citrus/board.mk    | 14 ++++++++++----
 hw/bsp/gr_citrus/gr_citrus.c |  2 ++
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/gr_citrus/board.mk
index 53f85aa7..241c12bc 100644
--- a/hw/bsp/gr_citrus/board.mk
+++ b/hw/bsp/gr_citrus/board.mk
@@ -1,6 +1,5 @@
 CFLAGS += \
   -nostartfiles \
-  -nostdinc \
   -ffunction-sections \
   -fdata-sections \
   -mcpu=rx610 \
@@ -17,10 +16,17 @@ else
 OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
 endif
 
-# mcu driver cause following warnings
-CFLAGS += -isystem $(OPTLIBINC)
+ifeq ($(RX_NEWLIB),0)
+# setup for optlib
+CFLAGS += -nostdinc \
+  -isystem $(OPTLIBINC) \
+  -DLWIP_NO_INTTYPES_H
 
-LIBS += -loptm -loptc
+LIBS += -loptc -loptm
+else
+# setup for newlib
+LIBS += -lm
+endif
 
 MCU_DIR = hw/mcu/renesas/rx63n
 
diff --git a/hw/bsp/gr_citrus/gr_citrus.c b/hw/bsp/gr_citrus/gr_citrus.c
index f8cf8b18..aadd4139 100644
--- a/hw/bsp/gr_citrus/gr_citrus.c
+++ b/hw/bsp/gr_citrus/gr_citrus.c
@@ -218,4 +218,6 @@ uint32_t board_millis(void)
 {
   return system_ticks;
 }
+#else
+uint32_t SystemCoreClock = 96000000;
 #endif

From 86dab3f7e9ce5880eb7f5eb340110735e8ace54f Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Mar 2021 20:22:32 +0900
Subject: [PATCH 41/72] added configurations for RX63X

---
 .../cdc_msc_freertos/src/FreeRTOSConfig.h     | 12 ++++++++++++
 .../cdc_msc_freertos/src/freertos_hook.c      | 19 +++++++++++++++++++
 examples/device/cdc_msc_freertos/src/main.c   |  4 +++-
 .../src/FreeRTOSConfig.h                      | 12 ++++++++++++
 .../src/freertos_hook.c                       | 19 +++++++++++++++++++
 .../device/hid_composite_freertos/src/main.c  |  4 +++-
 6 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
index 7b2b93d7..b76d5970 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
@@ -132,6 +132,16 @@ extern uint32_t SystemCoreClock;
   #define configASSERT( x )
 #endif
 
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
+#define vTickISR								INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
+
+#else
+
 /* FreeRTOS hooks to NVIC vectors */
 #define xPortPendSVHandler    PendSV_Handler
 #define xPortSysTickHandler   SysTick_Handler
@@ -164,4 +174,6 @@ to all Cortex-M ports, and do not rely on any particular library functions. */
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
 
+#endif
+
 #endif /* __FREERTOS_CONFIG__H */
diff --git a/examples/device/cdc_msc_freertos/src/freertos_hook.c b/examples/device/cdc_msc_freertos/src/freertos_hook.c
index df15a8de..273ad46e 100644
--- a/examples/device/cdc_msc_freertos/src/freertos_hook.c
+++ b/examples/device/cdc_msc_freertos/src/freertos_hook.c
@@ -93,3 +93,22 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, Stack
     configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
   *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
 }
+
+#if CFG_TUSB_MCU == OPT_MCU_RX63X
+#include "iodefine.h"
+void vApplicationSetupTimerInterrupt(void)
+{
+  /* Enable CMT0 */
+  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = (0xA5u<<8);
+
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
+  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+}
+#endif
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 5779b7d4..abb95f4f 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -97,9 +97,11 @@ int main(void)
   // skip starting scheduler (and return) for ESP32-S2
 #if CFG_TUSB_MCU != OPT_MCU_ESP32S2
   vTaskStartScheduler();
+#if CFG_TUSB_MCU != OPT_MCU_RX63X
   NVIC_SystemReset();
-  return 0;
 #endif
+#endif
+  return 0;
 }
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
index 7b2b93d7..b76d5970 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
@@ -132,6 +132,16 @@ extern uint32_t SystemCoreClock;
   #define configASSERT( x )
 #endif
 
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
+#define vTickISR								INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
+
+#else
+
 /* FreeRTOS hooks to NVIC vectors */
 #define xPortPendSVHandler    PendSV_Handler
 #define xPortSysTickHandler   SysTick_Handler
@@ -164,4 +174,6 @@ to all Cortex-M ports, and do not rely on any particular library functions. */
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
 
+#endif
+
 #endif /* __FREERTOS_CONFIG__H */
diff --git a/examples/device/hid_composite_freertos/src/freertos_hook.c b/examples/device/hid_composite_freertos/src/freertos_hook.c
index df15a8de..273ad46e 100644
--- a/examples/device/hid_composite_freertos/src/freertos_hook.c
+++ b/examples/device/hid_composite_freertos/src/freertos_hook.c
@@ -93,3 +93,22 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, Stack
     configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
   *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
 }
+
+#if CFG_TUSB_MCU == OPT_MCU_RX63X
+#include "iodefine.h"
+void vApplicationSetupTimerInterrupt(void)
+{
+  /* Enable CMT0 */
+  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = (0xA5u<<8);
+
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
+  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+}
+#endif
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 79dc2ec6..1b42cee4 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -98,9 +98,11 @@ int main(void)
   // skip starting scheduler (and return) for ESP32-S2
 #if CFG_TUSB_MCU != OPT_MCU_ESP32S2
   vTaskStartScheduler();
+#if CFG_TUSB_MCU != OPT_MCU_RX63X
   NVIC_SystemReset();
-  return 0;
 #endif
+#endif
+  return 0;
 }
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2

From 4c832a9195cfca5a2d840c30efc010da75f71b4b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Mar 2021 22:20:15 +0900
Subject: [PATCH 42/72] Set newlib as the default library

---
 hw/bsp/gr_citrus/board.mk | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/gr_citrus/board.mk
index 241c12bc..39aef2e9 100644
--- a/hw/bsp/gr_citrus/board.mk
+++ b/hw/bsp/gr_citrus/board.mk
@@ -10,22 +10,23 @@ CFLAGS += \
 # Cross Compiler for RX
 CROSS_COMPILE = rx-elf-
 
+RX_NEWLIB ?= 1
+
 ifeq ($(CMDEXE),1)
 OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
 else
 OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
 endif
 
-ifeq ($(RX_NEWLIB),0)
+ifeq ($(RX_NEWLIB),1)
+CFLAGS += -DSSIZE_MAX=__INT_MAX__
+else
 # setup for optlib
 CFLAGS += -nostdinc \
   -isystem $(OPTLIBINC) \
   -DLWIP_NO_INTTYPES_H
 
 LIBS += -loptc -loptm
-else
-# setup for newlib
-LIBS += -lm
 endif
 
 MCU_DIR = hw/mcu/renesas/rx63n

From 5f4e6dafc564847728712ceac14bafa4577c3862 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 28 Mar 2021 00:10:53 +0900
Subject: [PATCH 43/72] added short-enums into CFLAGS

---
 hw/bsp/gr_citrus/board.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/gr_citrus/board.mk
index 39aef2e9..06262184 100644
--- a/hw/bsp/gr_citrus/board.mk
+++ b/hw/bsp/gr_citrus/board.mk
@@ -2,6 +2,7 @@ CFLAGS += \
   -nostartfiles \
   -ffunction-sections \
   -fdata-sections \
+  -fshort-enums \
   -mcpu=rx610 \
   -misa=v1 \
   -mlittle-endian-data \

From 0b76a2da88d01f5defcc22c25d3d8bb4068dbf8d Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 28 Mar 2021 00:34:29 +0900
Subject: [PATCH 44/72] added a setting for RX63X

---
 hw/bsp/board_mcu.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 3c18f6d3..362e3289 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -123,6 +123,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12
   #include "em_device.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_RX63X
+  // no header needed
+
 #else
   #error "Missing MCU header"
 #endif

From 0e0f9a8da30780c9db711e08371465343247604e Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 28 Mar 2021 00:46:08 +0900
Subject: [PATCH 45/72] added a submodule for RX63N

---
 .gitmodules    | 3 +++
 hw/mcu/renesas | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 hw/mcu/renesas

diff --git a/.gitmodules b/.gitmodules
index 1a5ae2c5..e075e0c6 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -116,3 +116,6 @@
 [submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
 	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
 	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
+[submodule "hw/mcu/renesas"]
+	path = hw/mcu/renesas
+	url = https://github.com/kkitayam/rx_device.git
diff --git a/hw/mcu/renesas b/hw/mcu/renesas
new file mode 160000
index 00000000..4a51dfe6
--- /dev/null
+++ b/hw/mcu/renesas
@@ -0,0 +1 @@
+Subproject commit 4a51dfe6ecdf936d2d89f223f069e24a2d109207

From 4a597c969844d9b279279db0f678aa6732bae1a5 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 28 Mar 2021 12:42:28 +0900
Subject: [PATCH 46/72] cleanup

---
 src/portable/renesas/usba/dcd_usba.c | 102 ++++++++++++---------------
 1 file changed, 46 insertions(+), 56 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 844fa385..06ea1a3f 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -112,12 +112,11 @@ typedef union {
 
 typedef struct TU_ATTR_PACKED
 {
-  uintptr_t addr;
-  uint16_t  length;
-  uint16_t  remaining;
+  uintptr_t addr;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
   struct {
-    uint32_t ep  : 8;
-    uint32_t data: 1;
+    uint32_t ep  : 8;  /* an assigned endpoint address */
     uint32_t     : 0;
   };
 } pipe_state_t;
@@ -125,7 +124,7 @@ typedef struct TU_ATTR_PACKED
 typedef struct
 {
   pipe_state_t pipe[9];
-  uint8_t ep[2][16]; /* index for pipe number */
+  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
 } dcd_data_t;
 
 //--------------------------------------------------------------------+
@@ -231,10 +230,10 @@ static unsigned select_pipe(unsigned num, unsigned attr)
   return wait_for_pipe_ready();
 }
 
-/* 1 less than 64 bytes were written
- * 2 no bytes were written
- * 0 mps bytes were written */
-static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
+/* 1 less than mps bytes were written to FIFO
+ * 2 no bytes were written to FIFO
+ * 0 mps bytes were written to FIFO */
+static int fifo_write(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
 {
   unsigned rem  = pipe->remaining;
   if (!rem) return 2;
@@ -261,9 +260,10 @@ static int write_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
   return 0;
 }
 
-/* 1 if the number of bytes read is less than mps bytes
- * 0 otherwise */
-static int read_fifo(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size_t len)
+/* 1 less than mps bytes were read from FIFO
+ * 2 the end of the buffer reached.
+ * 0 mps bytes were read from FIFO */
+static int fifo_read(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size_t len)
 {
   unsigned rem  = pipe->remaining;
   if (!rem) return 2;
@@ -294,7 +294,6 @@ static void process_setup_packet(uint8_t rhport)
   setup_packet[3] = USB0.USBLENG;
   USB0.INTSTS0.WORD = ~USB_IS0_VALID;
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
-  //  TU_LOG1("S\r\n");
 }
 
 static void process_status_completion(uint8_t rhport)
@@ -309,7 +308,6 @@ static void process_status_completion(uint8_t rhport)
     ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
   }
   dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
-  //  TU_LOG1("C\r\n");
 }
 
 static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
@@ -317,11 +315,11 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   (void)rhport;
 
   pipe_state_t *pipe = &_dcd.pipe[0];
-  /* set fifo direction */
-  if (ep_addr) { /* IN */
+  /* configure fifo direction and access unit settings */
+  if (ep_addr) { /* IN, 2 bytes */
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16;
     while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
-  } else {       /* OUT */
+  } else {       /* OUT, a byte */
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
     while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
   }
@@ -329,21 +327,18 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     pipe->addr      = (uintptr_t)buffer;
     pipe->length    = total_bytes;
     pipe->remaining = total_bytes;
-    pipe->data      = USB0.DCPCTR.BIT.SQMON;
     if (ep_addr) { /* IN */
       TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      if (write_fifo(&USB0.CFIFO.WORD, pipe, 64)) {
+      if (fifo_write(&USB0.CFIFO.WORD, pipe, 64)) {
         USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
       }
     }
     USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
-    //    TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   } else {
     /* ZLP */
     pipe->addr       = 0;
     pipe->length     = 0;
     pipe->remaining  = 0;
-    pipe->data       = USB0.DCPCTR.BIT.SQMON;
     USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
   }
   return true;
@@ -352,18 +347,10 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
 static void process_edpt0_bemp(uint8_t rhport)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
-  unsigned data = pipe->data;
-  if (USB0.DCPCTR.BIT.SQMON == data) {
-    /* retry transfer */
-    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
-    if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    return;
-  }
   const unsigned rem = pipe->remaining;
   if (rem > 64) {
     pipe->remaining = rem - 64;
-    pipe->data      = data ^ 1;
-    int r = write_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
+    int r = fifo_write(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
     if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
     return;
   }
@@ -376,7 +363,7 @@ static void process_edpt0_bemp(uint8_t rhport)
 static void process_edpt0_brdy(uint8_t rhport)
 {
   size_t len = USB0.CFIFOCTR.BIT.DTLN;
-  int cplt = read_fifo(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, len);
+  int cplt = fifo_read(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, len);
   if (cplt || (len < 64)) {
     if (2 != cplt) {
       USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
@@ -407,7 +394,7 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   if (dir) { /* IN */
     USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
     while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
-    int r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps);
+    int r = fifo_write(&USB0.D0FIFO.WORD, pipe, mps);
     if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
     USB0.D0FIFOSEL.WORD = 0;
   } else {
@@ -428,11 +415,29 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
   pipe_state_t *pipe = &_dcd.pipe[num];
-  if (!tu_edpt_dir(pipe->ep)) {
+  if (tu_edpt_dir(pipe->ep)) { /* IN */
+    select_pipe(num, USB_FIFOSEL_MBW_16);
+    const unsigned mps = USB0.PIPEMAXP.WORD;
+    unsigned rem       = pipe->remaining;
+    rem               -= TU_MIN(rem, mps);
+    pipe->remaining    = rem;
+    if (rem) {
+      int r = 0;
+      r = fifo_write(&USB0.D0FIFO.WORD, pipe, mps);
+      if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      USB0.D0FIFOSEL.WORD = 0;
+      return;
+    }
+    USB0.D0FIFOSEL.WORD = 0;
+    pipe->addr      = 0;
+    pipe->remaining = 0;
+    dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
+                            XFER_RESULT_SUCCESS, true);
+  } else {
     const unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_8);
     const unsigned len = ctr & USB_FIFOCTR_DTLN;
     const unsigned mps = USB0.PIPEMAXP.WORD;
-    int cplt = read_fifo(&USB0.D0FIFO.WORD, pipe, mps, len);
+    int cplt = fifo_read(&USB0.D0FIFO.WORD, pipe, mps, len);
     if (cplt || (len < mps)) {
       if (2 != cplt) {
         USB0.D0FIFO.WORD = USB_FIFOCTR_BCLR;
@@ -444,24 +449,6 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
       return;
     }
     USB0.D0FIFOSEL.WORD = 0;
-  } else {
-    select_pipe(num, USB_FIFOSEL_MBW_16);
-    const unsigned mps = USB0.PIPEMAXP.WORD;
-    unsigned rem       = pipe->remaining;
-    rem               -= TU_MIN(rem, mps);
-    pipe->remaining    = rem;
-    if (rem) {
-      int r = 0;
-      r = write_fifo(&USB0.D0FIFO.WORD, pipe, mps);
-      if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      return;
-    }
-    USB0.D0FIFOSEL.WORD = 0;
-    pipe->addr      = 0;
-    pipe->remaining = 0;
-    dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
-                            XFER_RESULT_SUCCESS, true);
   }
 }
 
@@ -492,7 +479,6 @@ static void process_bus_reset(uint8_t rhport)
   }
   tu_varclr(&_dcd);
   dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
-  //  TU_LOG1("R\r\n");
 }
 
 static void process_set_address(uint8_t rhport)
@@ -674,10 +660,14 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   dcd_int_disable(rhport);
   *ctr = USB_PIPECTR_SQCLR;
 
-  if (ep_addr & TUSB_DIR_IN_MASK) {
+  if (tu_edpt_dir(ep_addr)) { /* IN */
     *ctr = USB_PIPECTR_PID_BUF;
   } else {
-    /* TODO */
+    const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
+    USB0.PIPESEL.WORD  = num;
+    if (USB0.PIPECFG.BIT.TYPE != 1) {
+      *ctr = USB_PIPECTR_PID_BUF;
+    }
   }
   dcd_int_enable(rhport);
 }

From 30687daf9b769f7795e4b17b9c7f8b88d3d11690 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 28 Mar 2021 16:45:53 +0900
Subject: [PATCH 47/72] added a submodule dependency

---
 hw/bsp/gr_citrus/board.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/gr_citrus/board.mk
index 06262184..9804f835 100644
--- a/hw/bsp/gr_citrus/board.mk
+++ b/hw/bsp/gr_citrus/board.mk
@@ -1,3 +1,5 @@
+DEPS_SUBMODULES += hw/mcu/renesas
+
 CFLAGS += \
   -nostartfiles \
   -ffunction-sections \

From d8efef94611f5744b7e141f424f02b907accd5b7 Mon Sep 17 00:00:00 2001
From: Szymon Janc <szymon.janc@codecoup.pl>
Date: Mon, 29 Mar 2021 11:06:03 +0200
Subject: [PATCH 48/72] Add releases to Mynewt repository.yml

This makes it possible to setup Mynewt project which checkouts
specified version of tinyusb.
---
 repository.yml | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/repository.yml b/repository.yml
index 3325587b..16afbca5 100644
--- a/repository.yml
+++ b/repository.yml
@@ -1,5 +1,12 @@
 repo.name: tinyusb
 repo.versions:
     "0.0.0": "master"
+    "0.5.0": "0.5.0"
+    "0.6.0": "0.6.0"
+    "0.7.0": "0.7.0"
+    "0.8.0": "0.8.0"
+    "0.9.0": "0.9.0"
+
+    "0-dev": "0.0.0"        # master
+    "0-latest": "0.9.0"     # latest stable release
 
-    "0-dev": "0.0.0"

From ef73a9864f5cdb33d959ffcc944aa317d1f45303 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 Mar 2021 22:51:11 +0700
Subject: [PATCH 49/72] add suffix _s to object of assembly file

---
 examples/rules.mk | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 9265bb68..6f494f4b 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -52,7 +52,8 @@ SRC_S := $(SRC_S:.S=.s)
 
 # Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
 # assembly file should be placed first in linking order
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=.o))
+# '_s' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_s.o))
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
 
 # Verbose mode
@@ -111,13 +112,13 @@ $(BUILD)/obj/%.o: %.c
 
 # ASM sources lower case .s
 vpath %.s . $(TOP)
-$(BUILD)/obj/%.o: %.s
+$(BUILD)/obj/%_s.o: %.s
 	@echo AS $(notdir $@)
 	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
 
 # ASM sources upper case .S
 vpath %.S . $(TOP)
-$(BUILD)/obj/%.o: %.S
+$(BUILD)/obj/%_s.o: %.S
 	@echo AS $(notdir $@)
 	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
 

From 5a0c594c719a1bd86bf49ad60175be4d51154655 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 Mar 2021 23:54:44 +0700
Subject: [PATCH 50/72] move rx63n into its own family

---
 hw/bsp/{ => rx63n/boards}/gr_citrus/board.mk     | 4 ++--
 hw/bsp/{ => rx63n/boards}/gr_citrus/gr_citrus.c  | 0
 hw/bsp/{ => rx63n/boards}/gr_citrus/hwinit.c     | 0
 hw/bsp/{ => rx63n/boards}/gr_citrus/r5f5631fd.ld | 0
 hw/bsp/rx63n/family.mk                           | 1 +
 5 files changed, 3 insertions(+), 2 deletions(-)
 rename hw/bsp/{ => rx63n/boards}/gr_citrus/board.mk (94%)
 rename hw/bsp/{ => rx63n/boards}/gr_citrus/gr_citrus.c (100%)
 rename hw/bsp/{ => rx63n/boards}/gr_citrus/hwinit.c (100%)
 rename hw/bsp/{ => rx63n/boards}/gr_citrus/r5f5631fd.ld (100%)
 create mode 100644 hw/bsp/rx63n/family.mk

diff --git a/hw/bsp/gr_citrus/board.mk b/hw/bsp/rx63n/boards/gr_citrus/board.mk
similarity index 94%
rename from hw/bsp/gr_citrus/board.mk
rename to hw/bsp/rx63n/boards/gr_citrus/board.mk
index 9804f835..e33f3b50 100644
--- a/hw/bsp/gr_citrus/board.mk
+++ b/hw/bsp/rx63n/boards/gr_citrus/board.mk
@@ -35,14 +35,14 @@ endif
 MCU_DIR = hw/mcu/renesas/rx63n
 
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/r5f5631fd.ld
+LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
 
 SRC_C += \
 	src/portable/renesas/usba/dcd_usba.c \
 	$(MCU_DIR)/vects.c
 
 INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)
 
 SRC_S += $(MCU_DIR)/start.S
diff --git a/hw/bsp/gr_citrus/gr_citrus.c b/hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c
similarity index 100%
rename from hw/bsp/gr_citrus/gr_citrus.c
rename to hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c
diff --git a/hw/bsp/gr_citrus/hwinit.c b/hw/bsp/rx63n/boards/gr_citrus/hwinit.c
similarity index 100%
rename from hw/bsp/gr_citrus/hwinit.c
rename to hw/bsp/rx63n/boards/gr_citrus/hwinit.c
diff --git a/hw/bsp/gr_citrus/r5f5631fd.ld b/hw/bsp/rx63n/boards/gr_citrus/r5f5631fd.ld
similarity index 100%
rename from hw/bsp/gr_citrus/r5f5631fd.ld
rename to hw/bsp/rx63n/boards/gr_citrus/r5f5631fd.ld
diff --git a/hw/bsp/rx63n/family.mk b/hw/bsp/rx63n/family.mk
new file mode 100644
index 00000000..d3c743ed
--- /dev/null
+++ b/hw/bsp/rx63n/family.mk
@@ -0,0 +1 @@
+include $(TOP)/$(BOARD_PATH)/board.mk
\ No newline at end of file

From 94d29d8578cd0baf2c629e0f9455cebd7c033896 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Mar 2021 00:06:06 +0700
Subject: [PATCH 51/72] add build-renesas for rx63n

---
 .github/workflows/build.yml | 67 +++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 0f2b9ea3..3e50980c 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -267,6 +267,73 @@ jobs:
         asset_name: ${{ matrix.family }}-tinyusb-${{ github.event.release.tag_name }}-examples.zip
         asset_content_type: application/zip
 
+  # ---------------------------------------
+  # Build Renesas family
+  # ---------------------------------------
+  build-renesas:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+        # Alphabetical order
+        - 'rx63n'
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v2
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v2
+
+    - name: Checkout common submodules in lib
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
+
+    - name: Set Toolchain URL
+      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run
+
+    - name: Cache Toolchain
+      uses: actions/cache@v2
+      id: cache-toolchain
+      with:
+        path: ~/cache/
+        key: ${{ runner.os }}-21-03-30-${{ env.TOOLCHAIN_URL }}
+
+    - name: Install Toolchain
+      if: steps.cache-toolchain.outputs.cache-hit != 'true'
+      run: |
+        mkdir -p ~/cache/toolchain/gnurx
+        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.run
+        chmod +x toolchain.run
+        ./toolchain.run -p ~/cache/toolchain/gnurx -y
+
+    - name: Set Toolchain Path
+      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+
+    - name: Build
+      run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - uses: actions/upload-artifact@v2
+      with:
+        name: ${{ matrix.family }}-tinyusb-examples
+        path: _bin/
+
+    - name: Create Release Asset
+      if: ${{ github.event_name == 'release' }}
+      run: |
+        cd _bin/
+        zip -r ../${{ matrix.family }}-tinyusb-${{ github.event.release.tag_name }}-examples.zip *
+
+    - name: Upload Release Asset
+      uses: actions/upload-release-asset@v1
+      env:
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+      if: ${{ github.event_name == 'release' }}
+      with:
+        upload_url: ${{ github.event.release.upload_url }}
+        asset_path: ${{ matrix.family }}-tinyusb-${{ github.event.release.tag_name }}-examples.zip
+        asset_name: ${{ matrix.family }}-tinyusb-${{ github.event.release.tag_name }}-examples.zip
+        asset_content_type: application/zip
+
   # ---------------------------------------
   # Build all no-family (opharned) boards
   # ---------------------------------------

From 2e4657d11178ba590131fb35c10aa1fe491d99a8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Mar 2021 01:09:17 +0700
Subject: [PATCH 52/72] change suffix to _asm to be more explicit

---
 examples/rules.mk | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 6f494f4b..a19cd678 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -52,8 +52,8 @@ SRC_S := $(SRC_S:.S=.s)
 
 # Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
 # assembly file should be placed first in linking order
-# '_s' suffix is added to object of assembly file
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_s.o))
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
 
 # Verbose mode
@@ -112,13 +112,13 @@ $(BUILD)/obj/%.o: %.c
 
 # ASM sources lower case .s
 vpath %.s . $(TOP)
-$(BUILD)/obj/%_s.o: %.s
+$(BUILD)/obj/%_asm.o: %.s
 	@echo AS $(notdir $@)
 	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
 
 # ASM sources upper case .S
 vpath %.S . $(TOP)
-$(BUILD)/obj/%_s.o: %.S
+$(BUILD)/obj/%_asm.o: %.S
 	@echo AS $(notdir $@)
 	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
 

From d135825e9ca36bcf50b3476e5dfdc1f74ae1c101 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Mar 2021 21:12:56 +0700
Subject: [PATCH 53/72] add hid keys from 0x6B to 0xA4

---
 src/class/hid/hid.h | 283 ++++++++++++++++++++++++++------------------
 1 file changed, 171 insertions(+), 112 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index a7db087a..79b4f48b 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -303,118 +303,177 @@ typedef enum
 //--------------------------------------------------------------------+
 // HID KEYCODE
 //--------------------------------------------------------------------+
-#define HID_KEY_NONE               0x00
-#define HID_KEY_A                  0x04
-#define HID_KEY_B                  0x05
-#define HID_KEY_C                  0x06
-#define HID_KEY_D                  0x07
-#define HID_KEY_E                  0x08
-#define HID_KEY_F                  0x09
-#define HID_KEY_G                  0x0A
-#define HID_KEY_H                  0x0B
-#define HID_KEY_I                  0x0C
-#define HID_KEY_J                  0x0D
-#define HID_KEY_K                  0x0E
-#define HID_KEY_L                  0x0F
-#define HID_KEY_M                  0x10
-#define HID_KEY_N                  0x11
-#define HID_KEY_O                  0x12
-#define HID_KEY_P                  0x13
-#define HID_KEY_Q                  0x14
-#define HID_KEY_R                  0x15
-#define HID_KEY_S                  0x16
-#define HID_KEY_T                  0x17
-#define HID_KEY_U                  0x18
-#define HID_KEY_V                  0x19
-#define HID_KEY_W                  0x1A
-#define HID_KEY_X                  0x1B
-#define HID_KEY_Y                  0x1C
-#define HID_KEY_Z                  0x1D
-#define HID_KEY_1                  0x1E
-#define HID_KEY_2                  0x1F
-#define HID_KEY_3                  0x20
-#define HID_KEY_4                  0x21
-#define HID_KEY_5                  0x22
-#define HID_KEY_6                  0x23
-#define HID_KEY_7                  0x24
-#define HID_KEY_8                  0x25
-#define HID_KEY_9                  0x26
-#define HID_KEY_0                  0x27
-#define HID_KEY_RETURN             0x28
-#define HID_KEY_ESCAPE             0x29
-#define HID_KEY_BACKSPACE          0x2A
-#define HID_KEY_TAB                0x2B
-#define HID_KEY_SPACE              0x2C
-#define HID_KEY_MINUS              0x2D
-#define HID_KEY_EQUAL              0x2E
-#define HID_KEY_BRACKET_LEFT       0x2F
-#define HID_KEY_BRACKET_RIGHT      0x30
-#define HID_KEY_BACKSLASH          0x31
-#define HID_KEY_EUROPE_1           0x32
-#define HID_KEY_SEMICOLON          0x33
-#define HID_KEY_APOSTROPHE         0x34
-#define HID_KEY_GRAVE              0x35
-#define HID_KEY_COMMA              0x36
-#define HID_KEY_PERIOD             0x37
-#define HID_KEY_SLASH              0x38
-#define HID_KEY_CAPS_LOCK          0x39
-#define HID_KEY_F1                 0x3A
-#define HID_KEY_F2                 0x3B
-#define HID_KEY_F3                 0x3C
-#define HID_KEY_F4                 0x3D
-#define HID_KEY_F5                 0x3E
-#define HID_KEY_F6                 0x3F
-#define HID_KEY_F7                 0x40
-#define HID_KEY_F8                 0x41
-#define HID_KEY_F9                 0x42
-#define HID_KEY_F10                0x43
-#define HID_KEY_F11                0x44
-#define HID_KEY_F12                0x45
-#define HID_KEY_PRINT_SCREEN       0x46
-#define HID_KEY_SCROLL_LOCK        0x47
-#define HID_KEY_PAUSE              0x48
-#define HID_KEY_INSERT             0x49
-#define HID_KEY_HOME               0x4A
-#define HID_KEY_PAGE_UP            0x4B
-#define HID_KEY_DELETE             0x4C
-#define HID_KEY_END                0x4D
-#define HID_KEY_PAGE_DOWN          0x4E
-#define HID_KEY_ARROW_RIGHT        0x4F
-#define HID_KEY_ARROW_LEFT         0x50
-#define HID_KEY_ARROW_DOWN         0x51
-#define HID_KEY_ARROW_UP           0x52
-#define HID_KEY_NUM_LOCK           0x53
-#define HID_KEY_KEYPAD_DIVIDE      0x54
-#define HID_KEY_KEYPAD_MULTIPLY    0x55
-#define HID_KEY_KEYPAD_SUBTRACT    0x56
-#define HID_KEY_KEYPAD_ADD         0x57
-#define HID_KEY_KEYPAD_ENTER       0x58
-#define HID_KEY_KEYPAD_1           0x59
-#define HID_KEY_KEYPAD_2           0x5A
-#define HID_KEY_KEYPAD_3           0x5B
-#define HID_KEY_KEYPAD_4           0x5C
-#define HID_KEY_KEYPAD_5           0x5D
-#define HID_KEY_KEYPAD_6           0x5E
-#define HID_KEY_KEYPAD_7           0x5F
-#define HID_KEY_KEYPAD_8           0x60
-#define HID_KEY_KEYPAD_9           0x61
-#define HID_KEY_KEYPAD_0           0x62
-#define HID_KEY_KEYPAD_DECIMAL     0x63
-#define HID_KEY_EUROPE_2           0x64
-#define HID_KEY_APPLICATION        0x65
-#define HID_KEY_POWER              0x66
-#define HID_KEY_KEYPAD_EQUAL       0x67
-#define HID_KEY_F13                0x68
-#define HID_KEY_F14                0x69
-#define HID_KEY_F15                0x6A
-#define HID_KEY_CONTROL_LEFT       0xE0
-#define HID_KEY_SHIFT_LEFT         0xE1
-#define HID_KEY_ALT_LEFT           0xE2
-#define HID_KEY_GUI_LEFT           0xE3
-#define HID_KEY_CONTROL_RIGHT      0xE4
-#define HID_KEY_SHIFT_RIGHT        0xE5
-#define HID_KEY_ALT_RIGHT          0xE6
-#define HID_KEY_GUI_RIGHT          0xE7
+#define HID_KEY_NONE                      0x00
+#define HID_KEY_A                         0x04
+#define HID_KEY_B                         0x05
+#define HID_KEY_C                         0x06
+#define HID_KEY_D                         0x07
+#define HID_KEY_E                         0x08
+#define HID_KEY_F                         0x09
+#define HID_KEY_G                         0x0A
+#define HID_KEY_H                         0x0B
+#define HID_KEY_I                         0x0C
+#define HID_KEY_J                         0x0D
+#define HID_KEY_K                         0x0E
+#define HID_KEY_L                         0x0F
+#define HID_KEY_M                         0x10
+#define HID_KEY_N                         0x11
+#define HID_KEY_O                         0x12
+#define HID_KEY_P                         0x13
+#define HID_KEY_Q                         0x14
+#define HID_KEY_R                         0x15
+#define HID_KEY_S                         0x16
+#define HID_KEY_T                         0x17
+#define HID_KEY_U                         0x18
+#define HID_KEY_V                         0x19
+#define HID_KEY_W                         0x1A
+#define HID_KEY_X                         0x1B
+#define HID_KEY_Y                         0x1C
+#define HID_KEY_Z                         0x1D
+#define HID_KEY_1                         0x1E
+#define HID_KEY_2                         0x1F
+#define HID_KEY_3                         0x20
+#define HID_KEY_4                         0x21
+#define HID_KEY_5                         0x22
+#define HID_KEY_6                         0x23
+#define HID_KEY_7                         0x24
+#define HID_KEY_8                         0x25
+#define HID_KEY_9                         0x26
+#define HID_KEY_0                         0x27
+#define HID_KEY_RETURN                    0x28
+#define HID_KEY_ESCAPE                    0x29
+#define HID_KEY_BACKSPACE                 0x2A
+#define HID_KEY_TAB                       0x2B
+#define HID_KEY_SPACE                     0x2C
+#define HID_KEY_MINUS                     0x2D
+#define HID_KEY_EQUAL                     0x2E
+#define HID_KEY_BRACKET_LEFT              0x2F
+#define HID_KEY_BRACKET_RIGHT             0x30
+#define HID_KEY_BACKSLASH                 0x31
+#define HID_KEY_EUROPE_1                  0x32
+#define HID_KEY_SEMICOLON                 0x33
+#define HID_KEY_APOSTROPHE                0x34
+#define HID_KEY_GRAVE                     0x35
+#define HID_KEY_COMMA                     0x36
+#define HID_KEY_PERIOD                    0x37
+#define HID_KEY_SLASH                     0x38
+#define HID_KEY_CAPS_LOCK                 0x39
+#define HID_KEY_F1                        0x3A
+#define HID_KEY_F2                        0x3B
+#define HID_KEY_F3                        0x3C
+#define HID_KEY_F4                        0x3D
+#define HID_KEY_F5                        0x3E
+#define HID_KEY_F6                        0x3F
+#define HID_KEY_F7                        0x40
+#define HID_KEY_F8                        0x41
+#define HID_KEY_F9                        0x42
+#define HID_KEY_F10                       0x43
+#define HID_KEY_F11                       0x44
+#define HID_KEY_F12                       0x45
+#define HID_KEY_PRINT_SCREEN              0x46
+#define HID_KEY_SCROLL_LOCK               0x47
+#define HID_KEY_PAUSE                     0x48
+#define HID_KEY_INSERT                    0x49
+#define HID_KEY_HOME                      0x4A
+#define HID_KEY_PAGE_UP                   0x4B
+#define HID_KEY_DELETE                    0x4C
+#define HID_KEY_END                       0x4D
+#define HID_KEY_PAGE_DOWN                 0x4E
+#define HID_KEY_ARROW_RIGHT               0x4F
+#define HID_KEY_ARROW_LEFT                0x50
+#define HID_KEY_ARROW_DOWN                0x51
+#define HID_KEY_ARROW_UP                  0x52
+#define HID_KEY_NUM_LOCK                  0x53
+#define HID_KEY_KEYPAD_DIVIDE             0x54
+#define HID_KEY_KEYPAD_MULTIPLY           0x55
+#define HID_KEY_KEYPAD_SUBTRACT           0x56
+#define HID_KEY_KEYPAD_ADD                0x57
+#define HID_KEY_KEYPAD_ENTER              0x58
+#define HID_KEY_KEYPAD_1                  0x59
+#define HID_KEY_KEYPAD_2                  0x5A
+#define HID_KEY_KEYPAD_3                  0x5B
+#define HID_KEY_KEYPAD_4                  0x5C
+#define HID_KEY_KEYPAD_5                  0x5D
+#define HID_KEY_KEYPAD_6                  0x5E
+#define HID_KEY_KEYPAD_7                  0x5F
+#define HID_KEY_KEYPAD_8                  0x60
+#define HID_KEY_KEYPAD_9                  0x61
+#define HID_KEY_KEYPAD_0                  0x62
+#define HID_KEY_KEYPAD_DECIMAL            0x63
+#define HID_KEY_EUROPE_2                  0x64
+#define HID_KEY_APPLICATION               0x65
+#define HID_KEY_POWER                     0x66
+#define HID_KEY_KEYPAD_EQUAL              0x67
+#define HID_KEY_F13                       0x68
+#define HID_KEY_F14                       0x69
+#define HID_KEY_F15                       0x6A
+#define HID_KEY_F16                       0x6B
+#define HID_KEY_F17                       0x6C
+#define HID_KEY_F18                       0x6D
+#define HID_KEY_F19                       0x6E
+#define HID_KEY_F20                       0x6F
+#define HID_KEY_F21                       0x70
+#define HID_KEY_F22                       0x71
+#define HID_KEY_F23                       0x72
+#define HID_KEY_F24                       0x73
+#define HID_KEY_EXECUTE                   0x74
+#define HID_KEY_HELP                      0x75
+#define HID_KEY_MENU                      0x76
+#define HID_KEY_SELECT                    0x77
+#define HID_KEY_STOP                      0x78
+#define HID_KEY_AGAIN                     0x79
+#define HID_KEY_UNDO                      0x7A
+#define HID_KEY_CUT                       0x7B
+#define HID_KEY_COPY                      0x7C
+#define HID_KEY_PASTE                     0x7D
+#define HID_KEY_FIND                      0x7E
+#define HID_KEY_MUTE                      0x7F
+#define HID_KEY_VOLUME_UP                 0x80
+#define HID_KEY_VOLUME_DOWN               0x81
+#define HID_KEY_LOCKING_CAPS_LOCK         0x82
+#define HID_KEY_LOCKING_NUM_LOCK          0x83
+#define HID_KEY_LOCKING_SCROLL_LOCK       0x84
+#define HID_KEY_KEYPAD_COMMA              0x85
+#define HID_KEY_KEYPAD_EQUAL_SIGN         0x86
+#define HID_KEY_KANJI1                    0x87
+#define HID_KEY_KANJI2                    0x88
+#define HID_KEY_KANJI3                    0x89
+#define HID_KEY_KANJI4                    0x8A
+#define HID_KEY_KANJI5                    0x8B
+#define HID_KEY_KANJI6                    0x8C
+#define HID_KEY_KANJI7                    0x8D
+#define HID_KEY_KANJI8                    0x8E
+#define HID_KEY_KANJI9                    0x8F
+#define HID_KEY_LANG1                     0x90
+#define HID_KEY_LANG2                     0x91
+#define HID_KEY_LANG3                     0x92
+#define HID_KEY_LANG4                     0x93
+#define HID_KEY_LANG5                     0x94
+#define HID_KEY_LANG6                     0x95
+#define HID_KEY_LANG7                     0x96
+#define HID_KEY_LANG8                     0x97
+#define HID_KEY_LANG9                     0x98
+#define HID_KEY_ALTERNATE_ERASE           0x99
+#define HID_KEY_SYSREQ_ATTENTION          0x9A
+#define HID_KEY_CANCEL                    0x9B
+#define HID_KEY_CLEAR                     0x9C
+#define HID_KEY_PRIOR                     0x9D
+#define HID_KEY_RETURN                    0x9E
+#define HID_KEY_SEPARATOR                 0x9F
+#define HID_KEY_OUT                       0xA0
+#define HID_KEY_OPER                      0xA1
+#define HID_KEY_CLEAR_AGAIN               0xA2
+#define HID_KEY_CRSEL_PROPS               0xA3
+#define HID_KEY_EXSEL                     0xA4
+// RESERVED					                      0xA5-DF
+#define HID_KEY_CONTROL_LEFT              0xE0
+#define HID_KEY_SHIFT_LEFT                0xE1
+#define HID_KEY_ALT_LEFT                  0xE2
+#define HID_KEY_GUI_LEFT                  0xE3
+#define HID_KEY_CONTROL_RIGHT             0xE4
+#define HID_KEY_SHIFT_RIGHT               0xE5
+#define HID_KEY_ALT_RIGHT                 0xE6
+#define HID_KEY_GUI_RIGHT                 0xE7
 
 
 //--------------------------------------------------------------------+

From 89a911ee43f2c7a17303b58739dc8b22cbd56294 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Mar 2021 21:26:35 +0700
Subject: [PATCH 54/72] correct hid key enter = 0x28, return = 0x9E

---
 src/class/hid/hid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 79b4f48b..351a4d60 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -340,7 +340,7 @@ typedef enum
 #define HID_KEY_8                         0x25
 #define HID_KEY_9                         0x26
 #define HID_KEY_0                         0x27
-#define HID_KEY_RETURN                    0x28
+#define HID_KEY_ENTER                     0x28
 #define HID_KEY_ESCAPE                    0x29
 #define HID_KEY_BACKSPACE                 0x2A
 #define HID_KEY_TAB                       0x2B

From c5aa661c892159b2eced9b2e3c1a4a1d8f92b1f6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Mar 2021 23:54:17 +0700
Subject: [PATCH 55/72] rename tud_midi_receive/send to
 tud_midi_packet_read/write

---
 src/class/midi/midi_device.c |  6 +++---
 src/class/midi/midi_device.h | 17 +++++++++--------
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 29019cc1..3772c475 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -127,7 +127,7 @@ uint32_t tud_midi_n_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t
 
   // Fill empty buffer
   if (midi->read_buffer_length == 0) {
-    if (!tud_midi_n_receive(itf, midi->read_buffer)) return 0;
+    if (!tud_midi_n_packet_read(itf, midi->read_buffer)) return 0;
 
     uint8_t code_index = midi->read_buffer[0] & 0x0f;
     // We always copy over the first byte.
@@ -166,7 +166,7 @@ void tud_midi_n_read_flush (uint8_t itf, uint8_t cable_num)
   _prep_out_transaction(p_midi);
 }
 
-bool tud_midi_n_receive (uint8_t itf, uint8_t packet[4])
+bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
 {
   midid_interface_t* p_midi = &_midid_itf[itf];
   uint32_t num_read = tu_fifo_read_n(&p_midi->rx_ff, packet, 4);
@@ -278,7 +278,7 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
   return i;
 }
 
-bool tud_midi_n_send (uint8_t itf, uint8_t const packet[4])
+bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
 {
   midid_interface_t* midi = &_midid_itf[itf];
   if (midi->itf_num == 0) {
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index 5e7df80a..f76554c7 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -68,8 +68,8 @@ uint32_t tud_midi_n_write      (uint8_t itf, uint8_t cable_num, uint8_t const* b
 static inline
 uint32_t tud_midi_n_write24    (uint8_t itf, uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3);
 
-bool tud_midi_n_receive        (uint8_t itf, uint8_t packet[4]);
-bool tud_midi_n_send           (uint8_t itf, uint8_t const packet[4]);
+bool tud_midi_n_packet_read    (uint8_t itf, uint8_t packet[4]);
+bool tud_midi_n_packet_write   (uint8_t itf, uint8_t const packet[4]);
 
 //--------------------------------------------------------------------+
 // Application API (Single Interface)
@@ -80,8 +80,9 @@ static inline uint32_t tud_midi_read       (void* buffer, uint32_t bufsize);
 static inline void     tud_midi_read_flush (void);
 static inline uint32_t tud_midi_write      (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 static inline uint32_t tud_midi_write24    (uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3);
-static inline bool     tud_midi_receive    (uint8_t packet[4]);
-static inline bool     tud_midi_send       (uint8_t const packet[4]);
+
+static inline bool     tud_midi_packet_read (uint8_t packet[4]);
+static inline bool     tud_midi_packet_write(uint8_t const packet[4]);
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
@@ -129,14 +130,14 @@ static inline uint32_t tud_midi_write24 (uint8_t cable_num, uint8_t b1, uint8_t
   return tud_midi_write(cable_num, msg, 3);
 }
 
-static inline bool tud_midi_receive (uint8_t packet[4])
+static inline bool tud_midi_packet_read (uint8_t packet[4])
 {
-  return tud_midi_n_receive(0, packet);
+  return tud_midi_n_packet_read(0, packet);
 }
 
-static inline bool tud_midi_send (uint8_t const packet[4])
+static inline bool tud_midi_packet_write (uint8_t const packet[4])
 {
-  return tud_midi_n_send(0, packet);
+  return tud_midi_n_packet_write(0, packet);
 }
 
 //--------------------------------------------------------------------+

From b05084e406b50c6378572974e47d7e2ec15f2045 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Mar 2021 23:56:55 +0700
Subject: [PATCH 56/72] remove tud_midi_read_flush()

---
 src/class/midi/midi_device.c | 8 --------
 src/class/midi/midi_device.h | 7 -------
 2 files changed, 15 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 3772c475..48e5a8e6 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -158,14 +158,6 @@ uint32_t tud_midi_n_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t
   return n;
 }
 
-void tud_midi_n_read_flush (uint8_t itf, uint8_t cable_num)
-{
-  (void) cable_num;
-  midid_interface_t* p_midi = &_midid_itf[itf];
-  tu_fifo_clear(&p_midi->rx_ff);
-  _prep_out_transaction(p_midi);
-}
-
 bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
 {
   midid_interface_t* p_midi = &_midid_itf[itf];
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index f76554c7..1060fd77 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -62,7 +62,6 @@
 bool     tud_midi_n_mounted    (uint8_t itf);
 uint32_t tud_midi_n_available  (uint8_t itf, uint8_t cable_num);
 uint32_t tud_midi_n_read       (uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize);
-void     tud_midi_n_read_flush (uint8_t itf, uint8_t cable_num);
 uint32_t tud_midi_n_write      (uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 
 static inline
@@ -77,7 +76,6 @@ bool tud_midi_n_packet_write   (uint8_t itf, uint8_t const packet[4]);
 static inline bool     tud_midi_mounted    (void);
 static inline uint32_t tud_midi_available  (void);
 static inline uint32_t tud_midi_read       (void* buffer, uint32_t bufsize);
-static inline void     tud_midi_read_flush (void);
 static inline uint32_t tud_midi_write      (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 static inline uint32_t tud_midi_write24    (uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3);
 
@@ -114,11 +112,6 @@ static inline uint32_t tud_midi_read (void* buffer, uint32_t bufsize)
   return tud_midi_n_read(0, 0, buffer, bufsize);
 }
 
-static inline void tud_midi_read_flush (void)
-{
-  tud_midi_n_read_flush(0, 0);
-}
-
 static inline uint32_t tud_midi_write (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
 {
   return tud_midi_n_write(0, cable_num, buffer, bufsize);

From 949ff791e0222d9d89fe54b7cab036125997b66e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 31 Mar 2021 00:34:09 +0700
Subject: [PATCH 57/72] code format

---
 src/class/midi/midi_device.c | 133 ++++++++++++++++++++---------------
 1 file changed, 78 insertions(+), 55 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 48e5a8e6..1ff81c39 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -200,67 +200,90 @@ static uint32_t write_flush(midid_interface_t* midi)
 uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
 {
   midid_interface_t* midi = &_midid_itf[itf];
-  if (midi->itf_num == 0) {
-    return 0;
-  }
+  TU_VERIFY(midi->itf_num, 0);
 
   uint32_t i = 0;
-  while (i < bufsize) {
+  while ( i < bufsize )
+  {
     uint8_t data = buffer[i];
-    if (midi->write_buffer_length == 0) {
-        uint8_t msg = data >> 4;
-        midi->write_buffer[1] = data;
+    if ( midi->write_buffer_length == 0 )
+    {
+      uint8_t msg = data >> 4;
+      midi->write_buffer[1] = data;
+      midi->write_buffer_length = 2;
+      // Check to see if we're still in a SysEx transmit.
+      if ( midi->write_buffer[0] == 0x4 )
+      {
+        if ( data == 0xf7 )
+        {
+          midi->write_buffer[0] = 0x5;
+          midi->write_target_length = 2;
+        }
+        else
+        {
+          midi->write_target_length = 4;
+        }
+      }
+      else if ( (msg >= 0x8 && msg <= 0xB) || msg == 0xE )
+      {
+        midi->write_buffer[0] = cable_num << 4 | msg;
+        midi->write_target_length = 4;
+      }
+      else if ( msg == 0xf )
+      {
+        if ( data == 0xf0 )
+        {
+          midi->write_buffer[0] = 0x4;
+          midi->write_target_length = 4;
+        }
+        else if ( data == 0xf1 || data == 0xf3 )
+        {
+          midi->write_buffer[0] = 0x2;
+          midi->write_target_length = 3;
+        }
+        else if ( data == 0xf2 )
+        {
+          midi->write_buffer[0] = 0x3;
+          midi->write_target_length = 4;
+        }
+        else
+        {
+          midi->write_buffer[0] = 0x5;
+          midi->write_target_length = 2;
+        }
+      }
+      else
+      {
+        // Pack individual bytes if we don't support packing them into words.
+        midi->write_buffer[0] = cable_num << 4 | 0xf;
+        midi->write_buffer[2] = 0;
+        midi->write_buffer[3] = 0;
         midi->write_buffer_length = 2;
-        // Check to see if we're still in a SysEx transmit.
-        if (midi->write_buffer[0] == 0x4) {
-            if (data == 0xf7) {
-                midi->write_buffer[0] = 0x5;
-                midi->write_target_length = 2;
-            } else {
-                midi->write_target_length = 4;
-            }
-        } else if ((msg >= 0x8 && msg <= 0xB) || msg == 0xE) {
-            midi->write_buffer[0] = cable_num << 4 | msg;
-            midi->write_target_length = 4;
-        } else if (msg == 0xf) {
-            if (data == 0xf0) {
-                midi->write_buffer[0] = 0x4;
-                midi->write_target_length = 4;
-            } else if (data == 0xf1 || data == 0xf3) {
-                midi->write_buffer[0] = 0x2;
-                midi->write_target_length = 3;
-            } else if (data == 0xf2) {
-                midi->write_buffer[0] = 0x3;
-                midi->write_target_length = 4;
-            } else {
-                midi->write_buffer[0] = 0x5;
-                midi->write_target_length = 2;
-            }
-        } else {
-            // Pack individual bytes if we don't support packing them into words.
-            midi->write_buffer[0] = cable_num << 4 | 0xf;
-            midi->write_buffer[2] = 0;
-            midi->write_buffer[3] = 0;
-            midi->write_buffer_length = 2;
-            midi->write_target_length = 2;
-        }
-    } else {
-        midi->write_buffer[midi->write_buffer_length] = data;
-        midi->write_buffer_length += 1;
-        // See if this byte ends a SysEx.
-        if (midi->write_buffer[0] == 0x4 && data == 0xf7) {
-            midi->write_buffer[0] = 0x4 + (midi->write_buffer_length - 1);
-            midi->write_target_length = midi->write_buffer_length;
-        }
+        midi->write_target_length = 2;
+      }
+    }
+    else
+    {
+      TU_ASSERT(midi->write_buffer_length < 4, 0);
+      midi->write_buffer[midi->write_buffer_length] = data;
+      midi->write_buffer_length += 1;
+      // See if this byte ends a SysEx.
+      if ( midi->write_buffer[0] == 0x4 && data == 0xf7 )
+      {
+        midi->write_buffer[0] = 0x4 + (midi->write_buffer_length - 1);
+        midi->write_target_length = midi->write_buffer_length;
+      }
     }
 
-    if (midi->write_buffer_length == midi->write_target_length) {
-        uint16_t written = tu_fifo_write_n(&midi->tx_ff, midi->write_buffer, 4);
-        if (written < 4) {
-            TU_ASSERT( written == 0 );
-            break;
-        }
-        midi->write_buffer_length = 0;
+    if ( midi->write_buffer_length == midi->write_target_length )
+    {
+      uint16_t written = tu_fifo_write_n(&midi->tx_ff, midi->write_buffer, 4);
+      if ( written < 4 )
+      {
+        TU_ASSERT(written == 0);
+        break;
+      }
+      midi->write_buffer_length = 0;
     }
     i++;
   }

From 74c8887c8eb22c7bc457dc7e4381061241d2fa84 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 31 Mar 2021 21:50:53 +0900
Subject: [PATCH 58/72] removed a submodule for Renesas

---
 .gitmodules    | 3 ---
 hw/mcu/renesas | 1 -
 2 files changed, 4 deletions(-)
 delete mode 160000 hw/mcu/renesas

diff --git a/.gitmodules b/.gitmodules
index e075e0c6..1a5ae2c5 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -116,6 +116,3 @@
 [submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
 	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
 	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
-[submodule "hw/mcu/renesas"]
-	path = hw/mcu/renesas
-	url = https://github.com/kkitayam/rx_device.git
diff --git a/hw/mcu/renesas b/hw/mcu/renesas
deleted file mode 160000
index 4a51dfe6..00000000
--- a/hw/mcu/renesas
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 4a51dfe6ecdf936d2d89f223f069e24a2d109207

From 25057022e3bb74097849e86c90f0eb4b35b90394 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 31 Mar 2021 21:53:15 +0900
Subject: [PATCH 59/72] add a submodule of Renesas RX family to
 `hw/mcu/renesas/rx`

---
 .gitmodules                            | 3 +++
 hw/bsp/rx63n/boards/gr_citrus/board.mk | 4 ++--
 hw/mcu/renesas/rx                      | 1 +
 3 files changed, 6 insertions(+), 2 deletions(-)
 create mode 160000 hw/mcu/renesas/rx

diff --git a/.gitmodules b/.gitmodules
index 1a5ae2c5..c0dd871f 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -116,3 +116,6 @@
 [submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
 	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
 	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
+[submodule "hw/mcu/renesas/rx"]
+	path = hw/mcu/renesas/rx
+	url = https://github.com/kkitayam/rx_device.git
diff --git a/hw/bsp/rx63n/boards/gr_citrus/board.mk b/hw/bsp/rx63n/boards/gr_citrus/board.mk
index e33f3b50..feab5b5e 100644
--- a/hw/bsp/rx63n/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx63n/boards/gr_citrus/board.mk
@@ -1,4 +1,4 @@
-DEPS_SUBMODULES += hw/mcu/renesas
+DEPS_SUBMODULES += hw/mcu/renesas/rx
 
 CFLAGS += \
   -nostartfiles \
@@ -32,7 +32,7 @@ CFLAGS += -nostdinc \
 LIBS += -loptc -loptm
 endif
 
-MCU_DIR = hw/mcu/renesas/rx63n
+MCU_DIR = hw/mcu/renesas/rx/rx63n
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
diff --git a/hw/mcu/renesas/rx b/hw/mcu/renesas/rx
new file mode 160000
index 00000000..4a51dfe6
--- /dev/null
+++ b/hw/mcu/renesas/rx
@@ -0,0 +1 @@
+Subproject commit 4a51dfe6ecdf936d2d89f223f069e24a2d109207

From ff2978d95fe80ec7abcabbc6c5a451f6b998dae2 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 31 Mar 2021 22:15:03 +0900
Subject: [PATCH 60/72] added comments for JLink connection work.

---
 hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c
index aadd4139..6697012a 100644
--- a/hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c
@@ -24,6 +24,38 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* How to connect JLink and GR-CITRUS
+ *
+ * GR-CITRUS needs to solder some pads to enable JTAG interface.
+ * - Short the following pads individually with solder.
+ *   - J4
+ *   - J5
+ * - Short EMLE pad and 3.3V(GR-CITRUS pin name) with a wire.
+ *
+ * The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2).
+ * 
+ * Connet the pins between GR-CITRUS and JLink as follows.
+ * 
+ * | JTAG Function | GR-CITRUS pin name| JLink pin No.| note     |
+ * |:-------------:|:-----------------:|:------------:|:--------:|
+ * | VTref         |   3.3V            |   1          |          |
+ * | TRST          |   5               |   3          |          |
+ * | GND           |   GND             |   4          |          |
+ * | TDI           |   3               |   5          |          |
+ * | TMS           |   2               |   7          |          |
+ * | TCK           |   14              |   9          | short J4 |
+ * | TDO           |   9               |  13          | short J5 |
+ * | nRES          |   RST             |  15          |          |
+ *
+ * JLink firmware needs to update to V6.96 or newer version to avoid
+ * [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
+ * regarding downloading.
+ *
+ * When using SEGGER RTT, `RX_NEWLIB=0` should be added to make command arguments.
+ * The option is used to change the C runtime library to `optlib` from `newlib`.
+ * RTT may not work with `newlib`.
+ */
+
 #include "../board.h"
 #include "iodefine.h"
 #include "interrupt_handlers.h"

From 1d8a79ef4f4f6603ea8102b08613e97e18ed7eb6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 31 Mar 2021 20:50:08 +0700
Subject: [PATCH 61/72] remove NVIC_SystemReset() in freertos examples

---
 examples/device/cdc_msc_freertos/src/main.c       | 4 +---
 examples/device/hid_composite_freertos/src/main.c | 4 +---
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index abb95f4f..ccff2e0f 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -97,10 +97,8 @@ int main(void)
   // skip starting scheduler (and return) for ESP32-S2
 #if CFG_TUSB_MCU != OPT_MCU_ESP32S2
   vTaskStartScheduler();
-#if CFG_TUSB_MCU != OPT_MCU_RX63X
-  NVIC_SystemReset();
-#endif
 #endif
+
   return 0;
 }
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 1b42cee4..37b4a0cf 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -98,10 +98,8 @@ int main(void)
   // skip starting scheduler (and return) for ESP32-S2
 #if CFG_TUSB_MCU != OPT_MCU_ESP32S2
   vTaskStartScheduler();
-#if CFG_TUSB_MCU != OPT_MCU_RX63X
-  NVIC_SystemReset();
-#endif
 #endif
+
   return 0;
 }
 

From 65a04f02b6cae39e87c350ffe4894918050dfe8d Mon Sep 17 00:00:00 2001
From: Rafael Silva <silvagracarafael@gmail.com>
Date: Tue, 23 Mar 2021 21:40:53 +0000
Subject: [PATCH 62/72] add sltb009a bsp

Signed-off-by: Rafael Silva <silvagracarafael@gmail.com>
---
 hw/bsp/sltb009a/board.mk   |  47 +++
 hw/bsp/sltb009a/sltb009a.c | 721 +++++++++++++++++++++++++++++++++++++
 2 files changed, 768 insertions(+)
 create mode 100644 hw/bsp/sltb009a/board.mk
 create mode 100644 hw/bsp/sltb009a/sltb009a.c

diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
new file mode 100644
index 00000000..e8a24d1b
--- /dev/null
+++ b/hw/bsp/sltb009a/board.mk
@@ -0,0 +1,47 @@
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -D__STARTUP_CLEAR_BSS \
+  -D__START=main \
+  -DEFM32GG12B810F1024GM64 \
+  -DCFG_TUSB_MCU=OPT_MCU_EFM32GG12 
+
+# mcu driver cause following warnings
+#CFLAGS += -Wno-error=unused-parameter
+
+SILABS_FAMILY = efm32gg12b
+SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(shell echo $(SILABS_FAMILY) | tr a-z A-Z)
+
+DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
+DEPS_SUBMODULES += lib/CMSIS_5
+
+# All source paths should be relative to the top level.
+LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld
+
+SRC_C += \
+  $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \
+  src/portable/silabs/efm32/dcd_efm32.c
+
+SRC_S += \
+  $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S
+
+INC += \
+  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+  $(TOP)/$(SILABS_CMSIS)/Include \
+  $(TOP)/hw/bsp/$(BOARD)
+
+# For TinyUSB port source
+VENDOR = silabs
+CHIP_FAMILY = efm32
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4
+
+# For flash-jlink target
+JLINK_DEVICE = EFM32GG12B810F1024
+
+flash: flash-jlink
diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c
new file mode 100644
index 00000000..b929adb1
--- /dev/null
+++ b/hw/bsp/sltb009a/sltb009a.c
@@ -0,0 +1,721 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Rafael Silva (@perigoso)
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+
+#include "em_device.h"
+
+/*--------------------------------------------------------------------*/
+/* MACRO TYPEDEF CONSTANT ENUM                                        */
+/*--------------------------------------------------------------------*/
+
+#define LED_PORT              0     // A
+#define LED_PIN_R             12    // 12
+#define LED_PIN_B             13    // 13
+#define LED_PIN_G             14    // 14
+#define LED_STATE_ON          0     // active-low
+
+#define BUTTON_PORT           3     // D
+#define BUTTON_PIN            5     // 5
+#define BUTTON_STATE_ACTIVE   0     // active-low
+
+/*--------------------------------------------------------------------*/
+/* Forward USB interrupt events to TinyUSB IRQ Handler                */
+/*--------------------------------------------------------------------*/
+
+void USB_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+/*--------------------------------------------------------------------*/
+/* Fault Handlers                                                     */
+/*--------------------------------------------------------------------*/
+
+void HardFault_Handler(void)
+{
+  asm("bkpt");
+}
+
+void MemManage_Handler(void)
+{
+  asm("bkpt");
+}
+
+void BusFault_Handler(void)
+{
+  asm("bkpt");
+}
+
+void UsageFault_Handler(void)
+{
+  asm("bkpt");
+}
+
+/*--------------------------------------------------------------------*/
+/* Startup                                                            */
+/*--------------------------------------------------------------------*/
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
+
+/*--------------------------------------------------------------------*/
+/* Initing Funcs                                                      */
+/*--------------------------------------------------------------------*/
+
+void emu_init(uint8_t immediate_switch)
+{
+  EMU->PWRCTRL = (immediate_switch ? EMU_PWRCTRL_IMMEDIATEPWRSWITCH : 0) | EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_ANASW_AVDD;
+}
+
+void emu_reg_init(float target_voltage)
+{
+    if(target_voltage < 2300.f || target_voltage >= 3800.f)
+        return;
+
+    uint8_t level = ((target_voltage - 2300.f) / 100.f);
+
+    EMU->R5VCTRL = EMU_R5VCTRL_INPUTMODE_AUTO;
+
+    EMU->R5VOUTLEVEL = level; /* Reg output to 3.3V*/
+}
+
+void emu_dcdc_init(float target_voltage, float max_ln_current, float max_lp_current, float max_reverse_current)
+{
+    if(target_voltage < 1800.f || target_voltage >= 3000.f)
+        return;
+
+    if(max_ln_current <= 0.f || max_ln_current > 200.f)
+        return;
+
+    if(max_lp_current <= 0.f || max_lp_current > 10000.f)
+        return;
+
+    if(max_reverse_current < 0.f || max_reverse_current > 160.f)
+        return;
+
+    // Low Power & Low Noise current limit
+    uint8_t lp_bias = 0;
+
+    if(max_lp_current < 75.f)
+        lp_bias = 0;
+    else if(max_lp_current < 500.f)
+        lp_bias = 1;
+    else if(max_lp_current < 2500.f)
+        lp_bias = 2;
+    else
+        lp_bias = 3;
+
+    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) | ((uint32_t)lp_bias << _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT);
+    EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; // Force CCM to prevent reverse current
+    EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; // Enable duty cycling of the bias for LP mode
+    EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) | 4; // Set RCO Band to 7MHz
+
+    uint8_t fet_count = 0;
+
+    if(max_ln_current < 20.f)
+        fet_count = 4;
+    else if(max_ln_current >= 20.f && max_ln_current < 40.f)
+        fet_count = 8;
+    else
+        fet_count = 16;
+
+    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~_EMU_DCDCMISCCTRL_NFETCNT_MASK) | ((uint32_t)(fet_count - 1) << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
+    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~_EMU_DCDCMISCCTRL_PFETCNT_MASK) | ((uint32_t)(fet_count - 1) << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT);
+
+    uint8_t ln_current_limit = (((max_ln_current + 40.f) * 1.5f) / (5.f * fet_count)) - 1;
+    uint8_t lp_current_limit = 1; // Recommended value
+
+    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) | ((uint32_t)ln_current_limit << _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT) | ((uint32_t)lp_current_limit << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT);
+
+    uint8_t z_det_limit = ((max_reverse_current + 40.f) * 1.5f) / (2.5f * fet_count);
+
+    EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) | ((uint32_t)z_det_limit << _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT);
+
+    EMU->DCDCCLIMCTRL |= EMU_DCDCCLIMCTRL_BYPLIMEN; // Enable bypass current limiter to prevent overcurrent when switching modes
+
+    // Output Voltage
+    if(target_voltage > 1800.f)
+    {
+        float max_vout = 3000.f;
+        float min_vout = 1800.f;
+        float diff_vout = max_vout - min_vout;
+
+        uint8_t ln_vref_high = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
+        uint8_t ln_vref_low = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
+
+        uint8_t ln_vref = ((target_voltage - min_vout) * (float)(ln_vref_high - ln_vref_low)) / diff_vout;
+        ln_vref += ln_vref_low;
+
+        EMU->DCDCLNVCTRL = (ln_vref << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) | EMU_DCDCLNVCTRL_LNATT;
+
+        uint8_t lp_vref_low = 0;
+        uint8_t lp_vref_high = 0;
+
+        switch(lp_bias)
+        {
+            case 0:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
+            }
+            break;
+            case 1:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
+            }
+            break;
+            case 2:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
+            }
+            break;
+            case 3:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
+            }
+            break;
+        }
+
+        uint8_t lp_vref = ((target_voltage - min_vout) * (float)(lp_vref_high - lp_vref_low)) / diff_vout;
+        lp_vref += lp_vref_low;
+
+        EMU->DCDCLPVCTRL = (lp_vref << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) | EMU_DCDCLPVCTRL_LPATT;
+    }
+    else
+    {
+        float max_vout = 1800.f;
+        float min_vout = 1200.f;
+        float diff_vout = max_vout - min_vout;
+
+        uint8_t ln_vref_high = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
+        uint8_t ln_vref_low = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
+
+        uint8_t ln_vref = ((target_voltage - min_vout) * (float)(ln_vref_high - ln_vref_low)) / diff_vout;
+        ln_vref += ln_vref_low;
+
+        EMU->DCDCLNVCTRL = ln_vref << _EMU_DCDCLNVCTRL_LNVREF_SHIFT;
+
+        uint8_t lp_vref_low = 0;
+        uint8_t lp_vref_high = 0;
+
+        switch(lp_bias)
+        {
+            case 0:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
+            }
+            break;
+            case 1:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
+            }
+            break;
+            case 2:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
+            }
+            break;
+            case 3:
+            {
+                lp_vref_high = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
+                lp_vref_low = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
+            }
+            break;
+        }
+
+        uint8_t lp_vref = ((target_voltage - min_vout) * (float)(lp_vref_high - lp_vref_low)) / diff_vout;
+        lp_vref += lp_vref_low;
+
+        EMU->DCDCLPVCTRL = lp_vref << _EMU_DCDCLPVCTRL_LPVREF_SHIFT;
+    }
+
+    EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | (((DEVINFO->DCDCLPCMPHYSSEL1 & (((uint32_t)0xFF) << (lp_bias * 8))) >> (lp_bias * 8)) << _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT);
+
+    while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); // Wait for configuration to write
+
+    // Calibration
+    //EMU->DCDCLNCOMPCTRL = 0x57204077; // Compensation for 1uF DCDC capacitor
+    EMU->DCDCLNCOMPCTRL = 0xB7102137; // Compensation for 4.7uF DCDC capacitor
+
+    // Enable DCDC converter
+    EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER | EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER | EMU_DCDCCTRL_DCDCMODE_LOWNOISE;
+
+    // Switch digital domain to DVDD
+    EMU->PWRCTRL = EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_ANASW_AVDD;
+}
+
+void cmu_hfxo_startup_calib(uint16_t ib_trim, uint16_t c_tune)
+{
+  if(CMU->STATUS & CMU_STATUS_HFXOENS)
+      return;
+
+  CMU->HFXOSTARTUPCTRL = (CMU->HFXOSTARTUPCTRL & ~(_CMU_HFXOSTARTUPCTRL_CTUNE_MASK | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)) | (((uint32_t)c_tune << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) & _CMU_HFXOSTARTUPCTRL_CTUNE_MASK) | (((uint32_t)ib_trim << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT) & _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK);
+}
+
+void cmu_hfxo_steady_calib(uint16_t ib_trim, uint16_t c_tune)
+{
+  if(CMU->STATUS & CMU_STATUS_HFXOENS)
+      return;
+
+  CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) | (((uint32_t)c_tune << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) & _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK) | (((uint32_t)ib_trim << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) & _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK);
+}
+
+void cmu_hfrco_calib(uint32_t calibration)
+{
+    if(CMU->STATUS & CMU_STATUS_DPLLENS)
+        return;
+
+    while(CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY);
+
+    CMU->HFRCOCTRL = calibration;
+
+    while(CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY);
+}
+
+void cmu_ushfrco_calib(uint8_t enable, uint32_t calibration)
+{
+    if(CMU->USBCRCTRL & CMU_USBCRCTRL_USBCREN)
+        return;
+
+    if(!enable)
+    {
+        CMU->OSCENCMD = CMU_OSCENCMD_USHFRCODIS;
+        while(CMU->STATUS & CMU_STATUS_USHFRCOENS);
+
+        return;
+    }
+
+    while(CMU->SYNCBUSY & CMU_SYNCBUSY_USHFRCOBSY);
+
+    CMU->USHFRCOCTRL = calibration | CMU_USHFRCOCTRL_FINETUNINGEN;
+
+    while(CMU->SYNCBUSY & CMU_SYNCBUSY_USHFRCOBSY);
+
+    if(enable && !(CMU->STATUS & CMU_STATUS_USHFRCOENS))
+    {
+        CMU->OSCENCMD = CMU_OSCENCMD_USHFRCOEN;
+
+        while(!(CMU->STATUS & CMU_STATUS_USHFRCORDY));
+    }
+}
+
+void cmu_auxhfrco_calib(uint8_t enable, uint32_t calibration)
+{
+    if(!enable)
+    {
+        CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS;
+        while(CMU->STATUS & CMU_STATUS_AUXHFRCOENS);
+
+        return;
+    }
+
+    while(CMU->SYNCBUSY & CMU_SYNCBUSY_AUXHFRCOBSY);
+
+    CMU->AUXHFRCOCTRL = calibration;
+
+    while(CMU->SYNCBUSY & CMU_SYNCBUSY_AUXHFRCOBSY);
+
+    if(enable && !(CMU->STATUS & CMU_STATUS_AUXHFRCOENS))
+    {
+        CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
+
+        while(!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY));
+    }
+}
+
+
+void cmu_init(void)
+{
+    // Change SDIO clock to HFXO if HFRCO selected and disable it
+    CMU->SDIOCTRL = CMU_SDIOCTRL_SDIOCLKDIS | CMU_SDIOCTRL_SDIOCLKSEL_HFXO;
+    while(CMU->STATUS & CMU_STATUS_SDIOCLKENS);
+
+    // Change QSPI clock to HFXO if HFRCO selected and disable it
+    CMU->QSPICTRL = CMU_QSPICTRL_QSPI0CLKDIS | CMU_QSPICTRL_QSPI0CLKSEL_HFXO;
+    while(CMU->STATUS & CMU_STATUS_QSPI0CLKENS);
+
+    // Disable DPLL if enabled
+    if(CMU->STATUS & CMU_STATUS_DPLLENS)
+    {
+        CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
+        while(CMU->STATUS & CMU_STATUS_DPLLENS);
+    }
+
+    // Disable HFXO if enabled
+    if(CMU->STATUS & CMU_STATUS_HFXOENS)
+    {
+        CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS;
+        while(CMU->STATUS & CMU_STATUS_HFXOENS);
+    }
+
+    // Setup HFXO
+    CMU->HFXOCTRL = CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD | CMU_HFXOCTRL_MODE_XTAL;
+    CMU->HFXOCTRL1 = CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT;
+    CMU->HFXOSTEADYSTATECTRL |= CMU_HFXOSTEADYSTATECTRL_PEAKMONEN;
+    CMU->HFXOTIMEOUTCTRL = (7 << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) | (8 << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) | (12 << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT);
+
+    // Enable HFXO and wait for it to be ready
+    CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN;
+    while(!(CMU->STATUS & CMU_STATUS_HFXORDY));
+
+    // Switch main clock to HFXO and wait for it to be selected
+    CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
+    while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFXO);
+
+    // Calibrate HFRCO for 72MHz and enable tunning by PLL
+    cmu_hfrco_calib((DEVINFO->HFRCOCAL16) | CMU_HFRCOCTRL_FINETUNINGEN);
+
+    // Setup the PLL
+    CMU->DPLLCTRL = CMU_DPLLCTRL_REFSEL_HFXO | CMU_DPLLCTRL_AUTORECOVER | CMU_DPLLCTRL_EDGESEL_RISE | CMU_DPLLCTRL_MODE_FREQLL;
+    // 72MHz = 50MHz (HFXO) * 1.44 (144/100)
+    CMU->DPLLCTRL1 = (143 << _CMU_DPLLCTRL1_N_SHIFT) | (99 << _CMU_DPLLCTRL1_M_SHIFT); // fHFRCO = fHFXO * (N + 1) / (M + 1)
+
+    // Enable the DPLL and wait for it to be ready
+    CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN;
+    while(!(CMU->STATUS & CMU_STATUS_DPLLRDY));
+
+    // Config peripherals for the new frequency (freq > 32MHz)
+    CMU->CTRL |= CMU_CTRL_WSHFLE;
+
+    // Set prescalers
+    CMU->HFPRESC = CMU_HFPRESC_HFCLKLEPRESC_DIV2 | CMU_HFPRESC_PRESC_NODIVISION;
+    CMU->HFBUSPRESC = 1 << _CMU_HFBUSPRESC_PRESC_SHIFT;
+    CMU->HFCOREPRESC = 0 << _CMU_HFCOREPRESC_PRESC_SHIFT;
+    CMU->HFPERPRESC = 1 << _CMU_HFPERPRESC_PRESC_SHIFT;
+    CMU->HFEXPPRESC = 0 << _CMU_HFEXPPRESC_PRESC_SHIFT;
+    CMU->HFPERPRESCB = 0 << _CMU_HFPERPRESCB_PRESC_SHIFT;
+    CMU->HFPERPRESCC = 1 << _CMU_HFPERPRESCC_PRESC_SHIFT;
+
+    // Enable clock to peripherals
+    CMU->CTRL |= CMU_CTRL_HFPERCLKEN;
+
+    // Switch main clock to HFRCO and wait for it to be selected
+    CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO;
+    while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFRCO);
+
+    // LFA Clock
+    CMU->LFACLKSEL = CMU_LFACLKSEL_LFA_LFRCO;
+
+    // LFB Clock
+    CMU->LFBCLKSEL = CMU_LFBCLKSEL_LFB_LFRCO;
+
+    // LFC Clock
+    CMU->LFCCLKSEL = CMU_LFCCLKSEL_LFC_LFRCO;
+
+    // LFE Clock
+    CMU->LFECLKSEL = CMU_LFECLKSEL_LFE_ULFRCO;
+}
+
+void systick_init(void)
+{
+    SysTick->LOAD = (72000000 / 1000) - 1;
+    SysTick->VAL = 0;
+    SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
+
+    SCB->SHP[11] = 7 << (8 - __NVIC_PRIO_BITS); // Set priority 3,1 (min)
+}
+
+void gpio_init(void)
+{
+    CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
+
+    // NC - Not Connected (not available in mcu package)
+    // NR - Not routed (no routing to pin on pcb, floating)
+    // NU - Not used (not currently in use)
+
+    // Port A
+    GPIO->P[0].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
+                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+    GPIO->P[0].MODEL  = GPIO_P_MODEL_MODE0_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE1_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE2_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE3_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE4_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE5_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE6_DISABLED          // NU
+                      | GPIO_P_MODEL_MODE7_DISABLED;         // NC
+    GPIO->P[0].MODEH  = GPIO_P_MODEH_MODE8_DISABLED          // GPIO - MIC_ENABLE
+                      | GPIO_P_MODEH_MODE9_DISABLED          // NC
+                      | GPIO_P_MODEH_MODE10_DISABLED         // NC
+                      | GPIO_P_MODEH_MODE11_DISABLED         // NC
+                      | GPIO_P_MODEH_MODE12_WIREDAND         // LED0R
+                      | GPIO_P_MODEH_MODE13_WIREDAND         // LED0B
+                      | GPIO_P_MODEH_MODE14_WIREDAND         // LED0G
+                      | GPIO_P_MODEH_MODE15_DISABLED;        // NU
+    GPIO->P[0].DOUT   = 0x7000; // Leds off By default
+    GPIO->P[0].OVTDIS = 0;
+
+    // Port B
+    GPIO->P[1].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
+                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+    GPIO->P[1].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE1_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE2_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE3_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE6_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE7_DISABLED;                // MAIN_LFXTAL_P
+    GPIO->P[1].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // MAIN_LFXTAL_N
+                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
+                      | GPIO_P_MODEH_MODE10_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE11_DISABLED                // PDM_DAT0 - MIC_DATA
+                      | GPIO_P_MODEH_MODE12_DISABLED                // PDM_CLK - MIC_CLOCK
+                      | GPIO_P_MODEH_MODE13_DISABLED                // MAIN_HFXTAL_P
+                      | GPIO_P_MODEH_MODE14_DISABLED                // MAIN_HFXTAL_N
+                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
+    GPIO->P[1].DOUT   = 0;
+    GPIO->P[1].OVTDIS = 0;
+
+    // Port C
+    GPIO->P[2].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
+                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (7 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+    GPIO->P[2].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE1_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE2_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE3_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE6_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE7_DISABLED;                // NC
+    GPIO->P[2].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // NC
+                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
+                      | GPIO_P_MODEH_MODE10_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE11_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE12_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE13_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE14_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
+    GPIO->P[2].DOUT   = 0;
+    GPIO->P[2].OVTDIS = 0;
+
+    // Port D
+    GPIO->P[3].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
+                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+    GPIO->P[3].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE1_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE2_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE3_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE5_INPUT                    // GPIO - BTN0
+                      | GPIO_P_MODEL_MODE6_WIREDAND                 // LED1R
+                      | GPIO_P_MODEL_MODE7_DISABLED;                // NU
+    GPIO->P[3].MODEH  = GPIO_P_MODEH_MODE8_INPUT                    // GPIO - BTN1
+                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
+                      | GPIO_P_MODEH_MODE10_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE11_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE12_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE13_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE14_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
+    GPIO->P[3].DOUT   = 0;
+    GPIO->P[3].OVTDIS = 0;
+
+    // Port E
+    GPIO->P[4].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
+                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+    GPIO->P[4].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE1_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE2_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE3_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE6_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE7_DISABLED;                // NU
+    GPIO->P[4].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // NU
+                      | GPIO_P_MODEH_MODE9_DISABLED                 // NU
+                      | GPIO_P_MODEH_MODE10_DISABLED                // NU
+                      | GPIO_P_MODEH_MODE11_DISABLED                // NU
+                      | GPIO_P_MODEH_MODE12_WIREDAND                // LED1B
+                      | GPIO_P_MODEH_MODE13_DISABLED                // NU
+                      | GPIO_P_MODEH_MODE14_DISABLED                // NU
+                      | GPIO_P_MODEH_MODE15_DISABLED;               // NU
+    GPIO->P[4].DOUT   = 0;
+    GPIO->P[4].OVTDIS = 0;
+
+    // Port F
+    GPIO->P[5].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
+                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+    GPIO->P[5].MODEL  = GPIO_P_MODEL_MODE0_PUSHPULL                 // SWCLK
+                      | GPIO_P_MODEL_MODE1_PUSHPULL                 // SWDIO
+                      | GPIO_P_MODEL_MODE2_PUSHPULL                 // SWO
+                      | GPIO_P_MODEL_MODE3_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE4_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
+                      | GPIO_P_MODEL_MODE6_DISABLED                 // NC
+                      | GPIO_P_MODEL_MODE7_DISABLED;                // NC
+    GPIO->P[5].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // NC
+                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
+                      | GPIO_P_MODEH_MODE10_DISABLED                // USB N
+                      | GPIO_P_MODEH_MODE11_DISABLED                // USB P
+                      | GPIO_P_MODEH_MODE12_WIREDAND                // LED1G
+                      | GPIO_P_MODEH_MODE13_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE14_DISABLED                // NC
+                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
+    GPIO->P[5].DOUT   = 0;
+
+    GPIO->P[5].OVTDIS = 0;
+
+    // Debugger Route
+    GPIO->ROUTEPEN &= ~(GPIO_ROUTEPEN_TDIPEN | GPIO_ROUTEPEN_TDOPEN);   // Disable JTAG
+    GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN;                             // Enable SWO
+    GPIO->ROUTELOC0 = GPIO_ROUTELOC0_SWVLOC_LOC0;                       // SWO on PF2
+
+    // External interrupts
+    GPIO->EXTIPSELL = GPIO_EXTIPSELL_EXTIPSEL0_PORTE            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL1_PORTB            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL2_PORTB            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL3_PORTB            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL4_PORTA            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL5_PORTA            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL6_PORTC            // NU
+                    | GPIO_EXTIPSELL_EXTIPSEL7_PORTC;           // NU
+    GPIO->EXTIPSELH = GPIO_EXTIPSELH_EXTIPSEL8_PORTA            // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL9_PORTE            // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL10_PORTF           // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL11_PORTA           // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL12_PORTA           // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL13_PORTE           // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL14_PORTF           // NU
+                    | GPIO_EXTIPSELH_EXTIPSEL15_PORTA;          // NU
+
+    GPIO->EXTIPINSELL = GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4       // NU
+                      | GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7;      // NU
+    GPIO->EXTIPINSELH = GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8       // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9       // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11     // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8      // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13     // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15     // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12     // NU
+                      | GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12;    // NU
+
+}
+
+/*--------------------------------------------------------------------*/
+/* Board Init                                                         */
+/*--------------------------------------------------------------------*/
+
+void board_init(void)
+{
+
+  emu_dcdc_init(1800.f, 50.f, 100.f, 0.f); // Init DC-DC converter (1.8 V, 50 mA active, 100 uA sleep, 0 mA reverse limit)
+  emu_init(0);
+  emu_reg_init(3300.f); // set output regulator to 3.3V
+
+  cmu_hfxo_startup_calib(0x200, 0x145); // Config HFXO Startup for 1280 uA, 36 pF (18 pF + 2 pF CLOAD)
+  cmu_hfxo_steady_calib(0x009, 0x145); // Config HFXO Steady for 12 uA, 36 pF (18 pF + 2 pF CLOAD)
+
+  cmu_init(); // Init Clock Management Unit
+
+  cmu_ushfrco_calib(1, DEVINFO->USHFRCOCAL13); // Enable and calibrate USHFRCO for 48 MHz
+  cmu_auxhfrco_calib(1, DEVINFO->AUXHFRCOCAL11); // Enable and calibrate AUXHFRCO for 32 MHz
+
+  CMU->USBCRCTRL = CMU_USBCRCTRL_USBCREN; // enable USB clock recovery
+  CMU->USBCTRL = CMU_USBCTRL_USBCLKSEL_USHFRCO | CMU_USBCTRL_USBCLKEN;  // select USHFRCO as USB Phy clock source and enable it
+
+  CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_USB;  // enable USB peripheral clock
+
+  systick_init(); // Init system tick
+
+  gpio_init(); // Init IOs
+
+}
+
+/*--------------------------------------------------------------------*/
+/* Board porting API                                                  */
+/*--------------------------------------------------------------------*/
+
+void board_led_write(bool state)
+{
+  // Combine red and blue for pink Because it looks good :)
+  GPIO->P[LED_PORT].DOUT = (GPIO->P[LED_PORT].DOUT & ~((1 << LED_PIN_R) | (1 << LED_PIN_B))) | (state << LED_PIN_R) | (state << LED_PIN_B);
+}
+
+uint32_t board_button_read(void)
+{
+  return !!(GPIO->P[BUTTON_PORT].DIN & (1 << BUTTON_PIN));
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(char *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */

From 735e0dff20e89387f07875aa945636abe094528b Mon Sep 17 00:00:00 2001
From: Rafael Silva <silvagracarafael@gmail.com>
Date: Wed, 31 Mar 2021 22:37:15 +0100
Subject: [PATCH 63/72] skip freertos example for efm32gg12

Signed-off-by: Rafael Silva <silvagracarafael@gmail.com>
---
 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12       | 0
 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 | 0
 2 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 b/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12
new file mode 100644
index 00000000..e69de29b
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 b/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12
new file mode 100644
index 00000000..e69de29b

From 080b14b292251e46b43aac9e1cf7807dc2d3eb2c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 13:26:55 +0700
Subject: [PATCH 64/72] fix midi tx fifo overflow cause data corruption

rename
---
 .../device/dynamic_configuration/src/main.c   |   2 +-
 examples/device/midi_test/src/main.c          |   8 +-
 examples/make.mk                              |   2 +-
 src/class/midi/midi.h                         |  45 ++++++++
 src/class/midi/midi_device.c                  | 103 +++++++++++-------
 src/class/midi/midi_device.h                  |  16 ++-
 6 files changed, 127 insertions(+), 49 deletions(-)

diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index acee295f..ce1f752d 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -172,7 +172,7 @@ void midi_task(void)
   // regardless of these being used or not. Therefore incoming traffic should be read
   // (possibly just discarded) to avoid the sender blocking in IO
   uint8_t packet[4];
-  while(tud_midi_available()) tud_midi_receive(packet);
+  while( tud_midi_available() ) tud_midi_packet_read(packet);
 
   // send note every 1000 ms
   if (board_millis() - start_ms < 286) return; // not enough time
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 858a096b..af10350d 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -132,7 +132,7 @@ void midi_task(void)
   // regardless of these being used or not. Therefore incoming traffic should be read
   // (possibly just discarded) to avoid the sender blocking in IO
   uint8_t packet[4];
-  while(tud_midi_available()) tud_midi_receive(packet);
+  while ( tud_midi_available() ) tud_midi_packet_read(packet);
 
   // send note every 1000 ms
   if (board_millis() - start_ms < 286) return; // not enough time
@@ -146,10 +146,12 @@ void midi_task(void)
   if (previous < 0) previous = sizeof(note_sequence) - 1;
 
   // Send Note On for current position at full velocity (127) on channel 1.
-  tud_midi_write24(cable_num, 0x90 | channel, note_sequence[note_pos], 127);
+  uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 };
+  tud_midi_write(cable_num, note_on, 3);
 
   // Send Note Off for previous note.
-  tud_midi_write24(cable_num, 0x80 | channel, note_sequence[previous], 0);
+  uint8_t note_off[3] = { 0x80 | channel, note_sequence[previous], 0};
+  tud_midi_write(cable_num, note_off, 3);
 
   // Increment position
   note_pos++;
diff --git a/examples/make.mk b/examples/make.mk
index e04a2592..ffcb8ee5 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -103,7 +103,7 @@ CFLAGS += \
 
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
-  CFLAGS += -Og
+  CFLAGS += -O0
 else
   CFLAGS += -Os
 endif
diff --git a/src/class/midi/midi.h b/src/class/midi/midi.h
index f758b6e1..74dc4174 100644
--- a/src/class/midi/midi.h
+++ b/src/class/midi/midi.h
@@ -61,6 +61,51 @@ typedef enum
   MIDI_JACK_EXTERNAL = 0x02
 } midi_jack_type_t;
 
+typedef enum
+{
+  MIDI_CIN_MISC              = 0,
+  MIDI_CIN_CABLE_EVENT       = 1,
+  MIDI_CIN_SYSCOM_2BYTE      = 2, // 2 byte system common message e.g MTC, SongSelect
+  MIDI_CIN_SYSCOM_3BYTE      = 3, // 3 byte system common message e.g SPP
+  MIDI_CIN_SYSEX_START       = 4, // SysEx starts or continue
+  MIDI_CIN_SYSEX_END_1BYTE   = 5, // SysEx ends with 1 data, or 1 byte system common message
+  MIDI_CIN_SYSEX_END_2BYTE   = 6, // SysEx ends with 2 data
+  MIDI_CIN_SYSEX_END_3BYTE   = 7, // SysEx ends with 3 data
+  MIDI_CIN_NOTE_ON           = 8,
+  MIDI_CIN_NOTE_OFF          = 9,
+  MIDI_CIN_POLY_KEYPRESS     = 10,
+  MIDI_CIN_CONTROL_CHANGE    = 11,
+  MIDI_CIN_PROGRAM_CHANGE    = 12,
+  MIDI_CIN_CHANNEL_PRESSURE  = 13,
+  MIDI_CIN_PITCH_BEND_CHANGE = 14,
+  MIDI_CIN_1BYTE_DATA = 15
+} midi_code_index_number_t;
+
+// MIDI 1.0 status byte
+enum
+{
+  //------------- System Exclusive -------------//
+  MIDI_STATUS_SYSEX_START                    = 0xF0,
+  MIDI_STATUS_SYSEX_END                      = 0xF7,
+
+  //------------- System Common -------------//
+  MIDI_STATUS_SYSCOM_TIME_CODE_QUARTER_FRAME = 0xF1,
+  MIDI_STATUS_SYSCOM_SONG_POSITION_POINTER   = 0xF2,
+  MIDI_STATUS_SYSCOM_SONG_SELECT             = 0xF3,
+  // F4, F5 is undefined
+  MIDI_STATUS_SYSCOM_TUNE_REQUEST            = 0xF6,
+
+  //------------- System RealTime  -------------//
+  MIDI_STATUS_SYSREAL_TIMING_CLOCK           = 0xF8,
+  // 0xF9 is undefined
+  MIDI_STATUS_SYSREAL_START                  = 0xFA,
+  MIDI_STATUS_SYSREAL_CONTINUE               = 0xFB,
+  MIDI_STATUS_SYSREAL_STOP                   = 0xFC,
+  // 0xFD is undefined
+  MIDI_STATUS_SYSREAL_ACTIVE_SENSING         = 0xFE,
+  MIDI_STATUS_SYSREAL_SYSTEM_RESET           = 0xFF,
+};
+
 /// MIDI Interface Header Descriptor
 typedef struct TU_ATTR_PACKED
 {
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 1ff81c39..cba1dcca 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -38,6 +38,7 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+
 typedef struct
 {
   uint8_t itf_num;
@@ -126,16 +127,19 @@ uint32_t tud_midi_n_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t
   midid_interface_t* midi = &_midid_itf[itf];
 
   // Fill empty buffer
-  if (midi->read_buffer_length == 0) {
-    if (!tud_midi_n_packet_read(itf, midi->read_buffer)) return 0;
+  if ( midi->read_buffer_length == 0 )
+  {
+    if ( !tud_midi_n_packet_read(itf, midi->read_buffer) ) return 0;
 
     uint8_t code_index = midi->read_buffer[0] & 0x0f;
     // We always copy over the first byte.
     uint8_t count = 1;
     // Ignore subsequent bytes based on the code.
-    if (code_index != 0x5 && code_index != 0xf) {
+    if ( code_index != 0x5 && code_index != 0xf )
+    {
       count = 2;
-      if (code_index != 0x2 && code_index != 0x6 && code_index != 0xc && code_index != 0xd) {
+      if ( code_index != 0x2 && code_index != 0x6 && code_index != 0xc && code_index != 0xd )
+      {
         count = 3;
       }
     }
@@ -150,7 +154,8 @@ uint32_t tud_midi_n_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t
   memcpy(buffer, midi->read_buffer + 1 + midi->read_target_length, n);
   midi->read_target_length += n;
 
-  if (midi->read_target_length == midi->read_buffer_length) {
+  if ( midi->read_target_length == midi->read_buffer_length )
+  {
     midi->read_buffer_length = 0;
     midi->read_target_length = 0;
   }
@@ -166,10 +171,6 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
   return (num_read == 4);
 }
 
-void midi_rx_done_cb(midid_interface_t* midi, uint8_t const* buffer, uint32_t bufsize) {
-  tu_fifo_write_n(&midi->rx_ff, buffer, bufsize);
-}
-
 //--------------------------------------------------------------------+
 // WRITE API
 //--------------------------------------------------------------------+
@@ -185,7 +186,8 @@ static uint32_t write_flush(midid_interface_t* midi)
   TU_VERIFY( usbd_edpt_claim(rhport, midi->ep_in), 0 );
 
   uint16_t count = tu_fifo_read_n(&midi->tx_ff, midi->epin_buf, CFG_TUD_MIDI_EP_BUFSIZE);
-  if (count > 0)
+
+  if (count)
   {
     TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, midi->epin_buf, count), 0 );
     return count;
@@ -202,21 +204,26 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->itf_num, 0);
 
+  uint32_t written = 0;
   uint32_t i = 0;
   while ( i < bufsize )
   {
-    uint8_t data = buffer[i];
+    uint8_t const data = buffer[i];
+
     if ( midi->write_buffer_length == 0 )
     {
-      uint8_t msg = data >> 4;
+      // new packet
+
+      uint8_t const msg = data >> 4;
       midi->write_buffer[1] = data;
       midi->write_buffer_length = 2;
+
       // Check to see if we're still in a SysEx transmit.
-      if ( midi->write_buffer[0] == 0x4 )
+      if ( midi->write_buffer[0] == MIDI_CIN_SYSEX_START )
       {
-        if ( data == 0xf7 )
+        if ( data == MIDI_STATUS_SYSEX_END )
         {
-          midi->write_buffer[0] = 0x5;
+          midi->write_buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
           midi->write_target_length = 2;
         }
         else
@@ -226,29 +233,31 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
       }
       else if ( (msg >= 0x8 && msg <= 0xB) || msg == 0xE )
       {
-        midi->write_buffer[0] = cable_num << 4 | msg;
+        // Channel Voice Messages
+        midi->write_buffer[0] = (cable_num << 4) | msg;
         midi->write_target_length = 4;
       }
       else if ( msg == 0xf )
       {
-        if ( data == 0xf0 )
+        // System message
+        if ( data == MIDI_STATUS_SYSEX_START )
         {
-          midi->write_buffer[0] = 0x4;
+          midi->write_buffer[0] = MIDI_CIN_SYSEX_START;
           midi->write_target_length = 4;
         }
-        else if ( data == 0xf1 || data == 0xf3 )
+        else if ( data == MIDI_STATUS_SYSCOM_TIME_CODE_QUARTER_FRAME || data == MIDI_STATUS_SYSCOM_SONG_SELECT )
         {
-          midi->write_buffer[0] = 0x2;
+          midi->write_buffer[0] = MIDI_CIN_SYSCOM_2BYTE;
           midi->write_target_length = 3;
         }
-        else if ( data == 0xf2 )
+        else if ( data == MIDI_STATUS_SYSCOM_SONG_POSITION_POINTER )
         {
-          midi->write_buffer[0] = 0x3;
+          midi->write_buffer[0] = MIDI_CIN_SYSCOM_3BYTE;
           midi->write_target_length = 4;
         }
         else
         {
-          midi->write_buffer[0] = 0x5;
+          midi->write_buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
           midi->write_target_length = 2;
         }
       }
@@ -264,33 +273,44 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
     }
     else
     {
+      // On-going packet
+
       TU_ASSERT(midi->write_buffer_length < 4, 0);
       midi->write_buffer[midi->write_buffer_length] = data;
-      midi->write_buffer_length += 1;
+      midi->write_buffer_length++;
+
       // See if this byte ends a SysEx.
-      if ( midi->write_buffer[0] == 0x4 && data == 0xf7 )
+      if ( midi->write_buffer[0] == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
       {
-        midi->write_buffer[0] = 0x4 + (midi->write_buffer_length - 1);
+        midi->write_buffer[0] = MIDI_CIN_SYSEX_START + (midi->write_buffer_length - 1);
         midi->write_target_length = midi->write_buffer_length;
       }
     }
 
+    // Send out packet
     if ( midi->write_buffer_length == midi->write_target_length )
     {
-      uint16_t written = tu_fifo_write_n(&midi->tx_ff, midi->write_buffer, 4);
-      if ( written < 4 )
-      {
-        TU_ASSERT(written == 0);
-        break;
-      }
-      midi->write_buffer_length = 0;
+      // zeroes unused bytes
+      for(uint8_t idx = midi->write_target_length; idx < 4; idx++) midi->write_buffer[idx] = 0;
+
+      uint16_t const count = tu_fifo_write_n(&midi->tx_ff, midi->write_buffer, 4);
+
+      // reset buffer
+      midi->write_buffer_length = midi->write_target_length = 0;
+
+      // fifo overflow, here we assume FIFO is multiple of 4 and didn't check remaining before writing
+      if ( count != 4 ) break;
+
+      // updated written if succeeded
+      written = i;
     }
+
     i++;
   }
 
   write_flush(midi);
 
-  return i;
+  return written;
 }
 
 bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
@@ -300,8 +320,7 @@ bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
     return 0;
   }
 
-  if (tu_fifo_remaining(&midi->tx_ff) < 4)
-    return false;
+  if (tu_fifo_remaining(&midi->tx_ff) < 4) return false;
 
   tu_fifo_write_n(&midi->tx_ff, packet, 4);
   write_flush(midi);
@@ -347,9 +366,9 @@ void midid_reset(uint8_t rhport)
 uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
 {
   // 1st Interface is Audio Control v1
-  TU_VERIFY(TUSB_CLASS_AUDIO                      == desc_itf->bInterfaceClass    &&
-            AUDIO_SUBCLASS_CONTROL                == desc_itf->bInterfaceSubClass &&
-            AUDIO_FUNC_PROTOCOL_CODE_UNDEF        == desc_itf->bInterfaceProtocol, 0);
+  TU_VERIFY(TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
+            AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
+            AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol, 0);
 
   uint16_t drv_len = tu_desc_len(desc_itf);
   uint8_t const * p_desc = tu_desc_next(desc_itf);
@@ -365,9 +384,9 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
   TU_VERIFY(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
   tusb_desc_interface_t const * desc_midi = (tusb_desc_interface_t const *) p_desc;
 
-  TU_VERIFY(TUSB_CLASS_AUDIO                      == desc_midi->bInterfaceClass    &&
-            AUDIO_SUBCLASS_MIDI_STREAMING         == desc_midi->bInterfaceSubClass &&
-            AUDIO_FUNC_PROTOCOL_CODE_UNDEF        == desc_midi->bInterfaceProtocol, 0);
+  TU_VERIFY(TUSB_CLASS_AUDIO               == desc_midi->bInterfaceClass    &&
+            AUDIO_SUBCLASS_MIDI_STREAMING  == desc_midi->bInterfaceSubClass &&
+            AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_midi->bInterfaceProtocol, 0);
 
   // Find available interface
   midid_interface_t * p_midi = NULL;
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index 1060fd77..aaceaf62 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -59,16 +59,28 @@
 // Application API (Multiple Interfaces)
 // CFG_TUD_MIDI > 1
 //--------------------------------------------------------------------+
+
+// Check if midi interface is mounted
 bool     tud_midi_n_mounted    (uint8_t itf);
+
+// Get the number of bytes available for reading
 uint32_t tud_midi_n_available  (uint8_t itf, uint8_t cable_num);
+
+// Read byte stream (legacy)
 uint32_t tud_midi_n_read       (uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize);
+
+// Write byte Stream (legacy)
 uint32_t tud_midi_n_write      (uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 
+// Write good-old 3 bytes data, this use write packet
 static inline
 uint32_t tud_midi_n_write24    (uint8_t itf, uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3);
 
-bool tud_midi_n_packet_read    (uint8_t itf, uint8_t packet[4]);
-bool tud_midi_n_packet_write   (uint8_t itf, uint8_t const packet[4]);
+// Read event packet (4 bytes)
+bool     tud_midi_n_packet_read    (uint8_t itf, uint8_t packet[4]);
+
+// Write event packet (4 bytes)
+bool     tud_midi_n_packet_write   (uint8_t itf, uint8_t const packet[4]);
 
 //--------------------------------------------------------------------+
 // Application API (Single Interface)

From 6b04efd443c3299131135849b736a2f2ce5877ac Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 13:55:51 +0700
Subject: [PATCH 65/72] refactor midi stream read

---
 src/class/midi/midi_device.c | 51 +++++++++++++++++++++++++++---------
 1 file changed, 39 insertions(+), 12 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index cba1dcca..14748f18 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -39,6 +39,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+typedef struct
+{
+  uint8_t buffer[4];
+  uint8_t index;
+  uint8_t total;
+}midid_stream_t;
+
 typedef struct
 {
   uint8_t itf_num;
@@ -57,12 +64,15 @@ typedef struct
   osal_mutex_def_t tx_ff_mutex;
   #endif
 
+  // For Stream read()/write() API
   // Messages are always 4 bytes long, queue them for reading and writing so the
   // callers can use the Stream interface with single-byte read/write calls.
   uint8_t write_buffer[4];
   uint8_t write_buffer_length;
   uint8_t write_target_length;
 
+//  midid_stream_t stream_write;
+
   uint8_t read_buffer[4];
   uint8_t read_buffer_length;
   uint8_t read_target_length;
@@ -129,26 +139,41 @@ uint32_t tud_midi_n_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t
   // Fill empty buffer
   if ( midi->read_buffer_length == 0 )
   {
-    if ( !tud_midi_n_packet_read(itf, midi->read_buffer) ) return 0;
+    TU_VERIFY(tud_midi_n_packet_read(itf, midi->read_buffer), 0);
 
-    uint8_t code_index = midi->read_buffer[0] & 0x0f;
-    // We always copy over the first byte.
-    uint8_t count = 1;
-    // Ignore subsequent bytes based on the code.
-    if ( code_index != 0x5 && code_index != 0xf )
+    uint8_t const code_index = midi->read_buffer[0] & 0x0f;
+    uint8_t count;
+
+    // MIDI 1.0 Table 4-1: Code Index Number Classifications
+    switch(code_index)
     {
-      count = 2;
-      if ( code_index != 0x2 && code_index != 0x6 && code_index != 0xc && code_index != 0xd )
-      {
+      case MIDI_CIN_MISC:
+      case MIDI_CIN_CABLE_EVENT:
+        // These are reserved and unused, possibly issue somewhere, skip this packet
+        return 0;
+      break;
+
+      case MIDI_CIN_SYSEX_END_1BYTE:
+      case MIDI_CIN_1BYTE_DATA:
+        count = 1;
+      break;
+
+      case MIDI_CIN_SYSCOM_2BYTE     :
+      case MIDI_CIN_SYSEX_END_2BYTE  :
+      case MIDI_CIN_PROGRAM_CHANGE   :
+      case MIDI_CIN_CHANNEL_PRESSURE :
+        count = 2;
+      break;
+
+      default:
         count = 3;
-      }
+      break;
     }
 
     midi->read_buffer_length = count;
   }
 
-  uint32_t n = midi->read_buffer_length - midi->read_target_length;
-  if (bufsize < n) n = bufsize;
+  uint32_t n = tu_min32(midi->read_buffer_length - midi->read_target_length, bufsize);
 
   // Skip the header in the buffer
   memcpy(buffer, midi->read_buffer + 1 + midi->read_target_length, n);
@@ -204,6 +229,8 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->itf_num, 0);
 
+//  midid_stream_t* stream = &midi->stream_write;
+
   uint32_t written = 0;
   uint32_t i = 0;
   while ( i < bufsize )

From 08fe16840fcc39e4cb7c1f55fa56762427734753 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 14:26:55 +0700
Subject: [PATCH 66/72] refactor midi write into stream

---
 src/class/midi/midi_device.c | 77 +++++++++++++++++-------------------
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 14748f18..49bf2a27 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -67,11 +67,7 @@ typedef struct
   // For Stream read()/write() API
   // Messages are always 4 bytes long, queue them for reading and writing so the
   // callers can use the Stream interface with single-byte read/write calls.
-  uint8_t write_buffer[4];
-  uint8_t write_buffer_length;
-  uint8_t write_target_length;
-
-//  midid_stream_t stream_write;
+  midid_stream_t stream_write;
 
   uint8_t read_buffer[4];
   uint8_t read_buffer_length;
@@ -229,7 +225,7 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->itf_num, 0);
 
-//  midid_stream_t* stream = &midi->stream_write;
+  midid_stream_t* stream = &midi->stream_write;
 
   uint32_t written = 0;
   uint32_t i = 0;
@@ -237,93 +233,94 @@ uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer,
   {
     uint8_t const data = buffer[i];
 
-    if ( midi->write_buffer_length == 0 )
+    if ( stream->index == 0 )
     {
-      // new packet
+      // new event packet
 
       uint8_t const msg = data >> 4;
-      midi->write_buffer[1] = data;
-      midi->write_buffer_length = 2;
+
+      stream->index = 2;
+      stream->buffer[1] = data;
 
       // Check to see if we're still in a SysEx transmit.
-      if ( midi->write_buffer[0] == MIDI_CIN_SYSEX_START )
+      if ( stream->buffer[0] == MIDI_CIN_SYSEX_START )
       {
         if ( data == MIDI_STATUS_SYSEX_END )
         {
-          midi->write_buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
-          midi->write_target_length = 2;
+          stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
+          stream->total = 2;
         }
         else
         {
-          midi->write_target_length = 4;
+          stream->total = 4;
         }
       }
       else if ( (msg >= 0x8 && msg <= 0xB) || msg == 0xE )
       {
         // Channel Voice Messages
-        midi->write_buffer[0] = (cable_num << 4) | msg;
-        midi->write_target_length = 4;
+        stream->buffer[0] = (cable_num << 4) | msg;
+        stream->total = 4;
       }
       else if ( msg == 0xf )
       {
         // System message
         if ( data == MIDI_STATUS_SYSEX_START )
         {
-          midi->write_buffer[0] = MIDI_CIN_SYSEX_START;
-          midi->write_target_length = 4;
+          stream->buffer[0] = MIDI_CIN_SYSEX_START;
+          stream->total = 4;
         }
         else if ( data == MIDI_STATUS_SYSCOM_TIME_CODE_QUARTER_FRAME || data == MIDI_STATUS_SYSCOM_SONG_SELECT )
         {
-          midi->write_buffer[0] = MIDI_CIN_SYSCOM_2BYTE;
-          midi->write_target_length = 3;
+          stream->buffer[0] = MIDI_CIN_SYSCOM_2BYTE;
+          stream->total = 3;
         }
         else if ( data == MIDI_STATUS_SYSCOM_SONG_POSITION_POINTER )
         {
-          midi->write_buffer[0] = MIDI_CIN_SYSCOM_3BYTE;
-          midi->write_target_length = 4;
+          stream->buffer[0] = MIDI_CIN_SYSCOM_3BYTE;
+          stream->total = 4;
         }
         else
         {
-          midi->write_buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
-          midi->write_target_length = 2;
+          stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
+          stream->total = 2;
         }
       }
       else
       {
         // Pack individual bytes if we don't support packing them into words.
-        midi->write_buffer[0] = cable_num << 4 | 0xf;
-        midi->write_buffer[2] = 0;
-        midi->write_buffer[3] = 0;
-        midi->write_buffer_length = 2;
-        midi->write_target_length = 2;
+        stream->buffer[0] = cable_num << 4 | 0xf;
+        stream->buffer[2] = 0;
+        stream->buffer[3] = 0;
+        stream->index = 2;
+        stream->total = 2;
       }
     }
     else
     {
-      // On-going packet
+      // On-going (buffering) packet
 
-      TU_ASSERT(midi->write_buffer_length < 4, 0);
-      midi->write_buffer[midi->write_buffer_length] = data;
-      midi->write_buffer_length++;
+      TU_ASSERT(stream->index < 4, written);
+      stream->buffer[stream->index] = data;
+      stream->index++;
 
       // See if this byte ends a SysEx.
-      if ( midi->write_buffer[0] == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
+      if ( stream->buffer[0] == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
       {
-        midi->write_buffer[0] = MIDI_CIN_SYSEX_START + (midi->write_buffer_length - 1);
-        midi->write_target_length = midi->write_buffer_length;
+        stream->buffer[0] = MIDI_CIN_SYSEX_START + (stream->index - 1);
+        stream->total = stream->index;
       }
     }
 
     // Send out packet
-    if ( midi->write_buffer_length == midi->write_target_length )
+    if ( stream->index == stream->total )
     {
       // zeroes unused bytes
-      for(uint8_t idx = midi->write_target_length; idx < 4; idx++) midi->write_buffer[idx] = 0;
+      for(uint8_t idx = stream->total; idx < 4; idx++) stream->buffer[idx] = 0;
 
-      uint16_t const count = tu_fifo_write_n(&midi->tx_ff, midi->write_buffer, 4);
+      uint16_t const count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4);
 
       // reset buffer
-      midi->write_buffer_length = midi->write_target_length = 0;
+      stream->index = stream->total = 0;
 
       // fifo overflow, here we assume FIFO is multiple of 4 and didn't check remaining before writing
       if ( count != 4 ) break;

From 99b78e62f2172988ffa3835b7d6bcaaf455cef10 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 14:34:13 +0700
Subject: [PATCH 67/72] removed tud_midi_write24()

---
 src/class/midi/midi_device.h | 31 ++++++++++++++-----------------
 1 file changed, 14 insertions(+), 17 deletions(-)

diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index aaceaf62..c875748f 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -72,10 +72,6 @@ uint32_t tud_midi_n_read       (uint8_t itf, uint8_t cable_num, void* buffer, ui
 // Write byte Stream (legacy)
 uint32_t tud_midi_n_write      (uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 
-// Write good-old 3 bytes data, this use write packet
-static inline
-uint32_t tud_midi_n_write24    (uint8_t itf, uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3);
-
 // Read event packet (4 bytes)
 bool     tud_midi_n_packet_read    (uint8_t itf, uint8_t packet[4]);
 
@@ -87,13 +83,26 @@ bool     tud_midi_n_packet_write   (uint8_t itf, uint8_t const packet[4]);
 //--------------------------------------------------------------------+
 static inline bool     tud_midi_mounted    (void);
 static inline uint32_t tud_midi_available  (void);
+
 static inline uint32_t tud_midi_read       (void* buffer, uint32_t bufsize);
 static inline uint32_t tud_midi_write      (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
-static inline uint32_t tud_midi_write24    (uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3);
 
 static inline bool     tud_midi_packet_read (uint8_t packet[4]);
 static inline bool     tud_midi_packet_write(uint8_t const packet[4]);
 
+// TODO remove after 0.10.0 release
+TU_ATTR_DEPRECATED("tud_midi_send() is renamed to tud_midi_packet_write()")
+static inline bool tud_midi_send(uint8_t packet[4])
+{
+  return tud_midi_packet_write(packet);
+}
+
+TU_ATTR_DEPRECATED("tud_midi_receive() is renamed to tud_midi_packet_read()")
+static inline bool tud_midi_receive(uint8_t packet[4])
+{
+  return tud_midi_packet_read(packet);
+}
+
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
@@ -103,12 +112,6 @@ TU_ATTR_WEAK void tud_midi_rx_cb(uint8_t itf);
 // Inline Functions
 //--------------------------------------------------------------------+
 
-static inline uint32_t tud_midi_n_write24 (uint8_t itf, uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3)
-{
-  uint8_t msg[3] = { b1, b2, b3 };
-  return tud_midi_n_write(itf, cable_num, msg, 3);
-}
-
 static inline bool tud_midi_mounted (void)
 {
   return tud_midi_n_mounted(0);
@@ -129,12 +132,6 @@ static inline uint32_t tud_midi_write (uint8_t cable_num, uint8_t const* buffer,
   return tud_midi_n_write(0, cable_num, buffer, bufsize);
 }
 
-static inline uint32_t tud_midi_write24 (uint8_t cable_num, uint8_t b1, uint8_t b2, uint8_t b3)
-{
-  uint8_t msg[3] = { b1, b2, b3 };
-  return tud_midi_write(cable_num, msg, 3);
-}
-
 static inline bool tud_midi_packet_read (uint8_t packet[4])
 {
   return tud_midi_n_packet_read(0, packet);

From da59c4ad4434b64691aa7a93e03381702633964d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 14:43:38 +0700
Subject: [PATCH 68/72] rename midi write()/read() to stream_write()
 stream_read()

also add deprecated for warning and rename hint
---
 .../device/dynamic_configuration/src/main.c   |  6 +-
 examples/device/midi_test/src/main.c          |  4 +-
 src/class/midi/midi_device.c                  |  4 +-
 src/class/midi/midi_device.h                  | 55 ++++++++++++-------
 4 files changed, 43 insertions(+), 26 deletions(-)

diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index ce1f752d..4c10f55b 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -186,10 +186,12 @@ void midi_task(void)
   if (previous < 0) previous = sizeof(note_sequence) - 1;
 
   // Send Note On for current position at full velocity (127) on channel 1.
-  tud_midi_write24(cable_num, 0x90 | channel, note_sequence[note_pos], 127);
+  uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 };
+  tud_midi_stream_write(cable_num, note_on, 3);
 
   // Send Note Off for previous note.
-  tud_midi_write24(cable_num, 0x80 | channel, note_sequence[previous], 0);
+  uint8_t note_off[3] = { 0x80 | channel, note_sequence[previous], 0};
+  tud_midi_stream_write(cable_num, note_off, 3);
 
   // Increment position
   note_pos++;
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index af10350d..9e0e82a1 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -147,11 +147,11 @@ void midi_task(void)
 
   // Send Note On for current position at full velocity (127) on channel 1.
   uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 };
-  tud_midi_write(cable_num, note_on, 3);
+  tud_midi_stream_write(cable_num, note_on, 3);
 
   // Send Note Off for previous note.
   uint8_t note_off[3] = { 0x80 | channel, note_sequence[previous], 0};
-  tud_midi_write(cable_num, note_off, 3);
+  tud_midi_stream_write(cable_num, note_off, 3);
 
   // Increment position
   note_pos++;
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 49bf2a27..e76f01db 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -127,7 +127,7 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num)
   return tu_fifo_count(&_midid_itf[itf].rx_ff);
 }
 
-uint32_t tud_midi_n_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize)
+uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize)
 {
   (void) cable_num;
   midid_interface_t* midi = &_midid_itf[itf];
@@ -220,7 +220,7 @@ static uint32_t write_flush(midid_interface_t* midi)
   }
 }
 
-uint32_t tud_midi_n_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
+uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
 {
   midid_interface_t* midi = &_midid_itf[itf];
   TU_VERIFY(midi->itf_num, 0);
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index c875748f..67f03930 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -61,36 +61,51 @@
 //--------------------------------------------------------------------+
 
 // Check if midi interface is mounted
-bool     tud_midi_n_mounted    (uint8_t itf);
+bool     tud_midi_n_mounted      (uint8_t itf);
 
 // Get the number of bytes available for reading
-uint32_t tud_midi_n_available  (uint8_t itf, uint8_t cable_num);
+uint32_t tud_midi_n_available    (uint8_t itf, uint8_t cable_num);
 
-// Read byte stream (legacy)
-uint32_t tud_midi_n_read       (uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize);
+// Read byte stream              (legacy)
+uint32_t tud_midi_n_stream_read  (uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize);
 
-// Write byte Stream (legacy)
-uint32_t tud_midi_n_write      (uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
+// Write byte Stream             (legacy)
+uint32_t tud_midi_n_stream_write (uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 
-// Read event packet (4 bytes)
-bool     tud_midi_n_packet_read    (uint8_t itf, uint8_t packet[4]);
+// Read event packet             (4 bytes)
+bool     tud_midi_n_packet_read  (uint8_t itf, uint8_t packet[4]);
 
-// Write event packet (4 bytes)
-bool     tud_midi_n_packet_write   (uint8_t itf, uint8_t const packet[4]);
+// Write event packet            (4 bytes)
+bool     tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4]);
 
 //--------------------------------------------------------------------+
 // Application API (Single Interface)
 //--------------------------------------------------------------------+
-static inline bool     tud_midi_mounted    (void);
-static inline uint32_t tud_midi_available  (void);
+static inline bool     tud_midi_mounted      (void);
+static inline uint32_t tud_midi_available    (void);
 
-static inline uint32_t tud_midi_read       (void* buffer, uint32_t bufsize);
-static inline uint32_t tud_midi_write      (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
+static inline uint32_t tud_midi_stream_read  (void* buffer, uint32_t bufsize);
+static inline uint32_t tud_midi_stream_write (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize);
 
-static inline bool     tud_midi_packet_read (uint8_t packet[4]);
-static inline bool     tud_midi_packet_write(uint8_t const packet[4]);
+static inline bool     tud_midi_packet_read  (uint8_t packet[4]);
+static inline bool     tud_midi_packet_write (uint8_t const packet[4]);
 
+//------------- Deprecated API name  -------------//
 // TODO remove after 0.10.0 release
+
+TU_ATTR_DEPRECATED("tud_midi_read() is renamed to tud_midi_stream_read()")
+static inline uint32_t tud_midi_read (void* buffer, uint32_t bufsize)
+{
+  return tud_midi_stream_read(buffer, bufsize);
+}
+
+TU_ATTR_DEPRECATED("tud_midi_write() is renamed to tud_midi_stream_write()")
+static inline uint32_t tud_midi_write(uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
+{
+  return tud_midi_stream_write(cable_num, buffer, bufsize);
+}
+
+
 TU_ATTR_DEPRECATED("tud_midi_send() is renamed to tud_midi_packet_write()")
 static inline bool tud_midi_send(uint8_t packet[4])
 {
@@ -122,14 +137,14 @@ static inline uint32_t tud_midi_available (void)
   return tud_midi_n_available(0, 0);
 }
 
-static inline uint32_t tud_midi_read (void* buffer, uint32_t bufsize)
+static inline uint32_t tud_midi_stream_read (void* buffer, uint32_t bufsize)
 {
-  return tud_midi_n_read(0, 0, buffer, bufsize);
+  return tud_midi_n_stream_read(0, 0, buffer, bufsize);
 }
 
-static inline uint32_t tud_midi_write (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
+static inline uint32_t tud_midi_stream_write (uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
 {
-  return tud_midi_n_write(0, cable_num, buffer, bufsize);
+  return tud_midi_n_stream_write(0, cable_num, buffer, bufsize);
 }
 
 static inline bool tud_midi_packet_read (uint8_t packet[4])

From 350eb1127755f3ee0dd3dd186cc31e9492916a0c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 14:52:44 +0700
Subject: [PATCH 69/72] refactor midi read buffer to stream

---
 src/class/midi/midi_device.c | 39 +++++++++++++++++-------------------
 1 file changed, 18 insertions(+), 21 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index e76f01db..a4cc104a 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -68,10 +68,7 @@ typedef struct
   // Messages are always 4 bytes long, queue them for reading and writing so the
   // callers can use the Stream interface with single-byte read/write calls.
   midid_stream_t stream_write;
-
-  uint8_t read_buffer[4];
-  uint8_t read_buffer_length;
-  uint8_t read_target_length;
+  midid_stream_t stream_read;
 
   // Endpoint Transfer buffer
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE];
@@ -131,14 +128,16 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
 {
   (void) cable_num;
   midid_interface_t* midi = &_midid_itf[itf];
+  midid_stream_t* stream = &midi->stream_read;
 
-  // Fill empty buffer
-  if ( midi->read_buffer_length == 0 )
+  TU_VERIFY(bufsize, 0);
+
+  // Get new packet from fifo
+  if ( stream->total == 0 )
   {
-    TU_VERIFY(tud_midi_n_packet_read(itf, midi->read_buffer), 0);
+    TU_VERIFY(tud_midi_n_packet_read(itf, stream->buffer), 0);
 
-    uint8_t const code_index = midi->read_buffer[0] & 0x0f;
-    uint8_t count;
+    uint8_t const code_index = stream->buffer[0] & 0x0f;
 
     // MIDI 1.0 Table 4-1: Code Index Number Classifications
     switch(code_index)
@@ -151,34 +150,32 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
 
       case MIDI_CIN_SYSEX_END_1BYTE:
       case MIDI_CIN_1BYTE_DATA:
-        count = 1;
+        stream->total = 1;
       break;
 
       case MIDI_CIN_SYSCOM_2BYTE     :
       case MIDI_CIN_SYSEX_END_2BYTE  :
       case MIDI_CIN_PROGRAM_CHANGE   :
       case MIDI_CIN_CHANNEL_PRESSURE :
-        count = 2;
+        stream->total = 2;
       break;
 
       default:
-        count = 3;
+        stream->total = 3;
       break;
     }
-
-    midi->read_buffer_length = count;
   }
 
-  uint32_t n = tu_min32(midi->read_buffer_length - midi->read_target_length, bufsize);
+  uint32_t const n = tu_min32(stream->total - stream->index, bufsize);
 
-  // Skip the header in the buffer
-  memcpy(buffer, midi->read_buffer + 1 + midi->read_target_length, n);
-  midi->read_target_length += n;
+  // Skip the header (1st byte) in the buffer
+  memcpy(buffer, stream->buffer + 1 + stream->index, n);
+  stream->index += n;
 
-  if ( midi->read_target_length == midi->read_buffer_length )
+  if ( stream->total == stream->index )
   {
-    midi->read_buffer_length = 0;
-    midi->read_target_length = 0;
+    stream->index = 0;
+    stream->total = 0;
   }
 
   return n;

From 48bb96f5072a173189d9076c5c2b1f5066327bf6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 15:08:36 +0700
Subject: [PATCH 70/72] correct midi stream read behavior to read until user
 buffer is full or no more data from usb fifo

---
 src/class/midi/midi_device.c | 117 +++++++++++++++++++----------------
 1 file changed, 65 insertions(+), 52 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index a4cc104a..9ccbb733 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -52,6 +52,12 @@ typedef struct
   uint8_t ep_in;
   uint8_t ep_out;
 
+  // For Stream read()/write() API
+  // Messages are always 4 bytes long, queue them for reading and writing so the
+  // callers can use the Stream interface with single-byte read/write calls.
+  midid_stream_t stream_write;
+  midid_stream_t stream_read;
+
   /*------------- From this point, data is not cleared by bus reset -------------*/
   // FIFO
   tu_fifo_t rx_ff;
@@ -64,12 +70,6 @@ typedef struct
   osal_mutex_def_t tx_ff_mutex;
   #endif
 
-  // For Stream read()/write() API
-  // Messages are always 4 bytes long, queue them for reading and writing so the
-  // callers can use the Stream interface with single-byte read/write calls.
-  midid_stream_t stream_write;
-  midid_stream_t stream_read;
-
   // Endpoint Transfer buffer
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE];
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_MIDI_EP_BUFSIZE];
@@ -127,58 +127,71 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num)
 uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize)
 {
   (void) cable_num;
+  TU_VERIFY(bufsize, 0);
+
+  uint8_t* buf8 = (uint8_t*) buffer;
+
   midid_interface_t* midi = &_midid_itf[itf];
   midid_stream_t* stream = &midi->stream_read;
 
-  TU_VERIFY(bufsize, 0);
-
-  // Get new packet from fifo
-  if ( stream->total == 0 )
+  uint32_t total_read = 0;
+  while( bufsize )
   {
-    TU_VERIFY(tud_midi_n_packet_read(itf, stream->buffer), 0);
-
-    uint8_t const code_index = stream->buffer[0] & 0x0f;
-
-    // MIDI 1.0 Table 4-1: Code Index Number Classifications
-    switch(code_index)
+    // Get new packet from fifo, then set packet expected bytes
+    if ( stream->total == 0 )
     {
-      case MIDI_CIN_MISC:
-      case MIDI_CIN_CABLE_EVENT:
-        // These are reserved and unused, possibly issue somewhere, skip this packet
-        return 0;
-      break;
+      // return if there is no more data from fifo
+      if ( !tud_midi_n_packet_read(itf, stream->buffer) ) return total_read;
 
-      case MIDI_CIN_SYSEX_END_1BYTE:
-      case MIDI_CIN_1BYTE_DATA:
-        stream->total = 1;
-      break;
+      uint8_t const code_index = stream->buffer[0] & 0x0f;
 
-      case MIDI_CIN_SYSCOM_2BYTE     :
-      case MIDI_CIN_SYSEX_END_2BYTE  :
-      case MIDI_CIN_PROGRAM_CHANGE   :
-      case MIDI_CIN_CHANNEL_PRESSURE :
-        stream->total = 2;
-      break;
+      // MIDI 1.0 Table 4-1: Code Index Number Classifications
+      switch(code_index)
+      {
+        case MIDI_CIN_MISC:
+        case MIDI_CIN_CABLE_EVENT:
+          // These are reserved and unused, possibly issue somewhere, skip this packet
+          return 0;
+        break;
 
-      default:
-        stream->total = 3;
-      break;
+        case MIDI_CIN_SYSEX_END_1BYTE:
+        case MIDI_CIN_1BYTE_DATA:
+          stream->total = 1;
+        break;
+
+        case MIDI_CIN_SYSCOM_2BYTE     :
+        case MIDI_CIN_SYSEX_END_2BYTE  :
+        case MIDI_CIN_PROGRAM_CHANGE   :
+        case MIDI_CIN_CHANNEL_PRESSURE :
+          stream->total = 2;
+        break;
+
+        default:
+          stream->total = 3;
+        break;
+      }
+    }
+
+    // Copy data up to bufsize
+    uint32_t const count = tu_min32(stream->total - stream->index, bufsize);
+
+    // Skip the header (1st byte) in the buffer
+    memcpy(buf8, stream->buffer + 1 + stream->index, count);
+
+    total_read += count;
+    stream->index += count;
+    buf8 += count;
+    bufsize -= count;
+
+    // complete current event packet, reset stream
+    if ( stream->total == stream->index )
+    {
+      stream->index = 0;
+      stream->total = 0;
     }
   }
 
-  uint32_t const n = tu_min32(stream->total - stream->index, bufsize);
-
-  // Skip the header (1st byte) in the buffer
-  memcpy(buffer, stream->buffer + 1 + stream->index, n);
-  stream->index += n;
-
-  if ( stream->total == stream->index )
-  {
-    stream->index = 0;
-    stream->total = 0;
-  }
-
-  return n;
+  return total_read;
 }
 
 bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
@@ -224,7 +237,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
 
   midid_stream_t* stream = &midi->stream_write;
 
-  uint32_t written = 0;
+  uint32_t total_written = 0;
   uint32_t i = 0;
   while ( i < bufsize )
   {
@@ -296,7 +309,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
     {
       // On-going (buffering) packet
 
-      TU_ASSERT(stream->index < 4, written);
+      TU_ASSERT(stream->index < 4, total_written);
       stream->buffer[stream->index] = data;
       stream->index++;
 
@@ -316,14 +329,14 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
 
       uint16_t const count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4);
 
-      // reset buffer
+      // complete current event packet, reset stream
       stream->index = stream->total = 0;
 
       // fifo overflow, here we assume FIFO is multiple of 4 and didn't check remaining before writing
       if ( count != 4 ) break;
 
       // updated written if succeeded
-      written = i;
+      total_written = i;
     }
 
     i++;
@@ -331,7 +344,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
 
   write_flush(midi);
 
-  return written;
+  return total_written;
 }
 
 bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])

From 7582528067fcfc0a4fe6039cfcb00d2f4c702b53 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 15:21:44 +0700
Subject: [PATCH 71/72] revert make optimize flag

---
 examples/make.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/make.mk b/examples/make.mk
index ffcb8ee5..e04a2592 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -103,7 +103,7 @@ CFLAGS += \
 
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
-  CFLAGS += -O0
+  CFLAGS += -Og
 else
   CFLAGS += -Os
 endif

From ab4d30fd6bca02c73eb9b4ff82db0b2b0f403344 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 2 Apr 2021 16:32:48 +0700
Subject: [PATCH 72/72] update readme and contributors for renesas rx63n and
 silabs efm32gg12 port (#767)

* update readme and contributors for renesas rx63n and silabs efm32gg12 port

also add some doc for changelog

* typo

* update more boards

* more typo

* typo 3
---
 CONTRIBUTORS.md   |  6 +++++-
 README.md         |  2 ++
 docs/boards.md    | 11 ++++++++++-
 docs/changelog.md | 12 ++++++++++++
 4 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md
index d75a9d78..5ce352f5 100644
--- a/CONTRIBUTORS.md
+++ b/CONTRIBUTORS.md
@@ -33,6 +33,7 @@
 
 - **[Koji KITAYAMA](https://github.com/kkitayam)**
   - Add new DCD port for **NXP Kinetis KL25**
+  - Add new DCD port for **Renesas RX63n** with GR-CITRUS board
 
 - **[Nathan Conrad](https://github.com/pigrew)**
   - Add new DCD port for **STM32 fsdev** Fullspeed device for STM32 L0, F0, F1, F3 etc ...
@@ -47,6 +48,9 @@
   - Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
   - Improve multiple cdc interfaces API & add cdc_dual_ports example
 
+- **[Rafael Silva](https://github.com/perigoso)**
+  - Add new DCD port for **Silabs EFM32GG12** with SLTB009A board
+
 - **[Raspberry Pi Team](https://github.com/raspberrypi)**
   - Add new DCD port for **Raspberry Pi RP2040**
 
@@ -59,7 +63,7 @@
   - Add new class driver for **Musical Instrument Digital Interface (MIDI)**
   - Improve USBD control transfer, MSC, CDC class driver
   - Board support for Metro M0 & M4 express
-  - Write the execellent porting.md documentation
+  - Write the excellent porting.md documentation
   - Add initial Makefile
 
 - **[Sean Cross](https://github.com/xobs)**
diff --git a/README.md b/README.md
index 78ff5f0c..ddbd8a7f 100644
--- a/README.md
+++ b/README.md
@@ -40,6 +40,8 @@ The stack supports the following MCUs:
   - Kinetis: KL25
   - LPC Series: 11Uxx, 13xx, 175x_6x, 177x_8x, 18xx, 40xx, 43xx, 51Uxx, 54xxx, 55xx
 - **Raspberry Pi:** RP2040
+- **Renesas:** RX63N
+- **Silabs:** EFM32GG12
 - **Sony:** CXD56
 - **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
 - **TI:** MSP430
diff --git a/docs/boards.md b/docs/boards.md
index 2b42b4d8..c23e7645 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -102,6 +102,10 @@ This code base already had supported for a handful of following boards (sorted a
 - [NGX LPC4330-Xplorer](https://www.nxp.com/design/designs/lpc4330-xplorer-board:OM13027)
 - [Double M33 Express](https://www.crowdsupply.com/steiert-solutions/double-m33-express)
 
+### Renesas RX
+
+- [GR-CITRUS](https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus)
+
 ### Raspberry Pi RP2040
 
 - [Adafruit Feather RP2040](https://www.adafruit.com/product/4884)
@@ -109,6 +113,10 @@ This code base already had supported for a handful of following boards (sorted a
 - [Adafruit QT Py RP2040](https://www.adafruit.com/product/4900)
 - [Raspberry Pi Pico](https://www.raspberrypi.org/products/raspberry-pi-pico/)
 
+### Silabs
+
+- [EFM32GG12 Thunderboard Kit (SLTB009A)](https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit)
+
 ### Sony
 
 - [Sony Spresense CXD5602](https://developer.sony.com/develop/spresense)
@@ -121,13 +129,14 @@ This code base already had supported for a handful of following boards (sorted a
 - [STM32 L035c8 Discovery](https://www.st.com/en/evaluation-tools/32l0538discovery.html)
 - [STM32 L4R5zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html)
 - [STM32 F070rb Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f070rb.html)
+- [STM32 F072 Evaluation](https://www.st.com/en/evaluation-tools/stm32072b-eval.html)
 - [STM32 F072rb Discovery](https://www.st.com/en/evaluation-tools/32f072bdiscovery.html)
 - STM32 F103c Blue Pill
 - [STM32 F207zg Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f207zg.html)
 - [STM32 F303vc Discovery](https://www.st.com/en/evaluation-tools/stm32f3discovery.html)
 - STM32 F401cc Black Pill
 - [STM32 F407vg Discovery](https://www.st.com/en/evaluation-tools/stm32f4discovery.html)
-- STM32 F411ce Black Pill
+- [STM32 F411ce Black Pill](https://www.adafruit.com/product/4877)
 - [STM32 F411ve Discovery](https://www.st.com/en/evaluation-tools/32f411ediscovery.html)
 - [STM32 F412zg Discovery](https://www.st.com/en/evaluation-tools/32f412gdiscovery.html)
 - [STM32 F723e Discovery](https://www.st.com/en/evaluation-tools/32f723ediscovery.html)
diff --git a/docs/changelog.md b/docs/changelog.md
index 0e5f12e8..96c7f689 100644
--- a/docs/changelog.md
+++ b/docs/changelog.md
@@ -1,5 +1,17 @@
 # TinyUSB Changelog
 
+## WIP
+
+- Add new port Silabs EFM32GG12, board EFM32GG12 Thunderboard Kit (SLTB009A)
+- Add new port Renesas RX63N, board GR-CITRUS
+- MIDI
+  - Fix MIDI buffer overflow issue
+  - Rename tud_midi_read() to tud_midi_stream_read()
+  - Rename tud_midi_write() to tud_midi_stream_write()
+  - Rename tud_midi_receive() to tud_midi_packet_read()
+  - Rename tud_midi_send() to tud_midi_packet_write()
+- New board stm32f072-eval
+
 ## 0.9.0 - 2021.03.12
 
 ### Device Stack